[Qemu-devel] Outreachy intro: micro:bit project

Hi, My name is Julia. I am a bachelor of mathematics from Moscow who is interested in system programming. I've been selected for Outreachy this year to work on the micro:bit project. The project is divided between two people - me and Steffen. We will develop support for the micro:bit board and the

Re: [Qemu-devel] [PATCH v7 1/2] Implement .hex file loader

> This patch adds Intel Hexadecimal Object File format support to > the loader. The file format specification is available here: > http://www.piclist.com/techref/fileext/hex/intel.htm > > The file format is mainly intended for embedded systems > and microcontrollers, such as Micro:bit Arduino,

[Qemu-devel] [PATCH] target/arm: Minor cleanup for ARMv6-M 32-bit instructions

The arrays were made static, "if" was simplified because V7M and V8M define V6 feature. Signed-off-by: Julia Suvorova --- target/arm/translate.c | 27 +-- 1 file changed, 13 insertions(+), 14 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c

[Qemu-devel] [PATCH] target/arm: Allow ARMv6-M Thumb2 instructions

ARMv6-M supports 6 Thumb2 instructions. This patch checks for these instructions and allows their execution. Like Thumb2 cores, ARMv6-M always interprets BL instruction as 32-bit. This patch is required for future Cortex-M0 support. Signed-off-by: Julia Suvorova --- target/arm/translate.c | 35

Re: [Qemu-devel] [PATCH] target/arm: Allow ARMv6-M Thumb2 instructions

On 13.06.2018 17:05, Stefan Hajnoczi wrote: On Tue, Jun 12, 2018 at 11:46:32PM +0300, Julia Suvorova wrote: ARMv6-M supports 6 Thumb2 instructions. This patch checks for these instructions and allows their execution. Like Thumb2 cores, ARMv6-M always interprets BL instruction as 32-bit. This

Re: [Qemu-devel] [PATCH] target/arm: Allow ARMv6-M Thumb2 instructions

On 15.06.2018 13:55, Peter Maydell wrote: On 12 June 2018 at 21:46, Julia Suvorova wrote: ARMv6-M supports 6 Thumb2 instructions. This patch checks for these instructions and allows their execution. Like Thumb2 cores, ARMv6-M always interprets BL instruction as 32-bit. This patch is required

Re: [Qemu-devel] [PATCH] target/arm: Allow ARMv6-M Thumb2 instructions

On 17.06.2018 19:33, Peter Maydell wrote: On 17 June 2018 at 06:36, Richard Henderson wrote: On 06/15/2018 12:55 AM, Peter Maydell wrote: +uint32_t armv6m_insn[] = {0xf3808000 /* msr */, 0xf3b08040 /* dsb */, + 0xf3b08050 /* dmb */, 0xf3b08060 /* isb */, +

[Qemu-devel] [PATCH] target/arm: Set strict alignment for ARMv6-M load/store

Unlike ARMv7-M, ARMv6-M only supports naturally aligned memory accesses for 16-bit halfword and 32-bit word accesses using the LDR, LDRH, LDRSH, STR and STRH instructions. Signed-off-by: Julia Suvorova --- target/arm/translate.c | 18 -- 1 file changed, 16 insertions(+), 2

[Qemu-devel] [RFC 0/3] nRF51 SoC: Add UART support

This series adds basic support for the nRF51 SoC UART, that used in BBC Micro:bit board, and QTest for it. Based-on: <20180503090532.3113-1-j...@jms.id.au> Julia Suvorova (3): hw/arm/nrf51_soc: Fix compilation and memory regions hw/char/nrf51_uart: Implement nRF51 SoC UART

[Qemu-devel] [RFC 3/3] tests/boot-serial-test: Add support for the microbit board

New mini-kernel test for nRF51 SoC UART. Signed-off-by: Julia Suvorova --- tests/boot-serial-test.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/tests/boot-serial-test.c b/tests/boot-serial-test.c index 4d6815c3e0..e6dbc8a293 100644 --- a/tests/boot-serial-test.c +++

[Qemu-devel] [RFC 2/3] hw/char/nrf51_uart: Implement nRF51 SoC UART

Basic implementation of nRF51 SoC UART. Description could be found here: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf The following features are not yet implemented: Control with SUSPEND/START*/STOP* CTS/NCTS flow control Mapping registers to pins Signed-off-by: Julia

[Qemu-devel] [RFC 1/3] hw/arm/nrf51_soc: Fix compilation and memory regions

nRF51 SoC implementation is intended for the BBC Micro:bit board, which has 256 KB flash and 16 KB RAM. Added FICR defines. Signed-off-by: Julia Suvorova --- hw/arm/nrf51_soc.c | 12 +++- include/hw/arm/nrf51_soc.h | 1 + 2 files changed, 8 insertions(+), 5 deletions(-) diff

Re: [Qemu-devel] [RFC 2/3] hw/char/nrf51_uart: Implement nRF51 SoC UART

On 31.05.2018 12:42, Stefan Hajnoczi wrote: > On Wed, May 30, 2018 at 01:03:37AM +0300, Julia Suvorova wrote: >> The following features are not yet implemented: >> Control with SUSPEND/START*/STOP* > > This is probably worth implementing for completeness. Just rx_enabled > and tx_enabled

Re: [Qemu-devel] [RFC 2/3] hw/char/nrf51_uart: Implement nRF51 SoC UART

On 01.06.2018 13:44, Stefan Hajnoczi wrote: On Fri, Jun 1, 2018 at 11:41 AM, Stefan Hajnoczi wrote: On Thu, May 31, 2018 at 2:58 PM, sundeep subbaraya wrote: On Wed, May 30, 2018 at 3:33 AM, Julia Suvorova via Qemu-devel wrote: +static uint64_t uart_read(void *opaque, hwaddr addr, unsigned

[Qemu-devel] [PATCH] qtest: Use cpu address space instead of system memory

Some devices (like nvic in armv7m) are not accessable through address_space_memory, therefore can not be tested with qtest. Signed-off-by: Julia Suvorova --- qtest.c | 39 ++- 1 file changed, 26 insertions(+), 13 deletions(-) diff --git a/qtest.c b/qtest.c

[Qemu-devel] [PATCH v2 2/2] target/arm: Strict alignment for ARMv6-M and ARMv8-M Baseline

Unlike ARMv7-M, ARMv6-M and ARMv8-M Baseline only supports naturally aligned memory accesses for load/store instructions. Signed-off-by: Julia Suvorova --- target/arm/translate.c | 18 -- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/target/arm/translate.c

[Qemu-devel] [PATCH v2 1/2] target/arm: Introduce ARM_FEATURE_M_MAIN

This feature is intended to distinguish ARMv8-M variants: Baseline and Mainline. ARMv7-M compatibility requires the Main Extension. ARMv6-M compatibility is provided by all ARMv8-M implementations. Signed-off-by: Julia Suvorova --- target/arm/cpu.c | 3 +++ target/arm/cpu.h | 1 + 2 files

[Qemu-devel] [PATCH v2 0/2] Strict alignment for ARMv6-M and ARMv8-M Baseline

v2: * Added feature bit for the Main Extention * Alignment patch is modified to use ARM_FEATURE_M_MAIN Julia Suvorova (2): target/arm: Introduce ARM_FEATURE_M_MAIN target/arm: Strict alignment for ARMv6-M and ARMv8-M Baseline target/arm/cpu.c | 3 +++ target/arm/cpu.h |

Re: [Qemu-devel] [PATCH v3 2/3] arm: Add Nordic Semiconductor nRF51 SoC

On 26.07.2018 05:36, Joel Stanley wrote: The nRF51 is a Cortex-M0 microcontroller with an on-board radio module, plus other common ARM SoC peripherals. http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf This defines a basic model of the CPU and memory, with no peripherals implemented at

Re: [Qemu-devel] [PATCH v3 2/3] arm: Add Nordic Semiconductor nRF51 SoC

On 30.07.2018 17:02, Joel Stanley wrote: On 26 July 2018 at 20:31, Julia Suvorova wrote: +++ b/hw/arm/nrf51_soc.c +static void nrf51_soc_init(Object *obj) +{ +NRF51State *s = NRF51_SOC(obj); + +memory_region_init(>container, obj, "nrf51-container", UINT64_MAX); + +

[Qemu-devel] [PATCH v2 1/4] hw/char: Implement nRF51 SoC UART

Not implemented: CTS/NCTS, PSEL*. Signed-off-by: Julia Suvorova --- hw/char/Makefile.objs| 1 + hw/char/nrf51_uart.c | 329 +++ hw/char/trace-events | 4 + include/hw/char/nrf51_uart.h | 78 + 4 files changed, 412

[Qemu-devel] [PATCH v2 2/4] hw/arm/nrf51_soc: Connect UART to nRF51 SoC

Wire up nRF51 UART in the corresponding SoC using in-place init/realize. Based-on: <20180803052137.10602-1-j...@jms.id.au> Signed-off-by: Julia Suvorova --- hw/arm/nrf51_soc.c | 20 include/hw/arm/nrf51_soc.h | 3 +++ 2 files changed, 23 insertions(+) diff --git

[Qemu-devel] [PATCH v2 4/4] tests/microbit-test: Check nRF51 UART functionality

Some functional tests for: Basic reception/transmittion Suspending INTEN* registers Based-on: <20180806100114.21410-6-cont...@steffen-goertz.de> Signed-off-by: Julia Suvorova --- tests/microbit-test.c | 106 -- 1 file changed, 103

[Qemu-devel] [PATCH v2 0/4] arm: Add nRF51 SoC UART support

This series adds support for the nRF51 SoC UART, that used in BBC Micro:bit board, and QTest for it. v2: * Suspend/Enable functionality added * Connection to SoC moved to a separate patch * Added QTest for checking reception functionality * Mini-kernel test changed to fit current

[Qemu-devel] [PATCH v2 3/4] tests/boot-serial-test: Add microbit board testcase

New mini-kernel test for nRF51 SoC UART. Signed-off-by: Julia Suvorova --- tests/boot-serial-test.c | 19 +++ 1 file changed, 19 insertions(+) diff --git a/tests/boot-serial-test.c b/tests/boot-serial-test.c index 952a2e7ead..19714c3f87 100644 --- a/tests/boot-serial-test.c +++

Re: [Qemu-devel] [PATCH 3/7] tests: Add bbc:microbit / nRF51 test suite

On 08.08.2018 12:09, Stefan Hajnoczi wrote: On Mon, Aug 6, 2018 at 11:01 AM, Steffen Görtz wrote: +#define PAGE_SIZE 1024 +#define FLASH_SIZE (256 * PAGE_SIZE) +#define FLASH_BASE 0x +#define UICR_BASE 0x10001000 +#define UICR_SIZE 0x100

Re: [Qemu-devel] [PATCH] chardev: Add websocket support

On 13.08.2018 15:02, Paolo Bonzini wrote: Thanks Julia, just a few cleanups to simplify the prototypes of some functions. Thanks for the review, I'll do the refactoring. Best regards, Julia Suvorova.

Re: [Qemu-devel] [PATCH] chardev: Add websocket support

On 13.08.2018 15:21, Daniel P. Berrangé wrote: On Mon, Aug 13, 2018 at 01:20:37PM +0300, Julia Suvorova via Qemu-devel wrote: New option "websock" added to allow using websocket protocol for chardev socket backend. Example: -chardev socket,websock,id=... Signed-off-by: Juli

Re: [Qemu-devel] [PATCH v2 1/4] hw/char: Implement nRF51 SoC UART

On 13.08.2018 12:47, Stefan Hajnoczi wrote: On Mon, Aug 13, 2018 at 10:08 AM Julia Suvorova wrote: On 10.08.2018 09:02, Stefan Hajnoczi wrote: On Wed, Aug 8, 2018 at 10:07 PM, Julia Suvorova wrote: +static uint64_t uart_read(void *opaque, hwaddr addr, unsigned int size) +{ +

[Qemu-devel] [PATCH] chardev: Add websocket support

New option "websock" added to allow using websocket protocol for chardev socket backend. Example: -chardev socket,websock,id=... Signed-off-by: Julia Suvorova --- chardev/char-socket.c | 75 --- chardev/char.c| 3 ++ qapi/char.json|

Re: [Qemu-devel] [PATCH v2 1/4] hw/char: Implement nRF51 SoC UART

On 10.08.2018 09:02, Stefan Hajnoczi wrote: On Wed, Aug 8, 2018 at 10:07 PM, Julia Suvorova wrote: +static uint64_t uart_read(void *opaque, hwaddr addr, unsigned int size) +{ +NRF51UARTState *s = NRF51_UART(opaque); +uint64_t r; + +if (!s->enabled) { +return 0; +} + +

[Qemu-devel] [PATCH] chardev/char-fe: Fix typos

Fixup some typos in the comments. Signed-off-by: Julia Suvorova --- include/chardev/char-fe.h | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/include/chardev/char-fe.h b/include/chardev/char-fe.h index 71cd069478..c67271f1ba 100644 --- a/include/chardev/char-fe.h

Re: [Qemu-devel] [PATCH 6/7] arm: Instantiate nRF51 peripherals

On 21.08.2018 14:43, Steffen Görtz wrote: Hi Peter, + +static uint64_t clock_read(void *opaque, hwaddr addr, unsigned int size) +{ +qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n", + __func__, addr, size); +return 1; +} + +static void clock_write(void *opaque,

Re: [Qemu-devel] [PATCH v2 1/2] chardev: Add websocket support

On 28.08.2018 12:02, Daniel P. Berrangé wrote: On Mon, Aug 27, 2018 at 09:41:02PM +0300, Julia Suvorova wrote: New option "websock" added to allow using websocket protocol for chardev socket backend. Example: -chardev socket,websock,id=... Signed-off-by: Julia Suvorova ---

Re: [Qemu-devel] [PATCH v2 1/2] chardev: Add websocket support

On 28.08.2018 13:09, Daniel P. Berrangé wrote: On Tue, Aug 28, 2018 at 01:04:41PM +0300, Julia Suvorova wrote: On 28.08.2018 12:02, Daniel P. Berrangé wrote: On Mon, Aug 27, 2018 at 09:41:02PM +0300, Julia Suvorova wrote: New option "websock" added to allow using websocket protocol for

[Qemu-devel] [PATCH v2 1/2] chardev: Add websocket support

New option "websock" added to allow using websocket protocol for chardev socket backend. Example: -chardev socket,websock,id=... Signed-off-by: Julia Suvorova --- chardev/char-socket.c | 124 +++--- chardev/char.c| 8 ++- qapi/char.json|

[Qemu-devel] [PATCH v2 2/2] tests/test-char: Check websocket chardev functionality

Test order: Creating server websocket chardev Creating usual tcp chardev client Sending handshake message from client Receiving handshake reply Sending ping frame with "hello" payload Receiving pong reply Sending binary data "world" Checking the received data on

[Qemu-devel] [PATCH v2 0/2] chardev: Add websocket support

v2: * Fixed initialization order [Daniel] * Function arguments refactoring [Paolo] * Added test [Stefan] * Added meaningful error message [Stefan] * Added "websock:" URI prefix support Julia Suvorova (2): chardev: Add websocket support tests/test-char: Check websocket

Re: [Qemu-devel] [PATCH v2] nvic: Change NVIC to support ARMv6-M

On 19.07.2018 19:25, Peter Maydell wrote: On 19 July 2018 at 13:16, Julia Suvorova wrote: The differences from ARMv7-M NVIC are: * ARMv6-M only supports up to 32 external interrupts (configurable feature already). The ICTR is reserved. * Active Bit Register is reserved. * ARMv6-M

Re: [Qemu-devel] [PATCH] arm: Add ARMv6-M programmer's model support

On 17.07.2018 16:49, Peter Maydell wrote: On 17 July 2018 at 14:42, Julia Suvorova wrote: On 17.07.2018 16:09, Peter Maydell wrote: This should be outside the "if v8" if(), because you also want it for v6M (giving you the v6M CCR value of STKALIGN and UNALIGN_TRP set and all other bits

Re: [Qemu-devel] [PATCH] arm: Add ARMv6-M programmer's model support

On 17.07.2018 16:09, Peter Maydell wrote: diff --git a/target/arm/cpu.c b/target/arm/cpu.c index a914ce4e8c..3788cb773d 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -220,6 +220,11 @@ static void arm_cpu_reset(CPUState *s) env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK;

Re: [Qemu-devel] [PATCH] nvic: Change NVIC to support ARMv6-M

On 17.07.2018 15:58, Peter Maydell wrote: On 10 July 2018 at 16:33, Julia Suvorova wrote: The differences from ARMv7-M NVIC are: * ARMv6-M only supports up to 32 external interrupts (configurable feature already). The ICTR is reserved. * Active Bit Register is reserved. * ARMv6-M

[Qemu-devel] [PATCH v2] arm: Add ARMv6-M programmer's model support

Forbid stack alignment change. (CCR) Reserve FAULTMASK, BASEPRI registers. Report any fault as a HardFault. Disable MemManage, BusFault and UsageFault, so they always escalated to HardFault. (SHCSR) Signed-off-by: Julia Suvorova --- v2: * Changed CCR reset value hw/intc/armv7m_nvic.c | 10

[Qemu-devel] [PATCH v2] nvic: Change NVIC to support ARMv6-M

The differences from ARMv7-M NVIC are: * ARMv6-M only supports up to 32 external interrupts (configurable feature already). The ICTR is reserved. * Active Bit Register is reserved. * ARMv6-M supports 4 priority levels against 256 in ARMv7-M. Signed-off-by: Julia Suvorova --- v2: *

Re: [Qemu-devel] [PATCH] target/arm: Forbid unprivileged mode for M Baseline

On 05.07.2018 13:33, Peter Maydell wrote: On 4 July 2018 at 21:36, Julia Suvorova wrote: MSR handling is the only place where CONTROL.nPRIV is modified. Signed-off-by: Julia Suvorova --- target/arm/helper.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git

Re: [Qemu-devel] [PATCH 1/2] nvic: Handle ARMv6-M SCS reserved registers

On 05.07.2018 13:54, Peter Maydell wrote: On 4 July 2018 at 20:58, Julia Suvorova wrote: Handle SCS reserved registers listed in ARMv6-M ARM D3.6.1. All reserved registers are RAZ/WI. Signed-off-by: Julia Suvorova --- hw/intc/armv7m_nvic.c | 69 +++

[Qemu-devel] [PATCH v2 0/2] nvic: Handle ARMv6-M SCS reserved registers

v2: * Use ARM_FEATURE_M_MAIN instead of ARM_FEATURE_V7 in most cases * Remove CPUID registers check * Use bad_offset instead of return * Misc style fixes Julia Suvorova (2): nvic: Handle ARMv6-M SCS reserved registers tests: Add ARMv6-M reserved register test

[Qemu-devel] [PATCH v2 1/2] nvic: Handle ARMv6-M SCS reserved registers

Handle SCS reserved registers listed in ARMv6-M ARM D3.6.1. All reserved registers are RAZ/WI. ARM_FEATURE_M_MAIN is used for the checks, because these registers are reserved in ARMv8-M Baseline too. Signed-off-by: Julia Suvorova --- hw/intc/armv7m_nvic.c | 51

Re: [Qemu-devel] [PATCH v2 0/2] nvic: Handle ARMv6-M SCS reserved registers

On 06.07.2018 00:50, Julia Suvorova wrote: v2: * Use ARM_FEATURE_M_MAIN instead of ARM_FEATURE_V7 in most cases * Remove CPUID registers check * Use bad_offset instead of return * Misc style fixes Julia Suvorova (2): nvic: Handle ARMv6-M SCS reserved registers tests:

[Qemu-devel] [RFC v2 2/2] tests: Add ARMv6-M reserved register test

Check that reserved SCS registers return 0 at read, and writes are ignored. Based-on: <20180627143815.1829-1-j...@jms.id.au> Based-on: <20180630091343.14391-1-stefa...@redhat.com> Signed-off-by: Julia Suvorova --- Test will work if Joel's patches will use ARMv6-M. tests/Makefile.include

[Qemu-devel] [PATCH v2] target/arm: Forbid unprivileged mode for M Baseline

MSR handling is the only place where CONTROL.nPRIV is modified. Signed-off-by: Julia Suvorova --- v2: * Add the check in the CONTROL_NS case target/arm/helper.c | 12 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index

[Qemu-devel] [RFC v3 2/2] tests: Add ARMv6-M reserved register test

Check that reserved SCS registers return 0 at read, and writes are ignored. Based-on: <20180627143815.1829-1-j...@jms.id.au> Based-on: <20180630091343.14391-1-stefa...@redhat.com> Signed-off-by: Julia Suvorova --- Test will work if Joel's patches will use ARMv6-M. tests/Makefile.include

[Qemu-devel] [PATCH v3 1/2] nvic: Handle ARMv6-M SCS reserved registers

Handle SCS reserved registers listed in ARMv6-M ARM D3.6.1. All reserved registers are RAZ/WI. ARM_FEATURE_M_MAIN is used for the checks, because these registers are reserved in ARMv8-M Baseline too. Signed-off-by: Julia Suvorova --- hw/intc/armv7m_nvic.c | 51

[Qemu-devel] [PATCH v3 0/2] nvic: Handle ARMv6-M SCS reserved registers

v3: * Fix indents v2: * Use ARM_FEATURE_M_MAIN instead of ARM_FEATURE_V7 in most cases * Remove CPUID registers check * Use bad_offset instead of return * Misc style fixes Julia Suvorova (2): nvic: Handle ARMv6-M SCS reserved registers tests: Add ARMv6-M reserved register

[Qemu-devel] [PATCH] nvic: Change NVIC to support ARMv6-M

The differences from ARMv7-M NVIC are: * ARMv6-M only supports up to 32 external interrupts (configurable feature already). The ICTR is reserved. * Active Bit Register is reserved. * ARMv6-M supports 4 priority levels against 256 in ARMv7-M. Signed-off-by: Julia Suvorova ---

[Qemu-devel] [PATCH] arm: Add ARMv6-M programmer's model support

Forbid stack alignment change. (CCR) Reserve FAULTMASK, BASEPRI registers. Report any fault as HardFault. Disable MemManage, BusFault and UsageFault, so they always escalated to HardFault. (SHCSR) Signed-off-by: Julia Suvorova --- This is the last cortex-m0 patch. hw/intc/armv7m_nvic.c | 10

[Qemu-devel] [PATCH 1/2] nvic: Handle ARMv6-M SCS reserved registers

Handle SCS reserved registers listed in ARMv6-M ARM D3.6.1. All reserved registers are RAZ/WI. Signed-off-by: Julia Suvorova --- hw/intc/armv7m_nvic.c | 69 +++ 1 file changed, 57 insertions(+), 12 deletions(-) diff --git a/hw/intc/armv7m_nvic.c

[Qemu-devel] [RFC 2/2] tests: Add ARMv6-M reserved register test

Check that reserved SCS registers return 0 at read, and writes are ignored. Based-on: <20180627143815.1829-1-j...@jms.id.au> Based-on: <20180630091343.14391-1-stefa...@redhat.com> Signed-off-by: Julia Suvorova --- Test will work if Joel's patches will use ARMv6-M. tests/Makefile.include

[Qemu-devel] [PATCH 0/2] nvic: Handle ARMv6-M SCS reserved registers

Julia Suvorova (2): nvic: Handle ARMv6-M SCS reserved registers tests: Add ARMv6-M reserved register test hw/intc/armv7m_nvic.c | 69 +-- tests/Makefile.include| 2 + tests/tcg/arm/test-reserved-reg.c | 60 +++ 3

[Qemu-devel] [PATCH] target/arm: Forbid unprivileged mode for M Baseline

MSR handling is the only place where CONTROL.nPRIV is modified. Signed-off-by: Julia Suvorova --- target/arm/helper.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 5ee229eb35..83cca554ad 100644 --- a/target/arm/helper.c

[Qemu-devel] [PATCH] use g_path_get_basename instead of basename

basename(3) and dirname(3) modify their argument and may return pointers to statically allocated memory which may be overwritten by subsequent calls. g_path_get_basename and g_path_get_dirname have no such issues, and therefore more preferable. Signed-off-by: Julia Suvorova ---

Re: [Qemu-devel] [PATCH] use g_path_get_basename instead of basename

On 01.03.2018 13:59, Cornelia Huck wrote: > On Thu, 1 Mar 2018 10:47:42 +0100 > Marc-André Lureau <marcandre.lur...@gmail.com> wrote: > >> Hi >> >> On Thu, Mar 1, 2018 at 8:08 AM, Julia Suvorova via Qemu-devel >> <qemu-devel@nongnu.org>

Re: [Qemu-devel] [PATCH] use g_path_get_basename instead of basename

On 01.03.2018 14:21, Paolo Bonzini wrote: > On 01/03/2018 11:59, Cornelia Huck wrote: Signed-off-by: Julia Suvorova >>> What about adding a warning for basename()/dirname() usage in >>> scripts/checkpatch.pl ? >> +1 to that. >> > > Good idea indeed. Julia, would

[Qemu-devel] [PATCH] net/vde: print error on vde_open() failure

Despite the fact that now when the initialization of vde fails, qemu does not end silently, no informative error is printed. The patch generates an error and pushes it through the calling function. Related bug: https://bugs.launchpad.net/qemu/+bug/676029 Signed-off-by: Julia Suvorova

[Qemu-devel] [PATCH] checkpatch: add a warning for basename/dirname

Signed-off-by: Julia Suvorova --- scripts/checkpatch.pl | 5 + 1 file changed, 5 insertions(+) diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl index 1b4b812..6c4fb42 100755 --- a/scripts/checkpatch.pl +++ b/scripts/checkpatch.pl @@ -2584,6 +2584,11 @@ sub process

Re: [Qemu-devel] [PATCH] checkpatch: add a warning for basename/dirname

On 02.03.2018 11:56, Paolo Bonzini wrote: > On 02/03/2018 09:22, Julia Suvorova wrote: >> Signed-off-by: Julia Suvorova >> --- >> scripts/checkpatch.pl | 5 + >> 1 file changed, 5 insertions(+) >> >> diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl >> index

[Qemu-devel] [PATCH v2] checkpatch: add a warning for basename/dirname

g_path_get_* do the same as g_strdup(basename/dirname(...)) but without modifying the argument. Signed-off-by: Julia Suvorova --- scripts/checkpatch.pl | 5 + 1 file changed, 5 insertions(+) diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl index 1b4b812..a88af61

[Qemu-devel] [PATCH v3 1/3] chardev/char-socket: Function headers refactoring

Upcoming websocket support requires additional parameters in function headers that are already overloaded. This patch replaces the bunch of parameters with a single structure pointer. Signed-off-by: Julia Suvorova --- chardev/char-socket.c | 55 +++ 1

[Qemu-devel] [PATCH v3 0/3] chardev: Add websocket support

v3: * Refactoring moved to a separate patch [Daniel] * "websock" option renamed to "websocket" [Stefan] * Added documentation [Daniel] v2: * Fixed initialization order [Daniel] * Function arguments refactoring [Paolo] * Added test [Stefan] * Added meaningful error

[Qemu-devel] [PATCH v3 2/3] chardev: Add websocket support

New option "websocket" added to allow using WebSocket protocol for chardev socket backend. Example: -chardev socket,websocket,server,id=... Signed-off-by: Julia Suvorova --- chardev/char-socket.c | 64 ++- chardev/char.c| 8 +-

[Qemu-devel] [PATCH v3 3/3] tests/test-char: Check websocket chardev functionality

Test order: Creating server websocket chardev Creating usual tcp chardev client Sending handshake message from client Receiving handshake reply Sending ping frame with "hello" payload Receiving pong reply Sending binary data "world" Checking the received data on

[Qemu-devel] [PATCH v3 2/3] hw/arm/nrf51_soc: Connect UART to nRF51 SoC

Wire up nRF51 UART in the corresponding SoC. Signed-off-by: Julia Suvorova --- hw/arm/microbit.c | 2 ++ hw/arm/nrf51_soc.c | 20 include/hw/arm/nrf51_soc.h | 3 +++ 3 files changed, 25 insertions(+) diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c

[Qemu-devel] [PATCH v3 0/3] arm: Add nRF51 SoC UART support

This series adds support for the nRF51 SoC UART, that used in BBC Micro:bit board, and QTest for it. v3: * serial_hd() moved to the board code * sysbus_init_child_obj() used for initialization * qemu_chr_fe_accept_input() called after byte popping v2: * Suspend/Enable

[Qemu-devel] [PATCH v3 3/3] tests/boot-serial-test: Add microbit board testcase

New mini-kernel test for nRF51 SoC UART. Signed-off-by: Julia Suvorova Acked-by: Thomas Huth Reviewed-by: Stefan Hajnoczi --- tests/boot-serial-test.c | 19 +++ 1 file changed, 19 insertions(+) diff --git a/tests/boot-serial-test.c b/tests/boot-serial-test.c index

[Qemu-devel] [PATCH v3 1/3] hw/char: Implement nRF51 SoC UART

Not implemented: CTS/NCTS, PSEL*. Signed-off-by: Julia Suvorova --- hw/char/Makefile.objs| 1 + hw/char/nrf51_uart.c | 330 +++ hw/char/trace-events | 4 + include/hw/char/nrf51_uart.h | 78 + 4 files changed, 413

Re: [Qemu-devel] [PATCH v3 02/13] arm: Add header to host common definition for nRF51 SOC peripherals

On 31.10.2018 00:25, Steffen Görtz wrote: Adds a header that provides definitions that are used across nRF51 peripherals Signed-off-by: Steffen Görtz --- hw/arm/nrf51_soc.c | 33 ++- include/hw/arm/nrf51.h | 44

[Qemu-devel] [PATCH v3] tests/microbit-test: Check nRF51 UART functionality

Some functional tests for: Basic reception/transmittion Suspending INTEN* registers Based-on: <20181031002526.14262-1-cont...@steffen-goertz.de> Signed-off-by: Julia Suvorova --- This patch was part of nRF51 UART patchset, but wasn't included in the latest revision. Due to upcoming

Re: [Qemu-devel] [PATCH v3] tests/microbit-test: Check nRF51 UART functionality

On 05.11.2018 15:24, Alex Bennée wrote: Julia Suvorova via Qemu-devel writes: Some functional tests for: Basic reception/transmittion Suspending INTEN* registers Based-on: <20181031002526.14262-1-cont...@steffen-goertz.de> Signed-off-by: Julia Suvorova --- This

Re: [Qemu-devel] [PATCH v3] tests/microbit-test: Check nRF51 UART functionality

On 05.11.2018 19:16, Philippe Mathieu-Daudé wrote: Hi Julia, On 5/11/18 11:45, Julia Suvorova via Qemu-devel wrote: Some functional tests for: Basic reception/transmittion Suspending INTEN* registers Based-on: <20181031002526.14262-1-cont...@steffen-goertz.de> Sign

Re: [Qemu-devel] [PATCH] hw/core/generic-loader: Fix PC overwriting

On 16.01.2019 0:51, Alistair Francis wrote: On Tue, Jan 15, 2019 at 7:04 AM Julia Suvorova via Qemu-devel wrote: If the memory is set using a file, and PC is specified on the command line, it will be overwritten with the value 'entry'. This is not only illogical, but also incorrect, because

[Qemu-devel] [PATCH v4 2/3] tests/microbit-test: Make test independent of global_qtest

Using of global_qtest is not required here. Let's replace functions like readl() with the corresponding qtest_* counterparts. Signed-off-by: Julia Suvorova --- tests/microbit-test.c | 247 ++ 1 file changed, 129 insertions(+), 118 deletions(-) diff --git

[Qemu-devel] [PATCH v4 1/3] tests/libqtest: Introduce qtest_init_with_serial()

Run qtest with a socket that connects QEMU chardev and test code. Signed-off-by: Julia Suvorova --- tests/libqtest.c | 26 ++ tests/libqtest.h | 11 +++ 2 files changed, 37 insertions(+) diff --git a/tests/libqtest.c b/tests/libqtest.c index

[Qemu-devel] [PATCH v4 3/3] tests/microbit-test: Check nRF51 UART functionality

Some functional tests for: Basic reception/transmittion Suspending INTEN* registers Signed-off-by: Julia Suvorova --- tests/microbit-test.c | 84 +++ 1 file changed, 84 insertions(+) diff --git a/tests/microbit-test.c b/tests/microbit-test.c

[Qemu-devel] [PATCH v4 0/3] tests/microbit-test: Add UART device test

v4: * Replace sprintf with g_strdup_printf [Peter] * Move socket connection to qtest library [Peter] * Use memcmp instead of strcmp [Stefan] * Remove using global_qtest [Thomas] v3: * Fix directory leak [Stefan] Based-on: <20190110094020.18354-1-stefa...@redhat.com> Julia

Re: [Qemu-devel] [PATCH] hw/core/generic-loader: Fix PC overwriting

On 17.01.2019 13:13, Stefan Hajnoczi wrote: On Wed, Jan 16, 2019 at 10:05:58PM +0300, Julia Suvorova via Qemu-devel wrote: On 16.01.2019 0:51, Alistair Francis wrote: On Tue, Jan 15, 2019 at 7:04 AM Julia Suvorova via Qemu-devel wrote: If the memory is set using a file, and PC is specified

[Qemu-devel] [PATCH] hw/core/generic-loader: Fix PC overwriting

If the memory is set using a file, and PC is specified on the command line, it will be overwritten with the value 'entry'. This is not only illogical, but also incorrect, because the load_ * functions do not take into account the specifics of the ARM-M PC. Signed-off-by: Julia Suvorova ---

Re: [Qemu-devel] [PATCH] hw/core/generic-loader: Fix PC overwriting

On 21.01.2019 20:24, Peter Maydell wrote: On Thu, 17 Jan 2019 at 19:27, Peter Maydell wrote: On Thu, 17 Jan 2019 at 10:58, Julia Suvorova wrote: On 17.01.2019 13:13, Stefan Hajnoczi wrote: generic_loader_reset() calls cpu_reset(s->cpu) followed by CPUClass->set_pc(s->cpu, s->addr). ARM's

[Qemu-devel] [PATCH v5 2/3] tests/microbit-test: Make test independent of global_qtest

Using of global_qtest is not required here. Let's replace functions like readl() with the corresponding qtest_* counterparts. Signed-off-by: Julia Suvorova Reviewed-by: Philippe Mathieu-Daudé Acked-by: Thomas Huth Reviewed-by: Stefan Hajnoczi --- tests/microbit-test.c | 247

[Qemu-devel] [PATCH v5 1/3] tests/libqtest: Introduce qtest_init_with_serial()

Run qtest with a socket that connects QEMU chardev and test code. Signed-off-by: Julia Suvorova Reviewed-by: Stefan Hajnoczi --- tests/libqtest.c | 25 + tests/libqtest.h | 11 +++ 2 files changed, 36 insertions(+) diff --git a/tests/libqtest.c

[Qemu-devel] [PATCH v5 3/3] tests/microbit-test: Check nRF51 UART functionality

Some functional tests for: Basic reception/transmittion Suspending INTEN* registers Signed-off-by: Julia Suvorova --- tests/microbit-test.c | 89 +++ 1 file changed, 89 insertions(+) diff --git a/tests/microbit-test.c b/tests/microbit-test.c

[Qemu-devel] [PATCH v5 0/3] tests/microbit-test: Add UART device test

v5: * Replace g_assert with g_assert_* [Thomas, Alex] * Increase the waiting time for an event [Thomas] * Remove 'nowait' [Thomas] * Rewrite uart_wait_for_event to use time difference instead of loop v4: * Replace sprintf with g_strdup_printf [Peter] * Move socket

Re: [Qemu-devel] [PATCH v2 2/2] tests/microbit-test: add TWI stub device test

On 10.01.2019 12:48, Thomas Huth wrote: On 2019-01-10 10:40, Stefan Hajnoczi wrote: This test verifies that we read back the expected I2C WHO_AM_I register values for the accelerometer/magnetometer. Signed-off-by: Stefan Hajnoczi --- tests/microbit-test.c | 44

Re: [Qemu-devel] [PATCH] monitor: Add whitelist support for QMP commands

On 12.02.2019 10:13, Markus Armbruster wrote: Julia Suvorova via Qemu-devel writes: On 01.02.2019 12:14, Markus Armbruster wrote: Julia Suvorova via Qemu-devel writes: The whitelist option allows to run a reduced monitor with a subset of QMP commands. This allows the monitor to run

Re: [Qemu-devel] [PATCH] monitor: Add whitelist support for QMP commands

On 11.02.2019 18:51, Daniel P. Berrangé wrote: On Thu, Jan 31, 2019 at 03:03:21PM -0600, Eric Blake wrote: On 1/31/19 2:26 PM, Julia Suvorova via Qemu-devel wrote: The whitelist option allows to run a reduced monitor with a subset of QMP commands. This allows the monitor to run in secure

Re: [Qemu-devel] [PATCH] monitor: Add whitelist support for QMP commands

On 01.02.2019 12:14, Markus Armbruster wrote: Julia Suvorova via Qemu-devel writes: The whitelist option allows to run a reduced monitor with a subset of QMP commands. This allows the monitor to run in secure mode, which is For a value of "secure". I'm not saying this can't

[Qemu-devel] [PATCH] monitor: Add whitelist support for QMP commands

The whitelist option allows to run a reduced monitor with a subset of QMP commands. This allows the monitor to run in secure mode, which is convenient for sending commands via the WebSocket monitor using the web UI. This is planned to be done on micro:bit board. The list of allowed commands

Re: [Qemu-devel] [PATCH] monitor: Add whitelist support for QMP commands

On 01.02.2019 0:03, Eric Blake wrote: On 1/31/19 2:26 PM, Julia Suvorova via Qemu-devel wrote: The whitelist option allows to run a reduced monitor with a subset of QMP commands. This allows the monitor to run in secure mode, which is convenient for sending commands via the WebSocket monitor

[Qemu-devel] [PATCH] arm: Clarify the logic of set_pc()

Until now, the set_pc logic was unclear, which raised questions about whether it should be used directly, applying a value to PC or adding additional checks, for example, set the Thumb bit in Arm cpu. Let's set the set_pc logic for “Configure the PC, as was done in the ELF file” and implement

[Qemu-devel] [PATCH] block/linux-aio: Drop unused BlockAIOCB submission method

Callback-based laio_submit() and laio_cancel() were left after rewriting Linux AIO backend to coroutines in hope that they would be used in other code that could bypass coroutines. They can be safely removed because they have not been used since that time. Signed-off-by: Julia Suvorova ---

Re: [Qemu-devel] [PATCH] block/linux-aio: explictly clear laiocb->co

On 30.05.2019 17:07, Paolo Bonzini wrote: On 30/05/19 10:42, Kevin Wolf wrote: Am 27.05.2019 um 11:23 hat Stefan Hajnoczi geschrieben: qemu_aio_get() does not zero allocated memory. Explicitly initialize laiocb->co to prevent an uninitialized memory access in qemu_laio_process_completion().

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