Re: [Qemu-devel] [PATCH] piix: do not reset APIC base address (0x80) on piix4_reset.

On Thu, Dec 19, 2013 at 08:03:15PM +0200, Marcel Apfelbaum wrote: > On Thu, 2013-12-19 at 11:06 -0500, Kevin O'Connor wrote: > > On Wed, Dec 18, 2013 at 06:55:24PM +0200, Marcel Apfelbaum wrote: > > > On Wed, 2013-12-18 at 11:34 -0500, Paolo Bonzini wrote: > > > &

Re: [Qemu-devel] [QEMU v6 PATCH 00/17] SMBIOS: build full tables in QEMU

On Tue, Apr 15, 2014 at 10:29:26AM +0200, Gerd Hoffmann wrote: > Leave the old interface code basically as-is. type0 and type1 > individual fields are passed like they are passed today. We don't > change to to pass full tables, and we don't extend that to new table > types. Continue to provide t

Re: [Qemu-devel] [PATCH V6 0/2] hw/pci: reserve IO and mem for pci-2-pci bridges with no devices attached

On Thu, Apr 10, 2014 at 09:55:20PM +0300, Marcel Apfelbaum wrote: > If a pci-2-pci bridge supports hot-plug functionality but there are no devices > connected to it, reserve IO/mem in order to be able to attach devices > later. Do not waste space, use minimum allowed. Thanks - I have committed thi

Re: [Qemu-devel] [SeaBIOS] seabios release?

On Wed, Apr 23, 2014 at 04:41:32PM +0200, Gerd Hoffmann wrote: > Hi, > > I think it's time to start planning the next seabios release. First, > because a bunch of changes have piled up in master. And second, because > of the smbios changes. They are a step forward in making seabios less > dep

[Qemu-devel] [PATCH] SMI handler should set the CPL to zero and save and restore it on rsm.

The current SMI interrupt handler is being run with the same CPL as the code it interrupts. If the existing code is running with CPL=3, then the SMI handler can cause spurious exceptions. The System Management Mode (SMM) should always run at the highest protection level. Signed-off-by: Kevin

Re: [Qemu-devel] [PATCH] SMI handler should set the CPL to zero and save and restore it on rsm.

On Sat, Apr 26, 2014 at 11:06:53AM +0200, Paolo Bonzini wrote: > Il 25/04/2014 19:17, Kevin O'Connor ha scritto: > >The current SMI interrupt handler is being run with the same CPL as > >the code it interrupts. If the existing code is running with CPL=3, > >then the SMI

Re: [Qemu-devel] [PATCH] SMI handler should set the CPL to zero and save and restore it on rsm.

On Sun, Apr 27, 2014 at 08:10:39AM +0200, Paolo Bonzini wrote: > Il 26/04/2014 21:36, Kevin O'Connor ha scritto: > >Yes, I was thinking of something like that as well. If QEMU > >internally observes the formula above, then something like the patch > >below should work in

Re: [Qemu-devel] [PATCH] SMI handler should set the CPL to zero and save and restore it on rsm.

On Sun, Apr 27, 2014 at 04:29:25PM +0200, Paolo Bonzini wrote: > Il 27/04/2014 14:22, Marcel Apfelbaum ha scritto: > >On Sat, 2014-04-26 at 11:06 +0200, Paolo Bonzini wrote: > >>KVM computes the CPL as follows: > >> > >>if (CR0.PE == 0) > >> return 0; > >> > >>if (!EFER.LMA && EFLAGS.VM) > >> r

Re: [Qemu-devel] [PATCH] SMI handler should set the CPL to zero and save and restore it on rsm.

On Sun, Apr 27, 2014 at 08:10:39AM +0200, Paolo Bonzini wrote: > Il 26/04/2014 21:36, Kevin O'Connor ha scritto: > >Yes, I was thinking of something like that as well. If QEMU > >internally observes the formula above, then something like the patch > >below should work in

Re: [Qemu-devel] [PATCH] SMI handler should set the CPL to zero and save and restore it on rsm.

On Sun, Apr 27, 2014 at 01:45:24PM -0400, Kevin O'Connor wrote: > On Sun, Apr 27, 2014 at 08:10:39AM +0200, Paolo Bonzini wrote: > > Il 26/04/2014 21:36, Kevin O'Connor ha scritto: > > >Yes, I was thinking of something like that as well. If QEMU > > >intern

[Qemu-devel] [PATCHv2 0/4] Set eflags prior to segments; fix cpl in SMM

alculate hflags lazily to eliminate these ordering issues. -Kevin Kevin O'Connor (4): Set eflags prior to calling svm_load_seg_cache() in svm_helper.c. Set eflags and cr0 prior to calling cpu_x86_load_seg_cache() in smm_helper.c. Set eflags prior to calling cpu_x86_load_seg_cache() in

[Qemu-devel] [PATCH 1/4] Set eflags prior to calling svm_load_seg_cache() in svm_helper.c.

The svm_load_seg_cache() function calls cpu_x86_load_seg_cache() which inspects env->eflags. So, make sure all changes to eflags are done prior to loading the segment cache. Signed-off-by: Kevin O'Connor --- target-i386/svm_helper.c | 7 ++- 1 file changed, 2 insertions(+), 5 d

[Qemu-devel] [PATCH 3/4] Set eflags prior to calling cpu_x86_load_seg_cache() in seg_helper.c.

The cpu_x86_load_seg_cache() function inspects eflags, so make sure all changes to eflags are done prior to loading the segment caches. Signed-off-by: Kevin O'Connor --- target-i386/seg_helper.c | 38 +++--- 1 file changed, 19 insertions(+), 19 deletions(-)

[Qemu-devel] [PATCH 2/4] Set eflags and cr0 prior to calling cpu_x86_load_seg_cache() in smm_helper.c.

The cpu_x86_load_seg_cache() function inspects cr0 and eflags, so make sure all changes to eflags and cr0 are done prior to loading the segment caches. Signed-off-by: Kevin O'Connor --- target-i386/smm_helper.c | 34 +- 1 file changed, 17 insertions(+

[Qemu-devel] [PATCH 4/4] The x86 CPL is stored in CS.selector - auto update hflags accordingly.

as it was not setting/restoring the CPL level manually. Signed-off-by: Kevin O'Connor --- bsd-user/main.c | 2 -- linux-user/main.c| 2 -- target-i386/cpu.h| 25 - target-i386/seg_helper.c | 15 --- target-i386/svm_helper.c

[Qemu-devel] [PATCHv3 4/4] The x86 CPL is stored in CS.selector - auto update hflags accordingly.

On Wed, Apr 30, 2014 at 09:57:21AM -0700, Richard Henderson wrote: > On 04/29/2014 01:38 PM, Kevin O'Connor wrote: > > +if (!(env->cr[0] & CR0_PE_MASK)) > > +cpl = 0; > > +else if (env->eflags & V

[Qemu-devel] [PATCHv3 2/4] Set eflags and cr0 prior to calling cpu_x86_load_seg_cache() in smm_helper.c.

On Wed, Apr 30, 2014 at 09:54:10AM -0700, Richard Henderson wrote: > On 04/29/2014 01:38 PM, Kevin O'Connor wrote: > > cpu_load_eflags(env, 0, ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | > >DF_MASK)); > > env->eip = 0x8000

Re: [Qemu-devel] [PATCH v2] map 64-bit PCI BARs at location provided by emulator

On Sun, Oct 13, 2013 at 03:31:23PM +0300, Michael S. Tsirkin wrote: > On Sun, Oct 13, 2013 at 02:13:44PM +0200, Igor Mammedov wrote: > > Currently 64-bit PCI BARs are unconditionally mapped by BIOS right > > over 4G + RamSizeOver4G location, which doesn't allow to reserve > > extra space before 64-

Re: [Qemu-devel] [SeaBIOS] [PATCH v2] map 64-bit PCI BARs at location provided by emulator

On Sun, Oct 13, 2013 at 08:19:16PM +0200, Igor Mammedov wrote: > On Sun, 13 Oct 2013 19:33:19 +0200 > Igor Mammedov wrote: > > On Sun, 13 Oct 2013 19:46:09 +0300 > > "Michael S. Tsirkin" wrote: > > > On Sun, Oct 13, 2013 at 06:23:28PM +0200, Igor Mammedov wrote: > > > > On Sun, 13 Oct 2013 18:59:

Re: [Qemu-devel] [SeaBIOS] qemu 1.7 & seabios -- release planning

On Tue, Oct 15, 2013 at 12:04:05PM +0200, Gerd Hoffmann wrote: > Hi, > > It's probably going to be a bit tough this time. We are pretty late in > the qemu 1.7 devel cycle, soft freeze today, and a big chunk of code > (ahci-tables-from qemu) which needs seabios support[1] is just about to > be p

Re: [Qemu-devel] [PATCH 2/2 (RFC)] QEMU: SMBIOS: Build full smbios tables

On Tue, Mar 04, 2014 at 02:20:06PM -0500, Gabriel L. Somlo wrote: > Kevin and Gerd: I'd like to get your acked-by for this patch (or any > future revision): you're the two people who've been editing src/fw/smbios.c > in SeaBIOS, and while I didn't directly cut'n'paste anything from there, > I did i

Re: [Qemu-devel] SMBIOS (Set of 10 patches)

On Tue, Mar 11, 2014 at 11:03:06AM +0100, Gerd Hoffmann wrote: > Issue #3: Running a diff on the dmidecode output with and without the > patches yields this: I think it would be best to get the patch series to the point that there is no diff between old and new. That will make review easier, and

Re: [Qemu-devel] [v2 PATCH 00/13] SMBIOS: build full tables in QEMU

that memory location at > the time. Typically it's 0x, but you happened to get 0x0003 :) I > figured I'd set it to a known value (0xFFFE or "n/a"). That's a seabios bug - I'll create a seabios patch. > On Tue, Mar 11, 2014 at 09:27:31AM -0400, Kevin O&#x

[Qemu-devel] [ANNOUNCE] SeaBIOS 1.8.0

The 1.8.0 version of SeaBIOS has now been released. For more information on the release, please see: http://seabios.org/Releases New in this release: * Several USB timing fixes for USB controllers on real hardware * Initial support for USB3 hubs * Initial support for SD cards (on QEMU only) *

Re: [Qemu-devel] Emulation failure on booting/rebooting VMs

On Wed, Mar 18, 2015 at 06:36:48PM +0100, Mohammed Gamal wrote: > Hi, > I've been sporadically getting my KVM virtual machines crashing with this > message while they're booting > > KVM internal error. Suberror: 1 > emulation failure > EAX= EBX= ECX= EDX=00600f12 > ESI=

Re: [Qemu-devel] [PATCH 6/6] qga: RFC: guest-side retrieval of fw_cfg file

On Tue, Mar 17, 2015 at 01:38:06PM +0100, Laszlo Ersek wrote: > On 03/16/15 15:15, Gabriel L. Somlo wrote: > > 1. I can't for the life of me figure out how to stop gcc -O2 > > from assuming the if() test below is ALWAYS FALSE, and thus > > optimizing it out completely. For now I've forc

Re: [Qemu-devel] [PATCH] checkrom: Fix typo in error message

On Thu, Mar 19, 2015 at 05:23:19PM +0100, Andreas Färber wrote: > increate -> increase > > Signed-off-by: Andreas Färber Thanks - I added it to my queue. -Kevin

Re: [Qemu-devel] E5-2620v2 - emulation stop error

On Wed, Mar 25, 2015 at 11:43:31PM +0300, Andrey Korolyov wrote: > On Mon, Mar 16, 2015 at 10:17 PM, Andrey Korolyov wrote: > > For now, it looks like bug have a mixed Murphy-Heisenberg nature, as > > it appearance is very rare (compared to the number of actual launches) > > and most probably boun

Re: [Qemu-devel] E5-2620v2 - emulation stop error

On Thu, Mar 26, 2015 at 01:31:11AM +0300, Andrey Korolyov wrote: > On Wed, Mar 25, 2015 at 11:54 PM, Kevin O'Connor wrote: > > > > Can you add something like: > > > > -chardev file,path=seabioslog.`date +%s`,id=seabios -device > > isa-debugcon,iobase=0x4

Re: [Qemu-devel] E5-2620v2 - emulation stop error

On Thu, Mar 26, 2015 at 02:35:58AM +0300, Andrey Korolyov wrote: > Thanks, strangely the reboot is always failing now and always reaching > seabios greeting. May be prints straightened up a race (e.g. it is not > int19 problem really). > > object file part: > > d331 : > irq_trampoline_0x19():

Re: [Qemu-devel] E5-2620v2 - emulation stop error

On Thu, Mar 26, 2015 at 04:58:07PM +0100, Radim Krčmář wrote: > 2015-03-25 20:05-0400, Kevin O'Connor: > > On Thu, Mar 26, 2015 at 02:35:58AM +0300, Andrey Korolyov wrote: > > > Thanks, strangely the reboot is always failing now and always reaching > > >

Re: [Qemu-devel] E5-2620v2 - emulation stop error

On Thu, Mar 26, 2015 at 07:48:09PM +0300, Andrey Korolyov wrote: > On Thu, Mar 26, 2015 at 7:36 PM, Kevin O'Connor wrote: > > I'm not sure if the crash always happens at the "int $0x19" location > > though. Andrey, does the crash always happen with "

Re: [Qemu-devel] E5-2620v2 - emulation stop error

On Thu, Mar 26, 2015 at 08:08:52PM +0300, Andrey Korolyov wrote: > On Thu, Mar 26, 2015 at 8:06 PM, Kevin O'Connor wrote: > > On Thu, Mar 26, 2015 at 07:48:09PM +0300, Andrey Korolyov wrote: > >> On Thu, Mar 26, 2015 at 7:36 PM, Kevin O'Connor wrote: > >&g

Re: [Qemu-devel] [SeaBIOS] [PATCH] smbios: ensure comparison SMBIOS string can't be paragraph aligned

On Tue, Mar 31, 2015 at 12:37:30PM -0400, Gabriel L. Somlo wrote: > On Tue, Mar 31, 2015 at 08:49:58AM -0600, Bruce Rogers wrote: > > >>> On 3/30/2015 at 10:02 PM, Kevin O'Connor wrote: > > > On Mon, Mar 30, 2015 at 05:06:30PM -0600, Bruce Rogers wrote: > &g

[Qemu-devel] [RFC][PATCH 0/4] Add support for SDHCI PCI devices

t if I can find an available qemu arm image. I'm not that familiar with QEMU internals. Comments welcome. -Kevin Kevin O'Connor (4): sdhci: Remove class "virtual" methods sdhci: Add "sysbus" to sdhci QOM types and methods sdhci: Support SDHCI devices on PCI s

[Qemu-devel] [PATCH 2/4] sdhci: Add "sysbus" to sdhci QOM types and methods

Update the sdhci sysbus QOM types and methods so that sysbus is in their name. This is in preparation for adding PCI versions of these types and methods. Signed-off-by: Kevin O'Connor --- hw/sd/sdhci.c | 39 --- hw/sd/sdhci.h | 6 +++--- 2 files change

[Qemu-devel] [PATCH 4/4] sdhci: Set a default frequency clock

The Linux SDHCI PCI driver will only register the device if there is a clock frequency set. So, set a default frequency of 52Mhz. Signed-off-by: Kevin O'Connor --- hw/sd/sdhci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 55

[Qemu-devel] [PATCH 1/4] sdhci: Remove class "virtual" methods

sdhci code to support PCI devices (which have a different parent class). Signed-off-by: Kevin O'Connor --- hw/sd/sdhci.c | 112 ++ hw/sd/sdhci.h | 24 - 2 files changed, 35 insertions(+), 101 deletions(-) diff --git a/hw/

[Qemu-devel] [PATCH 3/4] sdhci: Support SDHCI devices on PCI

Support for PCI devices following the "SD Host Controller Simplified Specification Version 2.00" spec. Signed-off-by: Kevin O'Connor --- default-configs/pci.mak | 2 ++ hw/sd/sdhci.c| 44 hw/sd/sdhci.h| 9 +++

Re: [Qemu-devel] [PATCH 2/5] exec: qemu_ram_alloc_device, qemu_ram_resize

On Wed, Nov 19, 2014 at 02:44:32PM +0100, Paolo Bonzini wrote: > So: > > qemu-2.0 -M pc-2.0 -> qemu-2.2 -M pc-2.0 > >uses 2.0 BIOS > > qemu-2.2 -M pc-2.0 -> qemu-2.0 -M pc-2.0 > >uses 2.2 BIOS > > Both should work, in general. BIOS is rarely the reason for > incompatibilities. Howeve

Re: [Qemu-devel] [PATCH 3/4] sdhci: Support SDHCI devices on PCI

On Tue, Nov 18, 2014 at 07:27:24AM +0100, Paolo Bonzini wrote: > On 18/11/2014 05:26, Kevin O'Connor wrote: > > --- a/include/hw/pci/pci.h > > +++ b/include/hw/pci/pci.h > > @@ -53,6 +53,7 @@ > > /* QEMU/Bochs VGA (0x1234) */ > > #define PCI_VENDOR_ID_

[Qemu-devel] [PATCHv2 3/5] sdhci: Define SDHCI PCI ids

Signed-off-by: Kevin O'Connor --- docs/specs/pci-ids.txt | 2 ++ include/hw/pci/pci.h | 1 + include/hw/pci/pci_ids.h | 1 + 3 files changed, 4 insertions(+) diff --git a/docs/specs/pci-ids.txt b/docs/specs/pci-ids.txt index 3c65e1a..9b57d5e 100644 --- a/docs/specs/pci-ids.txt +++ b

[Qemu-devel] [PATCHv2 0/5] Add support for SDHCI PCI devices

IDs instead of inventing new "qemu" IDs - Fix compile warnings when debugging is enabled -Kevin Kevin O'Connor (5): sdhci: Remove class "virtual" methods sdhci: Add "sysbus" to sdhci QOM types and methods sdhci: Define SDHCI PCI ids sdhci: Support SDH

[Qemu-devel] [PATCHv2 1/5] sdhci: Remove class "virtual" methods

sdhci code to support PCI devices (which have a different parent class). Signed-off-by: Kevin O'Connor --- hw/sd/sdhci.c | 118 +++--- hw/sd/sdhci.h | 24 2 files changed, 38 insertions(+), 104 deletions(-) diff --git a/hw/sd/

[Qemu-devel] [PATCHv2 4/5] sdhci: Support SDHCI devices on PCI

Support for PCI devices following the "SD Host Controller Simplified Specification Version 2.00" spec. Signed-off-by: Kevin O'Connor --- default-configs/pci.mak | 2 ++ hw/sd/sdhci.c | 44 hw/sd/sdhci.h | 9 +++

[Qemu-devel] [PATCHv2 2/5] sdhci: Add "sysbus" to sdhci QOM types and methods

Update the sdhci sysbus QOM types and methods so that sysbus is in their name. This is in preparation for adding PCI versions of these types and methods. Signed-off-by: Kevin O'Connor --- hw/sd/sdhci.c | 39 --- hw/sd/sdhci.h | 6 +++--- 2 files change

[Qemu-devel] [PATCHv2 5/5] sdhci: Set a default frequency clock

The Linux SDHCI PCI driver will only register the device if there is a clock frequency set. So, set a default frequency of 52Mhz. Signed-off-by: Kevin O'Connor --- hw/sd/sdhci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index c4

[Qemu-devel] [PATCHv3 0/5] Add support for SDHCI PCI devices

r the SD code in the MAINTAINERS file - let me know if I'm missing anyone on the CC list. Changes since V2: - Some additional compile warnings fixed when debugging is enabled Changes since V1: - Use RedHat PCI IDs instead of inventing new "qemu" IDs - Fix compile warnings when d

[Qemu-devel] [PATCHv3 3/5] sdhci: Define SDHCI PCI ids

Signed-off-by: Kevin O'Connor --- docs/specs/pci-ids.txt | 2 ++ include/hw/pci/pci.h | 1 + include/hw/pci/pci_ids.h | 1 + 3 files changed, 4 insertions(+) diff --git a/docs/specs/pci-ids.txt b/docs/specs/pci-ids.txt index 3c65e1a..9b57d5e 100644 --- a/docs/specs/pci-ids.txt +++ b

[Qemu-devel] [PATCHv3 1/5] sdhci: Remove class "virtual" methods

sdhci code to support PCI devices (which have a different parent class). Signed-off-by: Kevin O'Connor --- hw/sd/sdhci.c | 122 +++--- hw/sd/sdhci.h | 24 2 files changed, 40 insertions(+), 106 deletions(-) diff --git a/hw/sd/

[Qemu-devel] [PATCHv3 2/5] sdhci: Add "sysbus" to sdhci QOM types and methods

Update the sdhci sysbus QOM types and methods so that sysbus is in their name. This is in preparation for adding PCI versions of these types and methods. Signed-off-by: Kevin O'Connor --- hw/sd/sdhci.c | 39 --- hw/sd/sdhci.h | 6 +++--- 2 files change

[Qemu-devel] [PATCHv3 4/5] sdhci: Support SDHCI devices on PCI

Support for PCI devices following the "SD Host Controller Simplified Specification Version 2.00" spec. Signed-off-by: Kevin O'Connor --- default-configs/pci.mak | 2 ++ hw/sd/sdhci.c | 44 hw/sd/sdhci.h | 9 +++

[Qemu-devel] [PATCHv3 5/5] sdhci: Set a default frequency clock

The Linux SDHCI PCI driver will only register the device if there is a clock frequency set. So, set a default frequency of 52Mhz. Signed-off-by: Kevin O'Connor --- hw/sd/sdhci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index d2

Re: [Qemu-devel] about [SeaBIOS PATCH] Try to hard-reboot on rerun of post even on emulators.

On Tue, Apr 21, 2015 at 07:31:36AM +0800, Amos Kong wrote: > Hi Kevin, > > When I use old seabios in some stable linux release, some bootable > devices (2 ide disks) would be lost when I try to restart guest by > Ctrl+Alt+Delete during boot stage. > > Releated Red Hat BZ: https://bugzilla.redhat.

Re: [Qemu-devel] about [SeaBIOS PATCH] Try to hard-reboot on rerun of post even on emulators.

On Tue, Apr 21, 2015 at 10:37:49AM +0200, Laszlo Ersek wrote: > As to how you can fix > (which is the > motivation for this entire discussion): > > - You need to identify *what variable exactly* stores the list of > bootable devices. Is that

Re: [Qemu-devel] Announcing qboot, a minimal x86 firmware for QEMU

On Thu, May 21, 2015 at 03:51:43PM +0200, Paolo Bonzini wrote: > Some of you may have heard about the "Clear Containers" initiative from > Intel, which couple KVM with various kernel tricks to create extremely > lightweight virtual machines. The experimental Clear Containers setup > requires only

Re: [Qemu-devel] Announcing qboot, a minimal x86 firmware for QEMU

On Fri, May 22, 2015 at 07:23:27PM -0400, Kevin O'Connor wrote: > On Thu, May 21, 2015 at 03:51:43PM +0200, Paolo Bonzini wrote: > > Some of you may have heard about the "Clear Containers" initiative from > > Intel, which couple KVM with various kernel tricks to cr

Re: [Qemu-devel] Announcing qboot, a minimal x86 firmware for QEMU

On Mon, May 25, 2015 at 09:21:49AM +0300, Vasiliy Tolstov wrote: > 2015-05-23 6:55 GMT+03:00 Kevin O'Connor : > > Out of curiosity, I ran some additional timing tests. With SeaBIOS > > fully stripped down (via Kconfig), it takes ~20ms to get to the boot > > phase on m

Re: [Qemu-devel] Announcing qboot, a minimal x86 firmware for QEMU

On Mon, May 25, 2015 at 02:52:51PM +0200, Paolo Bonzini wrote: > On 23/05/2015 01:23, Kevin O'Connor wrote: > > I'm curious if you've tried profiling SeaBIOS to see where it is > > spending unnecessary time? > > No, I really wanted to get the absolute minimu

Re: [Qemu-devel] [PATCH v4 for-2.3 13/25] hw/acpi: remove from root bus 0 the crs resources used by other busses.

On Sun, Mar 08, 2015 at 01:16:15PM +0200, Marcel Apfelbaum wrote: > If multiple root busses are used, root bus 0 cannot use all the > pci holes ranges. Remove the IO/mem ranges used by the other > primary busses. [...] > -aml_append(crs, > -aml_word_io(aml_min_fixed, aml_max_fixed, > -

Re: [Qemu-devel] [PATCH v4 for-2.3 13/25] hw/acpi: remove from root bus 0 the crs resources used by other busses.

On Sun, Mar 08, 2015 at 07:51:42PM +0200, Marcel Apfelbaum wrote: > On 03/08/2015 06:13 PM, Kevin O'Connor wrote: > >If I read this correctly, it looks like a machine with two root buses > >and 20 devices, each with one memory range and one io range, would end > >up wit

Re: [Qemu-devel] [PATCH v4 for-2.3 13/25] hw/acpi: remove from root bus 0 the crs resources used by other busses.

On Sun, Mar 08, 2015 at 07:34:34PM +0100, Michael S. Tsirkin wrote: > On Sun, Mar 08, 2015 at 12:13:40PM -0400, Kevin O'Connor wrote: > > If I read this correctly, it looks like a machine with two root buses > > and 20 devices, each with one memory range and one io range, woul

Re: [Qemu-devel] E5-2620v2 - emulation stop error

gt; > 21f5826a04d38e19488f917e1eef22751490c769 is the first bad commit > > > > I can reproduce this on E5-2620 v2 with David's "while true" test. > > (The emulation failure I mean, not the suberror 2 that Andrey is seeing) > > The commit that seems

Re: [Qemu-devel] E5-2620v2 - emulation stop error

On Wed, Mar 11, 2015 at 03:53:07PM +, Dr. David Alan Gilbert wrote: > * Kevin O'Connor (ke...@koconnor.net) wrote: > > On Wed, Mar 11, 2015 at 01:45:57PM +, Dr. David Alan Gilbert wrote: > > > * Bandan Das (b...@redhat.com) wrote: > > > > "Dr. Davi

Re: [Qemu-devel] E5-2620v2 - emulation stop error

On Wed, Mar 11, 2015 at 01:09:42PM -0400, Bandan Das wrote: > "Kevin O'Connor" writes: > ... > > > > Something is very odd here. When I run the above command (on an older > > AMD machine) I get: > > > > Found 128 cpu(s) max supported 128 cpu(s)

Re: [Qemu-devel] E5-2620v2 - emulation stop error

On Wed, Mar 11, 2015 at 04:52:03PM +, Dr. David Alan Gilbert wrote: > * Kevin O'Connor (ke...@koconnor.net) wrote: > > So, I couldn't get this to fail on my older AMD machine at all with > > the default SeaBIOS code. But, when I change the code with the patch > &

Re: [Qemu-devel] seabios stable release

On Wed, Mar 11, 2015 at 02:48:18PM +0100, Gerd Hoffmann wrote: > Hi, > > Looks like we need a stable release branch for 1.8 and roll out a 1.8.1 > release with some fixes for qemu. > > Issue #1: support for multiple pci roots. > > Issue #2: There is a (not-yet fixed) emulation failure with new

Re: [Qemu-devel] E5-2620v2 - emulation stop error

On Wed, Mar 11, 2015 at 05:59:04PM +, Dr. David Alan Gilbert wrote: > * Kevin O'Connor (ke...@koconnor.net) wrote: > > On Wed, Mar 11, 2015 at 04:52:03PM +, Dr. David Alan Gilbert wrote: > > > * Kevin O'Connor (ke...@koconnor.net) wrote: > > > > So,

Re: [Qemu-devel] E5-2620v2 - emulation stop error

On Wed, Mar 11, 2015 at 02:40:39PM -0400, Kevin O'Connor wrote: > For what it's worth, I can't seem to trigger the problem if I move the > cmos read above the SIPI/LAPIC code (see patch below). Ugh! That's a seabios bug. Main processor modifies the rtc index (rtc_read

Re: [Qemu-devel] E5-2620v2 - emulation stop error

On Wed, Mar 11, 2015 at 02:45:31PM -0400, Kevin O'Connor wrote: > On Wed, Mar 11, 2015 at 02:40:39PM -0400, Kevin O'Connor wrote: > > For what it's worth, I can't seem to trigger the problem if I move the > > cmos read above the SIPI/LAPIC code (see patch belo

Re: [Qemu-devel] [PATCH] SeaBios/vTPM: Enable Xen stubdom vTPM for HVM virtual machine

On Tue, Mar 10, 2015 at 08:16:03AM -0400, Quan Xu wrote: > This patch series are only the SeaBios part to enable stubdom vTPM for HVM > virtual machine. It will work with Qemu patch series and Xen patch series. > > > *INTRODUCTION* > > The goal

[Qemu-devel] [ANNOUNCE] SeaBIOS 1.7.5

The 1.7.5 version of SeaBIOS has now been released. For more information on the release, please see: http://seabios.org/Releases New in this release: * Support for obtaining SMBIOS tables directly from QEMU. * XHCI USB controller fixes for real hardware (now tested on several boards) * SeaVGAB

Re: [Qemu-devel] [PATCH v4 0/7] fw_cfg DMA interface

On Thu, Oct 01, 2015 at 02:16:52PM +0200, Marc Marí wrote: > Implement host-side of the FW CFG DMA interface both for x86 and ARM. Thanks for working on this. The QEMU patches look good to me. -Kevin

Re: [Qemu-devel] [PATCH v4 6/7] Make the kernel image in the fw_cfg DMA interface bootable

On Thu, Oct 01, 2015 at 05:25:11PM +0200, Laszlo Ersek wrote: > On 10/01/15 14:16, Marc Marí wrote: > > Add an entry to the bootorder file with name "vmlinux". > > Give this entry more priority than the romfile. > > > > Signed-off-by: Marc Marí > > --- > > hw/i386/pc.c | 4 +++- > > 1 file chang

Re: [Qemu-devel] [PATCH v4 7/7] fw_cfg: Define a static signature to be returned on DMA port reads

On Thu, Oct 01, 2015 at 06:07:06PM +0200, Laszlo Ersek wrote: > On 10/01/15 14:16, Marc Marí wrote: > > From: Kevin O'Connor > > > > Return a static signature ("QEMU CFG") if the guest does a read to the > > DMA address io register. > > > >

Re: [Qemu-devel] [PATCH v4 6/7] Make the kernel image in the fw_cfg DMA interface bootable

On Fri, Oct 02, 2015 at 10:09:17AM +0200, Gerd Hoffmann wrote: > > - read four bytes from under the fw_cfg selector QEMU_CFG_KERNEL_SIZE > > (0x0008), > > - if it is zero,return -1 --> no kernel boot requested, > > - if it is nonzero, return 0 --> which means "top priority". > > > > In othe

Re: [Qemu-devel] [PATCH v4 6/7] Make the kernel image in the fw_cfg DMA interface bootable

On Fri, Oct 02, 2015 at 10:16:26AM +0200, Gerd Hoffmann wrote: > Hi, > > > That's fine with me. Marc - I think qemu_vmlinux_setup() in SeaBIOS > > with the following would work: > > > > void qemu_vmlinux_setup(void) > > { > > u32 kernel_size; > > qemu_cfg_read_entry(&kernel_size, QEMU_

Re: [Qemu-devel] [PATCH 1/2] target-i386: Use 1UL for bit shift

On Fri, Oct 02, 2015 at 02:07:32PM +0200, Paolo Bonzini wrote: > On 02/10/2015 13:14, Laszlo Ersek wrote: > > On 10/02/15 10:34, Paolo Bonzini wrote: > >> On 01/10/2015 21:17, Laszlo Ersek wrote: > >>> - In the firmware, allocate an array of bytes, dynamically. This array > >>> will have no decla

[Qemu-devel] [PATCHv2] fw_cfg: Define a static signature to be returned on DMA port reads

Return a static signature ("QEMU CFG") if the guest does a read to the DMA address io register. Signed-off-by: Kevin O'Connor --- Marc, if you decide to respin your fw_cfg series, I've updated the dma signature patch. This addresses the comments from Stefan, and I h

Re: [Qemu-devel] [PATCHv2] fw_cfg: Define a static signature to be returned on DMA port reads

On Tue, Oct 06, 2015 at 09:30:18AM +0200, Laszlo Ersek wrote: > On 10/06/15 01:51, Kevin O'Connor wrote: > > Return a static signature ("QEMU CFG") if the guest does a read to the > > DMA address io register. > > > > Signed-off-by: Kevin O'Connor

Re: [Qemu-devel] [PATCH] SeaBios: Fix reset procedure reentrancy problem on qemu-kvm platform

On Wed, Nov 04, 2015 at 08:48:20AM +0800, Gonglei wrote: > On 2015/11/3 14:58, Xulei (Stone, Euler) wrote: > > On qemu-kvm platform, when I reset a VM through "virsh reset", and > > coincidently > > the VM is in process of internal rebooting at the same time. Then the VM > > will > > not be succe

Re: [Qemu-devel] [PATCH] SeaBios: Fix reset procedure reentrancy problem on qemu-kvm platform

On Fri, Nov 06, 2015 at 09:12:34AM +, Xulei (Stone) wrote: > > >On Wed, Nov 04, 2015 at 08:48:20AM +0800, Gonglei wrote: > >> On 2015/11/3 14:58, Xulei (Stone, Euler) wrote: > >> > On qemu-kvm platform, when I reset a VM through "virsh reset", and > >> > coincidently > >> > the VM is in proce

Re: [Qemu-devel] [PATCH] SeaBios: Fix reset procedure reentrancy problem on qemu-kvm platform

On Mon, Nov 09, 2015 at 08:32:53AM -0500, Kevin O'Connor wrote: > On Fri, Nov 06, 2015 at 09:12:34AM +, Xulei (Stone) wrote: > > >On Wed, Nov 04, 2015 at 08:48:20AM +0800, Gonglei wrote: > > >I'm surprised you would see the above on a recent qemu/kvm though - as

Re: [Qemu-devel] [PATCH] SeaBios: Fix reset procedure reentrancy problem on qemu-kvm platform

On Mon, Nov 09, 2015 at 03:06:18PM -0500, Kevin O'Connor wrote: > On Mon, Nov 09, 2015 at 08:32:53AM -0500, Kevin O'Connor wrote: > > On Fri, Nov 06, 2015 at 09:12:34AM +, Xulei (Stone) wrote: > > > >On Wed, Nov 04, 2015 at 08:48:20AM +0800, Gonglei wrote: >

Re: [Qemu-devel] [PATCH v3] Add optionrom compatible with fw_cfg DMA version

On Wed, Jan 27, 2016 at 05:57:28PM +0100, Marc Marí wrote: > On Wed, 27 Jan 2016 16:43:29 + > Stefan Hajnoczi wrote: > > > On Tue, Jan 26, 2016 at 12:26:12PM +0100, Gerd Hoffmann wrote: > > > On Di, 2016-01-26 at 12:20 +0100, Marc Marí wrote: > > > > On Tue, 26 Jan 2016 11:11:54 + > > >

Re: [Qemu-devel] [PATCH v3] Add optionrom compatible with fw_cfg DMA version

On Mon, Jan 25, 2016 at 02:17:48PM +0100, Marc Marí wrote: > This optionrom is based on linuxboot.S. Hi Marc, Out of curiousity, how does the timing with this option rom compare to the previous SeaBIOS patches that implemented linux dma loading? When I first tried to compile this (on fc23), I g

Re: [Qemu-devel] [PATCH v3] Add optionrom compatible with fw_cfg DMA version

On Thu, Jan 28, 2016 at 12:20:33PM +0100, Marc Marí wrote: > A small cosmetic comment in this patch: is there any practical reason to > mix the three ways to put inline assembly (asm(), asm volatile() and > __asm__ __volatile__ ()) in this patch? No reason - it was just copy-and-paste crud. > >

Re: [Qemu-devel] [iGVT-g] [vfio-users] [PATCH v3 00/11] igd passthrough chipset tweaks

On Tue, Feb 02, 2016 at 09:56:20AM +0100, Gerd Hoffmann wrote: > Hi, > > > > I'd have qemu copy the data on 0xfc write then, so things continue to > > > work without updating seabios. So, the firmware has to allocate space, > > > reserve it etc., and programming the 0xfc register. Qemu has to

Re: [Qemu-devel] [SeaBIOS] [RFC PATCH v2] fw/pci: Add support for mapping Intel IGD OpRegion via QEMU

On Wed, Feb 03, 2016 at 02:38:47PM -0700, Alex Williamson wrote: > On Wed, 2016-02-03 at 12:43 -0700, Alex Williamson wrote: > > On Wed, 2016-02-03 at 10:04 +0100, Gerd Hoffmann wrote: > > >   Hi, > > >   > > > > +static void intel_igd_opregion_setup(struct pci_device *dev, void *arg) > > > > +{ >

Re: [Qemu-devel] [SeaBIOS] [RFC PATCH v2] fw/pci: Add support for mapping Intel IGD OpRegion via QEMU

On Thu, Feb 04, 2016 at 08:52:44AM +0100, Gerd Hoffmann wrote: > Hi, > > > the same or just use it on the first one we encounter. We're probably > > putting way too much thought into this scenario that Intel likely has no > > expectation of supporting though ;) Thanks, > > Yea, lets stick wit

[Qemu-devel] [ANNOUNCE] SeaBIOS 1.9.0

lease see: http://seabios.org/Download = git shortlog -n rel-1.8.0..rel-1.9.0 = Kevin O'Connor (126): docs: add page for SeaVGABIOS docs: Add page describing the patch contribution process docs: Add page on available CBFS/fw_cfg runtime config files docs:

Re: [Qemu-devel] [PATCH] SeaBios: Fix reset procedure reentrancy problem on qemu-kvm platform

On Thu, Nov 19, 2015 at 12:42:50PM +, Xulei (Stone) wrote: > Kevin, > > After deeply analyzing, i think there may be 3 possible reasons: > 1)wrong CountCPUs value. It seems CountCPUs++ in handle_smp() has no > lock to protect. So, sometimes, 2 or more vcpu may get the same > current value of

Re: [Qemu-devel] [PATCH v2 00/10] hw/sd: QOMify sd.c (and pxa2xx_mmci)

On Fri, Jan 22, 2016 at 04:16:32PM +, Peter Maydell wrote: > This series attempts to QOMify sd.c (the actual SD card model), > including a proper QOM bus between the controller and the card. > > This series removes the experimental x-drive property on sdhci-pci; > the syntax for using that dev

Re: [Qemu-devel] [RFC PATCH v3 3/3] fw/pci: Allocate IGD stolen memory

On Fri, Feb 12, 2016 at 05:23:18PM -0700, Alex Williamson wrote: > Intel IGD makes use of memory allocated and marked reserved by the > BIOS as a stolen memory range. For the most part, guest drivers don't > make use of this, but our achilles heel is the vBIOS. The vBIOS > programs the device to

Re: [Qemu-devel] [PULL 48/49] i386: populate floppy drive information in DSDT

On Tue, Feb 09, 2016 at 07:36:12PM +0100, Laszlo Ersek wrote: > On 02/09/16 17:22, John Snow wrote: > > On 02/09/2016 10:52 AM, Roman Kagan wrote: > >> On Mon, Feb 08, 2016 at 03:20:47PM -0500, John Snow wrote: > >>> On 02/08/2016 08:14 AM, Roman Kagan wrote: > On Fri, Feb 05, 2016 at 07:25:07

Re: [Qemu-devel] [RFC PATCH v3 3/3] fw/pci: Allocate IGD stolen memory

On Sat, Feb 13, 2016 at 08:12:09AM -0700, Alex Williamson wrote: > On Fri, 12 Feb 2016 21:49:04 -0500 > "Kevin O'Connor" wrote: > > On Fri, Feb 12, 2016 at 05:23:18PM -0700, Alex Williamson wrote: > > > Intel IGD makes use of memory allocated and marked re

Re: [Qemu-devel] [RFC PATCH v3 3/3] fw/pci: Allocate IGD stolen memory

On Sat, Feb 13, 2016 at 11:51:51AM -0700, Alex Williamson wrote: > On Sat, 13 Feb 2016 13:18:39 -0500 > "Kevin O'Connor" wrote: > > On Sat, Feb 13, 2016 at 08:12:09AM -0700, Alex Williamson wrote: > > > On Fri, 12 Feb 2016 21:49:04 -0500 > > > &quo

Re: [Qemu-devel] [RFC PATCH v3 3/3] fw/pci: Allocate IGD stolen memory

On Sat, Feb 13, 2016 at 01:57:09PM -0700, Alex Williamson wrote: > On Sat, 13 Feb 2016 15:05:09 -0500 > "Kevin O'Connor" wrote: > > On Sat, Feb 13, 2016 at 11:51:51AM -0700, Alex Williamson wrote: > > > On Sat, 13 Feb 2016 13:18:39 -0500 > > > &quo

Re: [Qemu-devel] [RFC PATCH v3 3/3] fw/pci: Allocate IGD stolen memory

On Sat, Feb 13, 2016 at 06:03:31PM -0700, Alex Williamson wrote: > On Sat, 13 Feb 2016 19:20:32 -0500 > "Kevin O'Connor" wrote: > > This confuses me - why didn't the host system BIOS turn on the LCD > > panel during host bootup? > > It turns off when

Re: [Qemu-devel] [RFC PATCH v3 3/3] fw/pci: Allocate IGD stolen memory

On Mon, Feb 15, 2016 at 09:29:26PM +0200, Michael S. Tsirkin wrote: > I can build a generic interface to pass addresses > allocated by bios back to QEMU. It looks like this would > be useful for other purposes as well. Interested? If this is undertaken, I suggest extending fw_cfg to support "writ

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