From: Kuo-Jung Su dant...@faraday-tech.com
These patches introduce Faraday A36x SoC platform support.
Faraday provides ARMv4/ARMv5TE compatible solutions,
and focus on ASIC design service.
Here are some public documents for your reference.
http://www.faraday-tech.com/html/documentation
From: Kuo-Jung Su dant...@faraday-tech.com
The Faraday A369 EVB is a Faraday SoC platform evalution board used for
Faraday IP functional verification based on the well-known ARM AMBA 2.0
architecture.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
---
hw/arm/Makefile.objs |1
From: Kuo-Jung Su dant...@faraday-tech.com
The FTWDT010 is used to prevent system from infinite loop
while software gets trapped in the deadlock.
Under the normal operation, users should restart FTWDT010
at the regular intervals before counter counts down to 0.
If the counter does reach 0
From: Kuo-Jung Su dant...@faraday-tech.com
The FTNANDC021 is an integrated NAND flash controller which
re-pack the NAND flash command set with a shorter built-in opcode.
It also provides a register base interface for user to easily
access the underlying NAND flash chips, and also supports HW ECC
From: Kuo-Jung Su dant...@faraday-tech.com
The Faraday A360 EVB is a Faraday SoC platform evaluation board used for
Faraday IP functional verification based on the well-known ARM AMBA 2.0
architecture.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
---
hw/arm/Makefile.objs |1
From: Kuo-Jung Su dant...@faraday-tech.com
The FTSSP010 is a multi-function synchronous serial port interface
controller which supports SSP, SPI, I2S, AC97 and SPDIF.
However only I2S and SPI protocol have been implemented in this patch.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
From: Kuo-Jung Su dant...@faraday-tech.com
The FTINTC020 interrupt controller supports both FIQ and IRQ signals
to the microprocessor.
It can handle up to 64 configurable IRQ sources and 64 FIQ sources.
The output signals to the microprocessor can be configured as
level-high/low active or edge
From: Kuo-Jung Su dant...@faraday-tech.com
The FTLCDC200 Color LCD controller performs translation of
pixel-coded data into the required formats and timings to
drive a variety of single/dual mono and color LCDs.
Depending on the LCD type and mode, the unpacked data can represent:
1. an actual
From: Kuo-Jung Su dant...@faraday-tech.com
The FTGMAC100 Ethernet controller has a DMA engine which handles
all data transfers between the system memory and on-chip memories.
Its DMA engine supports both 16-bits and 32-bits alignment,
and thus make it possible to support zero-copy transfer
From: Kuo-Jung Su dant...@faraday-tech.com
It provides separate second, minute, hour, and day counters. The second
counter is toggled each second, the minute counter is toggled each minute,
the hour counter is toggled each hour, and the day counter is toggled each day.
The FTRTC011 provides
From: Kuo-Jung Su dant...@faraday-tech.com
The FTTSC010 provides two operation modes to sample
the analog input voltage.
1. The manual operation mode needs to program
and control the panel drivers by software
step-by-step for the x-y position measurement.
2. The auto-scan mode
From: Kuo-Jung Su dant...@faraday-tech.com
The FTI2C010 is an I2C master controller.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
---
hw/arm/Makefile.objs |1 +
hw/arm/faraday_a360.c |6 ++
hw/arm/faraday_a369.c |6 ++
hw/arm/fti2c010.c | 206
From: Kuo-Jung Su dant...@faraday-tech.com
It's used to perform AHB remap and also QEMU RAM initialization
when SDRAM is initialized before AHB remap process activated.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
---
hw/arm/Makefile.objs |1 +
hw/arm/faraday_a369.c |6 ++
hw
From: Kuo-Jung Su dant...@faraday-tech.com
The FTDDRII030 is a DDRII SDRAM controller which is responsible for
SDRAM initialization.
In QEMU we simply emualte the SDRAM enable function, neither timing parameter
nor bank setup is handled.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
From: Kuo-Jung Su dant...@faraday-tech.com
The FTAPBBRG020 supports the DMA functions for the AHB-to-AHB,
AHB-to-APB, APB-to-AHB, and APB-to-APB transactions.
The DMA engine can support up to 4 DMA channels (A, B, C, and D)
and 15 handshaking channels. A DMA channel granted by the arbiter
block
From: Kuo-Jung Su dant...@faraday-tech.com
The FTTMR010 provides three independent sets of sub-timers.
Two match registers are provided for each sub-timer, whenever
the value of the match registers equals any one value of the
sub-timers, the timer interrupt will be immediately triggered
From: Kuo-Jung Su dant...@faraday-tech.com
The FTMAC110 is an Ethernet controller that provides AHB master capability
and is in full compliance with the IEEE 802.3 10/100 Mbps specifications.
Its DMA controller handles all data transfers between system memory
and on-chip memories.
It supports
From: Kuo-Jung Su dant...@faraday-tech.com
The FTPWMTMR010 is an APB device which provides up to 8 independent timers.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
---
hw/arm/Makefile.objs |1 +
hw/arm/faraday_a369.c | 11 +++
hw/arm/ftpwmtmr010.c | 246
From: Kuo-Jung Su dant...@faraday-tech.com
The Faraday FTDMAC020 provides eight configurable
channels for the memory-to-memory, memory-to-peripheral,
peripheral-to-peripheral, and peripheral-to-memory transfers.
Each DMA channel supports chain transfer and can be programmed
to one of the 16
From: Kuo-Jung Su dant...@faraday-tech.com
The FTSDC010 is a clone of Arm PrimeCell PL181.
While they share lots of design concept, the implementation
differ slightly.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
---
hw/arm/Makefile.objs |1 +
hw/arm/faraday_a360.c |7 +
hw/arm
From: Kuo-Jung Su dant...@faraday-tech.com
The FTSPI020 is an integrated SPI Flash controller
which supports upto 4 flash chips.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
---
hw/arm/Makefile.objs |1 +
hw/arm/faraday_a369.c | 12 ++
hw/arm/ftspi020.c | 345
\
2013/2/7 Peter Crosthwaite peter.crosthwa...@xilinx.com:
Hi Kuo-Jung,
On Wed, Feb 6, 2013 at 7:45 PM, Kuo-Jung Su dant...@gmail.com wrote:
From: Kuo-Jung Su dant...@faraday-tech.com
The FTSPI020 is an integrated SPI Flash controller
which supports upto 4 flash chips.
Signed-off-by: Kuo
2013/2/9 Blue Swirl blauwir...@gmail.com:
On Wed, Feb 6, 2013 at 9:45 AM, Kuo-Jung Su dant...@gmail.com wrote:
From: Kuo-Jung Su dant...@faraday-tech.com
The FTMAC110 is an Ethernet controller that provides AHB master capability
and is in full compliance with the IEEE 802.3 10/100 Mbps
2013/2/8 Igor Mitsyanko i.mitsya...@gmail.com
On 02/06/2013 01:45 PM, Kuo-Jung Su wrote:
From: Kuo-Jung Su dant...@faraday-tech.com
The Faraday A369 EVB is a Faraday SoC platform evalution board used for
Faraday IP functional verification based on the well-known ARM AMBA 2.0
architecture
2013/2/7 Peter Crosthwaite peter.crosthwa...@xilinx.com:
On Thu, Feb 7, 2013 at 4:59 PM, Kuo-Jung Su dant...@gmail.com wrote:
\
2013/2/7 Peter Crosthwaite peter.crosthwa...@xilinx.com:
Hi Kuo-Jung,
On Wed, Feb 6, 2013 at 7:45 PM, Kuo-Jung Su dant...@gmail.com wrote:
From: Kuo-Jung Su dant
2013/2/17 Peter Crosthwaite peter.crosthwa...@xilinx.com:
On Wed, Feb 6, 2013 at 7:45 PM, Kuo-Jung Su dant...@gmail.com wrote:
From: Kuo-Jung Su dant...@faraday-tech.com
The FTMAC110 is an Ethernet controller that provides AHB master capability
and is in full compliance with the IEEE 802.3 10
2013/2/17 Peter Crosthwaite peter.crosthwa...@xilinx.com:
Hi Dante,
On Wed, Feb 6, 2013 at 7:45 PM, Kuo-Jung Su dant...@gmail.com wrote:
From: Kuo-Jung Su dant...@faraday-tech.com
It's used to perform AHB remap and also QEMU RAM initialization
when SDRAM is initialized before AHB remap
.
* Replace vendor init callback with derived instance_init.
* Introduced enum for vendor registers.
* Replace magic number 0x34 with formula, so that it doesn't deviate.
From my Tegra2 FYI patch:
* None.
Cc: Gerd Hoffmann kra...@redhat.com
Cc: Kuo-Jung Su dant...@faraday-tech.com
Cc: Peter
2013/2/18 Andreas Färber afaer...@suse.de:
Am 06.02.2013 10:45, schrieb Kuo-Jung Su:
+typedef struct FaradayMachState {
+ARMCPU *cpu;
+DeviceState *scu;
+DeviceState *ahbc;
+DeviceState *ddrc;
+DeviceState *hdma[2]; /* AHB DMA */
+DeviceState *pdma[2
2013/2/8 Igor Mitsyanko i.mitsya...@gmail.com:
On 02/06/2013 01:45 PM, Kuo-Jung Su wrote:
From: Kuo-Jung Sudant...@faraday-tech.com
The Faraday A360 EVB is a Faraday SoC platform evaluation board used for
Faraday IP functional verification based on the well-known ARM AMBA 2.0
architecture
2013/2/8 Igor Mitsyanko i.mitsya...@gmail.com:
On 02/06/2013 01:45 PM, Kuo-Jung Su wrote:
From: Kuo-Jung Su dant...@faraday-tech.com
The FTDDRII030 is a DDRII SDRAM controller which is responsible for
SDRAM initialization.
In QEMU we simply emualte the SDRAM enable function, neither timing
2013/2/18 Stefan Hajnoczi stefa...@gmail.com:
On Wed, Feb 06, 2013 at 05:45:19PM +0800, Kuo-Jung Su wrote:
From: Kuo-Jung Su dant...@faraday-tech.com
The FTMAC110 is an Ethernet controller that provides AHB master capability
and is in full compliance with the IEEE 802.3 10/100 Mbps
2013/2/18 Andreas Färber afaer...@suse.de:
Am 07.02.2013 18:26, schrieb Igor Mitsyanko:
On 02/06/2013 01:45 PM, Kuo-Jung Su wrote:
+static void ftddrii030_reset(DeviceState *ds)
+{
+SysBusDevice *busdev = SYS_BUS_DEVICE(ds);
+Ftddrii030State *s = FTDDRII030(FROM_SYSBUS
2013/2/18 Andreas Färber afaer...@suse.de:
Am 18.02.2013 10:31, schrieb Kuo-Jung Su:
2013/2/8 Igor Mitsyanko i.mitsya...@gmail.com:
On 02/06/2013 01:45 PM, Kuo-Jung Su wrote:
+static void ftddrii030_reset(DeviceState *ds)
+{
+SysBusDevice *busdev = SYS_BUS_DEVICE(ds
2013/2/18 Stefan Hajnoczi stefa...@gmail.com:
On Mon, Feb 18, 2013 at 05:44:38PM +0800, Kuo-Jung Su wrote:
2013/2/18 Stefan Hajnoczi stefa...@gmail.com:
On Wed, Feb 06, 2013 at 05:45:19PM +0800, Kuo-Jung Su wrote:
From: Kuo-Jung Su dant...@faraday-tech.com
The FTMAC110 is an Ethernet
2013/2/19 Kuo-Jung Su dant...@gmail.com:
2013/2/18 Stefan Hajnoczi stefa...@gmail.com:
On Mon, Feb 18, 2013 at 05:44:38PM +0800, Kuo-Jung Su wrote:
2013/2/18 Stefan Hajnoczi stefa...@gmail.com:
On Wed, Feb 06, 2013 at 05:45:19PM +0800, Kuo-Jung Su wrote:
From: Kuo-Jung Su dant...@faraday
2013/2/8 Peter Crosthwaite peter.crosthwa...@xilinx.com:
On Thu, Feb 7, 2013 at 10:13 PM, Andreas Färber afaer...@suse.de wrote:
Am 07.02.2013 13:04, schrieb Peter Maydell:
On 7 February 2013 11:50, Andreas Färber afaer...@suse.de wrote:
Am 07.02.2013 07:59, schrieb Kuo-Jung Su
2013/2/19 Stefan Hajnoczi stefa...@gmail.com:
On Tue, Feb 19, 2013 at 09:43:27AM +0800, Kuo-Jung Su wrote:
2013/2/19 Kuo-Jung Su dant...@gmail.com:
2013/2/18 Stefan Hajnoczi stefa...@gmail.com:
On Mon, Feb 18, 2013 at 05:44:38PM +0800, Kuo-Jung Su wrote:
2013/2/18 Stefan Hajnoczi stefa
From: Kuo-Jung Su dant...@faraday-tech.com
Faraday processors are a series of ARMv4/ARMv5TE clone.
* ARMv4 series (FA526, FA626).
All of them are now out-of-date, so I have no plan for them.
* ARMv5TE series (FA606TE, FA626TE, FA616TE, FA726TE)
All the single core RISC listed above
From: Kuo-Jung Su dant...@faraday-tech.com
The status register coding for BUSY/READY(BIT6)
is actually [Busy:0, Ready:1].
BTW, this patch not only apply the bug fix to status bit,
but also update the Busy/Ready status upon nand flash read/write/erase.
Signed-off-by: Kuo-Jung Su dant...@faraday
From: Kuo-Jung Su dant...@faraday-tech.com
The s-addr should be reset along with the s-addrlen,
or it might contains the previous address at last address cycle,
and causes problem to nand erase operation.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
Cc: bal...@zabor.org
---
Changes
From: Kuo-Jung Su dant...@faraday-tech.com
Wolfson WM8731 is a simple audio codec for embedded systems.
It has 2 input and 1 output ports:
** Input **
1. Linue-In
2. Microphone
** Output **
1. Headphone out
BTW it's based on hw/wm8750.c with 16bit I2S support by default.
Signed
From: Kuo-Jung Su dant...@faraday-tech.com
The FTMAC110 is a high quality 10/100 Ethernet controller with DMA function.
It includes an AHB wrapper, DMA engine, on-chip memories (TX FIFO and RX
FIFO), MAC, and MII or RMII interface.
The FTMAC110 is an Ethernet controller that provides AHB master
From: Kuo-Jung Su dant...@faraday-tech.com
The Faraday FTDMAC020 is designed to enhance the system performance
and reduce the processor-interrupt generation. The system efficiency
is improved by employing the high-speed data transfers between the
system and device. The DMA controller provides
From: Kuo-Jung Su dant...@faraday-tech.com
The Faraday A360/A369 EVB is a Faraday platform main board used for the
Faraday IP functional verification based on the well-known ARM AMBA 2.0
architecture. This main board provides a fully verified microprocessor
platform, ATA-II, OTG 2.0 and USB 2.0
From: Kuo-Jung Su dant...@faraday-tech.com
The FTAPBBRG020 supports the DMA functions for the AHB-to-AHB,
AHB-to-APB, APB-to-AHB, and APB-to-APB transactions.
The DMA engine can support up to 4 DMA channels (A, B, C, and D)
and 15 handshaking channels. A DMA channel granted by the arbiter
block
From: Kuo-Jung Su dant...@faraday-tech.com
The FTWDT010 is used to prevent system from infinite loop
while software gets trapped in the deadlock.
Under the normal operation, users should restart FTWDT010
at the regular intervals before counter counts down to 0.
If the counter does reach 0
From: Kuo-Jung Su dant...@faraday-tech.com
The FTSDC010 functions as the master in an SD memory card interface.
It controls the communication between the AHB/APB bus and the SD card.
Its core supports the SD bus of the SD/SDIO operations and the MMC bus
of the MMC operation as well.
Signed-off
From: Kuo-Jung Su dant...@faraday-tech.com
Faraday keyboard/mouse controller (FTKBC010) is compliant with the
IBM PS/2 interface. The interface uses the bidirectional clock and
data lines to perform the half-duplex synchronous serial interface.
It also provides the configurable scan matrix
From: Kuo-Jung Su dant...@faraday-tech.com
The FTI2C010 allows the host processor to serve as a master or slave
in the I2C bus. Data are transmitted to and received from the I2C bus
via a buffered interface.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
---
hw/fti2c010.c | 205
From: Kuo-Jung Su dant...@faraday-tech.com
The FTNANDC021 NAND flash host controller allows the users to access
the NAND flash memory simply by reading or writing into the registers.
It provides the hardware-based NAND host controller so that data can
be transferred in the high speed mode
From: Kuo-Jung Su dant...@faraday-tech.com
The FTLCDC200 is an LCD controller that is compliant with the AMBA 2.0.
It is a reusable soft-IP block and provides all the necessary control
signals for a variety of TFT/CSTN/STN LCD panels. It was designed for
portable electronics, including Personal
From: Kuo-Jung Su dant...@faraday-tech.com
The FTSSP010 is a synchronous serial port interface that allows
the host processor to serve as a master or a slave. Various devices
can be connected to this controller by using the serial protocol.
It supports the TI Synchronous Serial Port (SSP
From: Kuo-Jung Su dant...@faraday-tech.com
The FTINTC020 interrupt controller supports both FIQ and IRQ signals
to the microprocessor.
It can handle up to 64 configurable IRQ sources and 64 FIQ sources.
The output signals to the microprocessor can be configured as
level-high/low active or edge
From: Kuo-Jung Su dant...@faraday-tech.com
Since the NAND and SPI flash memories do not support random access,
so most of the systems which use such memory as main storages
usually has some bootstrap code stored inside the embedded ROM of
its SoC, and the bootstrap code is responsible for SDRAM
From: Kuo-Jung Su dant...@faraday-tech.com
The FTTMR010 provides three independent sets of sub-timers.
Each sub-timer can use either the internal system clock (PCLK)
or the external clock (EXTCLK) for clock counting.
Two match registers are provided for each sub-timer, whenever
the value
From: Kuo-Jung Su dant...@faraday-tech.com
The FTGMAC100 is a high-quality Ethernet controller with DMA function.
It includes the AHB wrapper, DMA engine, on-chip memories (TX FIFO
and RX FIFO), MAC, and MII/GMII interfaces.
The FTGMAC100 is an Ethernet controller that provides AHB master
From: Kuo-Jung Su dant...@faraday-tech.com
Faraday FUSBH200 is a one-port host controller for USB 2.0,
which is fully compliant with the USB 2.0 specification and
the Enhanced Host Controller Interface (EHCI) specification.
This host controller supports the HS/FS/LS transactions,
Isochronous
From: Kuo-Jung Su dant...@faraday-tech.com
The FTRTC011 is a flexible, small-area, and low-power Real Time Clock (RTC).
It accepts two clock sources: APB bus clock (PCLK) and 32.768 kHz clock.
When the system enters the sleep mode, the PCLK clock will be gated by the
system while RTC will keep
From: Kuo-Jung Su dant...@faraday-tech.com
The FTPWMTMR010 is an APB device which provides up to 8 independent timers.
Each timer can use either the internal system clock (The PCLK of APB) or
external clock.
These timers can be used to generate internal interrupts to the CPU.
They can also
From: Kuo-Jung Su dant...@faraday-tech.com
The FTTSC010 provides controlling signals to handle ADC conversion
and panel driver. The control signal is base on Faraday 12-bit ADC
IP of FXADC140HC0H_TPANEL, which is a 12-bit SAR ADC with 8-to-1
multiplexer, IPGA and panel driver. The ADC provides 8
From: Kuo-Jung Su dant...@faraday-tech.com
These patches introduce Faraday A36x SoC platform support.
Faraday provides ARMv4/ARMv5TE compatible solutions,
and focus on ASIC design service.
Here are some public documents for you reference.
http://www.faraday-tech.com/html/documentation
From: Kuo-Jung Su dant...@faraday-tech.com
The FTSPI020 is primariy designed for high-speed spi flash support.
It supports double data rate and fast-read dual/quad for spi flash.
It use one AHB slave port and one SPI interface controller to execute
the SPI Flash command. Moreover, it also
on A369.
2. The keypad buttons monitored by FTKBC010 are some hard wired buttons on
the board.
So it's not appropriate to use existing PS2 keyboard emulation here.
Best Wishes
Dante Su
2013/1/26 Paul Brook p...@codesourcery.com
From: Kuo-Jung Su dant...@faraday-tech.com
Faraday keyboard
,
which
are directly mapped. This contradicts your desciption which talks about
serial flash.
Please look at how other boards work. There are already mechanisms for
creating rom areas, or preloading images into ram.
Paul
--
Best wishes,
Kuo-Jung Su
.
My bad, I forgot this, I'll fix it later.
I suspect a log of this code anc and should be shared with your other DMA
controller, and probably several of the existing DMA controllers.
Paul
--
Best wishes,
Kuo-Jung Su
2013/1/26 Paul Brook p...@codesourcery.com
The FTAPBBRG020 supports
answer.
Paul
yes, it's my bad. I'll try to use mutex later
--
Best wishes,
Kuo-Jung Su
-datacnt -= 4;
+if (s-datacnt = 0) {
+s-status |= STR_DAT_END;
+}
This will fail if datacnt is not a multiple of 4.
Paul
my bad, datacnt shall not be unsigned.
--
Best wishes,
Kuo-Jung Su
2013/1/28 Andreas Färber afaer...@suse.de
Am 28.01.2013 07:05, schrieb Kuo-Jung Su:
Sorry,
the description was directly copied from the introduction of its
datasheet,
it appears to be ambigous in this case.
I thought so for the high quality ethernet adapter. ;) The commit
message
the WEL(0x02) in status register to make sure the protection
is correctly turned off, so this patch is mandatory to me.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
---
hw/m25p80.c | 16
1 file changed, 16 insertions(+)
diff --git a/hw/m25p80.c b/hw/m25p80.c
2013/1/25 Peter Maydell peter.mayd...@linaro.org
On 25 January 2013 07:18, Kuo-Jung Su dant...@gmail.com wrote:
From: Kuo-Jung Su dant...@faraday-tech.com
Faraday processors are a series of ARMv4/ARMv5TE clone.
* ARMv4 series (FA526, FA626).
All of them are now out-of-date, so
sure, no problem.
2013/1/28 Andreas Färber afaer...@suse.de
Am 25.01.2013 10:07, schrieb Andreas Färber:
Am 25.01.2013 09:19, schrieb Kuo-Jung Su:
hw/a360.c| 271 +++
hw/a369.c| 581
++
hw
to facilitate this a little for you:
http://patchwork.ozlabs.org/patch/215919/
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
--
Best wishes,
Kuo-Jung Su
2013/1/28 Andreas Färber afaer...@suse.de
Am 25.01.2013 09:19, schrieb Kuo-Jung Su:
From: Kuo-Jung Su dant...@faraday-tech.com
These patches introduce Faraday A36x SoC platform support.
Faraday provides ARMv4/ARMv5TE compatible solutions,
and focus on ASIC design service.
Here
From: Kuo-Jung Su dant...@faraday-tech.com
First of all, Andreas's QOM realizefn patch for hcd-ehci-sysbus
must be applied prior to this patch set.
Here is the link to Andreas's QOM realizefn patch:
http://patchwork.ozlabs.org/patch/215919/
Now return to the topic, this patch set has 2 parts
From: Kuo-Jung Su dant...@faraday-tech.com
Replace PORTSC macros with variables which could then be
configured in ehci__class_init(...)
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
Cc: Gerd Hoffmann kra...@redhat.com
Cc: Andreas afaer...@suse.de
Cc: Peter Crosthwaite peter.crosthwa
From: Kuo-Jung Su dant...@faraday-tech.com
Add Faraday FUSBH200 support, which is slightly different from EHCI spec.
(Or maybe simply a bad/wrong implementation...)
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
Cc: Gerd Hoffmann kra...@redhat.com
Cc: Andreas afaer...@suse.de
Cc: Peter
,
Gerd
--
Best wishes,
Kuo-Jung Su
2013/1/29 Andreas Färber afaer...@suse.de
Am 29.01.2013 06:43, schrieb Kuo-Jung Su:
From: Kuo-Jung Su dant...@faraday-tech.com
Add Faraday FUSBH200 support, which is slightly different from EHCI spec.
(Or maybe simply a bad/wrong implementation...)
Signed-off-by: Kuo-Jung Su dant
--
Best wishes,
Kuo-Jung Su
2013/2/1 Igor Mitsyanko i.mitsya...@samsung.com
Hi, Kuo-Jung, please see several comments bellow.
On 01/25/2013 12:19 PM, Kuo-Jung Su wrote:
From: Kuo-Jung Su dant...@faraday-tech.com
The Faraday A360/A369 EVB is a Faraday platform main board used for the
Faraday IP functional
2013/1/31 Andreas Färber afaer...@suse.de:
Am 30.01.2013 01:44, schrieb Kuo-Jung Su:
2013/1/29 Andreas Färber afaer...@suse.de mailto:afaer...@suse.de
Gerd, what are your thoughts? If Kuo-Jung doesn't mind, I would offer to
send a v2 implementing the changes I suggested in the way
2013/2/1 Kuo-Jung Su dant...@gmail.com:
2013/2/1 Igor Mitsyanko i.mitsya...@samsung.com
Hi, Kuo-Jung, please see several comments bellow.
On 01/25/2013 12:19 PM, Kuo-Jung Su wrote:
From: Kuo-Jung Su dant...@faraday-tech.com
The Faraday A360/A369 EVB is a Faraday platform main board used
)
Best Wishes
Dante
2013/2/1 Andreas Färber afaer...@suse.de:
Hi,
Am 01.02.2013 02:39, schrieb Kuo-Jung Su:
2013/2/1 Igor Mitsyanko i.mitsya...@samsung.com
On 01/25/2013 12:19 PM, Kuo-Jung Su wrote:
+/* Board init. */
+static void
+a360_device_init(a360_state *s)
+{
+qemu_irq *pic
From: Kuo-Jung Su dant...@faraday-tech.com
Wolfson WM8731 is a simple audio codec for embedded systems.
It has 2 input and 1 output ports:
** Input **
1. Linue-In
2. Microphone
** Output **
1. Headphone out
BTW it's based on hw/wm8750.c with 16bit I2S support by default.
Signed
From: Kuo-Jung Su dant...@faraday-tech.com
Atmel, SST and Intel/Numonyx serial flash tend to power up
with the software protection bits set.
And thus the new m25p80.c in linux kernel would always tries
to use WREN(0x06) + WRSR(0x01) to turn-off the protection.
The WEL(0x02) of status register
From: Kuo-Jung Su dant...@faraday-tech.com
Faraday processors are a series of ARMv4/ARMv5TE clone.
* ARMv4 series (FA526, FA626).
All of them are now out-of-date, so I have no plan for them.
* ARMv5TE series (FA606TE, FA626TE, FA616TE, FA726TE)
All the single core RISC listed above
2013/2/1 Andreas Färber afaer...@suse.de:
嗨 國榮,
Am 01.02.2013 09:57, schrieb Kuo-Jung Su:
Thanks for the information, and sorry for the mess I've done.
You don't need to apologize for every review comment you get. It's
meant for improvements of results, not personal. :)
Thanks. It's so
From: Kuo-Jung Su dant...@faraday-tech.com
Replace PORTSC macros with variables which could then be
configured in ehci__class_init(...) to support some
non-standard EHCI controllers.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
Cc: Gerd Hoffmann kra...@redhat.com
Cc: Andreas afaer
From: Kuo-Jung Su dant...@faraday-tech.com
These patches introduce Faraday A36x SoC platform support.
Here are some public documents for your reference.
http://www.faraday-tech.com/html/documentation/index.html
The pre-built images are also available at my Google Drive:
https
From: Kuo-Jung Su dant...@faraday-tech.com
It's used to perform AHB remap and also QEMU RAM initialization
when SDRAM is initialized before AHB remap process activated.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
---
hw/arm/Makefile.objs |1 +
hw/arm/faraday_a369_soc.c |3
From: Kuo-Jung Su dant...@faraday-tech.com
The Faraday FTDMAC020 provides eight configurable
channels for the memory-to-memory, memory-to-peripheral,
peripheral-to-peripheral, and peripheral-to-memory transfers.
Each DMA channel supports chain transfer and can be programmed
to one of the 16
From: Kuo-Jung Su dant...@faraday-tech.com
The FTSSP010 is a multi-function synchronous serial port interface
controller which supports SSP, SPI, I2S, AC97 and SPDIF.
Only I2S and SPI protocol have been implemented in this patch.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
---
hw/arm
From: Kuo-Jung Su dant...@faraday-tech.com
Status Register(SR):
SR[6] behaves the same as R/B# pin
SR[6] = 0 indicates the device is busy;
SR[6] = 1 means the device is ready
Some NAND flash controller (i.e. ftnandc021) relies on the
SR[6] to determine if the NAND flash erase/program
From: Kuo-Jung Su dant...@faraday-tech.com
It provides separate second, minute, hour, and day counters. The second
counter is toggled each second, the minute counter is toggled each minute,
the hour counter is toggled each hour, and the day counter is toggled each day.
The FTRTC011 provides
From: Kuo-Jung Su dant...@faraday-tech.com
The FTAPBBRG020 supports the DMA functions for the AHB-to-AHB,
AHB-to-APB, APB-to-AHB, and APB-to-APB transactions.
The DMA engine can support up to 4 DMA channels (A, B, C, and D)
and 15 handshaking channels. A DMA channel granted by the arbiter
block
From: Kuo-Jung Su dant...@faraday-tech.com
This patch includes the single core support to FA606TE, FA626TE,
FA616TE, FA726TE and CP15 Faraday extensions (AUX and I/D-Scratchpad).
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
---
target-arm/cpu.c | 52
From: Kuo-Jung Su dant...@faraday-tech.com
The FTTMR010 provides three independent sets of sub-timers.
Two match registers are provided for each sub-timer, whenever
the value of the match registers equals any one value of the
sub-timers, the timer interrupt will be immediately triggered
From: Kuo-Jung Su dant...@faraday-tech.com
The FTGMAC100 Ethernet controller has a DMA engine which handles
all data transfers between the system memory and on-chip memories.
Its DMA engine supports both 16-bits and 32-bits alignment,
and thus make it possible to support zero-copy transfer
From: Kuo-Jung Su dant...@faraday-tech.com
The FTMAC110 is an Ethernet controller that provides AHB master capability
and is in full compliance with the IEEE 802.3 10/100 Mbps specifications.
Its DMA controller handles all data transfers between system memory
and on-chip memories.
It supports
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