on DSP extension, and
send the
> first patch in middle October.
>
> Could the maintainers tell me whether the specs referenced are
> appropriate? Is anyone working on these extensions? I'd like to get
> your status, and maybe discuss questions and work togather.
>
> Best Regards
>
> LIU Zhiwei
>
>
>
>
yone is busy with something at the moment
unfortunately.
Alistair
Best Regards
LIU Zhiwei
uint16_t *u16;
int16_t *s16;
uint8_t *u8;
int8_t *s8;
} mem;
target_ulong vxrm;
target_ulong vxsat;
target_ulong vl;
target_ulong vstart;
target_ulong vtype;
} vext
I can't find the way to get the direct offset of vreg from cpu_env.
Maybe I should spe
On 2020/2/12 0:11, Richard Henderson wrote:
On 2/10/20 8:12 AM, LIU Zhiwei wrote:
+static int vs(CPURISCVState *env, int csrno)
+{
+return 0;
+}
This should at least be testing RVV, a-la smode().
Testing RVV is ok.
I'm not quite understand "a -1a smode()" here. Could you
On 2020/2/11 23:53, Richard Henderson wrote:
On 2/10/20 8:12 AM, LIU Zhiwei wrote:
The 32 vector registers will be viewed as a continuous memory block.
It avoids the convension between element index and (regno,offset).
Thus elements can be directly accessed by offset from the first vector
On 2020/2/11 23:56, Richard Henderson wrote:
On 2/10/20 8:12 AM, LIU Zhiwei wrote:
+if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) {
+error_setg(errp,
+ "Vector extension implementation o
On 2020/2/12 0:56, Richard Henderson wrote:
On 2/10/20 8:12 AM, LIU Zhiwei wrote:
static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
-target_ulong *cs_base, uint32_t *flags
Hi, Richard
Thanks for comments.
On 2020/2/12 14:38, Richard Henderson wrote:
On 2/9/20 11:42 PM, LIU Zhiwei wrote:
+/*
+ * As simd_desc supports at most 256 bytes, and in this implementation,
+ * the max vector group length is 2048 bytes. So split it into two parts.
+ *
+ * The first part
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 395 +++
target/riscv/insn32.decode | 127 +++
target/riscv/insn_trans/trans_rvv.inc.c | 671 +++-
target/riscv/vector_helper.c| 1308 ++-
4 files changed, 2462
On 2020/2/29 2:46, Richard Henderson wrote:
On 2/28/20 1:19 AM, LIU Zhiwei wrote:
+#define GEN_VEXT_AMO_NOATOMIC_OP(NAME, ETYPE, MTYPE, H, DO_OP, SUF) \
+static void vext_##NAME##_noatomic_op(void *vs3, target_ulong addr, \
+ uint32_t wd, uint32_t idx, CPURISCVState *env
vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags
should update after configure instructions. The (ill, lmul, sew ) of vtype
and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags.
Signed-off-by: LIU Zhiwei
---
target/riscv/Makef
The v0.7.1 specification does not define vector status within mstatus.
A future revision will define the privileged portion of the vector status.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu_bits.h | 15 +
target/riscv/csr.c | 75 -
2 files
vlen is the vector register length in bits.
elen is the max element size in bits.
vext_spec is the vector specification version, default value is v0.7.1.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/cpu.c | 7 +++
target/riscv
The 32 vector registers will be viewed as a continuous memory block.
It avoids the convension between element index and (regno, offset).
Thus elements can be directly accessed by offset from the first vector
base address.
Signed-off-by: LIU Zhiwei
Acked-by: Alistair Francis
Reviewed-by: Richard
memory block for vector register description.
V2
* use float16_compare{_quiet}
* only use GETPC() in outer most helper
* add ctx.ext_v Property
LIU Zhiwei (4):
target/riscv: add vector extension field in CPURISCVState
target/riscv: implementation-defined constant parameters
target/r
On 2020/2/28 4:03, Richard Henderson wrote:
On 2/25/20 2:35 AM, LIU Zhiwei wrote:
+GEN_VEXT_LD_ELEM(vlbff_v_b, int8_t, int8_t, H1, ldsb)
+GEN_VEXT_LD_ELEM(vlbff_v_h, int8_t, int16_t, H2, ldsb)
+GEN_VEXT_LD_ELEM(vlbff_v_w, int8_t, int32_t, H4, ldsb)
+GEN_VEXT_LD_ELEM(vlbff_v_d, int8_t
On 2020/2/28 13:46, Richard Henderson wrote:
On 2/25/20 6:43 PM, LIU Zhiwei wrote:
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 395 +++
target/riscv/insn32.decode | 127 +++
target/riscv/insn_trans/trans_rvv.inc.c | 671
On 2020/2/28 3:49, Richard Henderson wrote:
On 2/25/20 2:35 AM, LIU Zhiwei wrote:
+vsxb_v ... 011 . . . 000 . 0100111 @r_nfvm
+vsxh_v ... 011 . . . 101 . 0100111 @r_nfvm
+vsxw_v ... 011 . . . 110 . 0100111 @r_nfvm
+vsxe_v ... 011
On 2020/2/28 11:33, Richard Henderson wrote:
On 2/27/20 5:50 PM, LIU Zhiwei wrote:
This is not what I had in mind, and looks wrong as well.
int idx = (index * mlen) / 64;
int pos = (index * mlen) % 64;
return (((uint64_t *)v0)[idx] >> pos) & 1;
You also migh
On 2020/2/28 3:17, Richard Henderson wrote:
On 2/25/20 2:35 AM, LIU Zhiwei wrote:
+static bool vext_check_reg(DisasContext *s, uint32_t reg, bool widen)
+{
+int legal = widen ? 2 << s->lmul : 1 << s->lmul;
+
+return !((s->lmul == 0x3 && widen) || (reg
On 2020/2/27 3:20, Alistair Francis wrote:
On Fri, Feb 21, 2020 at 1:45 AM LIU Zhiwei wrote:
vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags
should update after configure instructions. The (ill, lmul, sew ) of vtype
and the bit of (VSTART == 0 && VL
On 2020/2/27 2:42, Alistair Francis wrote:
On Fri, Feb 21, 2020 at 1:45 AM LIU Zhiwei wrote:
The v0.7.1 specification does not define vector status within mstatus.
A future revision will define the privileged portion of the vector status.
Signed-off-by: LIU Zhiwei
---
target/riscv
On 2020/2/28 3:36, Richard Henderson wrote:
On 2/25/20 2:35 AM, LIU Zhiwei wrote:
+GEN_VEXT_LD_ELEM(vlsb_v_b, int8_t, int8_t, H1, ldsb)
+GEN_VEXT_LD_ELEM(vlsb_v_h, int8_t, int16_t, H2, ldsb)
+GEN_VEXT_LD_ELEM(vlsb_v_w, int8_t, int32_t, H4, ldsb)
+GEN_VEXT_LD_ELEM(vlsb_v_d, int8_t
On 2020/2/28 13:38, Richard Henderson wrote:
On 2/25/20 2:35 AM, LIU Zhiwei wrote:
+if (s->sew < 2) {
+return false;
+}
This could just as easily be in amo_check?
Yes, it can be done in amo_check.
+
+if (tb_cflags(s->base.tb) & CF_PARALLEL) {
+#ifdef CO
-by: LIU Zhiwei
---
target/riscv/helper.h | 70
target/riscv/insn32.decode | 17 +
target/riscv/insn_trans/trans_rvv.inc.c | 188 +++
target/riscv/translate.c| 2 +
target/riscv/vector_helper.c| 404
5
Vector AMOs operate as if aq and rl bits were zero on each element
with regard to ordering relative to other instructions in the same hart.
Vector AMOs provide no ordering guarantee between element operations
in the same vector AMO instruction
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h
Vector strided operations access the first memory element at the base address,
and then access subsequent elements at address increments given by the byte
offset contained in the x register specified by rs2.
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 35
The unit-stride fault-only-fault load instructions are used to
vectorize loops with data-dependent exit conditions(while loops).
These instructions execute as a regular load except that they
will only take a trap on element 0.
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h
nux user mode.
* add atomic and noatomic operation for vector amo instructions.
V2
* use float16_compare{_quiet}
* only use GETPC() in outer most helper
* add ctx.ext_v Property
LIU Zhiwei (5):
target/riscv: add vector unit stride load and store instructions
target/riscv: add vector str
Vector indexed operations add the contents of each element of the
vector offset operand specified by vs2 to the base effective address
to give the effective address of each element.
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 35
target/riscv/insn32.decode
Hi, Alistair
On 2020/2/19 6:34, Alistair Francis wrote:
On Mon, Feb 10, 2020 at 12:12 AM LIU Zhiwei wrote:
Vector extension is default on only for "any" cpu. It can be turned
on by command line "-cpu rv64,v=true,vlen=128,elen=64,vext_spec=v0.7.1".
vlen is the vector regi
Hi, Richard
Thanks for your informative comments. I'm addressing these comments.
And a little confused in some comments.
On 2020/2/12 14:38, Richard Henderson wrote:
On 2/9/20 11:42 PM, LIU Zhiwei wrote:
+/*
+ * As simd_desc supports at most 256 bytes, and in this implementation,
+ * the max
vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags
should update after configure instructions. The (ill, lmul, sew ) of vtype
and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags.
Signed-off-by: LIU Zhiwei
---
MAI
The 32 vector registers will be viewed as a continuous memory block.
It avoids the convension between element index and (regno, offset).
Thus elements can be directly accessed by offset from the first vector
base address.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.h | 12
1
vlen is the vector register length in bits.
elen is the max element size in bits.
vext_spec is the vector specification version, default value is v0.7.1.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.c | 7 +++
target/riscv/cpu.h | 5 +
2 files changed, 12 insertions(+)
diff --git
PC() in outer most helper
* add ctx.ext_v Property
LIU Zhiwei (4):
target/riscv: add vector extension field in CPURISCVState
target/riscv: implementation-defined constant parameters
target/riscv: support vector extension csr
target/riscv: add vector configure instruction
The v0.7.1 specification does not define vector status within mstatus.
A future revision will define the privileged portion of the vector status.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu_bits.h | 15 +
target/riscv/csr.c | 75 -
2 files
vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags
should update after configure instructions. The (ill, lmul, sew ) of vtype
and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags.
Signed-off-by: LIU Zhiwei
---
MAI
The unit-stride fault-only-fault load instructions are used to
vectorize loops with data-dependent exit conditions(while loops).
These instructions execute as a regular load except that they
will only take a trap on element 0.
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h
Vector AMOs operate as if aq and rl bits were zero on each element
with regard to ordering relative to other instructions in the same hart.
Vector AMOs provide no ordering guarantee between element operations
in the same vector AMO instruction
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h
.
V2
* use float16_compare{_quiet}
* only use GETPC() in outer most helper
* add ctx.ext_v Property
LIU Zhiwei (5):
target/riscv: add vector unit stride load and store instructions
target/riscv: add vector stride load and store instructions
target/riscv: add vector index load and store
Vector indexed operations add the contents of each element of the
vector offset operand specified by vs2 to the base effective address
to give the effective address of each element.
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 35
target/riscv/insn32.decode
The 32 vector registers will be viewed as a continuous memory block.
It avoids the convension between element index and (regno,offset).
Thus elements can be directly accessed by offset from the first vector
base address.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.h | 13 +
1
The v0.7.1 specification does not define vector status within mstatus.
A future revision will define the privileged portion of the vector status.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu_bits.h | 15 +
target/riscv/csr.c | 72 +++--
2 files
ck for vector register description.
V2
* use float16_compare{_quiet}
* only use GETPC() in outer most helper
* add ctx.ext_v Property
LIU Zhiwei (4):
target/riscv: add vector extension field in CPURISCVState
target/riscv: configure and turn on vector extension from command line
target/r
t_spec is the vector specification version, default value is v0.7.1.
Thest properties and cpu can be specified with other values.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.c | 48 --
target/riscv/cpu.h | 8
2 files changed, 54 insertions(+),
-by: LIU Zhiwei
---
target/riscv/helper.h | 70
target/riscv/insn32.decode | 17 +
target/riscv/insn_trans/trans_rvv.inc.c | 294
target/riscv/translate.c| 2 +
target/riscv/vector_helper.c| 438
Vector strided operations access the first memory element at the base address,
and then access subsequent elements at address increments given by the byte
offset contained in the x register specified by rs2.
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 35
FIELD is more unified to define tb flags. It is easier to add new
filed to tb flags.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.h | 15 +--
target/riscv/translate.c | 5 +++--
2 files changed, 12 insertions(+), 8 deletions(-)
diff --git a/target/riscv/cpu.h b/target
There is no reason why RISCV32 can't use RVD extension,
or RISCV64 can't just use RVF extension. And gdb will check
flen according to RVD or RVF feature in elf header.
Signed-off-by: LIU Zhiwei
---
configure | 4 ++--
target/riscv/gdbstub.c | 14 ++
2 files changed, 8
The read or write interface must be called after the predicate fs return 0.
And the predicate will check (!env->debugger && !riscv_cpu_fp_enabled(env)),
S0 no need to check again.
Signed-off-by: LIU Zhiwei
---
target/riscv/csr.c | 24
1 file changed, 2
vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags
should update after configure instructions. The (ill, lmul, sew ) of vtype
and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags.
Signed-off-by: LIU Zhiwei
---
target/riscv/Makef
vector specification version, default value is v0.7.1.
Thest properties and cpu can be specified with other values.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.c | 42 --
target/riscv/cpu.h | 8
2 files changed, 48 insertions(+), 2 dele
Until v0.7.1 specification, vector status is still not defined for
mstatus.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu_bits.h | 15 +++
target/riscv/csr.c | 92 +
2 files changed, 80 insertions(+), 27 deletions(-)
diff --git a/target/riscv
The 32 vector registers will be viewed as a continuous memory block.
It avoids the convension between element index and (regno,offset).
Thus elements can be directly accessed by offset from the first vector
base address.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.h | 14 ++
1
use GETPC() in outer most helper
* add ctx.ext_v Property
LIU Zhiwei (4):
RISC-V: add vector extension field in CPURISCVState
RISC-V: configure and turn on vector extension from command line
RISC-V: support vector extension csr
RISC-V: add vector extension configure instruction
ta
On 2019/12/20 4:38, Richard Henderson wrote:
On 12/18/19 11:11 PM, LIU Zhiwei wrote:
I'm sorry that it's really hard to absorb your opinion. I don't know why clang
will fail
when index beyond the end of vreg[n] into vreg[n+1].
I thought sure one of the address sanitizer checks would detect
On 2019/12/28 9:14, Richard Henderson wrote:
On 12/25/19 8:36 PM, LIU Zhiwei wrote:
struct {
uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16);
target_ulong vxrm;
target_ulong vxsat;
target_ulong vl;
target_ulong vstart;
target_ulong
On 2020/1/7 6:00, Jim Wilson wrote:
On 1/2/20 7:33 PM, LIU Zhiwei wrote:
Until v0.7.1 specification, vector status is still not defined for
mstatus.
The v0.8 spec does define a VS bit in mstatus.
Yes, I will also support v0.8 spec after the v0.7.1 spec.
@@ -107,11 +112,6 @@ static int
On 2020/1/7 5:48, Jim Wilson wrote:
On 1/2/20 7:33 PM, LIU Zhiwei wrote:
+ if (cpu->cfg.vlen > RV_VLEN_MAX) {
+ error_setg(errp,
+ "Vector extension VLEN must <= %d",
RV_VLEN_MAX);
+ return;
There is no ar
Hi Richard,
Thanks for the comments of the part 1. It's really very helpful.
I accept most of the comments.
On 2020/1/4 7:41, Richard Henderson wrote:
On 1/3/20 2:33 PM, LIU Zhiwei wrote:
vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags
should update after configure
Hi Richard,
Sorry to reply so late for this comment. I will move forward on part 2.
On 2019/9/12 22:23, Richard Henderson wrote:
+static bool vector_lmul_check_reg(CPURISCVState *env, uint32_t lmul,
+uint32_t reg, bool widen)
+{
+int legal = widen ? (lmul * 2) : lmul;
+
+if
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 33 +++
target/riscv/insn32.decode | 10 +
target/riscv/insn_trans/trans_rvv.inc.c | 16 ++
target/riscv/vector_helper.c| 278
4 files changed, 337 insertions(+)
diff
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 17
target/riscv/insn32.decode | 5 +
target/riscv/insn_trans/trans_rvv.inc.c | 7 ++
target/riscv/vector_helper.c| 129
4 files changed, 158 insertions(+)
diff
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 9 +++
target/riscv/insn32.decode | 2 +
target/riscv/insn_trans/trans_rvv.inc.c | 4 +
target/riscv/vector_helper.c| 103
4 files changed, 118 insertions(+)
diff
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 13 +++
target/riscv/insn32.decode | 6 ++
target/riscv/insn_trans/trans_rvv.inc.c | 8 ++
target/riscv/vector_helper.c| 128
4 files changed, 155 insertions(+)
diff
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 16 +
target/riscv/insn32.decode | 5 +++
target/riscv/insn_trans/trans_rvv.inc.c | 7
target/riscv/vector_helper.c| 48 +
4 files changed, 76 insertions
user mode.
* generation atomic exit exception when in parallel environment.
* fixup a lot of concrete bugs.
V2
* use float16_compare{_quiet}
* only use GETPC() in outer most helper
* add ctx.ext_v Property
LIU Zhiwei (60):
target/riscv: add vector extension field in CPURISCVState
The unit-stride fault-only-fault load instructions are used to
vectorize loops with data-dependent exit conditions(while loops).
These instructions execute as a regular load except that they
will only take a trap on element 0.
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 25
target/riscv/insn32.decode | 9 +
target/riscv/insn_trans/trans_rvv.inc.c | 11 ++
target/riscv/vector_helper.c| 51 +
4 files changed, 96 insertions
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 49
target/riscv/insn32.decode | 16 +++
target/riscv/insn_trans/trans_rvv.inc.c | 154
target/riscv/vector_helper.c| 112 +
4 files changed, 331
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 25
target/riscv/insn32.decode | 9 +++
target/riscv/insn_trans/trans_rvv.inc.c | 44 +
target/riscv/vector_helper.c| 82 +
4 files changed, 160
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 57 +++
target/riscv/insn32.decode | 20
target/riscv/insn_trans/trans_rvv.inc.c | 66
target/riscv/vector_helper.c| 130
4 files changed, 273
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 5 +
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvv.inc.c | 4
target/riscv/vector_helper.c| 22 ++
4 files changed, 33 insertions(+)
diff --git
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 17 +++
target/riscv/insn32.decode | 8 ++
target/riscv/insn_trans/trans_rvv.inc.c | 131
target/riscv/vector_helper.c| 77 ++
4 files changed, 233 insertions
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 17 +
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvv.inc.c | 10 +++
target/riscv/vector_helper.c| 84 +
4 files changed, 119 insertions(+)
diff
Hi, forks
When I sent vector extension patchset v3(2020/03/09), my mail system
works some wrong,
and only part of the patchset were sent. When I try to send again, it
either can't work.
Even more, I found the mail list archives were polluted, many
repetitions and scattered
in many
Vector indexed operations add the contents of each element of the
vector offset operand specified by vs2 to the base effective address
to give the effective address of each element.
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 35 +++
target/riscv/insn32.decode
The 32 vector registers will be viewed as a continuous memory block.
It avoids the convension between element index and (regno, offset).
Thus elements can be directly accessed by offset from the first vector
base address.
Signed-off-by: LIU Zhiwei
Acked-by: Alistair Francis
Reviewed-by: Richard
the base effective address. It can been seen as a special
case of strided operations.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.h | 6 +
target/riscv/helper.h | 105 ++
target/riscv/insn32.decode | 32 ++
target/riscv/insn_trans
Vector AMOs operate as if aq and rl bits were zero on each element
with regard to ordering relative to other instructions in the same hart.
Vector AMOs provide no ordering guarantee between element operations
in the same vector AMO instruction
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.h
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 21 +++
target/riscv/insn32.decode | 10 ++
target/riscv/insn_trans/trans_rvv.inc.c | 220
target/riscv/vector_helper.c| 122 +
4 files changed, 373 insertions
vlen is the vector register length in bits.
elen is the max element size in bits.
vext_spec is the vector specification version, default value is v0.7.1.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/cpu.c | 7 +++
target/riscv
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 9
target/riscv/insn32.decode | 3 ++
target/riscv/insn_trans/trans_rvv.inc.c | 24 ++
target/riscv/vector_helper.c| 58 +
4 files changed, 94 insertions
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 33
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvv.inc.c | 10
target/riscv/vector_helper.c| 71 +
4 files changed, 122 insertions
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 33 ++
target/riscv/insn32.decode | 10 ++
target/riscv/insn_trans/trans_rvv.inc.c | 108 ++
target/riscv/vector_helper.c| 140
4 files changed, 291
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 49 +
target/riscv/insn32.decode | 16 ++
target/riscv/insn_trans/trans_rvv.inc.c | 18 ++
target/riscv/vector_helper.c| 228
4 files changed, 311 insertions(+)
diff
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 4 +++
target/riscv/insn32.decode | 3 ++
target/riscv/insn_trans/trans_rvv.inc.c | 37 +++
target/riscv/vector_helper.c| 40 +
4 files changed, 84
vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags
should update after configure instructions. The (ill, lmul, sew ) of vtype
and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags.
Signed-off-by: LIU Zhiwei
---
target/riscv/Makef
The v0.7.1 specification does not define vector status within mstatus.
A future revision will define the privileged portion of the vector status.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu_bits.h | 15 +
target/riscv/csr.c | 75 -
2 files
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 16
target/riscv/insn32.decode | 5 ++
target/riscv/insn_trans/trans_rvv.inc.c | 107
target/riscv/vector_helper.c| 89
4 files changed, 217
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 33 ++
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvv.inc.c | 10 +++
target/riscv/vector_helper.c| 88 +
4 files changed, 139 insertions
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 33 +++
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvv.inc.c | 10
target/riscv/vector_helper.c| 74 +
4 files changed, 125 insertions
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 17
target/riscv/insn32.decode | 6 ++
target/riscv/insn_trans/trans_rvv.inc.c | 8 ++
target/riscv/vector_helper.c| 109
4 files changed, 140 insertions(+)
diff
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 22
target/riscv/insn32.decode | 7
target/riscv/insn_trans/trans_rvv.inc.c | 9 +
target/riscv/vector_helper.c| 45 +
4 files changed, 83 insertions
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 22 +++
target/riscv/insn32.decode | 7 +
target/riscv/insn_trans/trans_rvv.inc.c | 9 ++
target/riscv/vector_helper.c| 180
4 files changed, 218 insertions(+)
diff
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 33 ++
target/riscv/insn32.decode | 8 ++
target/riscv/insn_trans/trans_rvv.inc.c | 10 ++
target/riscv/vector_helper.c| 147
4 files changed, 198 insertions(+)
diff
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 19 +
target/riscv/insn32.decode | 6 +++
target/riscv/insn_trans/trans_rvv.inc.c | 8
target/riscv/vector_helper.c| 51 +
4 files changed, 84 insertions
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 13
target/riscv/insn32.decode | 6 ++
target/riscv/insn_trans/trans_rvv.inc.c | 91 +
target/riscv/vector_helper.c| 14
4 files changed, 124 insertions(+)
diff
vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags
should update after configure instructions. The (ill, lmul, sew ) of vtype
and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags.
Signed-off-by: LIU Zhiwei
---
target/riscv/Makef
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