[PATCH v2 28/37] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions

SIMD 32-bit straight or crossed add/subtract with rounding, havling, or saturation. Signed-off-by: LIU Zhiwei --- include/tcg/tcg-op-gvec.h | 4 + target/riscv/helper.h | 29 +++ target/riscv/insn32.decode | 32 +++ target/riscv/insn_trans

[PATCH v2 33/37] target/riscv: RV64 Only 32-bit Multiply & Add Instructions

32x32 multiplication result is added to a third register with Q63 saturation Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 4 target/riscv/insn32.decode | 4 target/riscv/insn_trans/trans_rvp.c.inc | 5 target/riscv/packed_helper.c

[PATCH v2 21/37] target/riscv: 64-bit Add/Subtract Instructions

64-bit add/subtract with saturation or halving operation. Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 11 ++ target/riscv/insn32.decode | 11 ++ target/riscv/insn_trans/trans_rvp.c.inc | 74 + target/riscv/packed_helper.c| 132

[PATCH v2 36/37] target/riscv: RV64 Only 32-bit Packing Instructions

Concat two 32-bit elements to form a 64-bit element. Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 5 +++ target/riscv/insn32.decode | 5 +++ target/riscv/insn_trans/trans_rvp.c.inc | 6 target/riscv/packed_helper.c| 41

[PATCH v2 23/37] target/riscv: Signed 16-bit Multiply with 64-bit Add/Subtract Instructions

one or two 16x16 multiply as operands for an add/subtract operation with another 64-bit operand. Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 11 ++ target/riscv/insn32.decode | 11 ++ target/riscv/insn_trans/trans_rvp.c.inc | 12 ++ target/riscv

[PATCH v2 19/37] target/riscv: Partial-SIMD Miscellaneous Instructions

32-bit signed or unsigned clip value. 32-bit leading redundant sign, leading zero, leading one count. Parallel byte sum of absolute difference or parallel byte sum of absolute difference accumulation. Signed-off-by: LIU Zhiwei Acked-by: Alistair Francis --- target/riscv/helper.h

[PATCH v2 17/37] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions

Always contain a signed 16x16 multiply and the 32-bit result can be written to the destination register or as an operand for an add/subtract operation. Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 19 ++ target/riscv/insn32.decode | 19 ++ target/riscv

[PATCH v2 22/37] target/riscv: 32-bit Multiply 64-bit Add/Subtract Instructions

32x32 multiply as an operand for 64-bit add/subtract operation with saturation or not. Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 9 ++ target/riscv/insn32.decode | 9 ++ target/riscv/insn_trans/trans_rvp.c.inc | 67 ++ target/riscv

[PATCH v2 32/37] target/riscv: RV64 Only 32-bit Multiply Instructions

Multiply the straight or crossed 32-bit elements of two registers. Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 3 +++ target/riscv/insn32.decode | 3 +++ target/riscv/insn_trans/trans_rvp.c.inc | 4 target/riscv/packed_helper.c| 21

[PATCH v2 16/37] target/riscv: Signed MSW 32x16 Multiply and Add Instructions

Always contain a 32x16 multiplification and the most significant word can be used as the result, or an operand for an add or subtract operation with rounding or saturation. Signed-off-by: LIU Zhiwei Acked-by: Alistair Francis --- target/riscv/helper.h | 17 ++ target/riscv

[PATCH v2 18/37] target/riscv: Signed 16-bit Multiply 64-bit Add/Subtract Instructions

"16x16" with 64-bit Signed Addition(64 = 64 + 16x16). Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 2 + target/riscv/insn32.decode | 2 + target/riscv/insn_trans/trans_rvp.c.inc | 51 + target/riscv/packe

[PATCH v2 31/37] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions

Q15 saturation limits the result to the range [INT16_MIN, INT16_MAX]. Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 10 ++ target/riscv/insn32.decode | 10 ++ target/riscv/insn_trans/trans_rvp.c.inc | 19 target/riscv/packed_helper.c

[PATCH v2 20/37] target/riscv: 8-bit Multiply with 32-bit Add Instructions

Four "signed or unsigned 8 x signed or unsigned 8" with 32-bit addition (32 = 32 + 8x8 + 8x8 + 8x8 + 8x8). Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 4 +++ target/riscv/insn32.decode | 4 +++ target/riscv/insn_trans/trans_rvp.c.inc | 5 +

[PATCH v2 14/37] target/riscv: 16-bit Packing Instructions

Concat 16-bit elements from source register to 32-bit element in destination register. Signed-off-by: LIU Zhiwei Acked-by: Alistair Francis --- target/riscv/helper.h | 5 +++ target/riscv/insn32.decode | 5 +++ target/riscv/insn_trans/trans_rvp.c.inc | 9

[PATCH v2 26/37] target/riscv: 32-bit Computation Instructions

32-bit halving addition or subtraction, maximum, minimum, or multiply. Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 9 +++ target/riscv/insn32.decode | 9 +++ target/riscv/insn_trans/trans_rvp.c.inc | 10 +++ target/riscv/packed_helper.c| 92

[PATCH v2 11/37] target/riscv: SIMD 16-bit Miscellaneous Instructions

There are 11 instructions, including signed or unsigned minimum, maximum, clip value, absolute value, and leading zero, leading one count instructions. Signed-off-by: LIU Zhiwei Acked-by: Alistair Francis --- target/riscv/helper.h | 11 ++ target/riscv/insn32.decode

[PATCH v2 15/37] target/riscv: Signed MSW 32x32 Multiply and Add Instructions

Always contain a 32x32 multiplification and the most significant word can be used as the result, or an operand for an add or subtract operation with rounding or saturation. Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 9 ++ target/riscv/insn32.decode

[PATCH v2 12/37] target/riscv: SIMD 8-bit Miscellaneous Instructions

Instructions include signed or unsigned minimum, maximum, clip value, absolute value, and leading zero, leading one count instructions. Signed-off-by: LIU Zhiwei Acked-by: Alistair Francis --- target/riscv/helper.h | 12 +++ target/riscv/insn32.decode | 12

[PATCH v2 10/37] target/riscv: SIMD 8-bit Multiply Instructions

There are 6 instructions, including 8-bit signed or unsigned multiply, 8-bit signed or unsigned crossed multiply, Q7 signed or signed crossed saturating multiply. Signed-off-by: LIU Zhiwei Acked-by: Alistair Francis --- target/riscv/helper.h | 7 ++ target/riscv/insn32

[PATCH v2 13/37] target/riscv: 8-bit Unpacking Instructions

Sign-extend or zero-extend selected 8-bit elements to 16-bit elements. Signed-off-by: LIU Zhiwei Acked-by: Alistair Francis --- target/riscv/helper.h | 11 +++ target/riscv/insn32.decode | 11 +++ target/riscv/insn_trans/trans_rvp.c.inc | 12 +++ target/riscv

[PATCH v2 07/37] target/riscv: SIMD 16-bit Compare Instructions

There are 5 instructions here, including 16-bit compare equal, signed less than, signed less than & equal, unsigned less than, unsigned less than & equal. Signed-off-by: LIU Zhiwei Acked-by: Alistair Francis

[PATCH v2 08/37] target/riscv: SIMD 8-bit Compare Instructions

There are 5 instructions here, including 8-bit compare equal, signed less than, signed less than & equal, unsigned less than, unsigned less than & equal. Signed-off-by: LIU Zhiwei Acked-by: Alistair Francis --- target/riscv/helper.h | 6 target/riscv/insn3

[PATCH v2 06/37] target/riscv: SIMD 8-bit Shift Instructions

Instructions include right arithmetic shift, right logic shift, and left shift. The shift can be an immediate or a register scalar. The right shift has rounding operation. And the left shift has saturation operation. Signed-off-by: LIU Zhiwei Acked-by: Alistair Francis Reviewed-by: Palmer

[PATCH v2 09/37] target/riscv: SIMD 16-bit Multiply Instructions

There are 6 instructions, including 16-bit signed or unsigned multiply, 16-bit signed or unsigned crossed multiply, Q15 signed or signed crossed saturating multiply. Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 7 ++ target/riscv/insn32.decode | 7

[PATCH v2 03/37] target/riscv: 16-bit Addition & Subtraction Instructions

Include 5 groups: Wrap-around (dropping overflow), Signed Halving, Unsigned Halving, Signed Saturation, and Unsigned Saturation. Signed-off-by: LIU Zhiwei --- include/tcg/tcg-op-gvec.h | 10 + target/riscv/helper.h | 30 ++ target/riscv/insn32.decode

[PATCH v2 05/37] target/riscv: SIMD 16-bit Shift Instructions

Instructions include right arithmetic shift, right logic shift, and left shift. The shift can be an immediate or a register scalar. The right shift has rounding operation. And the left shift has saturation operation. Signed-off-by: LIU Zhiwei --- include/tcg/tcg-op-gvec.h | 9

[PATCH v2 04/37] target/riscv: 8-bit Addition & Subtraction Instruction

Include 5 groups: Wrap-around (dropping overflow), Signed Halving, Unsigned Halving, Signed Saturation, and Unsigned Saturation. Signed-off-by: LIU Zhiwei Acked-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- include/tcg/tcg-op-gvec.h | 6 ++ target/riscv/helper.h

[PATCH v2 02/37] target/riscv: Make the vector helper functions public

The saturate functions about add,subtract and shift functions can be used in packed extension.Therefore hoist them up. The endianess process macro is also be hoisted. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/internals.h | 50 ++ target

[PATCH v2 01/37] target/riscv: implementation-defined constant parameters

ext_psfoperand is whether to support Zpsfoperand sub-extension. pext_ver is the packed specification version, default value is v0.9.4. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 31 +++ target/riscv/cpu.h | 6

[PATCH v2 00/37] target/riscv: support packed extension v0.9.4

://github.com/riscv/riscv-p-spec/) * support basic packed extension. * support Zpsoperand. v2: * remove all the TARGET_RISCV64 macro. * use tcg_gen_vec_* to accelabrate. * update specficication to latest v0.9.4 * fix kmsxda32, kmsda32,kslra32,smal LIU Zhiwei (37): target/riscv: implementation

Re: TCG op for 32 bit only cpu on qemu-riscv64

On 6/7/21 11:52 PM, Richard Henderson wrote: On 6/6/21 8:07 PM, LIU Zhiwei wrote: Hi Alistair, As I see,  we are moving  on to remove TARGET_RISCV64 macro. I have some questions: 1) Which tcg op should use when translate an instruction for 32bit cpu. The tcg_*_i64, tcg_*_i32 or tcg_*_tl

Re: TCG op for 32 bit only cpu on qemu-riscv64

On 6/7/21 2:22 PM, Alistair Francis wrote: On Mon, Jun 7, 2021 at 1:09 PM LIU Zhiwei wrote: Hi Alistair, As I see, we are moving on to remove TARGET_RISCV64 macro. I have some questions: 1) Which tcg op should use when translate an instruction for 32bit cpu. The tcg_*_i64, tcg_*_i32

TCG op for 32 bit only cpu on qemu-riscv64

Hi Alistair, As I see,  we are moving  on to remove TARGET_RISCV64 macro. I have some questions: 1) Which tcg op should use when translate an instruction for 32bit cpu. The tcg_*_i64, tcg_*_i32 or tcg_*_tl? I see some API such as gen_get_gpr that are using the tcg_*_tl. But I am not sure if

Re: [PATCH] target/riscv: hardwire bits in hideleg and hedeleg

Reviewed-by: LIU Zhiwei Zhiwei On 5/22/21 11:59 PM, Jose Martins wrote: The specification mandates for certain bits to be hardwired in the hypervisor delegation registers. This was not being enforced. Signed-off-by: Jose Martins --- target/riscv/csr.c | 13 +++-- 1 file changed

Re: [PATCH] target/riscv: hardwire bits in hideleg and hedeleg

On 5/26/21 1:50 AM, Jose Martins wrote: We can use it directly if only one macro VS_MODE_INTERRUPTS. I wrote it like this to be more coherent with what was already there which also makes it more readable. Furthermore, the compiler will just probably optimize the variable away, right? Hi

Re: [PATCH v3] target/riscv: fix VS interrupts forwarding to HS

On 5/28/21 6:34 AM, Alistair Francis wrote: On Sun, May 23, 2021 at 1:45 AM Jose Martins wrote: VS interrupts (2, 6, 10) were not correctly forwarded to hs-mode when not delegated in hideleg (which was not being taken into account). This was mainly because hs level sie was not always

Re: [PATCH 1/1] target/riscv: Fix vsip vsie CSR ops in M and HS mode

On 5/28/21 6:19 AM, Alistair Francis wrote: On Thu, May 27, 2021 at 7:01 PM LIU Zhiwei wrote: When V=1, instructions that normally read or modify a supervisor CSR shall instead access the corresponding VS CSR. And the VS CSRs can be accessed as themselves from M-mode or HS-mode. In M and HS

[PATCH 1/1] target/riscv: Fix vsip vsie CSR ops in M and HS mode

When V=1, instructions that normally read or modify a supervisor CSR shall instead access the corresponding VS CSR. And the VS CSRs can be accessed as themselves from M-mode or HS-mode. In M and HS mode, VSIP or VSIE should be written normally instead of shift by 1. Signed-off-by: LIU Zhiwei

Re: [PATCH v3] target/riscv: fix VS interrupts forwarding to HS

On 5/26/21 7:50 PM, Jose Martins wrote: Hello Zhiwei, thank you for reviewing the patch. I'll split the patch in a series as you suggest. But first can you help me understand what the problems are with riscv_cpu_local_irq_pending? I think there are two errors in riscv_cpu_local_irq_pending.

Re: [PATCH v3] target/riscv: fix VS interrupts forwarding to HS

Hi Jose, For one patch, the commit message is too long and complex. I recommend to split this patch to a  patch set with 4 patches. The tremohread topic is 'target/riscv: Remove  force hs exception' 1) Define the right hsie to select pending_hs_irqs. diff --git a/target/riscv/cpu_helper.c

Re: [PATCH 05/38] target/riscv: 8-bit Addition & Subtraction Instruction

On 5/24/21 9:00 AM, Palmer Dabbelt wrote: On Mon, 15 Mar 2021 14:22:58 PDT (-0700), alistai...@gmail.com wrote: On Fri, Feb 12, 2021 at 10:14 AM LIU Zhiwei wrote: Signed-off-by: LIU Zhiwei Acked-by: Alistair Francis I saw some reviews on the other ones, but since others (like

Re: [PATCH] target/riscv: hardwire bits in hideleg and hedeleg

On 5/22/21 11:59 PM, Jose Martins wrote: The specification mandates for certain bits to be hardwired in the hypervisor delegation registers. This was not being enforced. Signed-off-by: Jose Martins --- target/riscv/csr.c | 13 +++-- 1 file changed, 11 insertions(+), 2 deletions(-)

[PATCH] target/riscv: Pass the same value to oprsz and maxsz.

Since commit e2e7168a214b0ed98dc357bba96816486a289762, if oprsz is still zero(as we don't use this field), simd_desc will trigger an assert. Besides, tcg_gen_gvec_*_ptr calls simd_desc in it's implementation. Here we pass the value to maxsz and oprsz to bypass the assert. Signed-off-by: LIU

Re: [PATCH v1 1/1] target/riscv/pmp: Add assert for ePMP operations

Reviewed-by: LIU Zhiwei On 5/21/21 6:55 AM, Alistair Francis wrote: Although we construct epmp_operation in such a way that it can only be between 0 and 15 Coverity complains that we don't handle the other possible cases. To fix Coverity and make it easier for humans to read add a default case

Re: [PULL v3 36/42] target/riscv: Remove the hardcoded MSTATUS_SD macro

On 5/21/21 6:55 AM, Alistair Francis wrote: On Thu, May 20, 2021 at 11:55 PM Peter Maydell wrote: On Tue, 11 May 2021 at 11:22, Alistair Francis wrote: Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Message-id:

Re: [RFC PATCH 00/11] RISC-V: support clic v0.9 specification

On 2021/4/20 下午2:26, Alistair Francis wrote: On Tue, Apr 20, 2021 at 11:45 AM LIU Zhiwei wrote: On 2021/4/20 上午7:30, Alistair Francis wrote: On Fri, Apr 9, 2021 at 5:56 PM LIU Zhiwei wrote: This patch set gives an implementation of "RISC-V Core-Local Interrupt Controller(CLIC) Ve

Re: [RFC PATCH 00/11] RISC-V: support clic v0.9 specification

On 2021/4/20 上午7:30, Alistair Francis wrote: On Fri, Apr 9, 2021 at 5:56 PM LIU Zhiwei wrote: This patch set gives an implementation of "RISC-V Core-Local Interrupt Controller(CLIC) Version 0.9-draft-20210217". It comes from [1], where you can find the pdf format or the source cod

Re: [RFC PATCH 03/11] hw/intc: Add CLIC device

On 2021/4/20 上午7:25, Alistair Francis wrote: On Fri, Apr 9, 2021 at 5:56 PM LIU Zhiwei wrote: The Core-Local Interrupt Controller (CLIC) provides low-latency, vectored, pre-emptive interrupts for RISC-V systems. The CLIC also supports a new Selective Hardware Vectoring feature that allow

Re: [RFC PATCH 01/11] target/riscv: Add CLIC CSR mintstatus

On 2021/4/20 上午7:23, Alistair Francis wrote: On Fri, Apr 9, 2021 at 5:52 PM LIU Zhiwei wrote: CSR mintstatus holds the active interrupt level for each supported privilege mode. sintstatus, and user, uintstatus, provide restricted views of mintstatus. Signed-off-by: LIU Zhiwei --- target

Re: [PATCH 00/38] target/riscv: support packed extension v0.9.2

On 2021/4/15 下午12:46, Alistair Francis wrote: On Tue, Apr 13, 2021 at 1:28 PM LIU Zhiwei wrote: ping +1. On 2021/2/12 下午11:02, LIU Zhiwei wrote: This patchset implements the packed extension for RISC-V on QEMU. This patchset have passed all my direct Linux user mode cases(RV64) and bare

Re: [Bug 1923629] [NEW] RISC-V Vector Instruction vssub.vv not saturating

, Alistair Francis wrote: + LIU Zhiwei and Kito Cheng Alistair On Wed, Apr 14, 2021 at 1:31 AM Tony Cole <1923...@bugs.launchpad.net> wrote: Public bug reported: I noticed doing a negate ( 0 – 0x8000 ) using vssub.vv produces an incorrect result of 0x8000 (should saturate to 0x7F

Re: [PATCH 00/38] target/riscv: support packed extension v0.9.2

ping +1. On 2021/2/12 下午11:02, LIU Zhiwei wrote: This patchset implements the packed extension for RISC-V on QEMU. This patchset have passed all my direct Linux user mode cases(RV64) and bare metal cases(RV32) on X86-64 Ubuntu host machine. I will later push these test cases to my repo(https

[RFC PATCH 03/11] hw/intc: Add CLIC device

The Core-Local Interrupt Controller (CLIC) provides low-latency, vectored, pre-emptive interrupts for RISC-V systems. The CLIC also supports a new Selective Hardware Vectoring feature that allow users to optimize each interrupt for either faster response or smaller code size. Signed-off-by: LIU

[RFC PATCH 00/11] RISC-V: support clic v0.9 specification

on website: https://github.com/riscv/riscv-fast-interrupt. [2] Michael Clark origin work: https://github.com/sifive/riscv-qemu/tree/sifive-clic. LIU Zhiwei (11): target/riscv: Add CLIC CSR mintstatus target/riscv: Update CSR xintthresh in CLIC mode hw/intc: Add CLIC device target/riscv: Upda

[RFC PATCH 02/11] target/riscv: Update CSR xintthresh in CLIC mode

The interrupt-level threshold (xintthresh) CSR holds an 8-bit field for the threshold level of the associated privilege mode. For horizontal interrupts, only the ones with higher interrupt levels than the threshold level are allowed to preempt. Signed-off-by: LIU Zhiwei --- target/riscv/cpu.h

[RFC PATCH 11/11] target/riscv: Update interrupt return in CLIC mode

When a vectored interrupt is selected and serviced, the hardware will automatically clear the corresponding pending bit in edge-triggered mode. This may lead to a lower priviledge interrupt pending forever. Therefore when interrupts return, pull a pending interrupt to service. Signed-off-by: LIU

[RFC PATCH 09/11] target/riscv: Update CSR mclicbase in CLIC mode

The machine mode mclicbase CSR is an XLEN-bit read-only register providing the base address of CLIC memory mapped registers. Signed-off-by: LIU Zhiwei --- hw/intc/riscv_clic.c | 1 + target/riscv/cpu.h | 1 + 2 files changed, 2 insertions(+) diff --git a/hw/intc/riscv_clic.c b/hw/intc

[RFC PATCH 07/11] target/riscv: Update CSR xtvt in CLIC mode

The xtvt WARL XLEN-bit CSR holds the base address of the trap vector table, aligned on a 64-byte or greater power-of-two boundary. Signed-off-by: LIU Zhiwei --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_bits.h | 2 ++ target/riscv/csr.c | 28 3 files

[RFC PATCH 01/11] target/riscv: Add CLIC CSR mintstatus

CSR mintstatus holds the active interrupt level for each supported privilege mode. sintstatus, and user, uintstatus, provide restricted views of mintstatus. Signed-off-by: LIU Zhiwei --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_bits.h | 11 +++ target/riscv/csr.c | 26

[RFC PATCH 10/11] target/riscv: Update interrupt handling in CLIC mode

Decode CLIC interrupt information from exccode, includes interrupt priviledge mode, interrupt level, and irq number. Then update CSRs xcause, xstatus, xepc, xintstatus and jump to correct PC according to the CLIC specification. Signed-off-by: LIU Zhiwei --- target/riscv/cpu_bits.h | 1

[RFC PATCH 06/11] target/riscv: Update CSR xtvec in CLIC mode

The new CLIC interrupt-handling mode is encoded as a new state in the existing WARL xtvec register, where the low two bits of are 11. Signed-off-by: LIU Zhiwei --- target/riscv/csr.c | 22 -- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/target/riscv/csr.c b

[RFC PATCH 05/11] target/riscv: Update CSR xip in CLIC mode

The xip CSR appears hardwired to zero in CLIC mode, replaced by separate memory-mapped interrupt pendings (clicintip[i]). Writes to xip will be ignored and will not trap (i.e., no access faults). Signed-off-by: LIU Zhiwei --- target/riscv/csr.c | 10 ++ 1 file changed, 10 insertions

[RFC PATCH 04/11] target/riscv: Update CSR xie in CLIC mode

The xie CSR appears hardwired to zero in CLIC mode, replaced by separate memory-mapped interrupt enables (clicintie[i]). Writes to xie will be ignored and will not trap (i.e., no access faults). Signed-off-by: LIU Zhiwei --- target/riscv/csr.c | 19 --- 1 file changed, 16

[RFC PATCH 08/11] target/riscv: Update CSR xnxti in CLIC mode

The CSR can be used by software to service the next horizontal interrupt when it has greater level than the saved interrupt context (held in xcause`.pil`) and greater level than the interrupt threshold of the corresponding privilege mode, Signed-off-by: LIU Zhiwei --- target/riscv/cpu_bits.h

Questions about qtest on interrupt controller

Hi folks, When I am writing  qtest  cases for an interrupt controller,  I encounter some problems. *1) Can't intercept both the irq in and irq out for the same device.* It's a necessary feature for an interrupt controller qtest. However, as you can see  from qtest.c,  when a device has

Re: [PATCH 06/38] target/riscv: SIMD 16-bit Shift Instructions

On 2021/3/17 3:54, Alistair Francis wrote: On Mon, Mar 15, 2021 at 10:40 PM LIU Zhiwei wrote: On 2021/3/16 5:25, Alistair Francis wrote: On Fri, Feb 12, 2021 at 10:16 AM LIU Zhiwei wrote: Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 9 ++ target/riscv

Re: [PATCH 06/38] target/riscv: SIMD 16-bit Shift Instructions

On 2021/3/16 5:25, Alistair Francis wrote: On Fri, Feb 12, 2021 at 10:16 AM LIU Zhiwei wrote: Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 9 ++ target/riscv/insn32.decode | 17 target/riscv/insn_trans/trans_rvp.c.inc | 115

Re: Question about edge-triggered interrupt

On 2021/3/12 0:50, Peter Maydell wrote: On Thu, 11 Mar 2021 at 16:40, LIU Zhiwei wrote: On 2021/3/12 0:07, Peter Maydell wrote: On Thu, 11 Mar 2021 at 16:01, LIU Zhiwei wrote: I'm pretty sure that there is some interaction between the CPU and the interrupt controller on a return-from

Re: Question about edge-triggered interrupt

On 2021/3/12 4:45, Alistair Francis wrote: On Thu, Mar 11, 2021 at 11:21 AM LIU Zhiwei wrote: On 2021/3/11 21:17, Peter Maydell wrote: On Thu, 11 Mar 2021 at 12:59, LIU Zhiwei wrote: From the specification, I find that software will not clean the pending bit on interrupt controller

Re: Question about edge-triggered interrupt

On 2021/3/12 0:07, Peter Maydell wrote: On Thu, 11 Mar 2021 at 16:01, LIU Zhiwei wrote: That's a case I can't understand. 1. An device causes an edge-triggered interrupt A. 2. The interrupt controller sample the interrupt A, and setting pending bit for A. 3. The interrupt controller

Re: Question about edge-triggered interrupt

On 2021/3/11 21:17, Peter Maydell wrote: On Thu, 11 Mar 2021 at 12:59, LIU Zhiwei wrote: From the specification, I find that software will not clean the pending bit on interrupt controller via a register write. "When a vectored interrupt is selected and serviced, the har

Re: Question about edge-triggered interrupt

On 2021/3/11 17:33, Peter Maydell wrote: On Thu, 11 Mar 2021 at 02:59, LIU Zhiwei wrote: Currently, I am writing an interrupt controller (CLIC) for RISC-V. I can't find a good way to process edge-triggered interrupt. According to edge-triggered definition, if I select an edge-triggered

Question about edge-triggered interrupt

Hi folks, Currently, I am writing an interrupt controller (CLIC) for RISC-V. I can't find a good way to process edge-triggered interrupt. According to edge-triggered definition, if I select an edge-triggered  interrupt to serve , it will clean its pending status. However after serving the

Re: [PATCH 00/38] target/riscv: support packed extension v0.9.2

ping On 2021/2/12 23:02, LIU Zhiwei wrote: This patchset implements the packed extension for RISC-V on QEMU. This patchset have passed all my direct Linux user mode cases(RV64) and bare metal cases(RV32) on X86-64 Ubuntu host machine. I will later push these test cases to my repo(https

Re: [PATCH 04/38] target/riscv: 16-bit Addition & Subtraction Instructions

On 2021/2/13 3:02, Richard Henderson wrote: On 2/12/21 7:02 AM, LIU Zhiwei wrote: +static void tcg_gen_simd_add16(TCGv d, TCGv a, TCGv b) +{ +TCGv t1 = tcg_temp_new(); +TCGv t2 = tcg_temp_new(); + +tcg_gen_andi_tl(t1, a, ~0x); +tcg_gen_add_tl(t2, a, b

Re: [PATCH 04/38] target/riscv: 16-bit Addition & Subtraction Instructions

On 2021/2/13 2:03, Richard Henderson wrote: On 2/12/21 7:02 AM, LIU Zhiwei wrote: +if (a->rd && a->rs1 && a->rs2) { +#ifdef TARGET_RISCV64 +f64(vece, offsetof(CPURISCVState, gpr[a->rd]), +offsetof(CPURISCVState, gpr[a->rs1]), +

[PATCH 38/38] target/riscv: configure and turn on packed extension from command line

on version, default value is v0.9.2. These properties can be specified with other values. Signed-off-by: LIU Zhiwei --- target/riscv/cpu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1b99f629ec..a94cef1cd1 100644 --- a/target/riscv/cpu.c +++ b/ta

[PATCH 37/38] target/riscv: RV64 Only 32-bit Packing Instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 5 +++ target/riscv/insn32-64.decode | 5 +++ target/riscv/insn_trans/trans_rvp.c.inc | 6 target/riscv/packed_helper.c| 41 + 4 files changed, 57 insertions(+) diff

[PATCH 36/38] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 2 ++ target/riscv/insn32-64.decode | 2 ++ target/riscv/insn_trans/trans_rvp.c.inc | 3 +++ target/riscv/packed_helper.c| 13 + 4 files changed, 20 insertions(+) diff --git a/target

[PATCH 35/38] target/riscv: RV64 Only 32-bit Parallel Multiply & Add Instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 12 ++ target/riscv/insn32-64.decode | 12 ++ target/riscv/insn_trans/trans_rvp.c.inc | 13 ++ target/riscv/packed_helper.c| 182 4 files changed, 219 insertions(+) diff

[PATCH 34/38] target/riscv: RV64 Only 32-bit Multiply & Add Instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 4 target/riscv/insn32-64.decode | 4 target/riscv/insn_trans/trans_rvp.c.inc | 5 target/riscv/packed_helper.c| 31 + 4 files changed, 44 insertions(+) diff

[PATCH 33/38] target/riscv: RV64 Only 32-bit Multiply Instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 3 +++ target/riscv/insn32-64.decode | 3 +++ target/riscv/insn_trans/trans_rvp.c.inc | 4 target/riscv/packed_helper.c| 19 +++ 4 files changed, 29 insertions(+) diff --git

[PATCH 32/38] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 10 ++ target/riscv/insn32-64.decode | 10 ++ target/riscv/insn_trans/trans_rvp.c.inc | 11 ++ target/riscv/packed_helper.c| 141 4 files changed, 172 insertions(+) diff

[PATCH 30/38] target/riscv: RV64 Only SIMD 32-bit Shift Instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 9 ++ target/riscv/insn32-64.decode | 15 target/riscv/insn_trans/trans_rvp.c.inc | 16 target/riscv/packed_helper.c| 104 4 files changed, 144 insertions(+) diff

[PATCH 31/38] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 6 +++ target/riscv/insn32-64.decode | 6 +++ target/riscv/insn_trans/trans_rvp.c.inc | 7 target/riscv/packed_helper.c| 55 + 4 files changed, 74 insertions(+) diff

[PATCH 29/38] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 30 +++ target/riscv/insn32-64.decode | 32 +++ target/riscv/insn_trans/trans_rvp.c.inc | 67 ++ target/riscv/packed_helper.c| 278 4 files changed, 407 insertions

[PATCH 28/38] target/riscv: Non-SIMD Miscellaneous Instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 6 + target/riscv/insn32.decode | 16 ++ target/riscv/insn_trans/trans_rvp.c.inc | 234 target/riscv/packed_helper.c| 77 4 files changed, 333 insertions

[PATCH 27/38] target/riscv: 32-bit Computation Instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 9 +++ target/riscv/insn32.decode | 9 +++ target/riscv/insn_trans/trans_rvp.c.inc | 10 +++ target/riscv/packed_helper.c| 92 + 4 files changed, 120 insertions(+) diff

[PATCH 26/38] target/riscv: Non-SIMD Q31 saturation ALU Instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 15 ++ target/riscv/insn32.decode | 16 ++ target/riscv/insn_trans/trans_rvp.c.inc | 17 ++ target/riscv/packed_helper.c| 214 4 files changed, 262 insertions(+) diff

[PATCH 25/38] target/riscv: Non-SIMD Q15 saturation ALU Instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 8 +++ target/riscv/insn32.decode | 8 +++ target/riscv/insn_trans/trans_rvp.c.inc | 12 target/riscv/packed_helper.c| 78 + 4 files changed, 106 insertions(+) diff

[PATCH 24/38] target/riscv: Signed 16-bit Multiply with 64-bit Add/Subtract Instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 11 ++ target/riscv/insn32.decode | 11 ++ target/riscv/insn_trans/trans_rvp.c.inc | 12 ++ target/riscv/packed_helper.c| 151 4 files changed, 185 insertions(+) diff

[PATCH 23/38] target/riscv: 32-bit Multiply 64-bit Add/Subtract Instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 9 ++ target/riscv/insn32.decode | 9 ++ target/riscv/insn_trans/trans_rvp.c.inc | 63 ++ target/riscv/packed_helper.c| 155 4 files changed, 236 insertions

[PATCH 22/38] target/riscv: 64-bit Add/Subtract Instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 11 ++ target/riscv/insn32.decode | 11 ++ target/riscv/insn_trans/trans_rvp.c.inc | 72 + target/riscv/packed_helper.c| 132 4 files changed, 226 insertions

[PATCH 21/38] target/riscv: 8-bit Multiply with 32-bit Add Instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 4 +++ target/riscv/insn32.decode | 4 +++ target/riscv/insn_trans/trans_rvp.c.inc | 5 +++ target/riscv/packed_helper.c| 44 + 4 files changed, 57 insertions(+) diff

[PATCH 20/38] target/riscv: Partial-SIMD Miscellaneous Instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 8 +++ target/riscv/insn32-64.decode | 4 -- target/riscv/insn32.decode | 10 target/riscv/insn_trans/trans_rvp.c.inc | 9 +++ target/riscv/packed_helper.c| 75

[PATCH 19/38] target/riscv: Signed 16-bit Multiply 64-bit Add/Subtract Instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 2 + target/riscv/insn32.decode | 2 + target/riscv/insn_trans/trans_rvp.c.inc | 54 + target/riscv/packed_helper.c| 25 4 files changed, 83 insertions(+) diff

[PATCH 18/38] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 19 ++ target/riscv/insn32.decode | 19 ++ target/riscv/insn_trans/trans_rvp.c.inc | 20 ++ target/riscv/packed_helper.c| 268 4 files changed, 326 insertions(+) diff

[PATCH 14/38] target/riscv: 8-bit Unpacking Instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 11 +++ target/riscv/insn32.decode | 11 +++ target/riscv/insn_trans/trans_rvp.c.inc | 12 +++ target/riscv/packed_helper.c| 121 4 files changed, 155 insertions(+) diff

[PATCH 17/38] target/riscv: Signed MSW 32x16 Multiply and Add Instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 17 ++ target/riscv/insn32.decode | 17 ++ target/riscv/insn_trans/trans_rvp.c.inc | 18 ++ target/riscv/packed_helper.c| 208 4 files changed, 260 insertions(+) diff

[PATCH 16/38] target/riscv: Signed MSW 32x32 Multiply and Add Instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 9 ++ target/riscv/insn32.decode | 9 ++ target/riscv/insn_trans/trans_rvp.c.inc | 44 ++ target/riscv/packed_helper.c| 109 4 files changed, 171 insertions

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