[PATCH 15/38] target/riscv: 16-bit Packing Instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 5 +++ target/riscv/insn32.decode | 5 +++ target/riscv/insn_trans/trans_rvp.c.inc | 9 + target/riscv/packed_helper.c| 45 + 4 files changed, 64 insertions(+) diff

[PATCH 13/38] target/riscv: SIMD 8-bit Miscellaneous Instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 12 +++ target/riscv/insn32.decode | 12 +++ target/riscv/insn_trans/trans_rvp.c.inc | 13 +++ target/riscv/packed_helper.c| 115 4 files changed, 152 insertions(+) diff

[PATCH 11/38] target/riscv: SIMD 8-bit Multiply Instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 7 ++ target/riscv/insn32.decode | 7 ++ target/riscv/insn_trans/trans_rvp.c.inc | 8 +++ target/riscv/packed_helper.c| 93 + 4 files changed, 115 insertions(+) diff --git

[PATCH 01/38] target/riscv: implementation-defined constant parameters

ext_p64 is whether to support Zp64 extension in RV32, default value is true. pext_ver is the packed specification version, default value is v0.9.2. Signed-off-by: LIU Zhiwei --- target/riscv/cpu.c | 29 + target/riscv/cpu.h | 6 ++ target/riscv

[PATCH 12/38] target/riscv: SIMD 16-bit Miscellaneous Instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 12 ++ target/riscv/insn32.decode | 13 ++ target/riscv/insn_trans/trans_rvp.c.inc | 42 ++ target/riscv/packed_helper.c| 167 4 files changed, 234 insertions(+) diff

[PATCH 09/38] target/riscv: SIMD 8-bit Compare Instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 6 target/riscv/insn32.decode | 6 target/riscv/insn_trans/trans_rvp.c.inc | 7 target/riscv/packed_helper.c| 46 + 4 files changed, 65 insertions(+) diff

[PATCH 10/38] target/riscv: SIMD 16-bit Multiply Instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 7 ++ target/riscv/insn32.decode | 7 ++ target/riscv/insn_trans/trans_rvp.c.inc | 53 target/riscv/packed_helper.c| 104 4 files changed, 171 insertions

[PATCH 08/38] target/riscv: SIMD 16-bit Compare Instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 6 target/riscv/insn32.decode | 6 target/riscv/insn_trans/trans_rvp.c.inc | 7 target/riscv/packed_helper.c| 46 + 4 files changed, 65 insertions(+) diff

[PATCH 06/38] target/riscv: SIMD 16-bit Shift Instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 9 ++ target/riscv/insn32.decode | 17 target/riscv/insn_trans/trans_rvp.c.inc | 115 target/riscv/packed_helper.c| 104 + 4 files changed, 245

[PATCH 07/38] target/riscv: SIMD 8-bit Shift Instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 9 +++ target/riscv/insn32.decode | 17 target/riscv/insn_trans/trans_rvp.c.inc | 16 target/riscv/packed_helper.c| 102 4 files changed, 144 insertions

[PATCH 05/38] target/riscv: 8-bit Addition & Subtraction Instruction

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 9 +++ target/riscv/insn32.decode | 11 target/riscv/insn_trans/trans_rvp.c.inc | 79 + target/riscv/packed_helper.c| 73 +++ 4 files changed, 172

[PATCH 04/38] target/riscv: 16-bit Addition & Subtraction Instructions

Include 5 groups: Wrap-around (dropping overflow), Signed Halving, Unsigned Halving, Signed Saturation, and Unsigned Saturation. Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 30 ++ target/riscv/insn32.decode | 32 +++ target/riscv/insn_trans

[PATCH 03/38] target/riscv: Fixup saturate subtract function

The overflow predication ((a - b) ^ a) & (a ^ b) & INT64_MIN is right. However, when the predication is ture and a is 0, it should return maximum. Signed-off-by: LIU Zhiwei --- target/riscv/vector_helper.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/targ

[PATCH 02/38] target/riscv: Hoist vector functions

The saturate functions about add,subtract and shift functions can be used in packed extension.Therefore hoist them up. The endianess process macro is also be hoisted. Signed-off-by: LIU Zhiwei --- target/riscv/internals.h | 50 ++ target/riscv/vector_helper.c | 82

[PATCH 00/38] target/riscv: support packed extension v0.9.2

Zp64. LIU Zhiwei (38): target/riscv: implementation-defined constant parameters target/riscv: Hoist vector functions target/riscv: Fixup saturate subtract function target/riscv: 16-bit Addition & Subtraction Instructions target/riscv: 8-bit Addition & Subtraction Instruction targ

Re: [PATCH 2/4] target/arm: Fixup contiguous first-fault and no-fault loads

On 2020/12/9 4:16, Richard Henderson wrote: On 12/6/20 10:46 PM, LIU Zhiwei wrote: First-fault or no-fault doesn't mean only access one page. But the implementation is *allowed* to access only one page. Thus the comment: -/* - * MemSingleNF is allowed to fail for any reason. We

[PATCH 4/4] target/arm: adjust CPTR_EL2 according to HCR_EL2.E2H

>From DDI0487Fc_armv8_arm.pdf, the CPTR_EL2 has two kinds of layouts according to HCR_EL2.E2H. When HCR_EL2.E2H is 1, fp_exception_el should refer to HCR_EL2.FPEN and sve_exception_el should refer to HCR_EL2.ZEN. Reviewed-by: Richard Henderson Signed-off-by: LIU Zhiwei --- target/arm/helpe

[PATCH 2/4] target/arm: Fixup contiguous first-fault and no-fault loads

First-fault or no-fault doesn't mean only access one page. When cross pages, for first-fault, if there is no fault in the first access, the second page should be accessed. And for no-fault, the second page should always be accessed. Signed-off-by: LIU Zhiwei --- target/arm/sve_helper.c | 35

[PATCH 0/4] target/arm bug fix

I found some bugs in target/arm. The first one is about SVE first-fault or no-fault load/store. The second is SIMD fcmla(by element). The third is about CPTR_EL2. I am not sure I really understand this code. Please confirm the patch set and let me know if I am wrong. LIU Zhiwei (4): target

[PATCH 3/4] target/arm: Fixup SIMD fcmla(by element) in 4H arrangement

For SIMD fcmla(by element), if the number of elements is less than the number of elements within one segment，i.e. 4H arrangement, we should not calculate the entire segment. Signed-off-by: LIU Zhiwei --- target/arm/vec_helper.c | 8 1 file changed, 8 insertions(+) diff --git a/target

[PATCH 1/4] target/arm: Fixup special cross page case for sve continuous load/store

If the split element is also the first active element of the vector, mem_off_first[0] should equal to mem_off_split. Signed-off-by: LIU Zhiwei --- target/arm/sve_helper.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c

Re: [PATCH v3 34/81] target/arm: Implement SVE2 WHILERW, WHILEWR

On 2020/9/19 2:37, Richard Henderson wrote: Signed-off-by: Richard Henderson --- v2: Fix decodetree typo --- target/arm/sve.decode | 3 ++ target/arm/translate-sve.c | 62 ++ 2 files changed, 65 insertions(+) diff --git a/target/arm/sve.decode

Re: [PATCH v3 45/81] target/arm: Implement SVE2 HISTCNT, HISTSEG

On 2020/9/19 2:37, Richard Henderson wrote: From: Stephen Long Signed-off-by: Stephen Long Message-Id: <20200416173109.8856-1-stepl...@quicinc.com> Signed-off-by: Richard Henderson --- v2: Fix overlap between output and input vectors. --- target/arm/helper-sve.h| 7 +++

Re: [PATCH v3 51/81] target/arm: Pass separate addend to {U, S}DOT helpers

On 2020/9/23 22:46, Richard Henderson wrote: On 9/23/20 3:01 AM, LIU Zhiwei wrote: On 2020/9/19 2:37, Richard Henderson wrote: For SVE, we potentially have a 4th argument coming from the movprfx instruction.  Currently we do not optimize movprfx, so the problem is not visible. Hi Richard

Re: [PATCH v3 51/81] target/arm: Pass separate addend to {U, S}DOT helpers

On 2020/9/19 2:37, Richard Henderson wrote: For SVE, we potentially have a 4th argument coming from the movprfx instruction. Currently we do not optimize movprfx, so the problem is not visible. Signed-off-by: Richard Henderson --- target/arm/helper.h | 20 +++---

Re: [PATCH v3 51/81] target/arm: Pass separate addend to {U, S}DOT helpers

On 2020/9/19 2:37, Richard Henderson wrote: For SVE, we potentially have a 4th argument coming from the movprfx instruction. Currently we do not optimize movprfx, so the problem is not visible. Hi Richard, I am a little confused.  If it is not immediately preceded by a MOVPRFX

Re: [PULL 00/18] riscv-to-apply queue

On 2020/8/26 6:30, Alistair Francis wrote: On Tue, Aug 25, 2020 at 2:50 PM Peter Maydell wrote: On Tue, 25 Aug 2020 at 22:32, Alistair Francis wrote: On Tue, Aug 25, 2020 at 2:24 PM Peter Maydell wrote: The hypervisor related patches don't seem to have any reviewed-by tags, which seems

Re: [PATCH] softfloat: Define comparison operations for bfloat16

emove the declarations. I see you have applied float16 comparison interfaces from Kito, and the corresponding bfloat16 interfaces have all been defined here. After remove the redundant declarations, Reviewed-by: LIU Zhiwei #define bfloat16_zero 0 #define bfloat16_half 0x3f00 #define bfloat16_one 0x3f80

[PATCH 1/3] fpu/softfloat: Define operations for bfloat16

This patch implements operations for bfloat16 except conversion and some misc operations. We also add FloatFmt and pack/unpack interfaces for bfloat16. As they are both static fields, we can't make a sperate patch for them. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- fpu

[PATCH 2/3] fpu/softfloat: Define convert operations for bfloat16

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- fpu/softfloat.c | 223 include/fpu/softfloat.h | 48 + 2 files changed, 271 insertions(+) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index d4205f92d5..afb121135d 100644

[PATCH 3/3] fpu/softfloat: Define misc operations for bfloat16

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- fpu/softfloat-specialize.inc.c | 38 +++ include/fpu/softfloat.h| 41 ++ 2 files changed, 79 insertions(+) diff --git a/fpu/softfloat-specialize.inc.c b/fpu

[PATCH 0/3] Implement blfoat16 in softfloat

As bfloat16 is more and more popular in many archs, implement bfloat16 interfaces in softfloat, so that archs can add their bfloat16 insns based on the blfoat16 interfaces here. These interfaces have been tested by RISU on RISC-V bfloat16 with XuanTie C906. LIU Zhiwei (3): fpu/softfloat

Re: [PATCH v3 00/13] RISC-V: Update the Hypervisor spec to v0.6.1

On 2020/8/13 3:13, Alistair Francis wrote: This series updates the experimental QEMU RISC-V Hypervisor spec to the v0.6.1 draft implementation. THis includes support for the new 2-stage lookup instructions and the new CSRs. It also includes the new 0.6.1 support for the virtual instruction

Re: [PULL 05/20] target/riscv: Check nanboxed inputs in trans_rvf.inc.c

Henderson Reviewed-by: LIU Zhiwei Message-Id: <20200724002807.441147-6-richard.hender...@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvf.inc.c | 71 +++-- target/riscv/translate.c| 18 +++ 2 files changed, 73 inse

[PATCH 1/1] target/arm: adjust CPTR_EL2 according to HCR_EL2.E2H

>From DDI0487Fc_armv8_arm.pdf, the CPTR_EL2 has two kinds of layouts according to HCR_EL2.E2H. When HCR_EL2.E2H is 1, fp_exception_el should refer to HCR_EL2.FPEN and sve_exception_el should refer to HCR_EL2.ZEN. Change-Id: If1c8f88db9fb505c36211ceafbf25e838ed96ec0 Signed-off-by: LIU Zhi

Re: [PATCH v2 5/7] target/riscv: Check nanboxed inputs in trans_rvf.inc.c

On 2020/8/8 22:18, LIU Zhiwei wrote: On 2020/8/8 4:24, Chih-Min Chao wrote: On Fri, Jul 24, 2020 at 8:28 AM Richard Henderson mailto:richard.hender...@linaro.org>> wrote: If a 32-bit input is not properly nanboxed, then the input is replaced with the default qnan.  Th

Re: [PATCH v2 5/7] target/riscv: Check nanboxed inputs in trans_rvf.inc.c

On 2020/8/8 4:24, Chih-Min Chao wrote: On Fri, Jul 24, 2020 at 8:28 AM Richard Henderson mailto:richard.hender...@linaro.org>> wrote: If a 32-bit input is not properly nanboxed, then the input is replaced with the default qnan.  The only inline expansion is for the sign-changing

Re: [PATCH v2 1/7] target/riscv: Generate nanboxed results from fp helpers

On 2020/8/6 16:42, Chih-Min Chao wrote: On Thu, Aug 6, 2020 at 3:05 PM LIU Zhiwei <mailto:zhiwei_...@c-sky.com>> wrote: On 2020/8/6 14:09, Chih-Min Chao wrote: On Fri, Jul 24, 2020 at 2:06 PM LIU Zhiwei mailto:zhiwei_...@c-sky.com>> wrote: On 2020/7/24

Re: [PATCH v2 1/7] target/riscv: Generate nanboxed results from fp helpers

On 2020/8/6 14:09, Chih-Min Chao wrote: On Fri, Jul 24, 2020 at 2:06 PM LIU Zhiwei <mailto:zhiwei_...@c-sky.com>> wrote: On 2020/7/24 11:55, Richard Henderson wrote: > On 7/23/20 7:35 PM, LIU Zhiwei wrote: >> >> On 2020/7/24 8:28, Richard Henderson

Re: [PATCH v2 1/7] target/riscv: Generate nanboxed results from fp helpers

On 2020/7/24 11:55, Richard Henderson wrote: On 7/23/20 7:35 PM, LIU Zhiwei wrote: On 2020/7/24 8:28, Richard Henderson wrote: Make sure that all results from single-precision scalar helpers are properly nan-boxed to 64-bits. Signed-off-by: Richard Henderson ---   target/riscv

Re: [PATCH v2 5/7] target/riscv: Check nanboxed inputs in trans_rvf.inc.c

n the canonical nan. + */ +static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) +{ +TCGv_i64 t_max = tcg_const_i64(0xull); +TCGv_i64 t_nan = tcg_const_i64(0x7fc0ull); + +tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); +tcg_temp_free_i64(t_max); +tcg

Re: [PATCH v2 4/7] target/riscv: Check nanboxed inputs to fp helpers

line float32 check_nanbox(uint64_t f, uint32_t flen) +{ +uint64_t mask = MAKE_64BIT_MASK(flen, 64 - flen); + +if (likely((f & mask) == mask)) { +return (uint32_t)f; +} else { +return (flen == 32) ? 0x7fc0u : 0x7e00u; /* default qnan */ +} +} + Reviewed-by: LI

Re: [PATCH v2 3/7] target/riscv: Generate nanboxed results from trans_rvf.inc.c

asContext *ctx, arg_fmv_w_x *a) #else tcg_gen_extu_i32_i64(cpu_fpr[a->rd], t0); #endif +gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]); mark_fs_dirty(ctx); tcg_temp_free(t0); Reviewed-by: LIU Zhiwei Zhiwei

Re: [PATCH v2 2/7] target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_s

(out, in, MAKE_64BIT_MASK(flen, 64 - flen)); +} + Reviewed-by: LIU Zhiwei Zhiwei static void generate_exception(DisasContext *ctx, int excp) { tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);

Re: [PATCH v2 1/7] target/riscv: Generate nanboxed results from fp helpers

); +} + So we can reuse it in fp16 or bf16 scalar instruction and in vector instructions. Reviewed-by: LIU Zhiwei Zhiwei #endif diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c index 4379756dc4..72541958a7 100644 --- a/target/riscv/fpu_helper.c +++ b/target/riscv/fpu_helper.c

Re: [PATCH v2 0/7] target/riscv: NaN-boxing for multiple precison

with flen is better in my opinion. So that it can be used everywhere, both in scalar and vector instructions, even the future fp16 or bf16 instructions. Zhiwei r~ LIU Zhiwei (2): target/riscv: Clean up fmv.w.x target/riscv: check before allocating TCG temps Richard Henderson (5): ta

Re: [PATCH 00/11] RISC-V risu porting

Ping. On 2020/7/12 0:16, LIU Zhiwei wrote: In contrast to the RFC, add more instructions description. Now it supports RV64IMACFD. Some cross verifications have been done, such as comparison between QEMU and TinyEMU, and comparison between QEMU and C906 FPGA. Now it has some productive

[PATCH 2/2] target/riscv: fix vector index load/store constraints

Although not explicitly specified that the the destination vector register groups cannot overlap the source vector register group, it is still necessary. And this constraint has been added to the v0.8 spec. Signed-off-by: LIU Zhiwei --- target/riscv/insn_trans/trans_rvv.inc.c | 10

[PATCH 1/2] target/riscv: Quiet Coverity complains about vamo*

Signed-off-by: LIU Zhiwei --- target/riscv/insn_trans/trans_rvv.inc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index c0b7375927..7b4752b911 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b

Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec

On 2020/7/14 21:59, Frank Chang wrote: On Tue, Jul 14, 2020 at 9:21 PM Richard Henderson mailto:richard.hender...@linaro.org>> wrote: On 7/13/20 7:59 PM, Frank Chang wrote: > The latest spec specified: > > Only the low *lg2(SEW) bits* are read to obtain the shift amount

Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec

On 2020/7/14 10:59, Frank Chang wrote: On Sat, Jul 11, 2020 at 12:27 AM Richard Henderson mailto:richard.hender...@linaro.org>> wrote: On 7/10/20 3:48 AM, frank.ch...@sifive.com wrote: > From: Frank Chang mailto:frank.ch...@sifive.com>> >

Re: [RFC PATCH 5/8] fpu/softfloat: define brain floating-point types

On 2020/7/14 3:26, Richard Henderson wrote: On 7/12/20 4:45 PM, LIU Zhiwei wrote: Signed-off-by: LIU Zhiwei --- include/fpu/softfloat-types.h | 8 1 file changed, 8 insertions(+) diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index 7680193ebc

Re: [RFC PATCH 2/8] fpu/softfloat: use the similiar logic to recognize sNaN and qNaN

On 2020/7/14 3:17, Richard Henderson wrote: On 7/12/20 4:45 PM, LIU Zhiwei wrote: Signed-off-by: LIU Zhiwei --- fpu/softfloat-specialize.inc.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/fpu/softfloat-specialize.inc.c b/fpu/softfloat-specialize.inc.c index

[RFC PATCH 6/8] fpu/softfloat: define operation for bfloat16

Signed-off-by: LIU Zhiwei --- fpu/softfloat.c | 146 +++- include/fpu/softfloat.h | 44 2 files changed, 189 insertions(+), 1 deletion(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 54fc889446..9a58107be3 100644 --- a/fpu

[RFC PATCH 3/8] fpu/softfloat: add FloatFmt for bfloat16

Signed-off-by: LIU Zhiwei --- fpu/softfloat.c | 4 1 file changed, 4 insertions(+) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 79be4f5840..1ef07d9160 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -554,6 +554,10 @@ static const FloatFmt float16_params_ahp

[RFC PATCH 2/8] fpu/softfloat: use the similiar logic to recognize sNaN and qNaN

Signed-off-by: LIU Zhiwei --- fpu/softfloat-specialize.inc.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/fpu/softfloat-specialize.inc.c b/fpu/softfloat-specialize.inc.c index 034d18199c..6b778a7830 100644 --- a/fpu/softfloat-specialize.inc.c +++ b/fpu/softfloat

[RFC PATCH 0/8] Implement blfoat16 in softfloat

! LIU Zhiwei (8): fpu/softfloat: fix up float16 nan recognition fpu/softfloat: use the similiar logic to recognize sNaN and qNaN fpu/softfloat: add FloatFmt for bfloat16 fpu/softfloat: add pack and unpack interfaces for bfloat16 fpu/softfloat: define brain floating-point types fpu

[RFC PATCH 5/8] fpu/softfloat: define brain floating-point types

Signed-off-by: LIU Zhiwei --- include/fpu/softfloat-types.h | 8 1 file changed, 8 insertions(+) diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index 7680193ebc..8f8fdfeecf 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h

[RFC PATCH 7/8] fpu/softfloat: define covert operation for bfloat16

Signed-off-by: LIU Zhiwei --- fpu/softfloat.c | 223 include/fpu/softfloat.h | 48 + 2 files changed, 271 insertions(+) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 9a58107be3..b6002d6856 100644 --- a/fpu/softfloat.c +++ b/fpu

[RFC PATCH 1/8] fpu/softfloat: fix up float16 nan recognition

Signed-off-by: LIU Zhiwei --- fpu/softfloat-specialize.inc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/fpu/softfloat-specialize.inc.c b/fpu/softfloat-specialize.inc.c index 44f5b661f8..034d18199c 100644 --- a/fpu/softfloat-specialize.inc.c +++ b/fpu/softfloat

[RFC PATCH 4/8] fpu/softfloat: add pack and unpack interfaces for bfloat16

Signed-off-by: LIU Zhiwei --- fpu/softfloat.c | 20 1 file changed, 20 insertions(+) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 1ef07d9160..54fc889446 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -584,6 +584,11 @@ static inline FloatParts

[RFC PATCH 8/8] fpu/softfloat: define misc operation for bfloat16

Signed-off-by: LIU Zhiwei --- fpu/softfloat-specialize.inc.c | 38 +++ include/fpu/softfloat.h| 41 ++ 2 files changed, 79 insertions(+) diff --git a/fpu/softfloat-specialize.inc.c b/fpu/softfloat-specialize.inc.c index

[PATCH 05/11] riscv: Add RV64D instructions description

For supporting multi-precison, split all 32 fp registers into two groups. The RV64D instructions will use only the 16 fp registers selected by gfp64(). Signed-off-by: LIU Zhiwei --- rv64.risu | 100 ++ 1 file changed, 100 insertions(+) diff

[PATCH 01/11] riscv: Add RV64I instructions description

Avoid using stack pointer(x2), thread pointer(x3), global pointer(x4), as they are not under control of risu. Besides, avoid using x0 as base address register, because we can't emit a valid random address by setting x0. Signed-off-by: LIU Zhiwei --- rv64.risu | 141

[PATCH 09/11] riscv: Define riscv struct reginfo

Signed-off-by: LIU Zhiwei --- risu_reginfo_riscv64.h | 28 1 file changed, 28 insertions(+) create mode 100644 risu_reginfo_riscv64.h diff --git a/risu_reginfo_riscv64.h b/risu_reginfo_riscv64.h new file mode 100644 index 000..4536480 --- /dev/null +++ b

[PATCH 08/11] riscv: Add standard test case

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- test_riscv64.s | 85 ++ 1 file changed, 85 insertions(+) create mode 100644 test_riscv64.s diff --git a/test_riscv64.s b/test_riscv64.s new file mode 100644 index 000..22a22b6

[PATCH 02/11] riscv: Add RV64M instructions description

Signed-off-by: LIU Zhiwei --- rv64.risu | 41 + 1 file changed, 41 insertions(+) diff --git a/rv64.risu b/rv64.risu index edf0d1f..2c4154e 100644 --- a/rv64.risu +++ b/rv64.risu @@ -139,3 +139,44 @@ SRLW RISCV 000 rs2:5 rs1:5 101 rd:5 0011011

[PATCH 07/11] riscv: Generate payload scripts

$bytecount to locate special float point values. 3. Use x10 as the special register pointing to the memory block. Signed-off-by: LIU Zhiwei --- risugen_riscv.pm | 643 +++ 1 file changed, 643 insertions(+) create mode 100644 risugen_riscv.pm diff --git

[PATCH 03/11] riscv: Add RV64A instructions description

Ensure $rs2 != $rs1, so that the $rs2 register's value will not be covered when setting the $rs1 register's value to get a valid address. Signed-off-by: LIU Zhiwei --- rv64.risu | 90 +++ 1 file changed, 90 insertions(+) diff --git a/rv64

[PATCH 11/11] riscv: Add configure script

For RV64 risu, make CFLAGS="-march=rv64g" Signed-off-by: LIU Zhiwei --- configure | 4 +- upstream/configure | 204 + 2 files changed, 207 insertions(+), 1 deletion(-) create mode 100644 upstream/configure diff --git a/c

[PATCH 06/11] riscv: Add RV64C instructions description

Make it a separate file, so that we can get subarch to recgonize the instrcution length. Signed-off-by: LIU Zhiwei --- rv64c.risu | 97 ++ 1 file changed, 97 insertions(+) create mode 100644 rv64c.risu diff --git a/rv64c.risu b/rv64c.risu

[PATCH 00/11] RISC-V risu porting

-precision float point. * support accurate special values generation. Todo: * support RVV and RVP. LIU Zhiwei (11): riscv: Add RV64I instructions description riscv: Add RV64M instructions description riscv: Add RV64A instructions description riscv: Add RV64F instructions description riscv

[PATCH 10/11] riscv: Implement payload load interfaces

When a risu op emits, the signal handler wll take over execution before running the payload again. The signal handler need some interfaces, such as setting struct reginfo and the comparison of struct reginfo. Signed-off-by: LIU Zhiwei --- risu_reginfo_riscv64.c | 132

[PATCH 04/11] riscv: Add RV64F instructions description

For supporting multi-precision, split all 32 fp registers into two groups. The RV64F instructions will use only 16 fp registers selected by gfp32(). Signed-off-by: LIU Zhiwei --- rv64.risu | 94 +++ 1 file changed, 94 insertions(+) diff --git

Re: [PATCH 0/6] target/riscv: NaN-boxing for multiple precison

On 2020/7/8 23:35, Richard Henderson wrote: On 7/7/20 2:45 PM, LIU Zhiwei wrote: On 2020/7/3 1:37, Richard Henderson wrote: I think it would be better to do all of the nan-boxing work inside of the helpers, including the return values. Do you mean a helper function just for nan-boxing work

Re: [PATCH 0/6] target/riscv: NaN-boxing for multiple precison

Hi Richard, Ping for other patches in this patch set. I may not get you ideas. Could you give more information? Zhiwei On 2020/7/3 20:33, LIU Zhiwei wrote: On 2020/7/3 1:37, Richard Henderson wrote: On 6/26/20 1:59 PM, LIU Zhiwei wrote: Multiple precison shoule be supported by NaN-boxing

Re: [PATCH v2 000/100] target/arm: Implement SVE2

On 2020/6/18 12:25, Richard Henderson wrote: I know this patch set is too big, and that there are parts that can be split out that are prepatory rather that specifically sve2. It's also not 100% tested. I have done some amount of testing vs ArmIE, but because of bugs and missing features

Re: [PULL v2 12/64] target/riscv: add vector amo operations

On 2020/7/7 4:48, Richard Henderson wrote: On 7/5/20 11:20 AM, Peter Maydell wrote: On Thu, 2 Jul 2020 at 17:33, Alistair Francis wrote: From: LIU Zhiwei Vector AMOs operate as if aq and rl bits were zero on each element with regard to ordering relative to other instructions in the same

Re: [PULL v2 12/64] target/riscv: add vector amo operations

On 2020/7/7 7:36, Alistair Francis wrote: On Sun, Jul 5, 2020 at 11:20 AM Peter Maydell wrote: On Thu, 2 Jul 2020 at 17:33, Alistair Francis wrote: From: LIU Zhiwei Vector AMOs operate as if aq and rl bits were zero on each element with regard to ordering relative to other instructions

Re: [PATCH] tcg: Fix do_nonatomic_op_* vs signed operations

On 2020/7/2 0:56, Richard Henderson wrote: The smin/smax/umin/umax operations require the operands to be properly sign extended. Do not drop the MO_SIGN bit from the load, and additionally extend the val input. Reported-by: LIU Zhiwei Signed-off-by: Richard Henderson --- tcg/tcg-op.c

Re: [PATCH 1/1] tcg/tcg-op: nonatomic_op should work with smaller memop

On 2020/7/2 0:25, Richard Henderson wrote: On 7/1/20 8:21 AM, LIU Zhiwei wrote: -tcg_gen_qemu_ld_i32(t1, addr, idx, memop & ~MO_SIGN); +tcg_gen_qemu_ld_i32(t1, addr, idx, memop); +tcg_gen_ext_i32(val, val, memop); gen(t2, t1, val); I was just about to post a simiar p

[PATCH v12 61/61] target/riscv: configure and turn on vector extension from command line

s, default value is 64 bit. vext_spec is the vector specification version, default value is v0.7.1. These properties can be specified with other values. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/

[PATCH v12 60/61] target/riscv: vector compress instruction

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 5 target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 32 + target/riscv/vector_helper.c| 26

[PATCH v12 59/61] target/riscv: vector register gather instruction

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 9 +++ target/riscv/insn32.decode | 3 + target/riscv/insn_trans/trans_rvv.inc.c | 78 + target/riscv/vector_helper.c| 60

[PATCH v12 58/61] target/riscv: vector slide instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 17 target/riscv/insn32.decode | 6 ++ target/riscv/insn_trans/trans_rvv.inc.c | 18 target/riscv/vector_helper.c| 114 4 files

[PATCH v12 57/61] target/riscv: floating-point scalar move instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 3 ++ target/riscv/insn_trans/trans_rvv.inc.c | 49 + 2 files changed, 52 insertions(+) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index

[PATCH v12 56/61] target/riscv: integer scalar move instruction

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 60 + target/riscv/internals.h| 6 +++ 3 files changed, 67 insertions(+) diff --git a/target/riscv

[PATCH v12 55/61] target/riscv: integer extract instruction

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 116 2 files changed, 117 insertions(+) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index

[PATCH v12 54/61] target/riscv: vector element index instruction

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 5 + target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/trans_rvv.inc.c | 25 + target/riscv/vector_helper.c| 24

[PATCH v12 53/61] target/riscv: vector iota instruction

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 5 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 27 +++ target/riscv/vector_helper.c| 29

[PATCH v12 52/61] target/riscv: set-X-first mask bit

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 4 ++ target/riscv/insn32.decode | 3 ++ target/riscv/insn_trans/trans_rvv.inc.c | 28 +++ target/riscv/vector_helper.c| 63 + 4

[PATCH v12 51/61] target/riscv: vmfirst find-first-set mask bit

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 2 ++ target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 32 + target/riscv/vector_helper.c| 19 +++ 4

[PATCH v12 50/61] target/riscv: vector mask population count vmpopc

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 2 ++ target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 32 + target/riscv/vector_helper.c| 20 4

[PATCH v12 49/61] target/riscv: vector mask-register logical instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 9 ++ target/riscv/insn32.decode | 8 + target/riscv/insn_trans/trans_rvv.inc.c | 35 ++ target/riscv/vector_helper.c| 40

[PATCH v12 48/61] target/riscv: vector widening floating-point reduction instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 3 ++ target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/trans_rvv.inc.c | 3 ++ target/riscv/vector_helper.c| 46

[PATCH v12 47/61] target/riscv: vector single-width floating-point reduction instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 10 +++ target/riscv/insn32.decode | 4 +++ target/riscv/insn_trans/trans_rvv.inc.c | 5 target/riscv/vector_helper.c| 39

[PATCH v12 46/61] target/riscv: vector wideing integer reduction instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 7 +++ target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/trans_rvv.inc.c | 4 target/riscv/vector_helper.c| 11

[PATCH v12 45/61] target/riscv: vector single-width integer reduction instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 33 +++ target/riscv/insn32.decode | 8 +++ target/riscv/insn_trans/trans_rvv.inc.c | 18 ++ target/riscv/vector_helper.c

[PATCH v12 44/61] target/riscv: narrowing floating-point/integer type-convert instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 11 ++ target/riscv/insn32.decode | 5 +++ target/riscv/insn_trans/trans_rvv.inc.c | 48 + target/riscv/vector_helper.c

[PATCH v12 43/61] target/riscv: widening floating-point/integer type-convert instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 11 ++ target/riscv/insn32.decode | 5 +++ target/riscv/insn_trans/trans_rvv.inc.c | 48 + target/riscv/vector_helper.c

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