[PATCH v11 16/61] target/riscv: vector integer comparison instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 57 +++ target/riscv/insn32.decode | 20 target/riscv/insn_trans/trans_rvv.inc.c | 46 + target/riscv/vector_helper.c

[PATCH v11 18/61] target/riscv: vector single-width integer multiply instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/helper.h | 33 + target/riscv/insn32.decode | 8 ++ target/riscv/insn_trans/trans_rvv.inc.c | 10 ++ target/riscv/vector_helper.c| 163

[PATCH v11 21/61] target/riscv: vector single-width integer multiply-add instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 33 ++ target/riscv/insn32.decode | 8 +++ target/riscv/insn_trans/trans_rvv.inc.c | 10 +++ target/riscv/vector_helper.c| 88

[PATCH v11 24/61] target/riscv: vector single-width saturating add and subtract

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 33 ++ target/riscv/insn32.decode | 10 + target/riscv/insn_trans/trans_rvv.inc.c | 16 + target/riscv/vector_helper.c| 385

[PATCH v11 23/61] target/riscv: vector integer merge and move instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/helper.h | 17 target/riscv/insn32.decode | 7 ++ target/riscv/insn_trans/trans_rvv.inc.c | 113 target/riscv/vector_helper.c

[PATCH v11 26/61] target/riscv: vector single-width fractional multiply with rounding and saturation

Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/helper.h | 9 ++ target/riscv/insn32.decode | 2 + target/riscv/insn_trans/trans_rvv.inc.c | 4 + target/riscv/vector_helper.c| 107

[PATCH v11 28/61] target/riscv: vector single-width scaling shift instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 17 target/riscv/insn32.decode | 6 ++ target/riscv/insn_trans/trans_rvv.inc.c | 8 ++ target/riscv/vector_helper.c| 117

[PATCH v11 30/61] target/riscv: vector single-width floating-point add/subtract instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 16 target/riscv/insn32.decode | 5 + target/riscv/insn_trans/trans_rvv.inc.c | 118 target/riscv/vector_helper.c

[PATCH v11 32/61] target/riscv: vector single-width floating-point multiply/divide instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 16 target/riscv/insn32.decode | 5 +++ target/riscv/insn_trans/trans_rvv.inc.c | 7 target/riscv/vector_helper.c| 49

[PATCH v9 59/61] target/riscv: vector register gather instruction

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 9 +++ target/riscv/insn32.decode | 3 + target/riscv/insn_trans/trans_rvv.inc.c | 78 + target/riscv/vector_helper.c| 60

[PATCH v9 60/61] target/riscv: vector compress instruction

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 5 target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 32 + target/riscv/vector_helper.c| 26

[PATCH v9 51/61] target/riscv: vmfirst find-first-set mask bit

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 2 ++ target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 32 + target/riscv/vector_helper.c| 19 +++ 4

[PATCH v9 56/61] target/riscv: integer scalar move instruction

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 60 + target/riscv/internals.h| 6 +++ 3 files changed, 67 insertions(+) diff --git a/target/riscv

[PATCH v9 53/61] target/riscv: vector iota instruction

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 5 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 27 +++ target/riscv/vector_helper.c| 29

[PATCH v9 54/61] target/riscv: vector element index instruction

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 5 + target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/trans_rvv.inc.c | 25 + target/riscv/vector_helper.c| 24

[PATCH v9 58/61] target/riscv: vector slide instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 17 target/riscv/insn32.decode | 7 ++ target/riscv/insn_trans/trans_rvv.inc.c | 18 target/riscv/vector_helper.c| 114 4 files

[PATCH v9 57/61] target/riscv: floating-point scalar move instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 2 + target/riscv/insn_trans/trans_rvv.inc.c | 49 + 2 files changed, 51 insertions(+) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index

[PATCH v9 55/61] target/riscv: integer extract instruction

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 116 2 files changed, 117 insertions(+) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index

[PATCH v9 61/61] target/riscv: configure and turn on vector extension from command line

s, default value is 64 bit. vext_spec is the vector specification version, default value is v0.7.1. These properties can be specified with other values. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/

[PATCH v9 52/61] target/riscv: set-X-first mask bit

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 4 ++ target/riscv/insn32.decode | 3 ++ target/riscv/insn_trans/trans_rvv.inc.c | 28 +++ target/riscv/vector_helper.c| 63 + 4

[PATCH v9 50/61] target/riscv: vector mask population count vmpopc

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 2 ++ target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 32 + target/riscv/vector_helper.c| 20 4

[PATCH v9 02/61] target/riscv: implementation-defined constant parameters

vlen is the vector register length in bits. elen is the max element size in bits. vext_spec is the vector specification version, default value is v0.7.1. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/cpu.c | 7 +++ target/riscv

[PATCH v9 04/61] target/riscv: add vector configure instruction

vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags should update after configure instructions. The (ill, lmul, sew ) of vtype and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis

[PATCH v9 03/61] target/riscv: support vector extension csr

The v0.7.1 specification does not define vector status within mstatus. A future revision will define the privileged portion of the vector status. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/cpu_bits.h | 15 + target/riscv

[PATCH v9 12/61] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/helper.h | 33 ++ target/riscv/insn32.decode | 11 ++ target/riscv/insn_trans/trans_rvv.inc.c | 113 +++ target/riscv/vector_helper.c

[PATCH v9 16/61] target/riscv: vector integer comparison instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 57 +++ target/riscv/insn32.decode | 20 target/riscv/insn_trans/trans_rvv.inc.c | 46 + target/riscv/vector_helper.c

[PATCH v9 21/61] target/riscv: vector single-width integer multiply-add instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 33 ++ target/riscv/insn32.decode | 8 +++ target/riscv/insn_trans/trans_rvv.inc.c | 10 +++ target/riscv/vector_helper.c| 88

[PATCH v9 23/61] target/riscv: vector integer merge and move instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/helper.h | 17 target/riscv/insn32.decode | 7 ++ target/riscv/insn_trans/trans_rvv.inc.c | 113 target/riscv/vector_helper.c

[PATCH v9 39/61] target/riscv: vector floating-point compare instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Richard Henderson --- target/riscv/helper.h | 37 + target/riscv/insn32.decode | 12 ++ target/riscv/insn_trans/trans_rvv.inc.c | 35 + target/riscv/vector_helper.c| 174

[PATCH v9 49/61] target/riscv: vector mask-register logical instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 9 ++ target/riscv/insn32.decode | 8 + target/riscv/insn_trans/trans_rvv.inc.c | 35 ++ target/riscv/vector_helper.c| 40

[PATCH v9 01/61] target/riscv: add vector extension field in CPURISCVState

The 32 vector registers will be viewed as a continuous memory block. It avoids the convension between element index and (regno, offset). Thus elements can be directly accessed by offset from the first vector base address. Signed-off-by: LIU Zhiwei Acked-by: Alistair Francis Reviewed-by: Richard

[PATCH v9 05/61] target/riscv: add an internals.h header

The internals.h keeps things that are not relevant to the actual architecture, only to the implementation, separate. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/internals.h | 24 1 file changed, 24 insertions

[PATCH v9 11/61] target/riscv: vector widening integer add and subtract

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 49 +++ target/riscv/insn32.decode | 16 ++ target/riscv/insn_trans/trans_rvv.inc.c | 186 target/riscv

[PATCH v9 17/61] target/riscv: vector integer min/max instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 33 target/riscv/insn32.decode | 8 +++ target/riscv/insn_trans/trans_rvv.inc.c | 10 target/riscv/vector_helper.c

[PATCH v9 32/61] target/riscv: vector single-width floating-point multiply/divide instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 16 target/riscv/insn32.decode | 5 +++ target/riscv/insn_trans/trans_rvv.inc.c | 7 target/riscv/vector_helper.c| 49

[PATCH v9 25/61] target/riscv: vector single-width averaging add and subtract

Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/helper.h | 17 target/riscv/insn32.decode | 5 ++ target/riscv/insn_trans/trans_rvv.inc.c | 7 ++ target/riscv/vector_helper.c| 100

[PATCH v9 31/61] target/riscv: vector widening floating-point add/subtract instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 17 +++ target/riscv/insn32.decode | 8 ++ target/riscv/insn_trans/trans_rvv.inc.c | 149 target/riscv/vector_helper.c

[PATCH v9 35/61] target/riscv: vector widening floating-point fused multiply-add instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 17 + target/riscv/insn32.decode | 8 +++ target/riscv/insn_trans/trans_rvv.inc.c | 10 +++ target/riscv/vector_helper.c| 91

[PATCH v9 34/61] target/riscv: vector single-width floating-point fused multiply-add instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 49 + target/riscv/insn32.decode | 16 ++ target/riscv/insn_trans/trans_rvv.inc.c | 18 ++ target/riscv/vector_helper.c| 251

[PATCH v9 42/61] target/riscv: vector floating-point/integer type-convert instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 13 ++ target/riscv/insn32.decode | 4 +++ target/riscv/insn_trans/trans_rvv.inc.c | 6 + target/riscv/vector_helper.c| 33

[PATCH v9 45/61] target/riscv: vector single-width integer reduction instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 33 +++ target/riscv/insn32.decode | 8 +++ target/riscv/insn_trans/trans_rvv.inc.c | 18 ++ target/riscv/vector_helper.c

[PATCH v9 00/61] target/riscv: support vector extension v0.7.1

LIU Zhiwei (61): target/riscv: add vector extension field in CPURISCVState target/riscv: implementation-defined constant parameters target/riscv: support vector extension csr target/riscv: add vector configure instruction target/riscv: add an internals.h header target/riscv: add vector

[PATCH v9 07/61] target/riscv: add vector index load and store instructions

Vector indexed operations add the contents of each element of the vector offset operand specified by vs2 to the base effective address to give the effective address of each element. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv

[PATCH v9 10/61] target/riscv: vector single-width integer add and subtract

Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/helper.h | 25 ++ target/riscv/insn32.decode | 10 + target/riscv/insn_trans/trans_rvv.inc.c | 291 target/riscv/vector_helper.c

[PATCH v9 28/61] target/riscv: vector single-width scaling shift instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 17 target/riscv/insn32.decode | 6 ++ target/riscv/insn_trans/trans_rvv.inc.c | 8 ++ target/riscv/vector_helper.c| 117

[PATCH v9 20/61] target/riscv: vector widening integer multiply instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 19 + target/riscv/insn32.decode | 6 +++ target/riscv/insn_trans/trans_rvv.inc.c | 8 target/riscv/vector_helper.c| 51

[PATCH v9 27/61] target/riscv: vector widening saturating scaled multiply-add

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 22 +++ target/riscv/insn32.decode | 7 + target/riscv/insn_trans/trans_rvv.inc.c | 9 ++ target/riscv/vector_helper.c| 205

[PATCH v9 22/61] target/riscv: vector widening integer multiply-add instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 22 target/riscv/insn32.decode | 7 target/riscv/insn_trans/trans_rvv.inc.c | 9 + target/riscv/vector_helper.c

[PATCH v9 36/61] target/riscv: vector floating-point square-root instruction

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 4 +++ target/riscv/insn32.decode | 3 ++ target/riscv/insn_trans/trans_rvv.inc.c | 43 + target/riscv/vector_helper.c

[PATCH v9 41/61] target/riscv: vector floating-point merge instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/helper.h | 4 +++ target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/trans_rvv.inc.c | 38 + target/riscv/vector_helper.c

[PATCH v9 09/61] target/riscv: add vector amo operations

Vector AMOs operate as if aq and rl bits were zero on each element with regard to ordering relative to other instructions in the same hart. Vector AMOs provide no ordering guarantee between element operations in the same vector AMO instruction Signed-off-by: LIU Zhiwei Reviewed-by: Alistair

[PATCH v9 14/61] target/riscv: vector single-width bit shift instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 25 target/riscv/insn32.decode | 9 +++ target/riscv/insn_trans/trans_rvv.inc.c | 52 target/riscv/vector_helper.c

[PATCH v9 19/61] target/riscv: vector integer divide instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 33 +++ target/riscv/insn32.decode | 8 +++ target/riscv/insn_trans/trans_rvv.inc.c | 10 target/riscv/vector_helper.c| 74

[PATCH v9 29/61] target/riscv: vector narrowing fixed-point clip instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 13 +++ target/riscv/insn32.decode | 6 + target/riscv/insn_trans/trans_rvv.inc.c | 8 ++ target/riscv/vector_helper.c| 141

[PATCH v9 26/61] target/riscv: vector single-width fractional multiply with rounding and saturation

Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/helper.h | 9 ++ target/riscv/insn32.decode | 2 + target/riscv/insn_trans/trans_rvv.inc.c | 4 + target/riscv/vector_helper.c| 107

[PATCH v9 37/61] target/riscv: vector floating-point min/max instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 13 target/riscv/insn32.decode | 4 target/riscv/insn_trans/trans_rvv.inc.c | 6 ++ target/riscv/vector_helper.c

[PATCH v9 40/61] target/riscv: vector floating-point classify instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/fpu_helper.c | 33 + target/riscv/helper.h | 4 ++ target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 3

[PATCH v9 43/61] target/riscv: widening floating-point/integer type-convert instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 11 ++ target/riscv/insn32.decode | 5 +++ target/riscv/insn_trans/trans_rvv.inc.c | 48 + target/riscv/vector_helper.c

[PATCH v9 47/61] target/riscv: vector single-width floating-point reduction instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 10 +++ target/riscv/insn32.decode | 4 +++ target/riscv/insn_trans/trans_rvv.inc.c | 5 target/riscv/vector_helper.c| 39

[PATCH v9 06/61] target/riscv: add vector stride load and store instructions

the base effective address. It can been seen as a special case of strided operations. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 105 ++ target/riscv/insn32.decode | 32 ++ target/riscv

[PATCH v9 08/61] target/riscv: add fault-only-first unit stride load

The unit-stride fault-only-fault load instructions are used to vectorize loops with data-dependent exit conditions(while loops). These instructions execute as a regular load except that they will only take a trap on element 0. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed

[PATCH v9 15/61] target/riscv: vector narrowing integer right shift instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 13 target/riscv/insn32.decode | 6 ++ target/riscv/insn_trans/trans_rvv.inc.c | 90 + target/riscv/vector_helper.c

[PATCH v9 13/61] target/riscv: vector bitwise logical instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 25 target/riscv/insn32.decode | 9 + target/riscv/insn_trans/trans_rvv.inc.c | 11 ++ target/riscv/vector_helper.c

[PATCH v9 18/61] target/riscv: vector single-width integer multiply instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/helper.h | 33 + target/riscv/insn32.decode | 8 ++ target/riscv/insn_trans/trans_rvv.inc.c | 10 ++ target/riscv/vector_helper.c| 163

[PATCH v9 30/61] target/riscv: vector single-width floating-point add/subtract instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 16 target/riscv/insn32.decode | 5 + target/riscv/insn_trans/trans_rvv.inc.c | 118 target/riscv/vector_helper.c

[PATCH v9 24/61] target/riscv: vector single-width saturating add and subtract

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 33 ++ target/riscv/insn32.decode | 10 + target/riscv/insn_trans/trans_rvv.inc.c | 16 + target/riscv/vector_helper.c| 385

[PATCH v9 33/61] target/riscv: vector widening floating-point multiply

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 5 + target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/trans_rvv.inc.c | 4 target/riscv/vector_helper.c| 22

[PATCH v9 38/61] target/riscv: vector floating-point sign-injection instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 19 ++ target/riscv/insn32.decode | 6 ++ target/riscv/insn_trans/trans_rvv.inc.c | 8 +++ target/riscv/vector_helper.c| 85

[PATCH v9 44/61] target/riscv: narrowing floating-point/integer type-convert instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 11 ++ target/riscv/insn32.decode | 5 +++ target/riscv/insn_trans/trans_rvv.inc.c | 48 + target/riscv/vector_helper.c

[PATCH v9 46/61] target/riscv: vector wideing integer reduction instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 7 +++ target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/trans_rvv.inc.c | 4 target/riscv/vector_helper.c| 11

[PATCH v9 48/61] target/riscv: vector widening floating-point reduction instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 3 ++ target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/trans_rvv.inc.c | 3 ++ target/riscv/vector_helper.c| 46

Re: [PATCH v5 07/11] hw/char: Initial commit of Ibex UART

On 2020/6/3 1:54, Alistair Francis wrote: On Tue, Jun 2, 2020 at 5:28 AM LIU Zhiwei wrote: Hi Alistair, There are still some questions I don't understand. 1. Is the baud rate or fifo a necessary feature to simulate? As you can see, qemu_chr_fe_write will send the byte as soon as possible

Re: hw/char: a question about watch callback function in serial

On 2020/6/5 10:19, LIU Zhiwei wrote: On 2020/6/4 21:32, Peter Maydell wrote: On Thu, 4 Jun 2020 at 13:15, LIU Zhiwei wrote: I see many UART implementations have a G_IO_OUT | G_IO_HUP callback function. In hw/serial.c, it is serial_watch_cb, setting by the following code, s

Re: [PATCH v8 30/62] target/riscv: Update fp_status when float rounding mode changes

On 2020/6/5 11:30, Richard Henderson wrote: On 6/4/20 7:50 PM, LIU Zhiwei wrote: So no scalar insns will require changes within a translation block. Not true -- scalar insns can encode rm into the instruction. I think there is a error in gen_set_rm static void gen_set_rm(DisasContext

fpu/softfloat: a question on BFloat 16 support on QEMU

Hi Richard, I am doing bfloat16 support on QEMU. Once I tried to reuse float32 interface, but I couldn't properly process rounding in some insns like fadd. What's your opinion about it? Should I expand the fpu/softfloat? Best Regards, Zhiwei

Re: fpu/softfloat: a question on BFloat 16 support on QEMU

On 2020/6/9 17:42, Alex Bennée wrote: LIU Zhiwei writes: On 2020/6/8 23:50, Alex Bennée wrote: LIU Zhiwei writes: Hi Richard, I am doing bfloat16 support on QEMU. Once I tried to reuse float32 interface, but I couldn't properly process rounding in some insns like fadd. What do you

Re: [PATCH v8 58/62] target/riscv: floating-point scalar move instructions

On 2020/6/5 5:32, Richard Henderson wrote: On 5/21/20 2:44 AM, LIU Zhiwei wrote: +static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a) +{ +if (!s->vill && has_ext(s, RVF) && +(s->mstatus_fs != 0) && (s->sew != 0)) { +

Re: hw/char: a question about watch callback function in serial

On 2020/6/4 21:32, Peter Maydell wrote: On Thu, 4 Jun 2020 at 13:15, LIU Zhiwei wrote: I see many UART implementations have a G_IO_OUT | G_IO_HUP callback function. In hw/serial.c, it is serial_watch_cb, setting by the following code, s->watch_tag = qemu_chr_fe_add_watch(>chr, G_

Re: [PATCH v8 40/62] target/riscv: vector floating-point compare instructions

On 2020/6/5 4:51, Richard Henderson wrote: On 5/21/20 2:43 AM, LIU Zhiwei wrote: +static uint8_t float16_eq_quiet(uint16_t a, uint16_t b, float_status *s) Return bool, better than uint8_t. Yes. +{ +int compare = float16_compare_quiet(a, b, s); New since your last revision

Re: [PATCH v8 30/62] target/riscv: Update fp_status when float rounding mode changes

On 2020/6/5 4:15, Richard Henderson wrote: On 6/2/20 10:46 PM, LIU Zhiwei wrote: I think you are right.  Maybe I should transmit frm to ctx->frm, and check ctx->frm in vector fp ops. We can set ctx->frm = env->frm instead of ctx->frm = -1 in riscv_tr_init_disas_conte

Re: [PATCH v9 39/61] target/riscv: vector floating-point compare instructions

On 2020/6/11 1:33, Richard Henderson wrote: On 6/10/20 4:37 AM, LIU Zhiwei wrote: Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Richard Henderson --- Missed the actual "Reviewed-by:" :-) I tried to make a reasonable explanation, but failed:-). "Reviewed-by: &qu

Re: [PATCH v5 07/11] hw/char: Initial commit of Ibex UART

On 2020/6/4 12:35, Alistair Francis wrote: On Wed, Jun 3, 2020 at 6:59 PM LIU Zhiwei wrote: On 2020/6/3 23:56, Alistair Francis wrote: On Wed, Jun 3, 2020 at 3:33 AM LIU Zhiwei wrote: On 2020/6/3 1:54, Alistair Francis wrote: On Tue, Jun 2, 2020 at 5:28 AM LIU Zhiwei wrote: Hi

Re: [PATCH v5 07/11] hw/char: Initial commit of Ibex UART

On 2020/6/4 12:35, Alistair Francis wrote: On Wed, Jun 3, 2020 at 6:59 PM LIU Zhiwei wrote: On 2020/6/3 23:56, Alistair Francis wrote: On Wed, Jun 3, 2020 at 3:33 AM LIU Zhiwei wrote: On 2020/6/3 1:54, Alistair Francis wrote: On Tue, Jun 2, 2020 at 5:28 AM LIU Zhiwei wrote: Hi

Re: [PATCH v5 07/11] hw/char: Initial commit of Ibex UART

On 2020/6/3 23:56, Alistair Francis wrote: On Wed, Jun 3, 2020 at 3:33 AM LIU Zhiwei wrote: On 2020/6/3 1:54, Alistair Francis wrote: On Tue, Jun 2, 2020 at 5:28 AM LIU Zhiwei wrote: Hi Alistair, There are still some questions I don't understand. 1. Is the baud rate or fifo

hw/char: a question about watch callback function in serial

Hi folks, I see many UART implementations have a G_IO_OUT | G_IO_HUP  callback function. In hw/serial.c, it is serial_watch_cb, setting by the following code,   s->watch_tag = qemu_chr_fe_add_watch(>chr, G_IO_OUT | G_IO_HUP,   serial_watch_cb, s); In hw/candence_uart.c,

Re: [PATCH v8 30/62] target/riscv: Update fp_status when float rounding mode changes

On 2020/6/3 12:27, Richard Henderson wrote: On 5/21/20 2:43 AM, LIU Zhiwei wrote: @@ -174,6 +175,9 @@ static int write_frm(CPURISCVState *env, int csrno, target_ulong val) env->mstatus |= MSTATUS_FS; #endif env->frm = val & (FSR_RD >&

Re: fpu/softfloat: a question on BFloat 16 support on QEMU

On 2020/6/8 23:50, Alex Bennée wrote: LIU Zhiwei writes: Hi Richard, I am doing bfloat16 support on QEMU. Once I tried to reuse float32 interface, but I couldn't properly process rounding in some insns like fadd. What do you mean by re-use the float32 interface? Once I think bfloat16

Re: fpu/softfloat: a question on BFloat 16 support on QEMU

On 2020/6/9 3:34, Richard Henderson wrote: On 6/8/20 5:53 AM, LIU Zhiwei wrote: Hi Richard, I am doing bfloat16 support on QEMU. Once I tried to reuse float32 interface, but I couldn't properly process rounding in some insns like fadd. What's your opinion about it? Should I expand the fpu

[PATCH 1/2] target/riscv: Quiet Coverity complains about vamo*

Signed-off-by: LIU Zhiwei --- target/riscv/insn_trans/trans_rvv.inc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index c0b7375927..7b4752b911 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b

[PATCH 2/2] target/riscv: fix vector index load/store constraints

Although not explicitly specified that the the destination vector register groups cannot overlap the source vector register group, it is still necessary. And this constraint has been added to the v0.8 spec. Signed-off-by: LIU Zhiwei --- target/riscv/insn_trans/trans_rvv.inc.c | 10

Re: [PATCH v2 3/7] target/riscv: Generate nanboxed results from trans_rvf.inc.c

asContext *ctx, arg_fmv_w_x *a) #else tcg_gen_extu_i32_i64(cpu_fpr[a->rd], t0); #endif +gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]); mark_fs_dirty(ctx); tcg_temp_free(t0); Reviewed-by: LIU Zhiwei Zhiwei

Re: [PATCH v2 2/7] target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_s

(out, in, MAKE_64BIT_MASK(flen, 64 - flen)); +} + Reviewed-by: LIU Zhiwei Zhiwei static void generate_exception(DisasContext *ctx, int excp) { tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);

Re: [PATCH v2 4/7] target/riscv: Check nanboxed inputs to fp helpers

line float32 check_nanbox(uint64_t f, uint32_t flen) +{ +uint64_t mask = MAKE_64BIT_MASK(flen, 64 - flen); + +if (likely((f & mask) == mask)) { +return (uint32_t)f; +} else { +return (flen == 32) ? 0x7fc0u : 0x7e00u; /* default qnan */ +} +} + Reviewed-by: LI

Re: [PATCH v2 0/7] target/riscv: NaN-boxing for multiple precison

with flen is better in my opinion. So that it can be used everywhere, both in scalar and vector instructions, even the future fp16 or bf16 instructions. Zhiwei r~ LIU Zhiwei (2): target/riscv: Clean up fmv.w.x target/riscv: check before allocating TCG temps Richard Henderson (5): ta

Re: [PATCH v2 1/7] target/riscv: Generate nanboxed results from fp helpers

On 2020/7/24 11:55, Richard Henderson wrote: On 7/23/20 7:35 PM, LIU Zhiwei wrote: On 2020/7/24 8:28, Richard Henderson wrote: Make sure that all results from single-precision scalar helpers are properly nan-boxed to 64-bits. Signed-off-by: Richard Henderson ---   target/riscv

Re: [PATCH v2 5/7] target/riscv: Check nanboxed inputs in trans_rvf.inc.c

n the canonical nan. + */ +static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) +{ +TCGv_i64 t_max = tcg_const_i64(0xull); +TCGv_i64 t_nan = tcg_const_i64(0x7fc0ull); + +tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); +tcg_temp_free_i64(t_max); +tcg

Re: [PATCH v2 1/7] target/riscv: Generate nanboxed results from fp helpers

); +} + So we can reuse it in fp16 or bf16 scalar instruction and in vector instructions. Reviewed-by: LIU Zhiwei Zhiwei #endif diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c index 4379756dc4..72541958a7 100644 --- a/target/riscv/fpu_helper.c +++ b/target/riscv/fpu_helper.c

Re: [PULL v2 12/64] target/riscv: add vector amo operations

On 2020/7/7 7:36, Alistair Francis wrote: On Sun, Jul 5, 2020 at 11:20 AM Peter Maydell wrote: On Thu, 2 Jul 2020 at 17:33, Alistair Francis wrote: From: LIU Zhiwei Vector AMOs operate as if aq and rl bits were zero on each element with regard to ordering relative to other instructions

[PATCH 4/4] target/arm: adjust CPTR_EL2 according to HCR_EL2.E2H

>From DDI0487Fc_armv8_arm.pdf, the CPTR_EL2 has two kinds of layouts according to HCR_EL2.E2H. When HCR_EL2.E2H is 1, fp_exception_el should refer to HCR_EL2.FPEN and sve_exception_el should refer to HCR_EL2.ZEN. Reviewed-by: Richard Henderson Signed-off-by: LIU Zhiwei --- target/arm/helpe

[PATCH 0/4] target/arm bug fix

I found some bugs in target/arm. The first one is about SVE first-fault or no-fault load/store. The second is SIMD fcmla(by element). The third is about CPTR_EL2. I am not sure I really understand this code. Please confirm the patch set and let me know if I am wrong. LIU Zhiwei (4): target

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