On Sun, 9 Jun 2013, Thomas Schwinge wrote:
In my reading of the relevant documents, the latter change is not correct
for o32, and empirically has interesting effects on the glibc math
testsuite, for example. Keeping the FR register unset for o32 I'm
proposing to fix with the following patch:
On Mon, 5 Aug 2013, Leon Alrae wrote:
Just to make sure that we are refering to the same thing :)
For MFHI:
page no. 303 in MIPS Architecture for Programmers Volume II-B: The
microMIPS32 Instruction Set (document MD00764)
page no. 140 in MIPS Architecture for Programmers Volume IV-e: The
On Sat, 3 Aug 2013, Aurelien Jarno wrote:
34Kf core does support DSP ASE.
CP0_Config3 configuration for 34Kf and description are wrong.
Please refer to MIPS32(R) 34Kf(TM) Processor Core Datasheet
Signed-off-by: Yongbok Kim yongbok@imgtec.com
---
changes from v1:
make
On Fri, 19 Jul 2013, Kwok Cheung Yeung wrote:
Decode trap instructions during the handling of an EXCP_BREAK or EXCP_TRAP
according to the current ISA mode.
Signed-off-by: Kwok Cheung Yeung k...@codesourcery.com
---
linux-user/main.c | 46 +++---
1
On Thu, 9 Aug 2012, Phil Staub wrote:
For this purpose the usual approach is to follow up to the patch
mail saying Ping and giving a url to the patch in patchwork,
like this one:
http://patchwork.ozlabs.org/patch/163705/
Eventually somebody will take pity on it and
Andreas,
Actually there were better patches for the same bug by Meador, including
git-style rather than SVN patches and adding a helper to initialize it
consistently at all call sites.
I find quilt patches easier to manage when I need to reorder them,
revert, manually edit the diffs
Hi Andreas,
I find quilt patches easier to manage when I need to reorder them,
revert, manually edit the diffs (that I routinely do), etc. Perhaps I'm
just outdated, but that's the workflow I've found most efficient for me
while not disturbing anyone else. I've used quilt patches
by setting Cause to 0x300 and
then Status to 0x201, and then making a few single steps, but that didn't
cause the interrupt exception to be taken for some reason. That does not
appear to be a problem with my change though. Perhaps there is a bug
elsewhere.
Signed-off-by: Maciej W. Rozycki ma
= 0x8000b46c __libc_init_array+136: lw ra,28(sp)
(gdb)
0x8000b470 in __libc_init_array ()
4: /x $ra = 0x8000891c
2: x/i $pc
= 0x8000b470 __libc_init_array+140: lw s2,24(sp)
(gdb)
Signed-off-by: Maciej W. Rozycki ma...@codesourcery.com
---
Sent on behalf of Nathan, who's since left the company
t1,c0_config
(gdb)
0x80004d34 in _start ()
5: x/i $pc
= 0x80004d34 _start+380: mtc0t1,c0_config
(gdb)
0x80004d34 in _start ()
5: x/i $pc
= 0x80004d34 _start+380: mtc0t1,c0_config
(gdb)
-- oops!
Signed-off-by: Maciej W. Rozycki ma...@codesourcery.com
---
Please apply,
Maciej
The CP1 FIR register is read-only, ignore any write attempts from the GDB
stub.
Signed-off-by: Maciej W. Rozycki ma...@codesourcery.com
---
Definitely obvious, please apply.
Maciej
qemu-mips-fir.diff
Index: qemu-git-trunk/gdbstub.c
-by: Maciej W. Rozycki ma...@codesourcery.com
---
Sent on behalf of Nathan, who's since left the company. Please apply.
Maciej
qemu-mips-fcr0.diff
Index: qemu-git-trunk/target-mips/translate.c
===
--- qemu-git-trunk.orig/target-mips
diverging -- all
the hflags state is initialized in one place now.
Signed-off-by: Maciej W. Rozycki ma...@codesourcery.com
---
This is effectively a follow-up to Nathan's FCR0 fix -- please apply.
Maciej
qemu-mips-hflags.patch
Index: qemu-git-trunk/target-mips/cpu.h
accordingly was missed and not
propagated. Here's an update to remove the obsolete and now misleading
comment.
Signed-off-by: Maciej W. Rozycki ma...@codesourcery.com
---
Mostly obvious, please apply.
Maciej
qemu-mips16-jal.diff
Index: qemu-git-trunk/target-mips/translate.c
obviously correct to me, and the same
calculation is already used in exception_resume_pc applied to ordinary,
Debug and NMI exceptions. This code on the other hand applies to reset
exceptions and instruction restarts in the context of I/O.
Signed-off-by: Maciej W. Rozycki ma...@codesourcery.com
On Fri, 8 Jun 2012, Meador Inge wrote:
The problem was seen with the 24Kf MIPS32r2 processor in user emulation.
The new approach prevents system and user emulation from diverging -- all
the hflags state is initialized in one place now.
I submitted a patch to fix this issue and the
On Fri, 8 Jun 2012, Andreas Färber wrote:
The problem was seen with the 24Kf MIPS32r2 processor in user emulation.
The new approach prevents system and user emulation from diverging -- all
the hflags state is initialized in one place now.
I submitted a patch to fix this issue and
On Mon, 10 Sep 2012, Matthew Ogilvie wrote:
This bug manifested itself when the guest was Microport UNIX
System V/386 v2.1 (ca. 1987), because it would sometimes mask
off IRQ14 in the slave IMR after it had already been asserted.
The master would still try to deliver an interrupt even
On Wed, 12 Sep 2012, Matthew Ogilvie wrote:
Also, how big of a concern is a very rare gained or lost IRQ0
actually? Under normal conditions, I would expect this to at most
cause a one time clock drift in the guest OS of a fraction of
a second. If that only happens when rebooting or
On Thu, 13 Sep 2012, Jan Kiszka wrote:
I've also just skimmed parts of the 8254 section of The Indispensable PC
Hardware Book, by Hans-Peter Messmer, Copyright 1994 Addison-Wesley,
although I probably ought to read it more carefully.
On Tue, 4 Sep 2012, Jan Kiszka wrote:
What I'm trying to understand and translate from the description is
rather note that for inputs a high-to-low transition cancels the
interrupt as in the level-triggered mode. This is surely not what we do
right now. OTOH, I'm afraid that switching to this
On Mon, 3 Sep 2012, Jan Kiszka wrote:
- Qemu output (without this patch):
elcr=0c00 cmdRead ummask mask sti irq15 unmask DONE
But on real hardware, the master seems to treat IRQ2 as level triggered,
That is not universally true, however in reality it does not matter, more
on
On Tue, 4 Sep 2012, Jan Kiszka wrote:
What I'm trying to understand and translate from the description is
rather note that for inputs a high-to-low transition cancels the
interrupt as in the level-triggered mode. This is surely not what we do
right now. OTOH, I'm afraid that switching to
On Mon, 10 Sep 2012, Avi Kivity wrote:
So the only difference between edge triggered and level triggered
is in the leading edge, with no difference in the trailing edge.
Hard to believe. So an edge while cpu interrupts are disabled is ignored?
Please note that x86 CPU's INT input is
On Sun, 9 Sep 2012, Matthew Ogilvie wrote:
This bug manifested itself when the guest was Microport UNIX
System V/386 v2.1 (ca. 1987), because it would sometimes mask
off IRQ14 in the slave IMR after it had already been asserted.
The master would still try to deliver an interrupt even though
On Mon, 29 Jul 2013, Maciej W. Rozycki wrote:
Decode trap instructions during the handling of an EXCP_BREAK or EXCP_TRAP
according to the current ISA mode.
Signed-off-by: Kwok Cheung Yeung k...@codesourcery.com
---
linux-user/main.c | 46
On Thu, 15 Aug 2013, Aurelien Jarno wrote:
+/* Probe for MIPS32 instructions. As no subsetting is allowed
+ by the specification, it is only necessary to probe for one
+ of the instructions. */
+#ifndef use_mips32_instructions
+got_sigill = 0;
+asm volatile(.set
On Thu, 15 Aug 2013, Aurelien Jarno wrote:
The MIPS32 instructions missing from Vr5500 are the EJTAG stuff (DERET
and SDBBP), JR.HB/JALR.HB (hmm, weird -- these are actually not guaranteed
to work on all MIPS32 chips either, e.g. the 4Kc didn't support these
encodings and trapped),
On Fri, 30 May 2014, Aurelien Jarno wrote:
Just a comment, not related to QEMU: while it looks at a first glance to
build a binary that runs on both pre-R6 and R6 by not using the removed
instructions, I do wonder how the transition would be done for unaligned
load/stores. On pre-R6,
On Fri, 1 Aug 2014, Yongbok Kim wrote:
Ping!
Patch for v2.1.0
-Original Message-
From: Yongbok Kim
Sent: 01 July 2014 17:43
To: qemu-devel@nongnu.org
Cc: aurel...@aurel32.net; Leon Alrae; Cristian Cuna; Yongbok Kim
Subject: [PATCH v2] target-mips: fix broken MIPS16 and
platforms (CONFIG_FULONG)
that are exclusively little-endian, 64-bit MIPS. Previously vt82c686.o
was pulled explicitly with obj-$(CONFIG_FULONG).
Signed-off-by: Maciej W. Rozycki ma...@codesourcery.com
---
Hi,
Trivial stuff first, tougher later on. Compile-tested only, this
addresses
-by: Maciej W. Rozycki ma...@codesourcery.com
---
I have a further change down the queue to clean up
`mips_cpu_gdb_read_register' and `mips_cpu_gdb_write_register' and make
them more consistent with respect to each other as far as the handling
of FP registers is concerned. For now please apply
CP1.FIR is read-only in hardware so gdbstub must respect it. We already
respect it for CTC1 instructions, so do it here too.
Signed-off-by: Maciej W. Rozycki ma...@codesourcery.com
---
Not much to say about it here. Please apply.
Maciej
qemu-mips-fir.diff
Index: qemu-git-trunk/target-mips
been easily missed because we have no hard-float
microMIPS CPU configuration present; in fact we have no microMIPS CPU
configuration of any kind present.
Signed-off-by: Maciej W. Rozycki ma...@codesourcery.com
---
The latter problem is easily fixed though, with a patch I'll be sending
right away
, in particular the
pipeline, stayed unchanged. Or to put it another way, the difference
between a 5K and a 5KE CPU corresponds to one between a 4K and a 4KE
CPU, except for the 64-bit rather than 32-bit ISA.
Signed-off-by: Maciej W. Rozycki ma...@codesourcery.com
---
For the curious:
$ cat /proc
Make the data type used for the CP0.Config4 and CP0.Config5 registers
and their mask signed, for consistency with the remaining 32-bit CP0
registers, like CP0.Config0, etc.
Signed-off-by: Maciej W. Rozycki ma...@codesourcery.com
---
qemu-mips-config-int32_t.diff
Index: qemu-git-trunk/target
, so these features are not marked,
making our support diverge from real hardware.
Signed-off-by: Sandra Loosemore san...@codesourcery.com
Signed-off-by: Maciej W. Rozycki ma...@codesourcery.com
---
Hopefully we'll get the missing features sometime sooner rather than
later, they should
Enable vectored interrupt support for the 74Kf CPU, reflecting hardware.
Signed-off-by: Maciej W. Rozycki ma...@codesourcery.com
---
qemu-mips-config-74k-vint.diff
Index: qemu-git-trunk/target-mips/translate_init.c
===
--- qemu-git
.DSP2P set or software won't detect its presence.
Signed-off-by: Maciej W. Rozycki ma...@codesourcery.com
---
qemu-mips-config-dsp.diff
Index: qemu-git-trunk/target-mips/translate_init.c
===
--- qemu-git-trunk.orig/target-mips
On Wed, 5 Nov 2014, Leon Alrae wrote:
The actual microMIPS CPU definition is indeed a worthwile addition -
thanks. It was on my TODO list to upstream such a CPU but I haven't got
round to it.
You may still be able to contribute here, by adding microMIPS DSP CPUs.
Regrettably I wasn't able
Signed-off-by: Maciej W. Rozycki ma...@codesourcery.com
---
qemu-mips-translate-decode-opc-format.diff
Index: qemu-git-trunk/target-mips/translate.c
===
--- qemu-git-trunk.orig/target-mips/translate.c 2014-11-02 18:51:04.838001276
Signed-off-by: Maciej W. Rozycki ma...@codesourcery.com
---
qemu-mips-translate-init-format.diff
Index: qemu-git-trunk/target-mips/translate_init.c
===
--- qemu-git-trunk.orig/target-mips/translate_init.c2014-11-02
18:50
Move the call to `update_fcr31' in `helper_float_cvtw_s' after the
exception flag check, for consistency with the remaining helpers that do
it last too.
Signed-off-by: Maciej W. Rozycki ma...@codesourcery.com
---
I hope there's no question about this, please apply.
Maciej
qemu-mips-op
Remove the `FLOAT_OP' macro, unused since commit
b6d96beda3a6cbf20a2d04a609eff78adebd8859 [Use temporary registers for
the MIPS FPU emulation.].
Signed-off-by: Maciej W. Rozycki ma...@codesourcery.com
---
qemu-mips-op-helper-float_op.diff
Index: qemu-git-trunk/target-mips/op_helper.c
more operations sprinkled across the file. Revert the mess by
moving FMA operations to a new ternary class inserted after the binary
class and move the misplaced unary and binary operations to where they
belong.
Signed-off-by: Maciej W. Rozycki ma...@codesourcery.com
---
I hope
On Wed, 5 Nov 2014, Leon Alrae wrote:
qemu-umips-cu1-ex.diff
Index: qemu-git-trunk/target-mips/translate.c
===
--- qemu-git-trunk.orig/target-mips/translate.c 2014-10-27
04:26:57.0 +
+++
t1,c0_config
(gdb)
0x80004d34 in _start ()
5: x/i $pc
= 0x80004d34 _start+380: mtc0t1,c0_config
(gdb)
0x80004d34 in _start ()
5: x/i $pc
= 0x80004d34 _start+380: mtc0t1,c0_config
(gdb)
-- oops!
Signed-off-by: Maciej W. Rozycki ma...@codesourcery.com
---
It's been lost
On Fri, 7 Nov 2014, Leon Alrae wrote:
When I've been applying this patch to my mips-next candidate branch for
2.2 I realized that you haven't rebased it onto the recent version where
MSA has been added to mips32r5-generic. Now I don't think that having
DSP and MSA on one CPU makes sense,
On Fri, 7 Nov 2014, Leon Alrae wrote:
I have been working with the current trunk, the change applies
correctly there AFAICT.
55a2201 commit added (1 CP0C3_MSAP) to CP0_Config3 for
mips32r5-generic which is not present on your patch.
Indeed, my mistake for some reason.
I have no
...@codesourcery.com
Signed-off-by: Maciej W. Rozycki ma...@codesourcery.com
---
Another change that has waited for too long, with the original
discussion archived here:
http://lists.nongnu.org/archive/html/qemu-devel/2012-06/msg01230.html
Resending with what hopefully is a better description
On Fri, 7 Nov 2014, Leon Alrae wrote:
I was considering making mips32r5-generic less artificial and slowly
evolve it towards some existing MIPS32R5 CPU, for example P5600 (which
supports MSA, but doesn't support DSP ASE). Furthermore, none from the
latest MIPS CPUs supports both ASEs.
-off-by: Maciej W. Rozycki ma...@codesourcery.com
---
Leon,
Noticed in porting the next change I'm going to post. NB I have no
reasonable way to do run-time checks of an r6 configuration, so please
double check this works for you even though I believe it is obviously
correct; I did check CP0
, and do not synchronise
the environment to evaluate side effects. We also write these registers
in the user emulation mode even though a real kernel presents them as
read only.
Signed-off-by: Maciej W. Rozycki ma...@codesourcery.com
---
Hi,
I have verified the correct operation of this patch
as one op is produced in generated
code rather than two (again, unless `rs' is 0, where it doesn't change
anything).
Signed-off-by: Maciej W. Rozycki ma...@codesourcery.com
---
This is rather obvious, but I also pushed it through full bare-iron GCC
regression testing with an o32 big-endian
Descriptions, p. 81.
[2] MIPS Architecture For Programmers, Volume I-A: Introduction to the
MIPS64 Architecture, Imagination Technologies, Inc., Document
Number: MD00083, Revision 6.00, March 31, 2014, Table 6.7 FCSR
Register Field Descriptions, p. 93.
Signed-off-by: Maciej W. Rozycki
On Wed, 12 Nov 2014, Andreas Färber wrote:
Please consistently use target-mips: when that's what you're
touching. (For hw/mips/ it's less consistent what to use.)
Sure. What about MIPS changes that span files contained within
target-mips/ and elsewhere? I have such changes in my queue.
On Wed, 12 Nov 2014, Peter Maydell wrote:
@@ -208,12 +206,12 @@ int cpu_load(QEMUFile *f, void *opaque,
MIPSCPU *cpu = mips_env_get_cpu(env);
int i;
-if (version_id 3) {
+if (version_id != CPU_SAVE_VERSION) {
return -EINVAL;
}
Shouldn't this
On Thu, 13 Nov 2014, Leon Alrae wrote:
It might be a good idea to split these changes into separate patches to
have more precise indication about touched subsystem (even though all
the changes were done in MIPS context). For example target-mips and
linux-user rather than just mips.
I split
Include CP0.Config2 through CP0.Config5 registers in the register dump
produced with the `info registers' monitor command. Align vertically
with the registers already output.
Signed-off-by: Maciej W. Rozycki ma...@codesourcery.com
---
Hi,
This proved useful in debugging a CP0.Config3
exception right away.
And then over and over again.
We already check the current setting of the CP0.Config3.ISAOnExc in
`set_hflags_for_handler' to set the ISA bit correctly on the exception
handler entry so it is the ability to set it that is missing only.
Signed-off-by: Maciej W. Rozycki ma
Tighten ISA level checks down to MIPS II that many of our instructions
are missing. Also make sure any 64-bit instruction enables are only
applied to 64-bit processors, that is ones that implement at least the
MIPS III ISA.
Signed-off-by: Maciej W. Rozycki ma...@codesourcery.com
---
Hi
that their semantics for stack accesses follows the architecture
specification. That in particular applies to user software run on
64-bit processors with the CP0.Status.UX bit clear where the address
space is wrapped to 32 bits.
Signed-off-by: Maciej W. Rozycki ma...@codesourcery.com
---
Hi
Descriptions, p. 81.
[2] MIPS Architecture For Programmers, Volume I-A: Introduction to the
MIPS64 Architecture, Imagination Technologies, Inc., Document
Number: MD00083, Revision 6.00, March 31, 2014, Table 6.7 FCSR
Register Field Descriptions, p. 93.
Signed-off-by: Maciej W. Rozycki
Rewrite the FPU register access parts of `mips_cpu_gdb_read_register'
and `mips_cpu_gdb_write_register' for consistency between each other.
Signed-off-by: Maciej W. Rozycki ma...@codesourcery.com
---
Hi,
This is the FPU register handling cleanup previously promised.
It was regression-tested
Make CP0.Status writes made with the MTTC0 instruction respect this
register's mask just like all the other places. Also preserve the
current values of masked out bits.
Signed-off-by: Maciej W. Rozycki ma...@codesourcery.com
---
Hi,
This should be obvious. Also quite obviously, we are missing
Replace the 20Kc original MIPS64 ISA processor used for 64-bit user
emulation with the 5KEf processor that implements the MIPS64r2 ISA,
complementing the choice of the 24Kf processor for 32-bit emulation.
Signed-off-by: Maciej W. Rozycki ma...@codesourcery.com
---
Hi,
For user emulation mode I
On Thu, 20 Nov 2014, Peter Maydell wrote:
For user emulation mode I think we want to default to the highest ISA
level supported, for maximum user flexibility. Currently the MIPS64r2
ISA is the highest 64-bit ISA we have a real processor support for so
use it and the 5KEf which is the
On Mon, 24 Nov 2014, Leon Alrae wrote:
All the patches up to this one have been applied to mips-next branch
(available at git://github.com/lalrae/qemu.git), thanks. I'll go through
the remaining soon.
Thanks. I am now back from a week's vacation and will continue posting
outstanding
On Tue, 2 Dec 2014, Leon Alrae wrote:
@@ -19276,6 +19276,10 @@ void mips_cpu_dump_state(CPUState *cs, F
env-CP0_Status, env-CP0_Cause, env-CP0_EPC);
cpu_fprintf(f, Config0 0x%08x Config1 0x%08x LLAddr 0x
TARGET_FMT_lx \n,
env-CP0_Config0,
On Tue, 2 Dec 2014, Leon Alrae wrote:
Please note that for this validation I'm using an artificial microMIPS
processor that also has an FPU implemented, so that our microMIPS FP
support is correctly validated too (I don't really know if there exists
any real microMIPS processor that
Hi Blue Swirl,
On Wed, 5 Nov 2014, Maciej W. Rozycki wrote:
Restore the order of helpers that used to be: unary operations (generic,
then MIPS-specific), binary operations (generic, then MIPS-specific),
compare operations. At one point FMA operations were inserted at a
random place
happening when building QEMU with the `--enable-werror' configuration
option present. Report any failure from `fwrite'.
Signed-off-by: Maciej W. Rozycki ma...@codesourcery.com
---
qemu-test-bios-tables-fwrite.diff
Index: qemu-git-trunk/tests/bios-tables-test.c
-off-by: Thomas Schwinge tho...@codesourcery.com
Signed-off-by: Maciej W. Rozycki ma...@codesourcery.com
---
qemu-mips-softfloat-status.diff
Index: qemu-git-trunk/target-mips/cpu.h
===
--- qemu-git-trunk.orig/target-mips/cpu.h 2014
On Tue, 2 Dec 2014, Peter Maydell wrote:
Is there ever a situation where you would want to
resynchronise only one of these two things? If not,
why not just have one function for synchronising
softfloat state from the FCR?
Good point, I think these are safe and cheap enough to be always
Reduce line wrapping throughout MSA helper macros by using a local float
status pointer rather than referring to the float status through the
environment each time. No functional change.
Signed-off-by: Maciej W. Rozycki ma...@codesourcery.com
---
Hi,
The same float status applies across
Set DisasContext's ulri member to 0 or 1 as with other bool members.
Signed-off-by: Maciej W. Rozycki ma...@codesourcery.com
---
qemu-mips-disas-ulri.diff
Index: qemu-git-trunk/target-mips/translate.c
===
--- qemu-git-trunk.orig
On Wed, 3 Dec 2014, Leon Alrae wrote:
-env-hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
+if (env-insn_flags ISA_MIPS3)
+env-hflags |= MIPS_HFLAG_64;
According to the CODING_STYLE braces are required even for a single
statement if block. This
On Wed, 19 Nov 2014, Maciej W. Rozycki wrote:
Tighten ISA level checks down to MIPS II that many of our instructions
are missing. Also make sure any 64-bit instruction enables are only
applied to 64-bit processors, that is ones that implement at least the
MIPS III ISA.
Signed-off-by: Maciej W
On Fri, 5 Dec 2014, Leon Alrae wrote:
I gave it a thought before making this change and concluded it would be
the lesser evil (plus loudly manifesting and easily correctable) if
someone accidentally makes QEMU refuse to load older images where in
fact no compatibility issue exists,
Tighten ISA level checks down to MIPS II that many of our instructions
are missing. Also make sure any 64-bit instruction enables are only
applied to 64-bit processors, that is ones that implement at least the
MIPS III ISA.
Signed-off-by: Maciej W. Rozycki ma...@codesourcery.com
---
Changes from
Rewrite the FPU register access parts of `mips_cpu_gdb_read_register'
and `mips_cpu_gdb_write_register' for consistency between each other.
Signed-off-by: Maciej W. Rozycki ma...@codesourcery.com
---
Changes from v1:
- missing braces added for blocks required with conditional statements.
qemu
On Thu, 4 Dec 2014, Leon Alrae wrote:
Index: qemu-git-trunk/target-mips/translate.c
===
--- qemu-git-trunk.orig/target-mips/translate.c 2014-11-12
07:41:26.597542010 +
+++ qemu-git-trunk/target-mips/translate.c
On Fri, 5 Dec 2014, Leon Alrae wrote:
qemu-mips-gdbstub-cleanup.diff
Index: qemu-git-trunk/target-mips/gdbstub.c
===
--- qemu-git-trunk.orig/target-mips/gdbstub.c 2014-11-20
10:44:24.058944521 +
+++
Hi,
This patch series comprises changes to QEMU, both the MIPS backend and
generic SoftFloat support code, to support IEEE 754-2008 features
introduced to revision 3.50 of the MIPS Architecture as follows.
1. IEEE 754-2008 NaN encoding.
As many of you have been aware it has been a long
for Floating-Point Arithmetic, IEEE Computer
Society, IEEE Std 754-2008, 29 August 2008, pp. 21-22
[2] same, p. 37
[3] same, p. 30
Signed-off-by: Maciej W. Rozycki ma...@codesourcery.com
---
This is in particular how MIPS hardware operates, other processors
supposedly do the same
Make the bit shuffling in one place only and replace input if required
instead.
Signed-off-by: Thomas Schwinge tho...@codesourcery.com
Signed-off-by: Maciej W. Rozycki ma...@codesourcery.com
---
qemu-softfloat-floatx80-nan.diff
Index: qemu-git-trunk/fpu/softfloat-specialize.h
to from softfloat.c, but external copies must be also produced for
external callers.
Signed-off-by: Thomas Schwinge tho...@codesourcery.com
Signed-off-by: Maciej W. Rozycki ma...@codesourcery.com
---
Eventually we might want to move the new inline functions into a
separate header to be included from
-by: Thomas Schwinge tho...@codesourcery.com
Signed-off-by: Maciej W. Rozycki ma...@codesourcery.com
---
I missed revision 5.00 of the architecture documents before they were
taken offline; however there have been no changes to Table 5.3 between
revision 5.00 and, respectively, revisions 5.02 and 5.01
Precompute the possible results, and then pick the suitable one. The
calculation of the unused result will be optimized away by the compiler
at any reasonable optimization level, so no run-time performance loss.
Signed-off-by: Thomas Schwinge tho...@codesourcery.com
Signed-off-by: Maciej W
Mechanically update `*_nan' functions with a SoftFloat status parameter
where qNaNs and sNaNs need to be told apart. Update all callers
accordingly.
Signed-off-by: Thomas Schwinge tho...@codesourcery.com
Signed-off-by: Maciej W. Rozycki ma...@codesourcery.com
---
BTW, this is another patch
, MIPS Technologies, Inc., Document Number:
MD00866, Revision 1.07, October 2, 2013, Section 3.3.2
Floating-Point Registers Mapping, p. 38
Signed-off-by: Thomas Schwinge tho...@codesourcery.com
Signed-off-by: Maciej W. Rozycki ma...@codesourcery.com
---
Shall I post the artificial *-nan2008
On Tue, 9 Dec 2014, Peter Maydell wrote:
I really really want to hold this patchset off until the softfloat
relicensing has gone through, because repeating that work would
be really painful...
Understood. Do you have an ETA for this to happen?
It's waiting for people to review the
W. Rozycki ma...@codesourcery.com
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To be applied first so as not to break the build and consequently
bisection with the configuration changes posted next.
Maciej
qemu-mips-configs.diff
Index: qemu-git-trunk/default-configs/mipsn32-softmmu.mak
Hi,
This mini patch series corrects some misguided assumptions in QEMU's MIPS
processor selection while also adding another configuration to support a
missing ABI-processor combination, and then corrects register widths used
by the GDB stub so as to match the processor selected (for the
,
- mipsn64|mipsn64el -- 64-bit CPUs only, n64 user and GDB ABI.
Signed-off-by: Maciej W. Rozycki ma...@codesourcery.com
---
qemu-mips64-abis.diff
Index: qemu-git-trunk/bsd-user/elfload.c
===
--- qemu-git-trunk.orig/bsd-user/elfload.c 2014
talking to a 32-bit processor.
Signed-off-by: Maciej W. Rozycki ma...@codesourcery.com
---
qemu-mips-regsize.diff
Index: qemu-git-trunk/gdbstub.c
===
--- qemu-git-trunk.orig/gdbstub.c 2014-12-05 18:38:40.847529339 +
+++ qemu-git
On Wed, 10 Dec 2014, Peter Maydell wrote:
Index: qemu-git-trunk/default-configs/mipsn32-softmmu.mak
Index: qemu-git-trunk/default-configs/mipsn32el-softmmu.mak
Index: qemu-git-trunk/default-configs/mipsn64el-linux-user.mak
Index: qemu-git-trunk/default-configs/mipsn64el-softmmu.mak
On Wed, 10 Dec 2014, Peter Maydell wrote:
This is a tricky change, the system emulation mode configuration also has
an ELF loader (invoked with the -kernel option) and as such is also
affected. There are three MIPS ELF flavours corresponding to the three
ABIs: ELF32 no-ABI2 for o32,
On Wed, 10 Dec 2014, Peter Maydell wrote:
Except that apart from coming to an agreement someone has to make it
happen yet. ;)
Ah, but I'm happy with the current state of the codebase...
Ack.
Fair enough, I want to move forward though. Would it make you happy if I
dropped the new
mode, o32 user ABI,
- mipsn32|mipsn32el -- 64-bit CPUs only, user emulation mode only, n32
user ABI,
- mipsn64|mipsn64el -- 64-bit CPUs only, user emulation mode only, n64
user ABI.
Signed-off-by: Maciej W. Rozycki ma...@codesourcery.com
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