On Sun, 2013-09-29 at 18:06 +0300, Michael S. Tsirkin wrote:
On Sun, Sep 29, 2013 at 05:40:54PM +0300, Marcel Apfelbaum wrote:
Interrupt pin is selected and saved into PCI_INTERRUPT_PIN
register during device initialization. Devices should not call
directly qemu_set_irq and specify the INTx
On Mon, 2013-09-30 at 12:14 +0300, Michael S. Tsirkin wrote:
On Mon, Sep 30, 2013 at 11:02:06AM +0200, Paolo Bonzini wrote:
Il 30/09/2013 10:58, Michael S. Tsirkin ha scritto:
As a next step, can we make pci_set_irq non-inline and make
it call pci_irq_handler directly, and get rid of
On Mon, 2013-09-30 at 13:10 +0300, Michael S. Tsirkin wrote:
On Mon, Sep 30, 2013 at 12:43:20PM +0300, Marcel Apfelbaum wrote:
On Mon, 2013-09-30 at 12:14 +0300, Michael S. Tsirkin wrote:
On Mon, Sep 30, 2013 at 11:02:06AM +0200, Paolo Bonzini wrote:
Il 30/09/2013 10:58, Michael S
based on PCI_INTERRUPT_PIN.
Added pci_allocate_irq wrapper to be used by devices that
still need PCIDevice infrastructure to assert irqs.
Renamed a static method which was named already pci_set_irq.
Signed-off-by: Marcel Apfelbaum marce...@redhat.com
---
Changes from v1:
- Added pci irq wrappers
pci_set_irq uses PCI_INTERRUPT_PIN config register
to compute device INTx pin to set.
An assert is used to ensure that intx received
from the quest OS corresponds to PCI_INTERRUPT_PIN.
Signed-off-by: Marcel Apfelbaum marce...@redhat.com
---
hw/net/vmxnet3.c | 13 +++--
1 file changed
qemu_allocate_irq returns a single qemu_irq.
The interface allows to specify an interrupt number.
qemu_free_irq frees it.
Signed-off-by: Marcel Apfelbaum marce...@redhat.com
---
hw/core/irq.c| 16
include/hw/irq.h | 7 +++
2 files changed, 23 insertions(+)
diff --git
The PCI_INTERRUPT_PIN will be used by shpc init, so
was moved before the call to shpc_init.
Signed-off-by: Marcel Apfelbaum marce...@redhat.com
---
hw/pci-bridge/pci_bridge_dev.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/pci-bridge/pci_bridge_dev.c b/hw/pci-bridge
pci_set_irq uses PCI_INTERRUPT_PIN config register
to compute device INTx pin to assert/deassert.
Removed irq field from xhci state.
Signed-off-by: Marcel Apfelbaum marce...@redhat.com
---
hw/usb/hcd-xhci.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/hw/usb/hcd
pci_set_irq and the other pci irq wrappers use
PCI_INTERRUPT_PIN config register to compute device
INTx pin to assert/deassert.
An irq is allocated using pci_allocate_irq wrapper
only if is needed by non pci devices.
Signed-off-by: Marcel Apfelbaum marce...@redhat.com
---
hw/audio/ac97.c
The fields hpev_intx and aer_intx were removed because
both AER and hot-plug events must use device's interrupt.
Assert/deassert interrupts using pci_set_irq wrapper instead.
Signed-off-by: Marcel Apfelbaum marce...@redhat.com
---
hw/pci/pcie.c | 4 ++--
hw/pci/pcie_aer.c | 4
pci_set_irq and the other pci irq wrappers use
PCI_INTERRUPT_PIN config register to compute device
INTx pin to assert/deassert.
Save INTx pin into the config register before calling
pci_set_irq
Signed-off-by: Marcel Apfelbaum marce...@redhat.com
---
hw/misc/vfio.c | 11 ++-
1 file
Instead of exposing the the irq field,
pci wrappers to qemu_set_irq or qemu_irq_*
can be used.
Signed-off-by: Marcel Apfelbaum marce...@redhat.com
---
hw/pci/pci.c | 2 --
include/hw/pci/pci.h | 3 ---
2 files changed, 5 deletions(-)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index
interface to allocate single irq
- Added pci wrappers to allocate and free pci irq
- Added pci irq wrappers for all qemu methods
setting irq and not only qemu_set_irq
- Replace all qemu irq setters with pci
wrappers
Marcel Apfelbaum (9):
hw/core: Add interface to allocate and free a single
On Wed, 2013-10-02 at 15:54 +0300, Michael S. Tsirkin wrote:
On Wed, Oct 02, 2013 at 03:41:27PM +0300, Marcel Apfelbaum wrote:
Interrupt pin is selected and saved into PCI_INTERRUPT_PIN
register during device initialization. Devices should not call
directly qemu_set_irq and specify the INTx
On Wed, 2013-10-02 at 15:58 +0300, Michael S. Tsirkin wrote:
On Wed, Oct 02, 2013 at 03:41:25PM +0300, Marcel Apfelbaum wrote:
Note: Added RFC because not all affected devices were
checked yet.
What do you have in mind exactly?
Sanity test for *all* modified devices.
Any other
On Wed, 2013-10-02 at 17:21 +0200, Paolo Bonzini wrote:
Il 02/10/2013 14:41, Marcel Apfelbaum ha scritto:
+static inline void pci_irq_pulse(PCIDevice *pci_dev)
+{
+pci_irq_lower(pci_dev);
+pci_irq_raise(pci_dev);
+}
+
Why is this in the opposite order, compared
On Wed, 2013-10-02 at 09:58 -0600, Alex Williamson wrote:
On Wed, 2013-10-02 at 15:41 +0300, Marcel Apfelbaum wrote:
pci_set_irq and the other pci irq wrappers use
PCI_INTERRUPT_PIN config register to compute device
INTx pin to assert/deassert.
Save INTx pin into the config register
On Mon, 2013-10-07 at 09:02 +0200, Gerd Hoffmann wrote:
On Mi, 2013-10-02 at 15:41 +0300, Marcel Apfelbaum wrote:
--- a/hw/usb/hcd-uhci.c
+++ b/hw/usb/hcd-uhci.c
@@ -381,7 +381,7 @@ static void uhci_update_irq(UHCIState *s)
} else {
level = 0;
}
-qemu_set_irq
pci irq wrappers for all qemu methods
setting irq and not only qemu_set_irq
- Replace all qemu irq setters with pci
wrappers
Marcel Apfelbaum (9):
hw/core: Add interface to allocate and free a single IRQ
hw/pci: add pci wrappers for allocating and asserting irqs
hw/pci-bridge: set
qemu_allocate_irq returns a single qemu_irq.
The interface allows to specify an interrupt number.
qemu_free_irq frees it.
Signed-off-by: Marcel Apfelbaum marce...@redhat.com
---
hw/core/irq.c| 16
include/hw/irq.h | 7 +++
2 files changed, 23 insertions(+)
diff --git
based on PCI_INTERRUPT_PIN.
Added pci_allocate_irq wrapper to be used by devices that
still need PCIDevice infrastructure to assert irqs.
Renamed a static method which was named already pci_set_irq.
Signed-off-by: Marcel Apfelbaum marce...@redhat.com
---
Changes from v2:
- Addressed Michael S
pci_set_irq uses PCI_INTERRUPT_PIN config register
to compute device INTx pin to assert/deassert.
An assert is used to ensure that intx received
from the quest OS corresponds to PCI_INTERRUPT_PIN.
Signed-off-by: Marcel Apfelbaum marce...@redhat.com
---
Changes from v2:
- Addressed Alex
-by: Marcel Apfelbaum marce...@redhat.com
---
Changes from v2:
- Addressed Alex Williamson's comments
- replaced calls to pci_set_irq with
pci_irq_assert/deassert when possible
- Addressed Gerd Hoffmann's comment
- removed irq_pin from UHCIState state
because it is not used anymore
hw
Instead of exposing the the irq field,
pci wrappers to qemu_set_irq or qemu_irq_*
can be used.
Signed-off-by: Marcel Apfelbaum marce...@redhat.com
---
hw/pci/pci.c | 2 --
include/hw/pci/pci.h | 3 ---
2 files changed, 5 deletions(-)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index
The PCI_INTERRUPT_PIN will be used by shpc init, so
was moved before the call to shpc_init.
Signed-off-by: Marcel Apfelbaum marce...@redhat.com
---
hw/pci-bridge/pci_bridge_dev.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/pci-bridge/pci_bridge_dev.c b/hw/pci-bridge
The fields hpev_intx and aer_intx were removed because
both AER and hot-plug events must use device's interrupt.
Assert/deassert interrupts using pci irq wrappers instead.
Signed-off-by: Marcel Apfelbaum marce...@redhat.com
---
Changes from v2:
- Addressed Alex Williamson's comments
pci_set_irq and the other pci irq wrappers use
PCI_INTERRUPT_PIN config register to compute device
INTx pin to assert/deassert.
save INTX pin into the config register before calling
pci_set_irq
Signed-off-by: Marcel Apfelbaum marce...@redhat.com
---
Changes from v2:
- Addressed Alex
static void uhci_reset(void *opaque)
@@ -1240,8 +1239,7 @@ static int usb_uhci_common_initfn(PCIDevice *dev)
/* TODO: reset value should be 0. */
pci_conf[USB_SBRN] = USB_RELEASE_1; // release number
-s-irq_pin = u-info.irq_pin;
-
On Thu, 2013-10-10 at 15:00 +0200, arm...@redhat.com wrote:
From: Markus Armbruster arm...@redhat.com
This reverts most of commit 3d1237fb2ab4edb926c717767bb5e31d6053a7c5.
The commit claims to sort the output of -device help by
functionality rather than alphabetical. Issues:
* The
device_add help with
no-user devices included.
I think that adding the category in each line may be
useful when using grep, but I suppose that we can grep by category
with -A x.
Thanks for continuing to improve the help output.
Marcel,
Reviewed-by: Marcel Apfelbaum marce...@redhat.com
Markus
the cast anymore.
Seems OK to me.
Reviewed-by: Marcel Apfelbaum marce...@redhat.com
+127,8 @@ static void qdev_print_devinfos(bool show_no_user)
Same question about show_no_user parameter, maybe give it a better
name?
Seems OK to me.
Reviewed-by: Marcel Apfelbaum marce...@redhat.com
if ((i DEVICE_CATEGORY_MAX
? !test_bit(i, dc-categories
On Tue, 2013-10-29 at 17:08 +0100, arm...@redhat.com wrote:
From: Markus Armbruster arm...@redhat.com
Many PCI host bridges consist of a sysbus device and a PCI device.
You need both for the thing to work. Arguably, these bridges should
be modelled as a single, composite devices instead of
assignments
from device class init functions.
Signed-off-by: Markus Armbruster arm...@redhat.com
Seems OK to me.
Reviewed-by: Marcel Apfelbaum marce...@redhat.com
---
hw/alpha/typhoon.c | 2 --
hw/arm/versatilepb.c | 1 -
hw/audio/pl041.c | 1 -
hw/core/sysbus.c
On Wed, 2013-10-30 at 13:15 +0100, Markus Armbruster wrote:
Marcel Apfelbaum marce...@redhat.com writes:
On Tue, 2013-10-29 at 17:08 +0100, arm...@redhat.com wrote:
From: Markus Armbruster arm...@redhat.com
Such devices have always been unavailable and omitted from the list
On Wed, 2013-10-30 at 14:54 +0100, Markus Armbruster wrote:
Andreas Färber afaer...@suse.de writes:
Am 30.10.2013 13:30, schrieb Markus Armbruster:
Marcel Apfelbaum marce...@redhat.com writes:
On Tue, 2013-10-29 at 17:08 +0100, arm...@redhat.com wrote:
From: Markus Armbruster arm
On Wed, 2013-10-30 at 17:28 +0100, arm...@redhat.com wrote:
From: Markus Armbruster arm...@redhat.com
A PIIX3/PIIX4 southbridge has multiple functions. We model each
function as a separate qdev. Two of them need some special wiring set
up in pc_init1() or mips_malta_init() to work: the ISA
for unwary users,
like this one:
$ qemu-system-x86_64 -nodefaults -monitor stdio -display none
QEMU 1.6.50 monitor - type 'help' for more information
(qemu) device_add apic
Segmentation fault (core dumped)
I call that a regression. Fix it.
Seems OK to me.
Reviewed-by: Marcel
On Wed, 2013-10-30 at 17:28 +0100, arm...@redhat.com wrote:
From: Markus Armbruster arm...@redhat.com
Drop it when there's no obvious reason why device_add could not work.
Else keep and document why.
* isa-fdc: drop
* i8042: drop, even though its I/O base is hardcoded (because you
On Thu, 2013-10-31 at 11:29 +0100, Markus Armbruster wrote:
Marcel Apfelbaum marce...@redhat.com writes:
On Wed, 2013-10-30 at 17:28 +0100, arm...@redhat.com wrote:
From: Markus Armbruster arm...@redhat.com
A PIIX3/PIIX4 southbridge has multiple functions. We model each
function
assumes that all the reads/writes to
pci address space are done by the cpu.
Changes from v1:
- pci-unassigned-mem MemoryRegion resides now in PCIBus and not on
various Host Bridges
- pci-unassgined-mem does not have a .valid.accept field and
implements read write methods
Marcel Apfelbaum (3
subregions.
Signed-off-by: Marcel Apfelbaum marce...@redhat.com
---
include/exec/memory.h | 6 +++---
memory.c | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/exec/memory.h b/include/exec/memory.h
index ebe0d24..6995087 100644
--- a/include/exec/memory.h
of the device that initiated the transaction
Note: This implementation assumes that all the reads/writes to
the pci address space are done by the cpu.
Signed-off-by: Marcel Apfelbaum marce...@redhat.com
---
Changes from v1:
- pci-unassigned-mem MemoryRegion resides now in PCIBus and not on
various
does not have a .valid.accept field and
implements read write methods
Marcel Apfelbaum (2):
memory: allow MemoryRegion's priority field to accept negative values
hw/pci: handle unassigned pci addresses
hw/pci/pci.c | 46 ++
include
subregions.
Signed-off-by: Marcel Apfelbaum marce...@redhat.com
---
include/exec/memory.h | 6 +++---
memory.c | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/exec/memory.h b/include/exec/memory.h
index ebe0d24..6995087 100644
--- a/include/exec/memory.h
of the device that initiated the transaction
Note: This implementation assumes that all the reads/writes to
the pci address space are done by the cpu.
Signed-off-by: Marcel Apfelbaum marce...@redhat.com
---
Changes from v1:
- pci-unassigned-mem MemoryRegion resides now in PCIBus and not on
various
On Mon, 2013-09-09 at 12:28 +0100, Peter Maydell wrote:
On 9 September 2013 12:11, Marcel Apfelbaum marce...@redhat.com wrote:
Priority is used to make visible some subregions by obscuring
the parent MemoryRegion addresses overlapping with the subregion.
By allowing the priority
On Mon, 2013-09-09 at 14:40 +0300, Michael S. Tsirkin wrote:
On Mon, Sep 09, 2013 at 02:11:54PM +0300, Marcel Apfelbaum wrote:
Created a MemoryRegion with negative priority that
spans over all the pci address space.
It intercepts the accesses to unassigned pci
address space
On Mon, 2013-09-02 at 15:38 +0100, Peter Maydell wrote:
On 2 September 2013 15:13, Marcel Apfelbaum marce...@redhat.com wrote:
Priority is used to make visible some subregions by obscuring
the parent MemoryRegion addresses overlapping with the subregion.
By allowing the priority
On Mon, 2013-09-09 at 15:23 +0300, Michael S. Tsirkin wrote:
On Mon, Sep 09, 2013 at 03:11:55PM +0300, Marcel Apfelbaum wrote:
On Mon, 2013-09-09 at 14:40 +0300, Michael S. Tsirkin wrote:
On Mon, Sep 09, 2013 at 02:11:54PM +0300, Marcel Apfelbaum wrote:
Created a MemoryRegion
On Mon, 2013-09-09 at 13:52 +0100, Peter Maydell wrote:
On 9 September 2013 13:43, Marcel Apfelbaum marce...@redhat.com wrote:
The scenario is covered only for the primary bus and not for buses
behind the PCI bridge (the later being handled differently.)
In this case, isn't the Host Bridge
On Mon, 2013-09-09 at 14:02 +0100, Peter Maydell wrote:
On 9 September 2013 13:59, Michael S. Tsirkin m...@redhat.com wrote:
On Mon, Sep 09, 2013 at 01:52:11PM +0100, Peter Maydell wrote:
It would be conceptually nicer not to treat host bridges as
a special case but instead to just report
On Mon, 2013-09-09 at 14:19 +0100, Peter Maydell wrote:
On 9 September 2013 14:15, Marcel Apfelbaum marce...@redhat.com wrote:
On Mon, 2013-09-09 at 14:02 +0100, Peter Maydell wrote:
Can you just pick the device which is (a subclass of)
TYPE_PCI_HOST_BRIDGE, or do we have host bridges which
On Mon, 2013-09-09 at 14:16 +0100, Peter Maydell wrote:
On 9 September 2013 14:07, Marcel Apfelbaum marce...@redhat.com wrote:
This is exactly my point. ALL device on the bus can be masters
of a DMA transaction. So adding an interface as suggested by
Michael: pci_set_master_for_master_abort
On Mon, 2013-09-09 at 14:39 +0100, Peter Maydell wrote:
On 9 September 2013 14:29, Marcel Apfelbaum marce...@redhat.com wrote:
My issue is that we have at least 2 ways to model the bridges:
1. TYPE_PCI_HOST_BRIDGE
* derives from TYPE_SYS_BUS_DEVICE
* has a bus
* one of the bus
On Mon, 2013-09-09 at 16:58 +0300, Michael S. Tsirkin wrote:
On Mon, Sep 09, 2013 at 03:43:49PM +0300, Marcel Apfelbaum wrote:
On Mon, 2013-09-09 at 15:23 +0300, Michael S. Tsirkin wrote:
On Mon, Sep 09, 2013 at 03:11:55PM +0300, Marcel Apfelbaum wrote:
On Mon, 2013-09-09 at 14:40 +0300
On Mon, 2013-09-09 at 17:04 +0300, Michael S. Tsirkin wrote:
On Mon, Sep 09, 2013 at 04:29:04PM +0300, Marcel Apfelbaum wrote:
On Mon, 2013-09-09 at 14:19 +0100, Peter Maydell wrote:
On 9 September 2013 14:15, Marcel Apfelbaum marce...@redhat.com wrote:
On Mon, 2013-09-09 at 14:02 +0100
On Mon, 2013-09-09 at 15:21 +0100, Peter Maydell wrote:
On 9 September 2013 15:04, Marcel Apfelbaum marce...@redhat.com wrote:
By the way, I am not sure that the upstream transactions (DMA)
can actually end with a master abort. Master abort would happen
if a transaction will not be claimed
Qemu is expected to quit if the same boot index value is used by two devices.
However, hot-plugging a device with a bootindex value already used should
fail with a friendly message rather than quitting a running VM.
Signed-off-by: Marcel Apfelbaum marce...@redhat.com
---
qdev-monitor.c | 33
On Wed, 2013-09-11 at 21:26 +0300, Marcel Apfelbaum wrote:
Qemu is expected to quit if the same boot index value is used by two devices.
However, hot-plugging a device with a bootindex value already used should
fail with a friendly message rather than quitting a running VM.
Signed-off
On Thu, 2013-09-12 at 09:49 +0200, Paolo Bonzini wrote:
Il 11/09/2013 20:26, Marcel Apfelbaum ha scritto:
Qemu is expected to quit if the same boot index value is used by two
devices.
However, hot-plugging a device with a bootindex value already used should
fail with a friendly message
On Thu, 2013-09-12 at 11:43 +0200, Markus Armbruster wrote:
Paolo Bonzini pbonz...@redhat.com writes:
Il 11/09/2013 20:26, Marcel Apfelbaum ha scritto:
Qemu is expected to quit if the same boot index value is used by two
devices.
However, hot-plugging a device with a bootindex value
On Thu, 2013-09-12 at 13:04 +0200, Markus Armbruster wrote:
Marcel Apfelbaum marce...@redhat.com writes:
On Thu, 2013-09-12 at 11:43 +0200, Markus Armbruster wrote:
Paolo Bonzini pbonz...@redhat.com writes:
Il 11/09/2013 20:26, Marcel Apfelbaum ha scritto:
Qemu is expected to quit
On Sun, 2013-09-15 at 00:08 +0300, Michael S. Tsirkin wrote:
On Mon, Sep 09, 2013 at 02:21:36PM +0300, Marcel Apfelbaum wrote:
Created a MemoryRegion with negative priority that
spans over all the pci address space.
It intercepts the accesses to unassigned pci
address space
On Tue, 2013-09-10 at 14:12 +0100, Peter Maydell wrote:
On 10 September 2013 14:02, Michael S. Tsirkin m...@redhat.com wrote:
On Tue, Sep 10, 2013 at 01:50:47PM +0100, Peter Maydell wrote:
On 10 September 2013 13:39, Michael S. Tsirkin m...@redhat.com wrote:
On Mon, Sep 09, 2013 at
register
of the device that initiated the transaction will be
implemented in another series
Note: This implementation handles only the reads/writes to
the pci address space that are done by the cpu.(downstream)
Signed-off-by: Marcel Apfelbaum marce...@redhat.com
---
Changes from v3
-unassigned-mem MemoryRegion resides now in PCIBus and not on
various Host Bridges
- pci-unassgined-mem does not have a .valid.accept field and
implements read write methods
Marcel Apfelbaum (3):
memory: allow MemoryRegion's priority field to accept negative values
docs/memory: Explictly
-by: Marcel Apfelbaum marce...@redhat.com
---
docs/memory.txt | 4
1 file changed, 4 insertions(+)
diff --git a/docs/memory.txt b/docs/memory.txt
index feb9fe9..174c0d7 100644
--- a/docs/memory.txt
+++ b/docs/memory.txt
@@ -80,6 +80,10 @@ guest. This is done
subregions.
Signed-off-by: Marcel Apfelbaum marce...@redhat.com
---
Changes from v3:
- Addressed Peter Maydell comments
- Removed unnecessary changes to priority of MemoryListener
- Ensured that priority is now signed in all related places
hw/core/sysbus.c | 4 ++--
include/exec
On Sun, 2013-09-15 at 20:30 +0300, Michael S. Tsirkin wrote:
On Sun, Sep 15, 2013 at 07:16:41PM +0300, Marcel Apfelbaum wrote:
A MemoryRegion with negative priority was created and
it spans over all the pci address space.
It intercepts the accesses to unassigned pci
address space
On Sun, 2013-09-15 at 18:32 +0100, Peter Maydell wrote:
On 15 September 2013 18:30, Michael S. Tsirkin m...@redhat.com wrote:
On Sun, Sep 15, 2013 at 07:16:41PM +0300, Marcel Apfelbaum wrote:
+static const MemoryRegionOps master_abort_mem_ops = {
+.read = master_abort_mem_read
from v2:
- minor: changed nr of patches in the title
- minor: modified series list
Changes from v1:
- pci-unassigned-mem MemoryRegion resides now in PCIBus and not on
various Host Bridges
- pci-unassgined-mem does not have a .valid.accept field and
implements read write methods
Marcel
to explicitly
specify a high priority for all the other regions, we can let them take
the default (zero) priority and specify a negative priority for the
background region.
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
Acked-by: Michael S. Tsirkin m...@redhat.com
Signed-off-by: Marcel
register
of the device that initiated the transaction will be
implemented in another series
Signed-off-by: Marcel Apfelbaum marce...@redhat.com
---
Changes from v4:
- Addressed Michael S. Tsirkin comments
- Changed PCI master_abort_mem ops endian-nes to DEVICE_LITTLE_ENDIAN
- Fixed
to explicitly
specify a high priority for all the other regions, we can let them take
the default (zero) priority and specify a negative priority for the
background region.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Signed-off-by: Marcel Apfelbaum marce...@redhat.com
---
Changes from v4
On Mon, 2013-09-16 at 12:04 +0300, Michael S. Tsirkin wrote:
On Mon, Sep 16, 2013 at 11:21:16AM +0300, Marcel Apfelbaum wrote:
A MemoryRegion with negative priority was created and
it spans over all the pci address space.
It intercepts the accesses to unassigned pci
address space
On Thu, 2013-09-12 at 13:04 +0200, Markus Armbruster wrote:
Marcel Apfelbaum marce...@redhat.com writes:
On Thu, 2013-09-12 at 11:43 +0200, Markus Armbruster wrote:
Paolo Bonzini pbonz...@redhat.com writes:
Il 11/09/2013 20:26, Marcel Apfelbaum ha scritto:
Qemu is expected to quit
On Mon, 2013-09-16 at 12:51 +0300, Michael S. Tsirkin wrote:
On Mon, Sep 16, 2013 at 12:11:32PM +0300, Marcel Apfelbaum wrote:
On Mon, 2013-09-16 at 12:04 +0300, Michael S. Tsirkin wrote:
On Mon, Sep 16, 2013 at 11:21:16AM +0300, Marcel Apfelbaum wrote:
A MemoryRegion with negative
Hi all,
I have an AddressSpace backed by a single MemoryRegion which is
initiated using memory_region_init_io (has ops).
Once I enable it, I get an assertion:
exec.c:806: register_subpage: Assertion `existing-mr-subpage ||
existing-mr == io_mem_unassigned' failed.
Here is the pseudo-code:
On Monday, September 16, 2013, Paolo Bonzini pbonz...@redhat.com wrote:
Il 16/09/2013 16:48, Marcel Apfelbaum ha scritto:
Hi all,
I have an AddressSpace backed by a single MemoryRegion which yis
initiated using memoy_region_init_io (has ops).
Once I enable it, I get an assertion:
exec.c
On Mon, 2013-09-16 at 16:52 +0200, Paolo Bonzini wrote:
Il 16/09/2013 16:48, Marcel Apfelbaum ha scritto:
Hi all,
I have an AddressSpace backed by a single MemoryRegion which is
initiated using memory_region_init_io (has ops).
Once I enable it, I get an assertion:
exec.c:806
On Mon, 2013-09-16 at 19:18 +0200, Paolo Bonzini wrote:
Il 16/09/2013 19:11, Marcel Apfelbaum ha scritto:
memory_region_init_io(my_reg, owner, my_ops, my_obj, my region,
INT64_MAX);
This is 2^63-1, not 2^64-1. You need UINT64_MAX here.
Ooops! Thanks a lot and sorry for the trouble
regions for PCI-2-PCI bridge's secondary bus.
Set Received Master Abort Bit on Status/Secondary Status
register as defined in the PCI Spec.
Signed-off-by: Marcel Apfelbaum marce...@redhat.com
---
hw/pci/pci.c | 115 ++-
hw/pci/pci_bridge.c
On Mon, 2013-09-23 at 14:27 +0300, Michael S. Tsirkin wrote:
On Mon, Sep 23, 2013 at 02:01:17PM +0300, Marcel Apfelbaum wrote:
This patch is implemented on top of series:
[PATCH v5 0/3] pci: implement upstream master abort protocol
Added master abort io background region for PCIBus
On Mon, 2013-09-23 at 16:45 +0300, Michael S. Tsirkin wrote:
On Mon, Sep 23, 2013 at 03:37:43PM +0300, Marcel Apfelbaum wrote:
On Mon, 2013-09-23 at 14:27 +0300, Michael S. Tsirkin wrote:
On Mon, Sep 23, 2013 at 02:01:17PM +0300, Marcel Apfelbaum wrote:
This patch is implemented on top
On Mon, 2013-09-23 at 18:10 +0300, Michael S. Tsirkin wrote:
On Mon, Sep 23, 2013 at 05:43:38PM +0300, Marcel Apfelbaum wrote:
On Mon, 2013-09-23 at 16:45 +0300, Michael S. Tsirkin wrote:
On Mon, Sep 23, 2013 at 03:37:43PM +0300, Marcel Apfelbaum wrote:
On Mon, 2013-09-23 at 14:27 +0300
On Mon, 2013-09-23 at 21:45 +0300, Michael S. Tsirkin wrote:
On Mon, Sep 23, 2013 at 08:49:53PM +0300, Marcel Apfelbaum wrote:
On Mon, 2013-09-23 at 18:10 +0300, Michael S. Tsirkin wrote:
On Mon, Sep 23, 2013 at 05:43:38PM +0300, Marcel Apfelbaum wrote:
On Mon, 2013-09-23 at 16:45 +0300
On Tue, 2013-09-24 at 11:29 +0300, Michael S. Tsirkin wrote:
On Tue, Sep 24, 2013 at 11:07:19AM +0300, Marcel Apfelbaum wrote:
On Mon, 2013-09-23 at 21:45 +0300, Michael S. Tsirkin wrote:
On Mon, Sep 23, 2013 at 08:49:53PM +0300, Marcel Apfelbaum wrote:
On Mon, 2013-09-23 at 18:10 +0300
On Tue, 2013-09-24 at 11:58 +0300, Michael S. Tsirkin wrote:
corrected Anthony's mail.
On Tue, Sep 24, 2013 at 11:44:57AM +0300, Marcel Apfelbaum wrote:
Not necessarily. Another bridge can claim it then
terminate with MA.
Example:
-[:00]-+-00.0
+-02.0
On Tue, 2013-09-24 at 19:55 +0900, Peter Maydell wrote:
On 24 September 2013 19:44, Marcel Apfelbaum marce...@redhat.com wrote:
We need to check all the bridges on each bus encountered
for their address range; if it corresponds to the transaction address,
we pass the bridge to the other bus
On Tue, 2013-09-24 at 20:21 +0900, Peter Maydell wrote:
On 24 September 2013 20:17, Marcel Apfelbaum marce...@redhat.com wrote:
I was suggesting an algorithm to find the MA device in order
to set MA Received Bit in its Status(Sec_Status) register.
The algorithm was to traverse the PCI
On Wed, 2013-09-25 at 10:01 +0300, Michael S. Tsirkin wrote:
On Tue, Sep 24, 2013 at 06:01:02AM -0400, Laine Stump wrote:
When I added support for the Q35-based machinetypes to libvirt, I
specifically prohibited attaching any PCI devices (with the exception of
graphics controllers) to the
pci_set_irq uses PCI_INTERRUPT_PIN config register
to compute device INTx pin to assert/deassert.
Signed-off-by: Marcel Apfelbaum marce...@redhat.com
---
hw/audio/ac97.c| 4 ++--
hw/audio/es1370.c | 2 +-
hw/audio/intel-hda.c | 2 +-
hw/char/serial-pci.c | 2 +-
hw/char/tpci200
The PCI_INTERRUPT_PIN will be used by shpc init, so
was moved before the call to shpc_init.
Signed-off-by: Marcel Apfelbaum marce...@redhat.com
---
hw/pci-bridge/pci_bridge_dev.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/pci-bridge/pci_bridge_dev.c b/hw/pci-bridge
Interrupt pin is selected and saved into PCI_INTERRUPT_PIN
register during device initialization. Devices should not call
directly qemu_set_irq and specify the INTx pin.
Replaced the call to qemu_set_irq with a new wrapper
pci_set_irq which triggers the irq based on PCI_INTERRUPT_PIN.
Marcel
.
Renamed a static method which was named already pci_set_irq.
Signed-off-by: Marcel Apfelbaum marce...@redhat.com
---
hw/pci/pci.c | 6 +++---
include/hw/pci/pci.h | 7 +++
2 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index 1f4e707
removed addresses:
av1...@comtv.ru
p...@codesourcery.com
On Sun, 2013-09-29 at 18:06 +0300, Michael S. Tsirkin wrote:
On Sun, Sep 29, 2013 at 05:40:54PM +0300, Marcel Apfelbaum wrote:
Interrupt pin is selected and saved into PCI_INTERRUPT_PIN
register during device initialization. Devices
Categorize devices that appear as output to -device ? command
by logical functionality. Sort the devices by logical categories
before showing them to user.
The sort is done by functionality rather than alphabetical.
Signed-off-by: Marcel Apfelbaum marce...@redhat.com
---
Changes from RFC
Made
/...
Management - controllers
...
(All others are self explanatory)
Changes from RFC patch:
Made category a bitmap to support multifunction PCI devices.
Assigned all devices to their category.
Marcel Apfelbaum (2):
qemu-help: Sort devices by logical functionality
devices: Associate devices
to their category.
Marcel Apfelbaum (3):
hw: import bitmap operations in qdev-core header
qemu-help: Sort devices by logical functionality
devices: Associate devices to their logical category
hw/9pfs/virtio-9p-device.c | 1 +
hw/audio/ac97.c| 1 +
hw/audio/adlib.c
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