qemu_malloc() is type-unsafe as it returns a void pointer. Introduce
QEMU_NEW() (and QEMU_NEWZ()), which return the correct type.
Just use g_new() and g_new0()
These bypass qemu_malloc(). Are we okay with that?
Yes. We can just make qemu_malloc use g_malloc.
It would be also possible
Dear,
Is anyone can help me? I'm deeply in trouble. I want boot by kernel by
qemu, i want boot from dhcp, but i got error,
i have no idea on this, two days... i cannot find the solution. Anyone knows
why? Thanks very much.
[...]
bellow is kernel error message:
[ 13.087298] VFS:
Hello.
+ case 13: /*QUOSi*/
+ tcg_gen_div_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
+ break;
I'm currently developing test suite for xtensa port and found that
with this implementation of QUOS (signed 32-bit division) guest that
divide 0x8000
Hello.
+ case 13: /*QUOSi*/
+ tcg_gen_div_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
+ break;
I'm currently developing test suite for xtensa port and found that
with this implementation of QUOS (signed 32-bit division) guest that
divide
Hi, all
I am trying to figure out why QEMU put some constraints on block
linking (chaining). Take x86 as an example, there are two places
put constraints on block linking, gen_goto_tb and cpu_exec.
- gen_goto_tb (target-i386/translate.c) ---
/* NOTE: we handle
If we link a TB with another TB from the different page, then the
second TB may disappear when the memory mapping changes and the
subsequent direct jump from the first TB will crash qemu.
Perhaps the guest OS swap the second TB out of the guest memory,
is it what you mean?
I meant TLB
Add myself as target-xtensa and DC232B maintainer.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
MAINTAINERS | 13 +
1 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 508ea1e..72b2099 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
See ISA, 4.4.6 (interrupt option), 4.4.7 (high priority interrupt
option) and 4.4.8 (timer interrupt option) for details.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
v2 - v3 changes:
- handle IRQ deassertion for INTTYPE_LEVEL interrupts only;
- initialize PS at reset in accordance
See ISA, 4.3.3 for details.
TB flag XTENSA_TBFLAG_LITBASE is used to track enable bit of LITBASE SR.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
v2 - v3 changes:
- correctly mask stored litbase value on wsr.
---
target-xtensa/cpu.h |6 ++
target-xtensa/helper.c|1
not support operations with privileged SRs
(see http://sourceware.org/ml/gdb/2011-07/msg00075.html). This support
may be enabled, see NUM_CORE_REGS comment in the gdbstub.c
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
gdbstub.c | 96 +++
target-xtensa
This is Diamond 232L Standard Core Rev.B (LE).
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
Makefile.target |1 +
hw/xtensa_dc232b.c| 112
target-xtensa/gdb-config-dc232b.c | 261 +
target-xtensa
- base + offset load/store operations for 1/2/4 byte values;
- cache operations (not implemented);
- multiprocessor synchronization operations.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/cpu.h |1 +
target-xtensa/translate.c | 89
See ISA, 4.4.4 for details.
Correct (aligned as per ISA) address for unaligned access is generated
in case this option is not enabled.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/helper.c|4 ++-
target-xtensa/op_helper.c | 26
target
Reserved opcodes must generate illegal instruction exception. Usually
they signal emulation quality problems.
Not implemented opcodes are good to see.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/translate.c | 110 -
1 files
NEG and ABS are the only members of RT0 group.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/translate.c | 19 +++
1 files changed, 19 insertions(+), 0 deletions(-)
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index 2ff5838..dcbc0ae
Group SNM0 (indirect jumps and calls).
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/translate.c | 43 +++
1 files changed, 43 insertions(+), 0 deletions(-)
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index
Sample board and sample CPU core are used for debug and may be used for
development of custom SoC emulators.
This board has two fixed size memory regions for DTCM and ITCM and
variable length SRAM region.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
Makefile.target|1 +
hw
All operations in this group are no-ops, because there are no delayed
side effects.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/translate.c | 31 ++-
1 files changed, 30 insertions(+), 1 deletions(-)
diff --git a/target-xtensa/translate.c b
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
configure| 12 +++-
default-configs/xtensa-softmmu.mak |1 +
default-configs/xtensaeb-softmmu.mak |1 +
3 files changed, 13 insertions(+), 1 deletions(-)
create mode 100644 default-configs/xtensa
See ISA, 4.7.1.3 for details.
Window check is inserted before commands that push used register
watermark beyond its current level. Used register watermark is reset on
instructions that change WINDOW_BASE/WINDOW_START SRs.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa
- TLB opcode group;
- region protection option (ISA, 4.6.3);
- region translation option (ISA, 4.6.4);
- MMU option (ISA, 4.6.5).
Cache control attribute bits are not used by this implementation.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/cpu.h | 56
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
hw/xtensa_sample.c|1 +
target-xtensa/cpu.h |2 ++
target-xtensa/translate.c |7 +++
3 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/hw/xtensa_sample.c b/hw/xtensa_sample.c
index 9f7733b..c2ad48a
is in separate patch.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/cpu.h |8 ++
target-xtensa/helper.c|1 +
target-xtensa/helpers.h |8 ++
target-xtensa/op_helper.c | 185 +
target-xtensa/translate.c | 144
or uregnames are considered valid.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/cpu.h |7 ++
target-xtensa/translate.c | 47 +++-
2 files changed, 52 insertions(+), 2 deletions(-)
diff --git a/target-xtensa/cpu.h b/target
- ST1: SAR (shift amount special register) manipulation, NSA(U);
- RST1: shifts, 16-bit multiplication.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/cpu.h |4 +
target-xtensa/helpers.h |2 +
target-xtensa/op_helper.c | 14 +++
target-xtensa/translate.c
looping code verifies actual LEND value.
Invalidation may be avoided for the TB at the new LEND address if
there's a way to associate LEND address with TB at compilation time and
later verify that it doesn't change.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/cpu.h |3
Set up disas_xtensa_insn switch structure, mark required options on high
level groups. Implement arithmetic/bit logic/jump/call0.
Implement code generation loop with single step/breakpoint checking.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/cpu.h | 67
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/cpu.h | 53 -
target-xtensa/helper.c|1 +
target-xtensa/translate.c | 29
3 files changed, 77 insertions(+), 6 deletions(-)
diff --git a/target
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
Makefile.target |2 +
arch_init.c |2 +
arch_init.h |1 +
cpu-exec.c|2 +
elf.h |2 +
hw/xtensa_pic.c | 38 ++
target-xtensa
See ISA, 4.4.3 for details.
Vector addresses recorded in core configuration are absolute values that
correspond to default VECBASE value.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/cpu.h |2 ++
target-xtensa/helper.c| 18 --
target-xtensa
Instructions with op0 = 8 are 2 bytes long, others are 3 bytes long.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/translate.c | 54 +
1 files changed, 54 insertions(+), 0 deletions(-)
diff --git a/target-xtensa/translate.c b
- access to Special Registers (wsr, rsr);
- access to User Registers (wur, rur);
- misc. operations option (value clamp, sign extension, min, max);
- conditional moves.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/translate.c | 161
by the testsuite;
- improve interrupt option implementation.
Git tree is available at git://jcmvbkbc.spb.ru/dumb/qemu-xtensa.git xtensa
Max Filippov (32):
target-xtensa: add target stubs
target-xtensa: add target to the configure script
target-xtensa: implement disas_xtensa_insn
target-xtensa: implement
- mark privileged opcodes with ring check;
- make debug exception on exception handler entry.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
cpu-exec.c|6 +++
target-xtensa/cpu.h | 67
target-xtensa/helper.c| 37
Tensilica iss provides support for applications running in freestanding
environment through SIMCALL command. It is used by Tensilica libc to
access argc/argv, for file I/O, etc.
Note that simcalls that accept buffer addresses expect virtual addresses.
Signed-off-by: Max Filippov jcmvb
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
v2 - v3 changes:
- handle integer overflow for QUOS/REMS.
---
target-xtensa/translate.c | 77 -
1 files changed, 76 insertions(+), 1 deletions(-)
diff --git a/target-xtensa/translate.c b/target
- BZ (comparison to zero);
- BI0 (comparison to signed immediate);
- BI1 (comparison to unsigned immediate);
- B (two registers comparison, bit sets comparison);
- BEQZ.N/BNEZ.N (narrow comparison to zero).
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/translate.c | 164
All operations in this group are no-ops, because cache ought to be
transparent to applications. However cache may be abused, then we'll
need to actually implement these opcodes.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/translate.c | 95
of identifiers starting with _[A-Z].
Git tree is available at git://jcmvbkbc.spb.ru/dumb/qemu-xtensa.git xtensa
Max Filippov (32):
target-xtensa: add target stubs
target-xtensa: add target to the configure script
target-xtensa: implement disas_xtensa_insn
target-xtensa: implement narrow
NEG and ABS are the only members of RT0 group.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/translate.c | 19 +++
1 files changed, 19 insertions(+), 0 deletions(-)
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index 7404098..c9e2c06
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
configure| 12 +++-
default-configs/xtensa-softmmu.mak |1 +
default-configs/xtensaeb-softmmu.mak |1 +
3 files changed, 13 insertions(+), 1 deletions(-)
create mode 100644 default-configs/xtensa
- mark privileged opcodes with ring check;
- make debug exception on exception handler entry.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
cpu-exec.c|6 +++
target-xtensa/cpu.h | 67
target-xtensa/helper.c| 37
looping code verifies actual LEND value.
Invalidation may be avoided for the TB at the new LEND address if
there's a way to associate LEND address with TB at compilation time and
later verify that it doesn't change.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/cpu.h |3
This is Diamond 232L Standard Core Rev.B (LE).
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
Makefile.target |1 +
hw/xtensa_dc232b.c| 112
target-xtensa/gdb-config-dc232b.c | 261 +
target-xtensa
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
Makefile.target |2 +
arch_init.c |2 +
arch_init.h |1 +
cpu-exec.c|2 +
elf.h |2 +
hw/xtensa_pic.c | 38 ++
target-xtensa
See ISA, 4.4.3 for details.
Vector addresses recorded in core configuration are absolute values that
correspond to default VECBASE value.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/cpu.h |2 ++
target-xtensa/helper.c| 18 --
target-xtensa
Tensilica iss provides support for applications running in freestanding
environment through SIMCALL command. It is used by Tensilica libc to
access argc/argv, for file I/O, etc.
Note that simcalls that accept buffer addresses expect virtual addresses.
Signed-off-by: Max Filippov jcmvb
Add myself as target-xtensa and DC232B maintainer.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
MAINTAINERS | 13 +
1 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 508ea1e..72b2099 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
See ISA, 4.4.4 for details.
Correct (aligned as per ISA) address for unaligned access is generated
in case this option is not enabled.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/helper.c|4 ++-
target-xtensa/op_helper.c | 26
target
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/translate.c | 77 -
1 files changed, 76 insertions(+), 1 deletions(-)
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index 4c9db9e..de5f947 100644
--- a/target
- BZ (comparison to zero);
- BI0 (comparison to signed immediate);
- BI1 (comparison to unsigned immediate);
- B (two registers comparison, bit sets comparison);
- BEQZ.N/BNEZ.N (narrow comparison to zero).
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/translate.c | 164
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
hw/xtensa_sample.c|1 +
target-xtensa/cpu.h |2 ++
target-xtensa/translate.c |7 +++
3 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/hw/xtensa_sample.c b/hw/xtensa_sample.c
index 9f7733b..c2ad48a
- access to Special Registers (wsr, rsr);
- access to User Registers (wur, rur);
- misc. operations option (value clamp, sign extension, min, max);
- conditional moves.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/translate.c | 161
- TLB opcode group;
- region protection option (ISA, 4.6.3);
- region translation option (ISA, 4.6.4);
- MMU option (ISA, 4.6.5).
Cache control attribute bits are not used by this implementation.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/cpu.h | 56
is in separate patch.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/cpu.h |8 ++
target-xtensa/helper.c|1 +
target-xtensa/helpers.h |8 ++
target-xtensa/op_helper.c | 185 +
target-xtensa/translate.c | 144
See ISA, 4.4.6 (interrupt option), 4.4.7 (high priority interrupt
option) and 4.4.8 (timer interrupt option) for details.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
hw/xtensa_pic.c | 96
target-xtensa/cpu.h | 45 +-
target
See ISA, 4.3.3 for details.
TB flag XTENSA_TBFLAG_LITBASE is used to track enable bit of LITBASE SR.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/cpu.h |6 ++
target-xtensa/helper.c|1 +
target-xtensa/translate.c | 37
See ISA, 4.7.1.3 for details.
Window check is inserted before commands that push used register
watermark beyond its current level. Used register watermark is reset on
instructions that change WINDOW_BASE/WINDOW_START SRs.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/cpu.h | 53 -
target-xtensa/helper.c|1 +
target-xtensa/translate.c | 29
3 files changed, 77 insertions(+), 6 deletions(-)
diff --git a/target
All operations in this group are no-ops, because there are no delayed
side effects.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/translate.c | 31 ++-
1 files changed, 30 insertions(+), 1 deletions(-)
diff --git a/target-xtensa/translate.c b
- ST1: SAR (shift amount special register) manipulation, NSA(U);
- RST1: shifts, 16-bit multiplication.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/cpu.h |4 +
target-xtensa/helpers.h |2 +
target-xtensa/op_helper.c | 14 +++
target-xtensa/translate.c
- base + offset load/store operations for 1/2/4 byte values;
- cache operations (not implemented);
- multiprocessor synchronization operations.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/cpu.h |1 +
target-xtensa/translate.c | 89
Reserved opcodes must generate illegal instruction exception. Usually
they signal emulation quality problems.
Not implemented opcodes are good to see.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/translate.c | 110 -
1 files
Sample board and sample CPU core are used for debug and may be used for
development of custom SoC emulators.
This board has two fixed size memory regions for DTCM and ITCM and
variable length SRAM region.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
Makefile.target|1 +
hw
Instructions with op0 = 8 are 2 bytes long, others are 3 bytes long.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/translate.c | 54 +
1 files changed, 54 insertions(+), 0 deletions(-)
diff --git a/target-xtensa/translate.c b
Set up disas_xtensa_insn switch structure, mark required options on high
level groups. Implement arithmetic/bit logic/jump/call0.
Implement code generation loop with single step/breakpoint checking.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/cpu.h | 67
All operations in this group are no-ops, because cache ought to be
transparent to applications. However cache may be abused, then we'll
need to actually implement these opcodes.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/translate.c | 95
Group SNM0 (indirect jumps and calls).
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/translate.c | 43 +++
1 files changed, 43 insertions(+), 0 deletions(-)
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index
not support operations with privileged SRs
(see http://sourceware.org/ml/gdb/2011-07/msg00075.html). This support
may be enabled, see NUM_CORE_REGS comment in the gdbstub.c
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
gdbstub.c | 96 +++
target-xtensa
or uregnames are considered valid.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/cpu.h |7 ++
target-xtensa/translate.c | 47 +++-
2 files changed, 52 insertions(+), 2 deletions(-)
diff --git a/target-xtensa/cpu.h b/target
I just had a very quick look and it Looks good to me too. Would be awesome
if Max could provide something to test with in binary form. Maybe we could
put it on the wiki's download page.
Tarball of my current kernel and rootfs is available at
- mark privileged opcodes with ring check;
- make debug exception on exception handler entry.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
cpu-exec.c|6 +++
target-xtensa/cpu.h | 67
target-xtensa/helper.c| 37
- TLB opcode group;
- region protection option (ISA, 4.6.3);
- region translation option (ISA, 4.6.4);
- MMU option (ISA, 4.6.5).
Cache control attribute bits are not used by this implementation.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/cpu.h | 56
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/cpu.h | 53 -
target-xtensa/helper.c|1 +
target-xtensa/translate.c | 29
3 files changed, 77 insertions(+), 6 deletions(-)
diff --git a/target
See ISA, 4.3.9
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/cpu.h |1 +
target-xtensa/translate.c | 109 +++--
2 files changed, 86 insertions(+), 24 deletions(-)
diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
index
See ISA, 4.7.1.3 for details.
Window check is inserted before commands that push used register
watermark beyond its current level. Used register watermark is reset on
instructions that change WINDOW_BASE/WINDOW_START SRs.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa
See ISA, 4.3.3 for details.
TB flag XTENSA_TBFLAG_LITBASE is used to track enable bit of LITBASE SR.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/cpu.h |6 ++
target-xtensa/helper.c|1 +
target-xtensa/translate.c | 37
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/translate.c | 77 -
1 files changed, 76 insertions(+), 1 deletions(-)
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index dccd453..bc04a10 100644
--- a/target
See ISA, 4.4.3 for details.
Vector addresses recorded in core configuration are absolute values that
correspond to default VECBASE value.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/cpu.h |2 ++
target-xtensa/helper.c| 18 --
target-xtensa
Tensilica iss provides support for applications running in freestanding
environment through SIMCALL command. It is used by Tensilica libc to
access argc/argv, for file I/O, etc.
Note that simcalls that accept buffer addresses expect virtual addresses.
Signed-off-by: Max Filippov jcmvb
- BZ (comparison to zero);
- BI0 (comparison to signed immediate);
- BI1 (comparison to unsigned immediate);
- B (two registers comparison, bit sets comparison);
- BEQZ.N/BNEZ.N (narrow comparison to zero).
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/translate.c | 164
or uregnames are considered valid.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/cpu.h |7 ++
target-xtensa/translate.c | 49 +++-
2 files changed, 54 insertions(+), 2 deletions(-)
diff --git a/target-xtensa/cpu.h b/target
See ISA, 4.4.4 for details.
Correct (aligned as per ISA) address for unaligned access is generated
in case this option is not enabled.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/helper.c|4 ++-
target-xtensa/op_helper.c | 26
target
Set up disas_xtensa_insn switch structure, mark required options on high
level groups. Implement arithmetic/bit logic/jump/call0.
Implement code generation loop with single step/breakpoint checking.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/cpu.h | 67
All operations in this group are no-ops, because cache ought to be
transparent to applications. However cache may be abused, then we'll
need to actually implement these opcodes.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/translate.c | 95
Add myself as target-xtensa and DC232B maintainer.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
MAINTAINERS | 13 +
1 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 508ea1e..72b2099 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
NEG and ABS are the only members of RT0 group.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/translate.c | 19 +++
1 files changed, 19 insertions(+), 0 deletions(-)
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index 4dfca2b..92547d2
Reserved opcodes must generate illegal instruction exception. Usually
they signal emulation quality problems.
Not implemented opcodes are good to see.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/translate.c | 110 -
1 files
- ST1: SAR (shift amount special register) manipulation, NSA(U);
- RST1: shifts, 16-bit multiplication.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/cpu.h |4 +
target-xtensa/helpers.h |2 +
target-xtensa/op_helper.c | 14 +++
target-xtensa/translate.c
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
Makefile.target |2 +
arch_init.c |2 +
arch_init.h |1 +
cpu-exec.c|2 +
elf.h |2 +
hw/xtensa_pic.c | 38 ++
target-xtensa
- base + offset load/store operations for 1/2/4 byte values;
- cache operations (not implemented);
- multiprocessor synchronization operations.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/cpu.h |1 +
target-xtensa/translate.c | 89
Group SNM0 (indirect jumps and calls).
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/translate.c | 43 +++
1 files changed, 43 insertions(+), 0 deletions(-)
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index
- access to Special Registers (wsr, rsr);
- access to User Registers (wur, rur);
- misc. operations option (value clamp, sign extension, min, max);
- conditional moves.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/translate.c | 161
Instructions with op0 = 8 are 2 bytes long, others are 3 bytes long.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/translate.c | 54 +
1 files changed, 54 insertions(+), 0 deletions(-)
diff --git a/target-xtensa/translate.c b
looping code verifies actual LEND value.
Invalidation may be avoided for the TB at the new LEND address if
there's a way to associate LEND address with TB at compilation time and
later verify that it doesn't change.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/cpu.h |3
Sample board and sample CPU core are used for debug and may be used for
development of custom SoC emulators.
This board has two fixed size memory regions for DTCM and ITCM and
variable length SRAM region.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
Makefile.target|1 +
hw
not support operations with privileged SRs
(see http://sourceware.org/ml/gdb/2011-07/msg00075.html). This support
may be enabled, see NUM_CORE_REGS comment in the gdbstub.c
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
gdbstub.c | 96 +++
target-xtensa
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
configure| 12 +++-
default-configs/xtensa-softmmu.mak |1 +
default-configs/xtensaeb-softmmu.mak |1 +
3 files changed, 13 insertions(+), 1 deletions(-)
create mode 100644 default-configs/xtensa
, comparison order, missing braces);
- turn WINDOWBASE_BOUND and WINDOWSTART_BIT macros into inline functions;
- convert sample boards to memory API.
Git tree is available at git://jcmvbkbc.spb.ru/dumb/qemu-xtensa.git xtensa
Max Filippov (33):
target-xtensa: add target stubs
target-xtensa: add target
See ISA, 4.4.6 (interrupt option), 4.4.7 (high priority interrupt
option) and 4.4.8 (timer interrupt option) for details.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
hw/xtensa_pic.c | 96
target-xtensa/cpu.h | 45 +-
target
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