On Tue, Jan 9, 2018 at 3:31 AM, Christoph Hellwig wrote:
> On Wed, Jan 03, 2018 at 01:44:15PM +1300, Michael Clark wrote:
> > HTIF (Host Target Interface) provides console emulation for QEMU. HTIF
> > allows identical copies of BBL (Berkeley Boot Loader) and linux to run
> &
On Fri, Jan 5, 2018 at 7:22 PM, Michael Clark wrote:
>
> On Fri, 5 Jan 2018 at 5:55 AM, Antony Pavlov
> wrote:
>
>> On Wed, 3 Jan 2018 13:44:25 +1300
>> Michael Clark wrote:
>>
>> > This adds RISC-V into the build system enabling the followi
On Mon, Jan 29, 2018 at 12:33 PM, Jim Wilson wrote:
> On Wed, Jan 24, 2018 at 3:47 PM, Richard Henderson
> wrote:
> > On 01/24/2018 10:58 AM, Jim Wilson wrote:
> >> Although, looking at this again, I see another statement in a
> >> different place that says:
> >>
> >> Except when otherwise state
On Mon, Jan 15, 2018 at 5:44 AM, Igor Mammedov wrote:
> On Wed, 10 Jan 2018 15:46:22 -0800
> Michael Clark wrote:
>
> > Add CPU state header, CPU definitions and initialization routines
> >
> > Signed-off-by: Michael Clark
> > ---
&
On Wed, Jan 24, 2018 at 8:16 AM, Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 01/23/2018 05:31 PM, Michael Clark wrote:
> > For the meantime we've greatly simplified cpu_mmu_index to just return
> the
> > processor mode as well as
On Tue, Jan 23, 2018 at 4:01 PM, Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 01/23/2018 01:37 PM, Michael Clark wrote:
> >
> >
> > On Wed, Jan 3, 2018 at 12:10 PM, Richard Henderson
> > mailto:richard.hender...@linaro.org>>
> wrote:
&
On Tue, Jan 23, 2018 at 3:15 PM, Michael Clark wrote:
>
>
> On Wed, Jan 3, 2018 at 12:10 PM, Richard Henderson <
> richard.hender...@linaro.org> wrote:
>
>> On 01/02/2018 04:44 PM, Michael Clark wrote:
>> > +/* convert RISC-V rounding mode to IEEE library n
On Wed, Jan 3, 2018 at 12:10 PM, Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 01/02/2018 04:44 PM, Michael Clark wrote:
> > +/* convert RISC-V rounding mode to IEEE library numbers */
> > +unsigned int ieee_rm[] = {
>
> static const.
>
>
On Wed, Jan 3, 2018 at 12:10 PM, Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 01/02/2018 04:44 PM, Michael Clark wrote:
> > +/* convert RISC-V rounding mode to IEEE library numbers */
> > +unsigned int ieee_rm[] = {
>
> static const.
Done.
>
On Fri, Jan 12, 2018 at 7:15 AM, Michael Clark wrote:
>
>
> On Fri, Jan 12, 2018 at 4:47 AM, Richard Henderson <
> richard.hender...@linaro.org> wrote:
>
>> On 01/10/2018 06:21 PM, Michael Clark wrote:
>> > TCG code generation for the RV32IMAFDC and R
On Fri, Jan 12, 2018 at 3:05 AM, Eric Blake wrote:
> On 01/10/2018 08:22 PM, Michael Clark wrote:
> > This adds RISC-V into the build system enabling the following targets:
> >
> > - riscv32-softmmu
> > - riscv64-softmmu
> > - riscv32-linux-user
> >
oning problem. In fact, device-tree should be frozen and versioned too
as it is only implicitly specified by the code that implements it.
On Thu, Jan 11, 2018 at 8:58 PM, Christoph Hellwig wrote:
> On Wed, Jan 10, 2018 at 03:46:19PM -0800, Michael Clark wrote:
> > - RISC-V Instruction Set
On Fri, Jan 12, 2018 at 4:47 AM, Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 01/10/2018 06:21 PM, Michael Clark wrote:
> > TCG code generation for the RV32IMAFDC and RV64IMAFDC. The QEMU
> > RISC-V code generator has complete coverage for the Base ISA v2.
On Fri, Jan 12, 2018 at 4:31 AM, Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 01/10/2018 06:21 PM, Michael Clark wrote:
> > Helper routines for FPU instructions and NaN definitions.
> >
> > Signed-off-by: Michael Clark
> > ---
> > fpu/soft
On Fri, Jan 12, 2018 at 3:37 AM, Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 01/10/2018 06:21 PM, Michael Clark wrote:
> > +static inline void cpu_get_tb_cpu_state(CPURISCVState *env,
> target_ulong *pc,
> > +
: Privileged ISA Version 1.9.1
- RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.10
Signed-off-by: Michael Clark
---
target/riscv/instmap.h | 377 +
target/riscv/translate.c | 1982 ++
2 files changed, 2359 insertions(+)
create
nf.sh'
script is updated to add the RISC-V ELF magic.
Expected checkpatch errors for consistency reasons:
ERROR: line over 90 characters
FILE: scripts/qemu-binfmt-conf.sh
Signed-off-by: Michael Clark
---
Makefile.objs | 1 +
arch_init.c
This provides a RISC-V Board compatible with the the SiFive E300 SDK.
The following machine is implemented:
- 'sifive_e300'; CLINT, PLIC, UART, AON, GPIO, QSPI, PWM
Signed-off-by: Michael Clark
---
hw/riscv/sifive_e300.c | 232 +
includ
1.10
Signed-off-by: Michael Clark
---
hw/riscv/spike_v1_09.c | 207 ++
hw/riscv/spike_v1_10.c | 281 +++
include/hw/riscv/spike.h | 51 +
3 files changed, 539 insertions(+)
create mode 100644 hw/riscv/spike_
reads the ELF kernel and locates the 'tohost' and
'fromhost' symbols which it uses for guest to host console MMIO.
The HTIT chardev implements the pre qom legacy interface consistent
with the 16550a UART in 'hw/char/serial.c'.
Signed-off-by: Michael Clark
---
hw/ri
The CLINT (Core Local Interruptor) device provides real-time clock, timer
and interprocessor interrupts based on SiFive's CLINT specification.
Signed-off-by: Michael Clark
---
hw/riscv/sifive_clint.c | 312
include/hw/riscv/sifive_clint.h
Privileged control and status register helpers and page fault handling.
Signed-off-by: Michael Clark
---
target/riscv/helper.c| 499 ++
target/riscv/helper.h| 78 ++
target/riscv/op_helper.c | 682 +++
3
This provides a RISC-V Board compatible with the the SiFive U500 SDK.
The following machine is implemented:
- 'sifive_u500'; CLINT, PLIC, UART, device-tree
Signed-off-by: Michael Clark
---
hw/riscv/sifive_u500.c | 338 +
includ
stency and brevity reasons:
ERROR: line over 90 characters
ERROR: trailing statements should be on next line
ERROR: space prohibited between function name and open parenthesis '('
Signed-off-by: Michael Clark
---
disas.c |2 +
disas/Makefile.objs |1 +
disas/
GDB Register read and write routines.
Signed-off-by: Michael Clark
---
target/riscv/gdbstub.c | 59 ++
1 file changed, 59 insertions(+)
create mode 100644 target/riscv/gdbstub.c
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
new
The PLIC (Platform Level Interrupt Controller) device provides a
parameterizable interrupt controller based on SiFive's PLIC specification.
Signed-off-by: Michael Clark
---
hw/riscv/sifive_plic.c | 554 +
include/hw/riscv/sifive_plic.h
RISC-V machine with device-tree, 16550a UART and VirtIO MMIO.
The following machine is implemented:
- 'virt'; CLINT, PLIC, 16550A UART, VirtIO MMIO, device-tree
Signed-off-by: Michael Clark
---
hw/riscv/virt.c | 364
includ
Implementation of linux user emulation for RISC-V.
Signed-off-by: Michael Clark
---
linux-user/elfload.c | 22 +++
linux-user/main.c | 114 +++
linux-user/riscv/syscall_nr.h | 275 +++
linux-user/riscv/target_cpu.h
Add CPU state header, CPU definitions and initialization routines
Signed-off-by: Michael Clark
---
target/riscv/cpu.c | 391 +
target/riscv/cpu.h | 271 +++
target/riscv/cpu_bits.h | 417
Simple model of the PRCI (Power, Reset, Clock, Interrupt) to emulate
register reads made by the SDK BSP.
Signed-off-by: Michael Clark
---
hw/riscv/sifive_prci.c | 107 +
include/hw/riscv/sifive_prci.h | 43 +
2 files changed, 150
/char/serial.c'.
Signed-off-by: Michael Clark
---
hw/riscv/sifive_uart.c | 182 +
include/hw/riscv/sifive_uart.h | 76 +
2 files changed, 258 insertions(+)
create mode 100644 hw/riscv/sifive_uart.c
create mode 100644 includ
preferable to keep
the code in-tree for folk that are interested in RISC-V PMP support.
Signed-off-by: Michael Clark
---
target/riscv/pmp.c | 386 +
target/riscv/pmp.h | 70 ++
2 files changed, 456 insertions(+)
create mode 100644 target
C, SiFive UART, device-tree, Priv v1.10
This is a list of RISC-V QEMU Port Contributors:
- Alex Suykov
- Antony Pavlov
- Bastian Koppelmann
- Bruce Hoult
- Chih-Min Chao
- Daire McNamara
- David Abdurachmanov
- Ivan Griffin
- Kito Cheng
- Michael Clark
- Palmer Dabbelt
- Sagar Karandikar
- Stefan
Helper routines for FPU instructions and NaN definitions.
Signed-off-by: Michael Clark
---
fpu/softfloat-specialize.h | 7 +-
target/riscv/fpu_helper.c | 591 +
2 files changed, 595 insertions(+), 3 deletions(-)
create mode 100644 target/riscv
Define RISC-V ELF machine EM_RISCV 243
Reviewed-by: Richard Henderson
Signed-off-by: Michael Clark
---
include/elf.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/elf.h b/include/elf.h
index e8a515c..8e457fc 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -112,6 +112,8
Holds the state of a heterogenous array of RISC-V hardware threads.
Signed-off-by: Michael Clark
---
hw/riscv/riscv_hart.c | 95 +++
include/hw/riscv/riscv_hart.h | 45
2 files changed, 140 insertions(+)
create mode 100644 hw
Add Michael Clark, Palmer Dabbelt, Sagar Karandikar and Bastian
Koppelmann as RISC-V Maintainers.
Signed-off-by: Michael Clark
---
MAINTAINERS | 11 +++
1 file changed, 11 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index bc2d3a4..17af5b4 100644
--- a/MAINTAINERS
+++ b
FYI - I intended these emails to go to the RISC-V Patches but unfortunately
had the wrong address on the 'cc.
This time around, the patches are in the qemu-devel archives here:
- http://lists.nongnu.org/archive/html/qemu-devel/2018-01/threads.html
On Thu, Jan 11, 2018 at 12:46 PM, Michael
stency and brevity reasons:
ERROR: line over 90 characters
ERROR: trailing statements should be on next line
ERROR: space prohibited between function name and open parenthesis '('
Signed-off-by: Michael Clark
---
disas.c |2 +
disas/Makefile.objs |1 +
disas/
This provides a RISC-V Board compatible with the the SiFive E300 SDK.
The following machine is implemented:
- 'sifive_e300'; CLINT, PLIC, UART, AON, GPIO, QSPI, PWM
Signed-off-by: Michael Clark
---
hw/riscv/sifive_e300.c | 232 +
includ
This provides a RISC-V Board compatible with the the SiFive U500 SDK.
The following machine is implemented:
- 'sifive_u500'; CLINT, PLIC, UART, device-tree
Signed-off-by: Michael Clark
---
hw/riscv/sifive_u500.c | 338 +
includ
1.10
Signed-off-by: Michael Clark
---
hw/riscv/spike_v1_09.c | 207 ++
hw/riscv/spike_v1_10.c | 281 +++
include/hw/riscv/spike.h | 51 +
3 files changed, 539 insertions(+)
create mode 100644 hw/riscv/spike_
: Privileged ISA Version 1.9.1
- RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.10
Signed-off-by: Michael Clark
---
target/riscv/instmap.h | 377 +
target/riscv/translate.c | 1982 ++
2 files changed, 2359 insertions(+)
create
nf.sh'
script is updated to add the RISC-V ELF magic.
Expected checkpatch errors for consistency reasons:
ERROR: line over 90 characters
FILE: scripts/qemu-binfmt-conf.sh
Signed-off-by: Michael Clark
---
Makefile.objs | 1 +
arch_init.c
The PLIC (Platform Level Interrupt Controller) device provides a
parameterizable interrupt controller based on SiFive's PLIC specification.
Signed-off-by: Michael Clark
---
hw/riscv/sifive_plic.c | 554 +
include/hw/riscv/sifive_plic.h
Simple model of the PRCI (Power, Reset, Clock, Interrupt) to emulate
register reads made by the SDK BSP.
Signed-off-by: Michael Clark
---
hw/riscv/sifive_prci.c | 107 +
include/hw/riscv/sifive_prci.h | 43 +
2 files changed, 150
RISC-V machine with device-tree, 16550a UART and VirtIO MMIO.
The following machine is implemented:
- 'virt'; CLINT, PLIC, 16550A UART, VirtIO MMIO, device-tree
Signed-off-by: Michael Clark
---
hw/riscv/virt.c | 364
includ
/char/serial.c'.
Signed-off-by: Michael Clark
---
hw/riscv/sifive_uart.c | 182 +
include/hw/riscv/sifive_uart.h | 76 +
2 files changed, 258 insertions(+)
create mode 100644 hw/riscv/sifive_uart.c
create mode 100644 includ
Holds the state of a heterogenous array of RISC-V hardware threads.
Signed-off-by: Michael Clark
---
hw/riscv/riscv_hart.c | 95 +++
include/hw/riscv/riscv_hart.h | 45
2 files changed, 140 insertions(+)
create mode 100644 hw
Implementation of linux user emulation for RISC-V.
Signed-off-by: Michael Clark
---
linux-user/elfload.c | 22 +++
linux-user/main.c | 114 +++
linux-user/riscv/syscall_nr.h | 275 +++
linux-user/riscv/target_cpu.h
reads the ELF kernel and locates the 'tohost' and
'fromhost' symbols which it uses for guest to host console MMIO.
The HTIT chardev implements the pre qom legacy interface consistent
with the 16550a UART in 'hw/char/serial.c'.
Signed-off-by: Michael Clark
---
hw/ri
The CLINT (Core Local Interruptor) device provides real-time clock, timer
and interprocessor interrupts based on SiFive's CLINT specification.
Signed-off-by: Michael Clark
---
hw/riscv/sifive_clint.c | 312
include/hw/riscv/sifive_clint.h
preferable to keep
the code in-tree for folk that are interested in RISC-V PMP support.
Signed-off-by: Michael Clark
---
target/riscv/pmp.c | 386 +
target/riscv/pmp.h | 70 ++
2 files changed, 456 insertions(+)
create mode 100644 target
Add CPU state header, CPU definitions and initialization routines
Signed-off-by: Michael Clark
---
target/riscv/cpu.c | 391 +
target/riscv/cpu.h | 271 +++
target/riscv/cpu_bits.h | 417
GDB Register read and write routines.
Signed-off-by: Michael Clark
---
target/riscv/gdbstub.c | 59 ++
1 file changed, 59 insertions(+)
create mode 100644 target/riscv/gdbstub.c
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
new
iv v1.10
This is a list of RISC-V QEMU Port Contributors:
- Alex Suykov
- Antony Pavlov
- Bastian Koppelmann
- Bruce Hoult
- Chih-Min Chao
- Daire McNamara
- David Abdurachmanov
- Ivan Griffin
- Kito Cheng
- Michael Clark
- Palmer Dabbelt
- Sagar Karandikar
- Stefan O'Rear
Notes:
- c
Privileged control and status register helpers and page fault handling.
Signed-off-by: Michael Clark
---
target/riscv/helper.c| 499 ++
target/riscv/helper.h| 78 ++
target/riscv/op_helper.c | 682 +++
3
Helper routines for FPU instructions and NaN definitions.
Signed-off-by: Michael Clark
---
fpu/softfloat-specialize.h | 7 +-
target/riscv/fpu_helper.c | 591 +
2 files changed, 595 insertions(+), 3 deletions(-)
create mode 100644 target/riscv
Add Michael Clark, Palmer Dabbelt, Sagar Karandikar and Bastian
Koppelmann as RISC-V Maintainers.
Signed-off-by: Michael Clark
---
MAINTAINERS | 11 +++
1 file changed, 11 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index bc2d3a4..17af5b4 100644
--- a/MAINTAINERS
+++ b
Define RISC-V ELF machine EM_RISCV 243
Reviewed-by: Richard Henderson
Signed-off-by: Michael Clark
---
include/elf.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/elf.h b/include/elf.h
index e8a515c..8e457fc 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -112,6 +112,8
github.com/michaeljclark/riscv-qemu/commits/qemu-devel
Hopefully, I'll have a new spin relatively soon... I'm making good progress
on getting target/riscv clean enough for re-submission...
Michael.
On Thu, Jan 4, 2018 at 11:30 AM, Michael Clark wrote:
>
>
> On Wed, Jan 3, 2018
On Thu, Jan 4, 2018 at 12:47 PM, Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 01/02/2018 04:44 PM, Michael Clark wrote:
> > diff --git a/linux-user/elfload.c b/linux-user/elfload.c
> > index 20f3d8c..178af56 100644
> > --- a/linux-user/elfload.c
>
On Thu, Jan 4, 2018 at 12:23 PM, Eric Blake wrote:
> On 01/02/2018 06:44 PM, Michael Clark wrote:
> > This adds RISC-V into the build system enabling the following targets:
> >
> > - riscv32-softmmu
> > - riscv64-softmmu
> > - riscv32-linux-user
> >
On Thu, Jan 4, 2018 at 3:57 AM, KONRAD Frederic wrote:
> Hi all,
>
>
> On 01/03/2018 01:44 AM, Michael Clark wrote:
>
>> QEMU model of the UART on the SiFive E300 and U500 series SOCs.
>> BBL supports the SiFive UART for early console access via the SBI
>> (Sup
On Fri, 5 Jan 2018 at 5:55 AM, Antony Pavlov
wrote:
> On Wed, 3 Jan 2018 13:44:25 +1300
> Michael Clark wrote:
>
> > This adds RISC-V into the build system enabling the following targets:
> >
> > - riscv32-softmmu
> > - riscv64-softmmu
> > - risc
On Fri, 5 Jan 2018 at 9:53 AM, Antony Pavlov
wrote:
> On Wed, 3 Jan 2018 13:44:21 +1300
> Michael Clark wrote:
>
> > QEMU model of the UART on the SiFive E300 and U500 series SOCs.
> > BBL supports the SiFive UART for early console access via the SBI
> > (Superviso
On Fri, 5 Jan 2018 at 6:39 AM, Antony Pavlov
wrote:
> On Thu, 4 Jan 2018 20:33:57 +1300
> Michael Clark wrote:
>
> > On Thu, Jan 4, 2018 at 7:47 PM, Antony Pavlov
> > wrote:
> >
> > > On Wed, 3 Jan 2018 13:44:07 +1300
> > > Michael Clark w
On Thu, Jan 4, 2018 at 7:47 PM, Antony Pavlov
wrote:
> On Wed, 3 Jan 2018 13:44:07 +1300
> Michael Clark wrote:
>
> > Add CPU state header, CPU definitions and initialization routines
> >
> > Signed-off-by: Michael Clark
> > ---
&
On Wed, Jan 3, 2018 at 8:12 PM, Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 01/02/2018 04:44 PM, Michael Clark wrote:
> > +target_ulong mode = env->priv;
> > +if (access_type != MMU_INST_FETCH) {
> > +if (get_fi
On Wed, Jan 3, 2018 at 6:21 PM, Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 01/02/2018 04:44 PM, Michael Clark wrote:
> > +#ifdef CONFIG_USER_ONLY
> > +static bool riscv_cpu_has_work(CPUState *cs)
> > +{
> > +return 0;
> > +}
> &g
On Wed, Jan 3, 2018 at 6:30 PM, Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 01/02/2018 04:44 PM, Michael Clark wrote:
> > +static const char *rv_ireg_name_sym[] = {
> > +"zero", "ra", "sp", "gp", "
On Thu, Jan 4, 2018 at 4:02 AM, KONRAD Frederic wrote:
>
>
> On 01/03/2018 01:44 AM, Michael Clark wrote:
>
>> Simple model of the PRCI (Power, Reset, Clock, Interrupt) to emulate
>> register reads made by the SDK BSP.
>>
>> Signed-off-by: Michael Clark
On Thu, Jan 4, 2018 at 12:35 AM, Richard W.M. Jones
wrote:
> Just a few small points:
>
> (1) I've built Fedora RPMs from this patch set [approximately - I'm
> using a very slightly different / slightly older version, but it's not
> substantively different]:
>
> http://copr-fe.cloud.fedoraproje
On Wed, Jan 3, 2018 at 3:41 PM, Fam Zheng wrote:
> On Wed, 01/03 15:00, Michael Clark wrote:
> > So it's essentially one error, the single line case pattern for
> > table-driven decode which flags for long lines and asks to separate break
> > onto its own line.
> &
e with the required verbosity.
On Wed, Jan 3, 2018 at 2:46 PM, Michael Clark wrote:
> Hi famz,
>
> If you read the patch logs, you'll see we mention that two of the patches
> don't pass checkpatch. The checkpatch warnings are in the patch comments.
>
> [0004/0021] RI
Hi famz,
If you read the patch logs, you'll see we mention that two of the patches
don't pass checkpatch. The checkpatch warnings are in the patch comments.
[0004/0021] RISC-V Disassembler violates some select standards for brevity.
It is repetitive machine generated code. LOC will blow up.
[0021
The CLINT (Core Local Interruptor) device provides real-time clock, timer
and interprocessor interrupts based on SiFive's CLINT specification.
Signed-off-by: Michael Clark
---
hw/riscv/sifive_clint.c | 312
include/hw/riscv/sifive_clint.h
nf.sh'
script is updated to add the RISC-V ELF magic.
Expected checkpatch errors for consistency reasons:
ERROR: line over 90 characters
FILE: scripts/qemu-binfmt-conf.sh
Signed-off-by: Michael Clark
---
Makefile.objs | 1 +
arch_init.c
This provides a RISC-V Board compatible with the the SiFive U500 SDK.
The following machine is implemented:
- 'sifive_u500'; CLINT, PLIC, UART, device-tree
Signed-off-by: Michael Clark
---
hw/riscv/sifive_u500.c | 338 +
includ
This provides a RISC-V Board compatible with the the SiFive E300 SDK.
The following machine is implemented:
- 'sifive_e300'; CLINT, PLIC, UART, AON, GPIO, QSPI, PWM
Signed-off-by: Michael Clark
---
hw/riscv/sifive_e300.c | 232 +
includ
: Privileged ISA Version 1.9.1
- RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.10
Signed-off-by: Michael Clark
---
target/riscv/instmap.h | 377 +
target/riscv/translate.c | 2032 ++
2 files changed, 2409 insertions(+)
create
/char/serial.c'.
Signed-off-by: Michael Clark
---
hw/riscv/sifive_uart.c | 182 +
include/hw/riscv/sifive_uart.h | 76 +
2 files changed, 258 insertions(+)
create mode 100644 hw/riscv/sifive_uart.c
create mode 100644 includ
RISC-V machine with device-tree, 16550a UART and VirtIO MMIO.
The following machine is implemented:
- 'virt'; CLINT, PLIC, 16550A UART, VirtIO MMIO, device-tree
Signed-off-by: Michael Clark
---
hw/riscv/virt.c | 364
includ
Simple model of the PRCI (Power, Reset, Clock, Interrupt) to emulate
register reads made by the SDK BSP.
Signed-off-by: Michael Clark
---
hw/riscv/sifive_prci.c | 107 +
include/hw/riscv/sifive_prci.h | 43 +
2 files changed, 150
1.10
Signed-off-by: Michael Clark
---
hw/riscv/spike_v1_09.c | 207 ++
hw/riscv/spike_v1_10.c | 281 +++
include/hw/riscv/spike.h | 51 +
3 files changed, 539 insertions(+)
create mode 100644 hw/riscv/spike_
Implements the physical memory protection extension as specified in
Privileged ISA Version 1.10.
Signed-off-by: Michael Clark
---
target/riscv/pmp.c | 381 +
target/riscv/pmp.h | 70 ++
2 files changed, 451 insertions(+)
create mode
Holds the state of a heterogenous array of RISC-V hardware threads.
Signed-off-by: Michael Clark
---
hw/riscv/riscv_hart.c | 95 +++
include/hw/riscv/riscv_hart.h | 45
2 files changed, 140 insertions(+)
create mode 100644 hw
reads the ELF kernel and locates the 'tohost' and
'fromhost' symbols which it uses for guest to host console MMIO.
The HTIT chardev implements the pre qom legacy interface consistent
with the 16550a UART in 'hw/char/serial.c'.
Signed-off-by: Michael Clark
---
hw/ri
The PLIC (Platform Level Interrupt Controller) device provides a
parameterizable interrupt controller based on SiFive's PLIC specification.
Signed-off-by: Michael Clark
---
hw/riscv/sifive_plic.c | 558 +
include/hw/riscv/sifive_plic.h
stency and brevity reasons:
ERROR: line over 90 characters
ERROR: trailing statements should be on next line
ERROR: space prohibited between function name and open parenthesis '('
Signed-off-by: Michael Clark
---
disas.c |2 +
disas/Makefile.objs |1 +
disas/
Helper routines for FPU instructions and NaN definitions.
Signed-off-by: Michael Clark
---
fpu/softfloat-specialize.h | 7 +-
target/riscv/fpu_helper.c | 591 +
2 files changed, 595 insertions(+), 3 deletions(-)
create mode 100644 target/riscv
GDB Register read and write routines.
Signed-off-by: Michael Clark
---
target/riscv/gdbstub.c | 59 ++
1 file changed, 59 insertions(+)
create mode 100644 target/riscv/gdbstub.c
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
new
Implementation of linux user emulation for RISC-V.
Signed-off-by: Michael Clark
---
linux-user/elfload.c | 22 +++
linux-user/main.c | 130 -
linux-user/riscv/syscall_nr.h | 275 +++
linux-user/riscv/target_cpu.h
Privileged control and status register helpers and page fault handling.
Signed-off-by: Michael Clark
---
target/riscv/helper.c| 494 +
target/riscv/helper.h| 78 ++
target/riscv/op_helper.c | 707 +++
3
Add Michael Clark, Sagar Karandikar and Bastian Koppelmann as
RISC-V Maintainers.
Signed-off-by: Michael Clark
---
MAINTAINERS | 10 ++
1 file changed, 10 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 73a..09a1314 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -209,6
Add CPU state header, CPU definitions and initialization routines
Signed-off-by: Michael Clark
---
target/riscv/cpu.c | 338 +++
target/riscv/cpu.h | 363 ++
target/riscv/cpu_bits.h | 411
Koppelmann
- Bruce Hoult
- Chih-Min Chao
- Daire McNamara
- David Abdurachmanov
- Ivan Griffin
- Kito Cheng
- Michael Clark
- Palmer Dabbelt
- Sagar Karandikar
- Stefan O'Rear
Notes:
- contributor email addresses available off-list on request.
- checkpatch has been run on all 21 pat
Define RISC-V ELF machine EM_RISCV 243
Signed-off-by: Michael Clark
---
include/elf.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/elf.h b/include/elf.h
index e8a515c..8e457fc 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -112,6 +112,8 @@ typedef int64_t Elf64_Sxword
> On 27 Jul 2017, at 8:58 AM, kr...@berkeley.edu wrote:
>
>
> Given that one of the goals of RISC-V is extensibility, it would be
> nice if the QEMU port was done in a way to make it easier to extend by
> third parties, including other automated tools. I'm sure that, over
> time, the preprocess
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