Re: [Qemu-devel] [PATCH v2] riscv: remove define cpu_init()

On Wed, May 16, 2018 at 4:00 AM, Igor Mammedov <imamm...@redhat.com> wrote: > cpu_init() was removed since 2.12, so drop the define that is now unused. > > Signed-off-by: Igor Mammedov <imamm...@redhat.com> > Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org> &g

Re: [Qemu-devel] [PATCH v3 2/7] hw/riscv/sifive_e: Create a SiFive E SoC object

On Tue, May 15, 2018 at 12:07 PM, Alistair Francis <alistair.fran...@wdc.com > wrote: > Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> > Reviewed-by: Michael Clark <m...@sifive.com> > --- > hw/riscv/sifive_e.c | 97 +++

Re: [Qemu-devel] [PATCH v3 4/7] hw/riscv/sifive_u: Set the soc device tree node as a simple-bus

On Tue, May 15, 2018 at 12:07 PM, Alistair Francis <alistair.fran...@wdc.com > wrote: > To allow Linux to ennumerate devices on the /soc/ node set it as a > "simple-bus". > > Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> > Reviewed-by: Michael

Re: [Qemu-devel] [PATCH 5/9] target/riscv: Honor CPU_DUMP_FPU

On Sun, May 13, 2018 at 12:52 PM, Philippe Mathieu-Daudé <f4...@amsat.org> wrote: > On 05/11/2018 12:52 AM, Richard Henderson wrote: > > Cc: Michael Clark <m...@sifive.com> > > Cc: Palmer Dabbelt <pal...@sifive.com> > > Cc: Sagar Karandikar <sag...@eec

Re: [Qemu-devel] [PATCH v4 16/40] hw/riscv: Use the IEC binary prefix definitions

ff-by: Philippe Mathieu-Daudé > Reviewed-by: Michael Clark > --- > hw/riscv/virt.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index ad03113e0f..34d48993a2 100644 > --- a/hw/riscv/virt.c > +++ b/h

Re: [Qemu-devel] [PATCH v1 3/5] hw/riscv/virt: Connect the Xilinx PCIe

> On 23/06/2018, at 1:07 PM, Peter Maydell wrote: > > On 22 June 2018 at 20:30, Alistair Francis wrote: >> Connect the Xilinx PCIe device based on the device tree included in the >> HiFive Unleashed ROM. > > Did you consider using the 'gpex' generic PCIe controller here? Yes. Alastair and

Re: [Qemu-devel] [PATCH v8 00/35] QEMU 2.13 Privileged ISA emulation updates

and brcond2 so that large guest support on 32-bit is transparent for targets that don't override the defaults, so no worries about regressing the core. Yet... :-D Michael. On Thu, Apr 26, 2018 at 1:42 PM, Michael Clark <m...@sifive.com> wrote: > Hi All, > > As a first-time QEMU contributo

Re: [Qemu-devel] [PULL 15/19] hw/arm/highbank: don't make sysram 'nomigrate'

-version migration compatibility > break for the "highbank" and "midway" machines. > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> > Reviewed-by: Michael Clark <m...@sifive.com> > Message-id: 20180420124835.7268-2-peter.mayd...@lin

Re: [Qemu-devel] Who is running QEMU automated tests, and when?

On Fri, Apr 27, 2018 at 2:04 AM, Peter Maydell wrote: > On 26 April 2018 at 14:57, Eduardo Habkost wrote: > > Peter, do you have additional tests you run before merging a pull > > request? Additional test sets run before tagging a release? > > I

Re: [Qemu-devel] [PATCH v8 00/35] QEMU 2.13 Privileged ISA emulation updates

On Fri, Apr 27, 2018 at 12:35 PM, Richard Henderson < richard.hender...@linaro.org> wrote: > On 04/26/2018 08:22 AM, Alistair Francis wrote: > > On Wed, Apr 25, 2018 at 7:01 PM Michael Clark <m...@sifive.com> wrote: > >> We can make a PR for the first 9 patche

Re: [Qemu-devel] [PATCH v8 11/35] RISC-V: Mark ROM read-only after copying in code

On Fri, Apr 27, 2018 at 4:48 AM, Alistair Francis <alistai...@gmail.com> wrote: > On Wed, Apr 25, 2018 at 5:03 PM Michael Clark <m...@sifive.com> wrote: > > > The sifive_u machine already marks its ROM readonly. This fixes > > the remaining boards. This co

Re: [Qemu-devel] [PATCH v8 11/35] RISC-V: Mark ROM read-only after copying in code

On Fri, Apr 27, 2018 at 5:22 PM, Michael Clark <m...@sifive.com> wrote: > > > On Fri, Apr 27, 2018 at 4:48 AM, Alistair Francis <alistai...@gmail.com> > wrote: > >> On Wed, Apr 25, 2018 at 5:03 PM Michael Clark <m...@sifive.com> wrote: >> >> &g

Re: [Qemu-devel] [PATCH v8 00/35] QEMU 2.13 Privileged ISA emulation updates

On Fri, Apr 27, 2018 at 6:22 AM, Alistair Francis <alistai...@gmail.com> wrote: > On Wed, Apr 25, 2018 at 7:01 PM Michael Clark <m...@sifive.com> wrote: > > > One last quick note. > > > We are tracking RISC-V QEMU issues in the riscv.org repo: > > > -

[Qemu-devel] [PATCH] RISC-V: Fix missing break statement in disassembler

er.mayd...@linaro.org> Signed-off-by: Michael Clark <m...@sifive.com> --- disas/riscv.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/disas/riscv.c b/disas/riscv.c index 74ad16eacdd3..ea19f6fbe2b1 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -1470,8 +1470,9 @@

Re: [Qemu-devel] [PATCH 5/9] target/riscv: Use new atomic min/max expanders

On Sat, Apr 28, 2018 at 5:53 AM, Richard Henderson < richard.hender...@linaro.org> wrote: > On 04/26/2018 09:24 PM, Michael Clark wrote: > > > > > > On Fri, Apr 27, 2018 at 12:26 PM, Richard Henderson > > <richard.hender...@linaro.org <mailto:richard.hender.

Re: [Qemu-devel] [PATCH v8 18/23] RISC-V VirtIO Machine

On Sat, Apr 28, 2018 at 2:17 AM, Peter Maydell <peter.mayd...@linaro.org> wrote: > On 2 March 2018 at 13:51, Michael Clark <m...@sifive.com> wrote: > > RISC-V machine with device-tree, 16550a UART and VirtIO MMIO. > > The following machine is implemented: > >

Re: [Qemu-devel] [PATCH v8 04/23] RISC-V Disassembler

On Sat, Apr 28, 2018 at 12:26 AM, Peter Maydell <peter.mayd...@linaro.org> wrote: > On 2 March 2018 at 13:51, Michael Clark <m...@sifive.com> wrote: > > The RISC-V disassembler has no dependencies outside of the 'disas' > > directory so it can be applied

[Qemu-devel] [PATCH] device_tree: Add qemu_fdt_totalsize function

Currently the device-tree create_device_tree function returns the size of the allocated device tree buffer however there is no way to get the actual amount of buffer space used by the device-tree. 14ec3cbd7c1e31dca4d23f028100c8f43e156573 increases the FDT_MAX_SIZE to 1 MiB. This creates an issue

Re: [Qemu-devel] [PATCH v8 11/35] RISC-V: Mark ROM read-only after copying in code

On Sat, Apr 28, 2018 at 4:17 AM, Alistair Francis <alistai...@gmail.com> wrote: > On Thu, Apr 26, 2018 at 10:34 PM Michael Clark <m...@sifive.com> wrote: > > > > > On Fri, Apr 27, 2018 at 5:22 PM, Michael Clark <m...@sifive.com> wrote: > > > > >

Re: [Qemu-devel] [PATCH v8 26/35] RISC-V: Update CSR and interrupt definitions

On Fri, May 4, 2018 at 8:56 AM, Alistair Francis <alistai...@gmail.com> wrote: > On Wed, Apr 25, 2018 at 5:02 PM Michael Clark <m...@sifive.com> wrote: > > > * Add user-mode CSR defininitions. > > * Reorder CSR definitions to match the specification. > &g

Re: [Qemu-devel] [PATCH v1 03/21] RISC-V CPU Core Definition

On Fri, 5 Jan 2018 at 6:39 AM, Antony Pavlov <antonynpav...@gmail.com> wrote: > On Thu, 4 Jan 2018 20:33:57 +1300 > Michael Clark <m...@sifive.com> wrote: > > > On Thu, Jan 4, 2018 at 7:47 PM, Antony Pavlov <antonynpav...@gmail.com> > > wrote: >

Re: [Qemu-devel] [PATCH v1 21/21] RISC-V Build Infrastructure

On Fri, 5 Jan 2018 at 5:55 AM, Antony Pavlov <antonynpav...@gmail.com> wrote: > On Wed, 3 Jan 2018 13:44:25 +1300 > Michael Clark <m...@sifive.com> wrote: > > > This adds RISC-V into the build system enabling the following targets: > > > > - riscv32-soft

Re: [Qemu-devel] [PATCH v1 17/21] SiFive RISC-V UART Device

On Thu, Jan 4, 2018 at 3:57 AM, KONRAD Frederic <frederic.kon...@adacore.com > wrote: > Hi all, > > > On 01/03/2018 01:44 AM, Michael Clark wrote: > >> QEMU model of the UART on the SiFive E300 and U500 series SOCs. >> BBL supports the SiFive UART for

Re: [Qemu-devel] [PATCH v1 10/21] RISC-V Linux User Emulation

On Thu, Jan 4, 2018 at 12:47 PM, Richard Henderson < richard.hender...@linaro.org> wrote: > On 01/02/2018 04:44 PM, Michael Clark wrote: > > diff --git a/linux-user/elfload.c b/linux-user/elfload.c > > index 20f3d8c..178af56 100644 > > --- a/linux-user/elfload.c >

Re: [Qemu-devel] [PATCH v1 17/21] SiFive RISC-V UART Device

On Fri, 5 Jan 2018 at 9:53 AM, Antony Pavlov <antonynpav...@gmail.com> wrote: > On Wed, 3 Jan 2018 13:44:21 +1300 > Michael Clark <m...@sifive.com> wrote: > > > QEMU model of the UART on the SiFive E300 and U500 series SOCs. > > BBL supports the SiFive UART for

Re: [Qemu-devel] [PATCH v1 21/21] RISC-V Build Infrastructure

On Thu, Jan 4, 2018 at 12:23 PM, Eric Blake <ebl...@redhat.com> wrote: > On 01/02/2018 06:44 PM, Michael Clark wrote: > > This adds RISC-V into the build system enabling the following targets: > > > > - riscv32-softmmu > > - riscv64-softmmu > > - risc

Re: [Qemu-devel] [PATCH v1 03/21] RISC-V CPU Core Definition

/michaeljclark/riscv-qemu/commits/qemu-devel Hopefully, I'll have a new spin relatively soon... I'm making good progress on getting target/riscv clean enough for re-submission... Michael. On Thu, Jan 4, 2018 at 11:30 AM, Michael Clark <m...@sifive.com> wrote: > > > On Wed, Jan 3, 2018 at 6

[Qemu-devel] [PATCH v3 09/21] RISC-V Physical Memory Protection

be preferable to keep the code in-tree for folk that are interested in RISC-V PMP support. Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/pmp.c | 386 + target/riscv/pmp.h | 70 ++ 2 files changed, 456 insertions(+) creat

[Qemu-devel] [PATCH v3 00/21] RISC-V QEMU Port Submission v3

ykov - Antony Pavlov - Bastian Koppelmann - Bruce Hoult - Chih-Min Chao - Daire McNamara - David Abdurachmanov - Ivan Griffin - Kito Cheng - Michael Clark - Palmer Dabbelt - Sagar Karandikar - Stefan O'Rear Notes: - contributor email addresses available off-list on request. - checkpatch has been r

[Qemu-devel] [PATCH v3 17/21] SiFive RISC-V UART Device

/serial.c'. Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/sifive_uart.c | 182 + include/hw/riscv/sifive_uart.h | 76 + 2 files changed, 258 insertions(+) create mode 100644 hw/riscv/sifive_uart.c create mode

[Qemu-devel] [PATCH v3 18/21] SiFive RISC-V PRCI Block

Simple model of the PRCI (Power, Reset, Clock, Interrupt) to emulate register reads made by the SDK BSP. Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/sifive_prci.c | 107 + include/hw/riscv/sifive_prci.h | 43 ++

[Qemu-devel] [PATCH v3 02/21] RISC-V ELF Machine Definition

Define RISC-V ELF machine EM_RISCV 243 Reviewed-by: Richard Henderson <richard.hender...@linaro.org> Signed-off-by: Michael Clark <m...@sifive.com> --- include/elf.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/elf.h b/include/elf.h index e8a515c..8e457fc 100644 -

[Qemu-devel] [PATCH v3 12/21] RISC-V HART Array

Holds the state of a heterogenous array of RISC-V hardware threads. Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/riscv_hart.c | 95 +++ include/hw/riscv/riscv_hart.h | 45 2 files changed, 140 inse

[Qemu-devel] [PATCH v3 06/21] RISC-V FPU Support

Helper routines for FPU instructions and NaN definitions. Signed-off-by: Michael Clark <m...@sifive.com> --- fpu/softfloat-specialize.h | 7 +- target/riscv/fpu_helper.c | 591 + 2 files changed, 595 insertions(+), 3 deletions(-) create mode

[Qemu-devel] [PATCH v3 01/21] RISC-V Maintainers

Add Michael Clark, Palmer Dabbelt, Sagar Karandikar and Bastian Koppelmann as RISC-V Maintainers. Signed-off-by: Michael Clark <m...@sifive.com> --- MAINTAINERS | 11 +++ 1 file changed, 11 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index bc2d3a4..17af5b4

[Qemu-devel] [PATCH v3 05/21] RISC-V CPU Helpers

Privileged control and status register helpers and page fault handling. Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/helper.c| 499 ++ target/riscv/helper.h| 78 ++ target/riscv/op_helper.c

[Qemu-devel] [PATCH v3 13/21] SiFive RISC-V CLINT Block

The CLINT (Core Local Interruptor) device provides real-time clock, timer and interprocessor interrupts based on SiFive's CLINT specification. Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/sifive_clint.c | 312 include/hw

[Qemu-devel] [PATCH v3 03/21] RISC-V CPU Core Definition

Add CPU state header, CPU definitions and initialization routines Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/cpu.c | 391 + target/riscv/cpu.h | 271 +++ target/riscv/cpu_bits.h

[Qemu-devel] [PATCH v3 10/21] RISC-V Linux User Emulation

Implementation of linux user emulation for RISC-V. Signed-off-by: Michael Clark <m...@sifive.com> --- linux-user/elfload.c | 22 +++ linux-user/main.c | 114 +++ linux-user/riscv/syscall_nr.h | 275 +++ linu

[Qemu-devel] [PATCH v3 14/21] SiFive RISC-V PLIC Block

The PLIC (Platform Level Interrupt Controller) device provides a parameterizable interrupt controller based on SiFive's PLIC specification. Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/sifive_plic.c | 554 + include/hw

[Qemu-devel] [PATCH v3 16/21] RISC-V VirtIO Machine

RISC-V machine with device-tree, 16550a UART and VirtIO MMIO. The following machine is implemented: - 'virt'; CLINT, PLIC, 16550A UART, VirtIO MMIO, device-tree Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/virt.c

[Qemu-devel] [PATCH v3 11/21] RISC-V HTIF Console

reads the ELF kernel and locates the 'tohost' and 'fromhost' symbols which it uses for guest to host console MMIO. The HTIT chardev implements the pre qom legacy interface consistent with the 16550a UART in 'hw/char/serial.c'. Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/riscv

[Qemu-devel] [PATCH v3 08/21] RISC-V TCG Code Generation

: Privileged ISA Version 1.9.1 - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.10 Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/instmap.h | 377 + target/riscv/translate.c | 1982 ++ 2 files changed

[Qemu-devel] [PATCH v3 04/21] RISC-V Disassembler

and brevity reasons: ERROR: line over 90 characters ERROR: trailing statements should be on next line ERROR: space prohibited between function name and open parenthesis '(' Signed-off-by: Michael Clark <m...@sifive.com> --- disas.c |2 + disas/Makefile.objs |1 + disas/r

[Qemu-devel] [PATCH v3 07/21] RISC-V GDB Stub

GDB Register read and write routines. Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/gdbstub.c | 59 ++ 1 file changed, 59 insertions(+) create mode 100644 target/riscv/gdbstub.c diff --git a/target/riscv/gdbstub.c b/target

[Qemu-devel] [PATCH v3 15/21] RISC-V Spike Machines

-by: Michael Clark <m...@sifive.com> --- hw/riscv/spike_v1_09.c | 207 ++ hw/riscv/spike_v1_10.c | 281 +++ include/hw/riscv/spike.h | 51 + 3 files changed, 539 insertions(+) create mode 100644 hw/riscv/spike

[Qemu-devel] [PATCH v3 20/21] SiFive Freedom U500 RISC-V Machine

This provides a RISC-V Board compatible with the the SiFive U500 SDK. The following machine is implemented: - 'sifive_u500'; CLINT, PLIC, UART, device-tree Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/sifive_u500.c | 338 + i

[Qemu-devel] [PATCH v3 19/21] SiFive Freedom E300 RISC-V Machine

This provides a RISC-V Board compatible with the the SiFive E300 SDK. The following machine is implemented: - 'sifive_e300'; CLINT, PLIC, UART, AON, GPIO, QSPI, PWM Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/sifive_e300.c

[Qemu-devel] [PATCH v3 21/21] RISC-V Build Infrastructure

' script is updated to add the RISC-V ELF magic. Expected checkpatch errors for consistency reasons: ERROR: line over 90 characters FILE: scripts/qemu-binfmt-conf.sh Signed-off-by: Michael Clark <m...@sifive.com> --- Makefile.objs | 1 + arch_

[Qemu-devel] [PATCH v2 02/21] RISC-V ELF Machine Definition

Define RISC-V ELF machine EM_RISCV 243 Reviewed-by: Richard Henderson <richard.hender...@linaro.org> Signed-off-by: Michael Clark <m...@sifive.com> --- include/elf.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/elf.h b/include/elf.h index e8a515c..8e457fc 100644 -

[Qemu-devel] [PATCH v2 06/21] RISC-V FPU Support

Helper routines for FPU instructions and NaN definitions. Signed-off-by: Michael Clark <m...@sifive.com> --- fpu/softfloat-specialize.h | 7 +- target/riscv/fpu_helper.c | 591 + 2 files changed, 595 insertions(+), 3 deletions(-) create mode

[Qemu-devel] [PATCH v2 01/21] RISC-V Maintainers

Add Michael Clark, Palmer Dabbelt, Sagar Karandikar and Bastian Koppelmann as RISC-V Maintainers. Signed-off-by: Michael Clark <m...@sifive.com> --- MAINTAINERS | 11 +++ 1 file changed, 11 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index bc2d3a4..17af5b4

[Qemu-devel] [PATCH v2 05/21] RISC-V CPU Helpers

Privileged control and status register helpers and page fault handling. Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/helper.c| 499 ++ target/riscv/helper.h| 78 ++ target/riscv/op_helper.c

[Qemu-devel] [PATCH v2 03/21] RISC-V CPU Core Definition

Add CPU state header, CPU definitions and initialization routines Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/cpu.c | 391 + target/riscv/cpu.h | 271 +++ target/riscv/cpu_bits.h

[Qemu-devel] [PATCH v2 07/21] RISC-V GDB Stub

GDB Register read and write routines. Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/gdbstub.c | 59 ++ 1 file changed, 59 insertions(+) create mode 100644 target/riscv/gdbstub.c diff --git a/target/riscv/gdbstub.c b/target

[Qemu-devel] [PATCH v2 00/21] RISC-V QEMU Port Submission v2

- Bastian Koppelmann - Bruce Hoult - Chih-Min Chao - Daire McNamara - David Abdurachmanov - Ivan Griffin - Kito Cheng - Michael Clark - Palmer Dabbelt - Sagar Karandikar - Stefan O'Rear Notes: - contributor email addresses available off-list on request. - checkpatch has been run on all 21 p

[Qemu-devel] [PATCH v2 09/21] RISC-V Physical Memory Protection

be preferable to keep the code in-tree for folk that are interested in RISC-V PMP support. Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/pmp.c | 386 + target/riscv/pmp.h | 70 ++ 2 files changed, 456 insertions(+) creat

[Qemu-devel] [PATCH v2 13/21] SiFive RISC-V CLINT Block

The CLINT (Core Local Interruptor) device provides real-time clock, timer and interprocessor interrupts based on SiFive's CLINT specification. Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/sifive_clint.c | 312 include/hw

[Qemu-devel] [PATCH v2 11/21] RISC-V HTIF Console

reads the ELF kernel and locates the 'tohost' and 'fromhost' symbols which it uses for guest to host console MMIO. The HTIT chardev implements the pre qom legacy interface consistent with the 16550a UART in 'hw/char/serial.c'. Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/riscv

[Qemu-devel] [PATCH v2 12/21] RISC-V HART Array

Holds the state of a heterogenous array of RISC-V hardware threads. Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/riscv_hart.c | 95 +++ include/hw/riscv/riscv_hart.h | 45 2 files changed, 140 inse

[Qemu-devel] [PATCH v2 10/21] RISC-V Linux User Emulation

Implementation of linux user emulation for RISC-V. Signed-off-by: Michael Clark <m...@sifive.com> --- linux-user/elfload.c | 22 +++ linux-user/main.c | 114 +++ linux-user/riscv/syscall_nr.h | 275 +++ linu

[Qemu-devel] [PATCH v2 17/21] SiFive RISC-V UART Device

/serial.c'. Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/sifive_uart.c | 182 + include/hw/riscv/sifive_uart.h | 76 + 2 files changed, 258 insertions(+) create mode 100644 hw/riscv/sifive_uart.c create mode

[Qemu-devel] [PATCH v2 16/21] RISC-V VirtIO Machine

RISC-V machine with device-tree, 16550a UART and VirtIO MMIO. The following machine is implemented: - 'virt'; CLINT, PLIC, 16550A UART, VirtIO MMIO, device-tree Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/virt.c

[Qemu-devel] [PATCH v2 18/21] SiFive RISC-V PRCI Block

Simple model of the PRCI (Power, Reset, Clock, Interrupt) to emulate register reads made by the SDK BSP. Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/sifive_prci.c | 107 + include/hw/riscv/sifive_prci.h | 43 ++

[Qemu-devel] [PATCH v2 14/21] SiFive RISC-V PLIC Block

The PLIC (Platform Level Interrupt Controller) device provides a parameterizable interrupt controller based on SiFive's PLIC specification. Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/sifive_plic.c | 554 + include/hw

[Qemu-devel] [PATCH v2 08/21] RISC-V TCG Code Generation

: Privileged ISA Version 1.9.1 - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.10 Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/instmap.h | 377 + target/riscv/translate.c | 1982 ++ 2 files changed

[Qemu-devel] [PATCH v2 21/21] RISC-V Build Infrastructure

' script is updated to add the RISC-V ELF magic. Expected checkpatch errors for consistency reasons: ERROR: line over 90 characters FILE: scripts/qemu-binfmt-conf.sh Signed-off-by: Michael Clark <m...@sifive.com> --- Makefile.objs | 1 + arch_

[Qemu-devel] [PATCH v2 20/21] SiFive Freedom U500 RISC-V Machine

This provides a RISC-V Board compatible with the the SiFive U500 SDK. The following machine is implemented: - 'sifive_u500'; CLINT, PLIC, UART, device-tree Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/sifive_u500.c | 338 + i

[Qemu-devel] [PATCH v2 15/21] RISC-V Spike Machines

-by: Michael Clark <m...@sifive.com> --- hw/riscv/spike_v1_09.c | 207 ++ hw/riscv/spike_v1_10.c | 281 +++ include/hw/riscv/spike.h | 51 + 3 files changed, 539 insertions(+) create mode 100644 hw/riscv/spike

[Qemu-devel] [PATCH v2 04/21] RISC-V Disassembler

and brevity reasons: ERROR: line over 90 characters ERROR: trailing statements should be on next line ERROR: space prohibited between function name and open parenthesis '(' Signed-off-by: Michael Clark <m...@sifive.com> --- disas.c |2 + disas/Makefile.objs |1 + disas/r

[Qemu-devel] [PATCH v2 19/21] SiFive Freedom E300 RISC-V Machine

This provides a RISC-V Board compatible with the the SiFive E300 SDK. The following machine is implemented: - 'sifive_e300'; CLINT, PLIC, UART, AON, GPIO, QSPI, PWM Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/sifive_e300.c

Re: [Qemu-devel] [PATCH v2 00/21] RISC-V QEMU Port Submission v2

FYI - I intended these emails to go to the RISC-V Patches but unfortunately had the wrong address on the 'cc. This time around, the patches are in the qemu-devel archives here: - http://lists.nongnu.org/archive/html/qemu-devel/2018-01/threads.html On Thu, Jan 11, 2018 at 12:46 PM, Michael Clark

Re: [Qemu-devel] [PATCH v2 03/21] RISC-V CPU Core Definition

On Mon, Jan 15, 2018 at 5:44 AM, Igor Mammedov <imamm...@redhat.com> wrote: > On Wed, 10 Jan 2018 15:46:22 -0800 > Michael Clark <m...@sifive.com> wrote: > > > Add CPU state header, CPU definitions and initialization routines > > > > Signed

Re: [Qemu-devel] [PATCH v1 06/21] RISC-V FPU Support

On Wed, Jan 24, 2018 at 8:16 AM, Richard Henderson < richard.hender...@linaro.org> wrote: > On 01/23/2018 05:31 PM, Michael Clark wrote: > > For the meantime we've greatly simplified cpu_mmu_index to just return > the > > processor mode as well as a

Re: [Qemu-devel] [PATCH v3 21/21] RISC-V Build Infrastructure

On Fri, Jan 12, 2018 at 3:05 AM, Eric Blake <ebl...@redhat.com> wrote: > On 01/10/2018 08:22 PM, Michael Clark wrote: > > This adds RISC-V into the build system enabling the following targets: > > > > - riscv32-softmmu > > - riscv64-softmmu > > - risc

Re: [Qemu-devel] [PATCH v2 00/21] RISC-V QEMU Port Submission v2

ct, device-tree should be frozen and versioned too as it is only implicitly specified by the code that implements it. On Thu, Jan 11, 2018 at 8:58 PM, Christoph Hellwig <h...@lst.de> wrote: > On Wed, Jan 10, 2018 at 03:46:19PM -0800, Michael Clark wrote: > > - RISC-V Instruction Set Ma

Re: [Qemu-devel] [PATCH v3 06/21] RISC-V FPU Support

On Fri, Jan 12, 2018 at 4:31 AM, Richard Henderson < richard.hender...@linaro.org> wrote: > On 01/10/2018 06:21 PM, Michael Clark wrote: > > Helper routines for FPU instructions and NaN definitions. > > > > Signed-off-by: Michael Clark <m...@sifive.com> > &

Re: [Qemu-devel] [PATCH v3 03/21] RISC-V CPU Core Definition

On Fri, Jan 12, 2018 at 3:37 AM, Richard Henderson < richard.hender...@linaro.org> wrote: > On 01/10/2018 06:21 PM, Michael Clark wrote: > > +static inline void cpu_get_tb_cpu_state(CPURISCVState *env, > target_ulong *pc, > > +

Re: [Qemu-devel] [PATCH v3 08/21] RISC-V TCG Code Generation

On Fri, Jan 12, 2018 at 4:47 AM, Richard Henderson < richard.hender...@linaro.org> wrote: > On 01/10/2018 06:21 PM, Michael Clark wrote: > > TCG code generation for the RV32IMAFDC and RV64IMAFDC. The QEMU > > RISC-V code generator has complete coverage for the Base ISA v2.

Re: [Qemu-devel] [PATCH v3 08/21] RISC-V TCG Code Generation

On Fri, Jan 12, 2018 at 7:15 AM, Michael Clark <m...@sifive.com> wrote: > > > On Fri, Jan 12, 2018 at 4:47 AM, Richard Henderson < > richard.hender...@linaro.org> wrote: > >> On 01/10/2018 06:21 PM, Michael Clark wrote: >> > TCG code generation f

Re: [Qemu-devel] [PATCH v1 06/21] RISC-V FPU Support

On Mon, Jan 29, 2018 at 12:33 PM, Jim Wilson wrote: > On Wed, Jan 24, 2018 at 3:47 PM, Richard Henderson > wrote: > > On 01/24/2018 10:58 AM, Jim Wilson wrote: > >> Although, looking at this again, I see another statement in a > >> different place

Re: [Qemu-devel] [PATCH v1 11/21] RISC-V HTIF Console

On Tue, Jan 9, 2018 at 3:31 AM, Christoph Hellwig <h...@lst.de> wrote: > On Wed, Jan 03, 2018 at 01:44:15PM +1300, Michael Clark wrote: > > HTIF (Host Target Interface) provides console emulation for QEMU. HTIF > > allows identical copies of BBL (Berkeley Boot Loader) and lin

Re: [Qemu-devel] [PATCH v3 21/21] RISC-V Build Infrastructure

On Fri, Jan 12, 2018 at 7:43 AM, Michael Clark <m...@sifive.com> wrote: > > > On Fri, Jan 12, 2018 at 3:05 AM, Eric Blake <ebl...@redhat.com> wrote: > >> On 01/10/2018 08:22 PM, Michael Clark wrote: >> > This adds RISC-V into the build system enabling the

Re: [Qemu-devel] [PATCH v1 11/21] RISC-V HTIF Console

On Mon, Feb 5, 2018 at 10:29 AM, Christoph Hellwig <h...@lst.de> wrote: > On Mon, Feb 05, 2018 at 09:19:46AM +1300, Michael Clark wrote: > > BTW I've created branches in my own personal trees for Privileged ISA > > v1.9.1. These trees are what I use for v1.9.1 backward comp

[Qemu-devel] [PATCH v4 00/22] RISC-V QEMU Port Submission

- Bastian Koppelmann - Bruce Hoult - Chih-Min Chao - Daire McNamara - Darius Rad - David Abdurachmanov - Ivan Griffin - Jim Wilson - Kito Cheng - Michael Clark - Palmer Dabbelt - Richard Henderon - Sagar Karandikar - Stefan O'Rear Notes: - contributor email addresses available off-list on request. -

[Qemu-devel] [PATCH v4 03/22] RISC-V CPU Core Definition

Add CPU state header, CPU definitions and initialization routines Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/cpu.c | 385 target/riscv/cpu.h | 256 + target/riscv/cpu_bits.h

[Qemu-devel] [PATCH v4 05/22] RISC-V CPU Helpers

Privileged control and status register helpers and page fault handling. Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/helper.c| 464 ++ target/riscv/helper.h| 78 ++ target/riscv/op_helper.c

[Qemu-devel] [PATCH v4 08/22] RISC-V TCG Code Generation

: Privileged ISA Version 1.9.1 - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.10 Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/instmap.h | 366 + target/riscv/translate.c | 1964 ++ 2 files changed

[Qemu-devel] [PATCH v4 16/22] RISC-V VirtIO Machine

RISC-V machine with device-tree, 16550a UART and VirtIO MMIO. The following machine is implemented: - 'virt'; CLINT, PLIC, 16550A UART, VirtIO MMIO, device-tree Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/virt.c

[Qemu-devel] [PATCH v4 21/22] SiFive Freedom U500 RISC-V Machine

This provides a RISC-V Board compatible with the the SiFive U500 SDK. The following machine is implemented: - 'sifive_u500'; CLINT, PLIC, UART, device-tree Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/sifive_u500.c | 338 + i

[Qemu-devel] [PATCH v4 14/22] SiFive RISC-V PLIC Block

The PLIC (Platform Level Interrupt Controller) device provides a parameterizable interrupt controller based on SiFive's PLIC specification. Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/sifive_plic.c | 554 + include/hw

[Qemu-devel] [PATCH v4 09/22] RISC-V Physical Memory Protection

be preferable to keep the code in-tree for folk that are interested in RISC-V PMP support. Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/pmp.c | 386 + target/riscv/pmp.h | 70 ++ 2 files changed, 456 insertions(+) creat

[Qemu-devel] [PATCH v4 11/22] RISC-V HTIF Console

reads the ELF kernel and locates the 'tohost' and 'fromhost' symbols which it uses for guest to host console MMIO. The HTIT chardev implements the pre qom legacy interface consistent with the 16550a UART in 'hw/char/serial.c'. Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/riscv

[Qemu-devel] [PATCH v4 19/22] SiFive RISC-V Test Finisher

Test finisher memory mapped device used to exit simulation. Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/sifive_test.c | 99 ++ include/hw/riscv/sifive_test.h | 48 2 files changed, 147 insertions(+) creat

[Qemu-devel] [PATCH v4 07/22] RISC-V GDB Stub

GDB Register read and write routines. Reviewed-by: Richard Henderson <richard.hender...@linaro.org> Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/gdbstub.c | 60 ++ 1 file changed, 60 insertions(+) create mode 100644

[Qemu-devel] [PATCH v4 02/22] RISC-V ELF Machine Definition

Define RISC-V ELF machine EM_RISCV 243 Reviewed-by: Richard Henderson <richard.hender...@linaro.org> Signed-off-by: Michael Clark <m...@sifive.com> --- include/elf.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/elf.h b/include/elf.h index e8a515c..8e457fc 100644 -

[Qemu-devel] [PATCH v4 01/22] RISC-V Maintainers

Add Michael Clark, Palmer Dabbelt, Sagar Karandikar and Bastian Koppelmann as RISC-V Maintainers. Signed-off-by: Michael Clark <m...@sifive.com> --- MAINTAINERS | 11 +++ 1 file changed, 11 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 0f952d4..d607039

[Qemu-devel] [PATCH v4 06/22] RISC-V FPU Support

Helper routines for FPU instructions and NaN definitions. Signed-off-by: Michael Clark <m...@sifive.com> --- fpu/softfloat-specialize.h | 7 +- target/riscv/fpu_helper.c | 375 + 2 files changed, 379 insertions(+), 3 deletions(-) create mode

[Qemu-devel] [PATCH v4 04/22] RISC-V Disassembler

and brevity reasons: ERROR: line over 90 characters ERROR: trailing statements should be on next line ERROR: space prohibited between function name and open parenthesis '(' Reviewed-by: Richard Henderson <richard.hender...@linaro.org> Signed-off-by: Michael Clark <m...@sifive.com>

[Qemu-devel] [PATCH v4 12/22] RISC-V HART Array

Holds the state of a heterogenous array of RISC-V hardware threads. Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/riscv_hart.c | 95 +++ include/hw/riscv/riscv_hart.h | 45 2 files changed, 140 inse

<    1   2   3   4   5   6   7   >