[Qemu-devel] MMU address collision.

2011-11-23 Thread Michael Rolnik
there is an infinite loop. -- Best Regards, Michael Rolnik

Re: [Qemu-devel] MMU address collision.

2011-11-23 Thread Michael Rolnik
Hi all, I have a question regarding MMU. I've built SPARC based small embedded system. at this system addresses *0x-0x8000* (32KB) belong to ROM and *0x8000 - 0x80001000* to HW devices. the problem is that when a code from first ROM page accesses a HW device register there is an

[Qemu-devel] TLB collision

2011-11-24 Thread Michael Rolnik
they will always look into way0. 2. *tlb_set_page* should copy way0 to way1 and program way0 with new values 3. all other routines dealing with TLB should search both ways. what do you think? -- Best Regards, Michael Rolnik

[Qemu-devel] [Bug 916720] Re: select fails on windows because a non-socket fd is in the rfds set

2012-03-06 Thread Michael Rolnik
it seems that g_main_context_default creates a semaphore which is added into rfds passed to glib_select_fill function, that's why select fails. -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/916720

[Qemu-devel] [PATCH 07/10] target-avr: adding instruction decoder

2016-06-02 Thread Michael Rolnik
Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/decode.c | 724 1 file changed, 724 insertions(+) create mode 100644 target-avr/decode.c diff --git a/target-avr/decode.c b/target-avr/decode.c new file mode 100644

[Qemu-devel] [PATCH 01/10] target-avr: AVR cores support is added. 1. basic CPU structure 2. registers 3. no instructions

2016-06-02 Thread Michael Rolnik
Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- arch_init.c | 2 + configure | 5 + default-configs/avr-softmmu.mak | 1 + disas/Makefile.objs | 1 + disas/avr.c | 10 ++ include/disas/bfd.h

[Qemu-devel] [PATCH 08/10] target-avr: adding instruction translation

2016-06-02 Thread Michael Rolnik
Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/translate-inst.c | 2443 +++ target-avr/translate.h | 123 +++ 2 files changed, 2566 insertions(+) create mode 100644 target-avr/translate-inst.c create mode 100644 targ

[Qemu-devel] [PATCH 05/10] target-avr: adding AVR interrupt handling

2016-06-02 Thread Michael Rolnik
Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/helper.c | 64 - 1 file changed, 63 insertions(+), 1 deletion(-) diff --git a/target-avr/helper.c b/target-avr/helper.c index aec37af..ed22b37 100644 --- a/target-avr/he

[Qemu-devel] [PATCH 04/10] target-avr: adding instructions encodings

2016-06-02 Thread Michael Rolnik
Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/translate-inst.h | 838 1 file changed, 838 insertions(+) create mode 100644 target-avr/translate-inst.h diff --git a/target-avr/translate-inst.h b/target-avr/translate-inst.h ne

[Qemu-devel] [PATCH 08/10] target-avr: adding instruction translation

2016-06-02 Thread Michael Rolnik
Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/translate-inst.c | 2443 +++ target-avr/translate.h | 123 +++ 2 files changed, 2566 insertions(+) create mode 100644 target-avr/translate-inst.c create mode 100644 targ

[Qemu-devel] [PATCH 01/10] target-avr: AVR cores support is added. 1. basic CPU structure 2. registers 3. no instructions

2016-06-02 Thread Michael Rolnik
Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- arch_init.c | 2 + configure | 5 + default-configs/avr-softmmu.mak | 1 + disas/Makefile.objs | 1 + disas/avr.c | 10 ++ include/disas/bfd.h

[Qemu-devel] [PATCH 10/10] target-avr: fixing code style

2016-06-02 Thread Michael Rolnik
Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/cpu-qom.h| 38 + target-avr/cpu.c| 100 +--- target-avr/cpu.h| 74 target-avr/gdbstub.c

[Qemu-devel] [PATCH 03/10] target-avr: adding a sample AVR board

2016-06-02 Thread Michael Rolnik
Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- hw/Makefile.objs | 1 + hw/avr/Makefile.objs | 1 + hw/avr/sample-io.c | 246 +++ hw/avr/sample.c | 120 + 4 files changed, 368 insertions(+) creat

[Qemu-devel] [PATCH 06/10] target-avr: adding helpers for IN, OUT, SLEEP, WBR & unsupported instructions

2016-06-02 Thread Michael Rolnik
Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/helper.c | 103 target-avr/helper.h | 5 +++ 2 files changed, 108 insertions(+) diff --git a/target-avr/helper.c b/target-avr/helper.c index ed22b37..450f598

[Qemu-devel] [PATCH 07/10] target-avr: adding instruction decoder

2016-06-02 Thread Michael Rolnik
Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/decode.c | 724 1 file changed, 724 insertions(+) create mode 100644 target-avr/decode.c diff --git a/target-avr/decode.c b/target-avr/decode.c new file mode 100644

[Qemu-devel] [PATCH 03/10] target-avr: adding a sample AVR board

2016-06-02 Thread Michael Rolnik
Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- hw/Makefile.objs | 1 + hw/avr/Makefile.objs | 1 + hw/avr/sample-io.c | 246 +++ hw/avr/sample.c | 120 + 4 files changed, 368 insertions(+) creat

[Qemu-devel] [PATCH 09/10] target-avr: updating translate.c to use instructions translation

2016-06-02 Thread Michael Rolnik
Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/Makefile.objs | 4 +- target-avr/translate.c | 148 ++- 2 files changed, 72 insertions(+), 80 deletions(-) diff --git a/target-avr/Makefile.objs b/target-avr/Makefile.objs

[Qemu-devel] [PATCH 10/10] target-avr: fixing code style

2016-06-02 Thread Michael Rolnik
Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/cpu-qom.h| 38 + target-avr/cpu.c| 100 +--- target-avr/cpu.h| 74 target-avr/gdbstub.c

[Qemu-devel] [PATCH 06/10] target-avr: adding helpers for IN, OUT, SLEEP, WBR & unsupported instructions

2016-06-02 Thread Michael Rolnik
Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/helper.c | 103 target-avr/helper.h | 5 +++ 2 files changed, 108 insertions(+) diff --git a/target-avr/helper.c b/target-avr/helper.c index ed22b37..450f598

[Qemu-devel] [PATCH 02/10] target-avr: adding AVR CPU features/flavors

2016-06-02 Thread Michael Rolnik
Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/cpu.c | 326 ++- target-avr/cpu.h | 59 ++ 2 files changed, 383 insertions(+), 2 deletions(-) diff --git a/target-avr/cpu.c b/target-avr/cpu.c index ff26018..9

[Qemu-devel] [PATCH 04/10] target-avr: adding instructions encodings

2016-06-02 Thread Michael Rolnik
Signed-off-by: Michael Rolnik <mrol...@gmail.co> --- target-avr/translate-inst.h | 838 1 file changed, 838 insertions(+) create mode 100644 target-avr/translate-inst.h diff --git a/target-avr/translate-inst.h b/target-avr/translate-inst.h ne

[Qemu-devel] [PATCH 02/10] target-avr: adding AVR CPU features/flavors

2016-06-02 Thread Michael Rolnik
Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/cpu.c | 326 ++- target-avr/cpu.h | 59 ++ 2 files changed, 383 insertions(+), 2 deletions(-) diff --git a/target-avr/cpu.c b/target-avr/cpu.c index ff26018..9

[Qemu-devel] [PATCH 09/10] target-avr: updating translate.c to use instructions translation

2016-06-02 Thread Michael Rolnik
Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/Makefile.objs | 4 +- target-avr/translate.c | 148 ++- 2 files changed, 72 insertions(+), 80 deletions(-) diff --git a/target-avr/Makefile.objs b/target-avr/Makefile.objs

[Qemu-devel] [PATCH 05/10] target-avr: adding AVR interrupt handling

2016-06-02 Thread Michael Rolnik
Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/helper.c | 64 - 1 file changed, 63 insertions(+), 1 deletion(-) diff --git a/target-avr/helper.c b/target-avr/helper.c index aec37af..ed22b37 100644 --- a/target-avr/he

Re: [Qemu-devel] [PATCH 10/10] target-avr: fixing code style

2016-06-04 Thread Michael Rolnik
> > In addition, use --subject-prefix="PATCH vN" so that we know which patch > set is newest. > > Also, do not send follow-up patch sets as replies to earlier patch sets. > Doing this means that patch sets get lost. > > > r~ > -- Best Regards, Michael Rolnik

[Qemu-devel] [PATCH 6/9] target-avr: adding helpers for IN, OUT, SLEEP, WBR & unsupported instructions

2016-06-02 Thread Michael Rolnik
Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/helper.c | 117 +++- target-avr/helper.h | 5 +++ 2 files changed, 111 insertions(+), 11 deletions(-) diff --git a/target-avr/helper.c b/target-avr/helper.c index bb47a87..b

[Qemu-devel] [PATCH 9/9] target-avr: updating translate.c to use instructions translation

2016-06-02 Thread Michael Rolnik
Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/Makefile.objs | 4 +- target-avr/translate.c | 132 --- 2 files changed, 59 insertions(+), 77 deletions(-) diff --git a/target-avr/Makefile.objs b/target-avr/Makefile.objs

[Qemu-devel] [PATCH 4/9] target-avr: adding instructions encodings

2016-06-02 Thread Michael Rolnik
Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/translate-inst.h | 838 1 file changed, 838 insertions(+) create mode 100644 target-avr/translate-inst.h diff --git a/target-avr/translate-inst.h b/target-avr/translate-inst.h ne

[Qemu-devel] [PATCH 2/9] target-avr: adding AVR CPU features/flavors

2016-06-02 Thread Michael Rolnik
Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/cpu.c | 311 ++- target-avr/cpu.h | 59 +++ 2 files changed, 368 insertions(+), 2 deletions(-) diff --git a/target-avr/cpu.c b/target-avr/cpu.c index cfc1aee..9

[Qemu-devel] AVR cores

2016-06-02 Thread Michael Rolnik
This series of patches adds 8bit AVR cores to QEMU. All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully tested yet. However I was able to execute simple code with functions. e.g fibonacci calculation. This series of patches include a non real, sample board. No fuses support

[Qemu-devel] [PATCH 8/9] target-avr: adding instruction translation

2016-06-02 Thread Michael Rolnik
Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/translate-inst.c | 2511 +++ target-avr/translate.h | 123 +++ 2 files changed, 2634 insertions(+) create mode 100644 target-avr/translate-inst.c create mode 100644 targ

[Qemu-devel] [PATCH 3/9] target-avr: adding a sample AVR board

2016-06-02 Thread Michael Rolnik
Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- hw/Makefile.objs | 1 + hw/avr/Makefile.objs | 1 + hw/avr/sample-io.c | 217 +++ hw/avr/sample.c | 118 4 files changed, 337 insertions(+)

[Qemu-devel] [PATCH 7/9] target-avr: adding instruction decoder

2016-06-02 Thread Michael Rolnik
Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/decode.c | 724 1 file changed, 724 insertions(+) create mode 100644 target-avr/decode.c diff --git a/target-avr/decode.c b/target-avr/decode.c new file mode 100644

[Qemu-devel] [PATCH 1/9] target-avr: AVR cores support is added. 1. basic CPU structure 2. registers 3. no instructions

2016-06-02 Thread Michael Rolnik
Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- arch_init.c | 2 + configure | 5 + default-configs/avr-softmmu.mak | 1 + disas/Makefile.objs | 1 + disas/avr.c | 10 ++ include/disas/bfd.h

[Qemu-devel] [PATCH 5/9] target-avr: adding AVR interrupt handling

2016-06-02 Thread Michael Rolnik
Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/helper.c | 64 - 1 file changed, 63 insertions(+), 1 deletion(-) diff --git a/target-avr/helper.c b/target-avr/helper.c index fbab91d..bb47a87 100644 --- a/target-avr/he

Re: [Qemu-devel] [PATCH 06/10] target-avr: adding helpers for IN, OUT, SLEEP, WBR & unsupported instructions

2016-06-04 Thread Michael Rolnik
switched to qemu_log. it will be removed after a while. On Sun, Jun 5, 2016 at 1:48 AM, Richard Henderson <r...@twiddle.net> wrote: > On 06/02/2016 01:06 PM, Michael Rolnik wrote: > >> +voidhelper_unsupported( >> +

Re: [Qemu-devel] [PATCH 05/10] target-avr: adding AVR interrupt handling

2016-06-04 Thread Michael Rolnik
fixed. On Sun, Jun 5, 2016 at 1:26 AM, Richard Henderson <r...@twiddle.net> wrote: > On 06/02/2016 01:06 PM, Michael Rolnik wrote: > >> +} else if (env->intsrc != 0) { >> +vector = __builtin_ffs(env->intsrc); >> +} >> > > Use eith

Re: [Qemu-devel] [PATCH 07/10] target-avr: adding instruction decoder

2016-06-04 Thread Michael Rolnik
, Jun 5, 2016 at 2:00 AM, Richard Henderson <r...@twiddle.net> wrote: > On 06/02/2016 01:06 PM, Michael Rolnik wrote: > >> +uint32_tavr_decode(uint32_t pc, uint32_t *length, uint32_t code, >> translate_function_t *translate) >> +{ >> +uint32_topcode = ex

Re: [Qemu-devel] [PATCH v4 1/9] target-avr: AVR cores support is added. 1. basic CPU structure 2. registers 3. no instructions

2016-06-07 Thread Michael Rolnik
Henderson <r...@twiddle.net> wrote: > On 06/06/2016 03:37 AM, Michael Rolnik wrote: > >> +int print_insn_avr(bfd_vma addr, disassemble_info *info) >> +{ >> +int length = 0;; >> +/* TODO*/ >> +return length; >> +} >> > > Again,

Re: [Qemu-devel] [PATCH v4 1/9] target-avr: AVR cores support is added. 1. basic CPU structure 2. registers 3. no instructions

2016-06-08 Thread Michael Rolnik
Hi Richard. how can I test it? On Tue, Jun 7, 2016 at 5:28 PM, Richard Henderson <r...@twiddle.net> wrote: > On 06/06/2016 11:32 PM, Michael Rolnik wrote: > > Hi Richard, > > > > /Consider making the vm save state reflect the actual hardware format. > That &

[Qemu-devel] [PATCH v5 10/10] target-avr: saving sreg, rampD, rampX, rampY, rampD, eind in HW representation saving cpu features

2016-06-08 Thread Michael Rolnik
From: Michael Rolnik <mrol...@gmail.com> From: Michael Rolnik <rol...@amazon.com> Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/machine.c | 105 --- 1 file changed, 84 insertions(+), 21 deletions(-) diff

Re: [Qemu-devel] [PATCH v4 2/9] target-avr: adding AVR CPU features/flavors

2016-06-08 Thread Michael Rolnik
Richard, do you want to delete all empty lines? On Mon, Jun 6, 2016 at 11:25 PM, Richard Henderson <r...@twiddle.net> wrote: > On 06/06/2016 03:37 AM, Michael Rolnik wrote: > >> @@ -55,12 +55,14 @@ static void avr_cpu_reset(CPUState *s) >> AVRCPU *cpu = AVR_CPU(s);

[Qemu-devel] [PATCH v5 00/10] 8bit AVR cores

2016-06-08 Thread Michael Rolnik
From: Michael Rolnik <mrol...@gmail.com> This series of patches adds 8bit AVR cores to QEMU. All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully tested yet. However I was able to execute simple code with functions. e.g fibonacci calculation. This series of patches i

[Qemu-devel] [PATCH v5 06/10] target-avr: adding helpers for IN, OUT, SLEEP, WBR & unsupported instructions

2016-06-08 Thread Michael Rolnik
From: Michael Rolnik <mrol...@gmail.com> From: Michael Rolnik <rol...@amazon.com> Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/helper.c | 145 target-avr/helper.h | 5 ++ 2 files changed, 140 insertion

[Qemu-devel] [PATCH v5 08/10] target-avr: adding instruction translation

2016-06-08 Thread Michael Rolnik
From: Michael Rolnik <mrol...@gmail.com> From: Michael Rolnik <rol...@amazon.com> Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/translate-inst.c | 2624 +++ target-avr/translate.h | 119 ++ 2 files change

[Qemu-devel] [PATCH v5 01/10] target-avr: AVR cores support is added. 1. basic CPU structure 2. registers 3. no instructions

2016-06-08 Thread Michael Rolnik
From: Michael Rolnik <mrol...@gmail.com> From: Michael Rolnik <rol...@amazon.com> Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- arch_init.c | 2 + configure | 7 +- default-configs/avr-softmmu.mak | 21 +++ i

[Qemu-devel] [PATCH v5 07/10] target-avr: adding instruction decoder

2016-06-08 Thread Michael Rolnik
From: Michael Rolnik <mrol...@gmail.com> From: Michael Rolnik <rol...@amazon.com> Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/decode.c | 693 1 file changed, 693 insertions(+) create mode 100644 target-

[Qemu-devel] [PATCH v5 05/10] target-avr: adding AVR interrupt handling

2016-06-08 Thread Michael Rolnik
From: Michael Rolnik <mrol...@gmail.com> From: Michael Rolnik <rol...@amazon.com> Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/helper.c | 59 - 1 file changed, 58 insertions(+), 1 deletion(-) diff

[Qemu-devel] [PATCH v4 4/9] target-avr: adding instructions encodings

2016-06-06 Thread Michael Rolnik
Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/translate-inst.h | 730 1 file changed, 730 insertions(+) create mode 100644 target-avr/translate-inst.h diff --git a/target-avr/translate-inst.h b/target-avr/translate-inst.h ne

[Qemu-devel] [PATCH v4 9/9] target-avr: updating translate.c to use instructions translation

2016-06-06 Thread Michael Rolnik
Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/Makefile.objs | 4 +- target-avr/translate.c | 132 --- 2 files changed, 59 insertions(+), 77 deletions(-) diff --git a/target-avr/Makefile.objs b/target-avr/Makefile.objs

[Qemu-devel] [PATCH v4 5/9] target-avr: adding AVR interrupt handling

2016-06-06 Thread Michael Rolnik
Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/helper.c | 59 - 1 file changed, 58 insertions(+), 1 deletion(-) diff --git a/target-avr/helper.c b/target-avr/helper.c index fbab91d..e798dd9 100644 --- a/target-avr/he

[Qemu-devel] [PATCH v4 7/9] target-avr: adding instruction decoder

2016-06-06 Thread Michael Rolnik
Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/decode.c | 724 1 file changed, 724 insertions(+) create mode 100644 target-avr/decode.c diff --git a/target-avr/decode.c b/target-avr/decode.c new file mode 100644

[Qemu-devel] [PATCH v4 8/9] target-avr: adding instruction translation

2016-06-06 Thread Michael Rolnik
Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/translate-inst.c | 2499 +++ target-avr/translate.h | 120 +++ 2 files changed, 2619 insertions(+) create mode 100644 target-avr/translate-inst.c create mode 100644 targ

[Qemu-devel] [PATCH v4 0/9] 8bit AVR cores

2016-06-06 Thread Michael Rolnik
tent 12.using SUB for NEG 13.fixing tcg_gen_qemu_ld/st call in XCH A big thanks to Richard Henderson for the review. Michael Rolnik (9): target-avr: AVR cores support is added. 1. basic CPU structure 2. registers 3. no instructions target-avr: adding AVR CPU f

[Qemu-devel] [PATCH v4 1/9] target-avr: AVR cores support is added. 1. basic CPU structure 2. registers 3. no instructions

2016-06-06 Thread Michael Rolnik
Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- arch_init.c | 2 + configure | 5 + default-configs/avr-softmmu.mak | 1 + disas/Makefile.objs | 1 + disas/avr.c | 10 ++ include/disas/bfd.h

[Qemu-devel] [PATCH v4 2/9] target-avr: adding AVR CPU features/flavors

2016-06-06 Thread Michael Rolnik
Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/cpu.c | 311 ++- target-avr/cpu.h | 59 +++ 2 files changed, 368 insertions(+), 2 deletions(-) diff --git a/target-avr/cpu.c b/target-avr/cpu.c index cfc1aee..9

[Qemu-devel] [PATCH v4 3/9] target-avr: adding a sample AVR board

2016-06-06 Thread Michael Rolnik
Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- hw/Makefile.objs | 1 + hw/avr/Makefile.objs | 1 + hw/avr/sample-io.c | 217 +++ hw/avr/sample.c | 118 4 files changed, 337 insertions(+)

Re: [Qemu-devel] [PATCH v4 0/9] 8bit AVR cores

2016-06-06 Thread Michael Rolnik
print_insn_avr (bfd_vma, disassemble_info*); On Mon, Jun 6, 2016 at 10:40 PM, Richard Henderson <r...@twiddle.net> wrote: > On 06/06/2016 03:37 AM, Michael Rolnik wrote: > >> changes since v3 >> 1. rampD/X/Y/Z registers are encoded as 0x00ff and not 0x00

Re: [Qemu-devel] [PATCH 08/10] target-avr: adding instruction translation

2016-06-06 Thread Michael Rolnik
On Mon, Jun 6, 2016 at 10:17 PM, Richard Henderson <r...@twiddle.net> wrote: > On 06/05/2016 11:52 PM, Michael Rolnik wrote: > >> truth table shows that these computations are different. >> > > You're not giving the right inputs to the truth table. > > you can'

Re: [Qemu-devel] [PATCH v4 0/9] 8bit AVR cores

2016-06-06 Thread Michael Rolnik
WARNING: architecture specific defines should be avoided #574: FILE: target-avr/cpu.h:32: +#if !defined(__CPU_AVR_H__) it was not my invention, I took it from either target-alpha or target-ppc. On Mon, Jun 6, 2016 at 10:49 PM, Michael Rolnik <mrol...@gmail.com> wrote: > please advise.

[Qemu-devel] [PATCH v6 02/11] target-avr: adding AVR CPU features/flavors

2016-06-12 Thread Michael Rolnik
From: Michael Rolnik <rol...@amazon.com> Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/cpu.c | 307 ++- target-avr/cpu.h | 53 ++ 2 files changed, 359 insertions(+), 1 deletion(-) diff --git a/target

[Qemu-devel] [PATCH v6 01/11] target-avr: AVR cores support is added. 1. basic CPU structure 2. registers 3. no instructions

2016-06-12 Thread Michael Rolnik
From: Michael Rolnik <rol...@amazon.com> Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- arch_init.c | 2 + configure | 7 +- default-configs/avr-softmmu.mak | 21 +++ include/disas/bfd.h | 6 + include/sysemu

[Qemu-devel] [PATCH v6 00/11] 8bit AVR cores

2016-06-12 Thread Michael Rolnik
saving CPU features (savevm) changes since v5 1. BLD bug fix 2. decoder generator is added Michael Rolnik (11): target-avr: AVR cores support is added. 1. basic CPU structure 2. registers 3. no instructions target-avr: adding AVR CPU features/flavors target-a

[Qemu-devel] [PATCH v6 11/11] target-avr: decoder generator. currently not used by the build, can be used manually

2016-06-12 Thread Michael Rolnik
From: Michael Rolnik <rol...@amazon.com> --- target-avr/cpugen/CMakeLists.txt | 38 +++ target-avr/cpugen/README.md| 17 + target-avr/cpugen/cpu/avr.yaml | 218 target-avr/cpugen/src/CMakeLists.txt | 62 target-avr/cpug

[Qemu-devel] [PATCH v6 07/11] target-avr: adding instruction decoder

2016-06-12 Thread Michael Rolnik
From: Michael Rolnik <rol...@amazon.com> Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/decode.c | 693 1 file changed, 693 insertions(+) create mode 100644 target-avr/decode.c diff --git a/target-avr/decode.c

[Qemu-devel] [PATCH v6 08/11] target-avr: adding instruction translation

2016-06-12 Thread Michael Rolnik
From: Michael Rolnik <rol...@amazon.com> Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/translate-inst.c | 2624 +++ target-avr/translate.h | 119 ++ 2 files changed, 2743 insertions(+) create mode 100644 target-a

[Qemu-devel] [PATCH v6 09/11] target-avr: updating translate.c to use instructions translation

2016-06-12 Thread Michael Rolnik
From: Michael Rolnik <rol...@amazon.com> Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/Makefile.objs | 4 +- target-avr/translate.c | 148 +-- 2 files changed, 69 insertions(+), 83 deletions(-) diff --git

[Qemu-devel] [PATCH v6 06/11] target-avr: adding helpers for IN, OUT, SLEEP, WBR & unsupported instructions

2016-06-12 Thread Michael Rolnik
From: Michael Rolnik <rol...@amazon.com> Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/helper.c | 145 target-avr/helper.h | 5 ++ 2 files changed, 140 insertions(+), 10 deletions(-) diff --git a/target-av

[Qemu-devel] [PATCH v6 04/11] target-avr: adding instructions encodings

2016-06-12 Thread Michael Rolnik
From: Michael Rolnik <rol...@amazon.com> Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/translate-inst.h | 762 1 file changed, 762 insertions(+) create mode 100644 target-avr/translate-inst.h diff --git a/target-a

[Qemu-devel] [PATCH v6 03/11] target-avr: adding a sample AVR board

2016-06-12 Thread Michael Rolnik
From: Michael Rolnik <rol...@amazon.com> Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- hw/Makefile.objs | 1 + hw/avr/Makefile.objs | 21 + hw/avr/sample-io.c | 215 +++ hw/avr/sample.

[Qemu-devel] [PATCH v6 05/11] target-avr: adding AVR interrupt handling

2016-06-12 Thread Michael Rolnik
From: Michael Rolnik <rol...@amazon.com> Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/helper.c | 59 - 1 file changed, 58 insertions(+), 1 deletion(-) diff --git a/target-avr/helper.c b/target-avr/helper.c i

[Qemu-devel] [PATCH v6 10/11] target-avr: saving sreg, rampD, rampX, rampY, rampD, eind in HW representation saving cpu features

2016-06-12 Thread Michael Rolnik
From: Michael Rolnik <rol...@amazon.com> Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/machine.c | 105 --- 1 file changed, 84 insertions(+), 21 deletions(-) diff --git a/target-avr/machine.c b/target-avr/machine.c i

[Qemu-devel] [PATCH v7 01/12] target-avr: AVR cores support is added. 1. basic CPU structure 2. registers 3. no instructions

2016-06-14 Thread Michael Rolnik
Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- arch_init.c | 2 + configure | 7 +- default-configs/avr-softmmu.mak | 21 +++ include/disas/bfd.h | 6 + include/sysemu/arch_init.h | 1 + target-avr/Makefil

[Qemu-devel] [PATCH v7 08/12] target-avr: adding instruction translation

2016-06-14 Thread Michael Rolnik
Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/translate-inst.c | 2624 +++ target-avr/translate.h | 119 ++ 2 files changed, 2743 insertions(+) create mode 100644 target-avr/translate-inst.c create mode 100644 targ

[Qemu-devel] [PATCH v7 09/12] target-avr: updating translate.c to use instructions translation

2016-06-14 Thread Michael Rolnik
Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/Makefile.objs | 4 +- target-avr/translate.c | 148 +-- 2 files changed, 69 insertions(+), 83 deletions(-) diff --git a/target-avr/Makefile.objs b/target-avr/Makefile.objs

[Qemu-devel] [PATCH v7 11/12] target-avr: decoder generator. currently not used by the build, can be used manually

2016-06-14 Thread Michael Rolnik
Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/cpugen/CMakeLists.txt | 38 +++ target-avr/cpugen/README.md| 17 ++ target-avr/cpugen/cpu/avr.yaml | 214 ++ target-avr/cpugen/src/CMakeLists.txt | 62 targ

[Qemu-devel] [PATCH v7 03/12] target-avr: adding a sample AVR board

2016-06-14 Thread Michael Rolnik
Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- hw/Makefile.objs | 1 + hw/avr/Makefile.objs | 21 + hw/avr/sample-io.c | 215 +++ hw/avr/sample.c | 118 4 files changed, 355 insertions(+)

[Qemu-devel] [PATCH v7 06/12] target-avr: adding helpers for IN, OUT, SLEEP, WBR & unsupported instructions

2016-06-14 Thread Michael Rolnik
Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/helper.c | 145 target-avr/helper.h | 5 ++ 2 files changed, 140 insertions(+), 10 deletions(-) diff --git a/target-avr/helper.c b/target-avr/helper.c index f96fa27..9

[Qemu-devel] [PATCH v7 00/12] 8bit AVR cores

2016-06-14 Thread Michael Rolnik
esting gen_push_ret/gen_pop_ret Michael Rolnik (12): target-avr: AVR cores support is added. 1. basic CPU structure 2. registers 3. no instructions target-avr: adding AVR CPU features/flavors target-avr: adding a sample AVR board target-avr: adding instructions enc

[Qemu-devel] [PATCH v7 02/12] target-avr: adding AVR CPU features/flavors

2016-06-14 Thread Michael Rolnik
Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/cpu.c | 307 ++- target-avr/cpu.h | 53 ++ 2 files changed, 359 insertions(+), 1 deletion(-) diff --git a/target-avr/cpu.c b/target-avr/cpu.c index 99bd788..1

[Qemu-devel] [PATCH v7 10/12] target-avr: saving sreg, rampD, rampX, rampY, rampD, eind in HW representation saving cpu features

2016-06-14 Thread Michael Rolnik
Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/cpu-qom.h | 2 +- target-avr/cpu.c | 2 +- target-avr/machine.c | 107 --- 3 files changed, 87 insertions(+), 24 deletions(-) diff --git a/target-avr/cpu-qom.h b/targ

[Qemu-devel] [PATCH v7 12/12] target-avr: 1. use cpu_get/set_sreg function at avr_cpu_gdb_read_register/avr_cpu_gdb_read_register 2. configuring target as little endian 3. fixing and testing gen_push_

2016-06-14 Thread Michael Rolnik
Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- configure | 2 +- target-avr/gdbstub.c| 19 ++- target-avr/translate-inst.c | 45 + target-avr/translate.c | 5 - 4 files changed, 28 inse

[Qemu-devel] [PATCH v7 05/12] target-avr: adding AVR interrupt handling

2016-06-14 Thread Michael Rolnik
Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/helper.c | 59 - 1 file changed, 58 insertions(+), 1 deletion(-) diff --git a/target-avr/helper.c b/target-avr/helper.c index ad8f83e..f96fa27 100644 --- a/target-avr/he

[Qemu-devel] [PATCH v7 04/12] target-avr: adding instructions encodings

2016-06-14 Thread Michael Rolnik
Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/translate-inst.h | 762 1 file changed, 762 insertions(+) create mode 100644 target-avr/translate-inst.h diff --git a/target-avr/translate-inst.h b/target-avr/translate-inst.h ne

[Qemu-devel] [PATCH v7 07/12] target-avr: adding instruction decoder

2016-06-14 Thread Michael Rolnik
Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/decode.c | 693 1 file changed, 693 insertions(+) create mode 100644 target-avr/decode.c diff --git a/target-avr/decode.c b/target-avr/decode.c new file mode 100644

Re: [Qemu-devel] [PATCH v6 08/11] target-avr: adding instruction translation

2016-06-13 Thread Michael Rolnik
what is the difference between tcg_gen_qemu_st16 and tcg_gen_qemu_st_tl On Mon, Jun 13, 2016 at 7:06 PM, Richard Henderson <r...@twiddle.net> wrote: > On 06/12/2016 12:01 PM, Michael Rolnik wrote: > >> +void gen_push_ret(CPUAVRState *env, int ret) >> +{ >

Re: [Qemu-devel] [PATCH 09/10] target-avr: updating translate.c to use instructions translation

2016-06-05 Thread Michael Rolnik
get_opcode no longer present. I use it for the sake of skip instruction. I do not know a priori the length of the next instruction as it can be either 16 or 32 bits. On Sun, Jun 5, 2016 at 6:33 AM, Richard Henderson <r...@twiddle.net> wrote: > On 06/02/2016 01:07 PM, Michael Rol

Re: [Qemu-devel] [PATCH 08/10] target-avr: adding instruction translation

2016-06-05 Thread Michael Rolnik
please see my answer inside. On Sun, Jun 5, 2016 at 6:27 AM, Richard Henderson <r...@twiddle.net> wrote: > On 06/02/2016 01:07 PM, Michael Rolnik wrote: > >> Signed-off-by: Michael Rolnik <mrol...@gmail.com> >> --- >>

Re: [Qemu-devel] [PATCH 04/10] target-avr: adding instructions encodings

2016-06-04 Thread Michael Rolnik
, 2016 at 1:17 AM, Richard Henderson <r...@twiddle.net> wrote: > On 06/02/2016 01:06 PM, Michael Rolnik wrote: > >> Signed-off-by: Michael Rolnik <mrol...@gmail.com> >> --- >> target-avr/translate-inst.h | 838 >> +

Re: [Qemu-devel] [PATCH 08/10] target-avr: adding instruction translation

2016-06-06 Thread Michael Rolnik
On Mon, Jun 6, 2016 at 2:34 AM, Richard Henderson <r...@twiddle.net> wrote: > On 06/05/2016 02:47 PM, Michael Rolnik wrote: > >> Is there a reason this code isn't going into translate.c? >> You wouldn't need the declarations in translate-inst.h or translate.h. >

[Qemu-devel] [PATCH v5 02/10] target-avr: adding AVR CPU features/flavors

2016-06-08 Thread Michael Rolnik
From: Michael Rolnik <mrol...@gmail.com> From: Michael Rolnik <rol...@amazon.com> Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/cpu.c | 307 ++- target-avr/cpu.h | 53 ++ 2 files changed, 35

[Qemu-devel] [PATCH v5 04/10] target-avr: adding instructions encodings

2016-06-08 Thread Michael Rolnik
From: Michael Rolnik <mrol...@gmail.com> From: Michael Rolnik <rol...@amazon.com> Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/translate-inst.h | 762 1 file changed, 762 insertions(+) create mode 100644 ta

[Qemu-devel] [PATCH v5 03/10] target-avr: adding a sample AVR board

2016-06-08 Thread Michael Rolnik
From: Michael Rolnik <mrol...@gmail.com> From: Michael Rolnik <rol...@amazon.com> Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- hw/Makefile.objs | 1 + hw/avr/Makefile.objs | 21 + hw/avr/sample-io.c | 215 ++

[Qemu-devel] [PATCH v5 09/10] target-avr: updating translate.c to use instructions translation

2016-06-08 Thread Michael Rolnik
From: Michael Rolnik <mrol...@gmail.com> From: Michael Rolnik <rol...@amazon.com> Signed-off-by: Michael Rolnik <mrol...@gmail.com> --- target-avr/Makefile.objs | 4 +- target-avr/translate.c | 148 +-- 2 files changed, 69

Re: [Qemu-devel] [PATCH v4 4/9] target-avr: adding instructions encodings

2016-06-08 Thread Michael Rolnik
wrote: > On 6 June 2016 at 22:38, Richard Henderson <r...@twiddle.net> wrote: > > On 06/06/2016 03:37 AM, Michael Rolnik wrote: > >> > >> Signed-off-by: Michael Rolnik <mrol...@gmail.com> > >> --- > >> target-avr/translate-inst.h | 730 > &g

Re: [Qemu-devel] [PATCH 1/9] AVR cores support is added. 1. basic CPU structure 2. registers 3. no instructions

2016-06-02 Thread Michael Rolnik
I ran checkpatch.pl on my patches and it was ok. I will fix it. On Thu, Jun 2, 2016 at 9:39 AM, Richard Henderson <r...@twiddle.net> wrote: > On 05/29/2016 06:23 PM, Michael Rolnik wrote: > >> +static void avr_cpu_set_pc( >> +

Re: [Qemu-devel] [PATCH 4/9] adding instructions encodings for LE and BE compilers.

2016-06-02 Thread Michael Rolnik
I disagree. it's non portable as long as you don't know what compiler you are using. if bitfields are not acceptable at all, I will regenerate my code. thanks. On Thu, Jun 2, 2016 at 9:32 AM, Richard Henderson <r...@twiddle.net> wrote: > On 05/29/2016 06:23 PM, Michael Rolnik wrote: &

Re: [Qemu-devel] [PATCH 8/9] adding instruction translations

2016-06-02 Thread Michael Rolnik
right. no reason. I can make it just a C file. when I started I was not sure what was the best way to do it as I generate some come code. thanks, I will fix it. On Thu, Jun 2, 2016 at 9:44 AM, Richard Henderson <r...@twiddle.net> wrote: > On 05/29/2016 06:23 PM, Michael Rolnik wrote: &g

[Qemu-devel] heterogenous cores

2016-06-01 Thread Michael Rolnik
Hi all, Is there a way to build a platform with two or more different cores e.g. PPC & ARM ? -- Best Regards, Michael Rolnik

Re: [Qemu-devel] heterogenous cores

2016-06-01 Thread Michael Rolnik
as I understand it's not possible right off the shelf as some functions like gen_intermediate_code are global. so, the question is *is it a complex task to make a heterogenous setup possible*? On Thu, Jun 2, 2016 at 12:28 AM, Michael Rolnik <mrol...@gmail.com> wrote: > Hi all, > >

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