der instructions to match AVR documentation
4. fix elf loader function bug introduced by prev version
changes since v39
1. rename target/avr to hw/avr for hw related commits
2. spread instruction decoding commit
3. add frequency parameter to AVR timer
4. fix offset of some unimplemented registers
This includes:
- MOV, MOVW
- LDI, LDS LDX LDY LDZ
- LDDY, LDDZ
- STS, STX STY STZ
- STDY, STDZ
- LPM, LPMX
- ELPM, ELPMX
- SPM, SPMX
- IN, OUT
- PUSH, POP
- XCH
- LAS, LAC LAT
Signed-off-by: Michael Rolnik
---
target/avr/translate.c | 986
Signed-off-by: Michael Rolnik
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
---
target/avr/translate.c | 172 +
1 file changed, 172 insertions(+)
create mode 100644 target/avr/translate.c
diff --git a/target/avr/translate.c b
Signed-off-by: Michael Rolnik
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Aleksandar Markovic
---
tests/machine-none-test.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/machine-none-test.c b/tests/machine-none-test.c
index 5953d31755..3e5c74e73e 100644
--- a/tests/machine-none
This is a simple device of just one register, whenver this register is
written it calls qemu_set_irq function for each of 8 bits/IRQs..
It is used to implement AVR Power Reduction
Signed-off-by: Michael Rolnik
---
include/hw/misc/avr_mask.h | 47
hw/misc/avr_mask.c
These were designed to facilitate testing but should provide enough function to
be useful in other contexts.
Only a subset of the functions of each peripheral is implemented, mainly due to
the lack of a standard way to handle electrical connections (like GPIO pins).
Signed-off-by: Sarah Harris
Add AVR related definitions into QEMU
Signed-off-by: Michael Rolnik
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Aleksandar Markovic
include/disas/dis-asm.h
---
qapi/machine.json | 3 ++-
include/disas/dis-asm.h| 19 +++
include/sysemu/arch_init.h | 1
This includes:
- ADD, ADC, ADIW
- SBIW, SUB, SUBI, SBC, SBCI
- AND, ANDI
- OR, ORI, EOR
- COM, NEG
- INC, DEC
- MUL, MULS, MULSU
- FMUL, FMULS, FMULSU
- DES
Signed-off-by: Michael Rolnik
Tested-by: Philippe Mathieu-Daudé
---
target/avr/translate.c | 751
, r24
0x04c2: RET
...
```
Signed-off-by: Michael Rolnik
Suggested-by: Richard Henderson
Suggested-by: Philippe Mathieu-Daudé
Suggested-by: Aleksandar Markovic
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
---
target/avr/cpu.h | 1 +
target/avr/cpu.c
This includes:
- RJMP, IJMP, EIJMP, JMP
- RCALL, ICALL, EICALL, CALL
- RET, RETI
- CPSE, CP, CPC, CPI
- SBRC, SBRS, SBIC, SBIS
- BRBC, BRBS
Signed-off-by: Michael Rolnik
Tested-by: Philippe Mathieu-Daudé
---
target/avr/translate.c | 533
Co-developed-by: Richard Henderson
Co-developed-by: Michael Rolnik
Signed-off-by: Michael Rolnik
Tested-by: Philippe Mathieu-Daudé
---
target/avr/translate.c | 234 +
1 file changed, 234 insertions(+)
diff --git a/target/avr/translate.c b/target/avr
Include AVR maintaners in MAINTAINERS file
Signed-off-by: Michael Rolnik
---
MAINTAINERS | 21 +
1 file changed, 21 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 387879aebc..90c0a0c27f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -163,6 +163,15 @@ S
This includes:
- CPU data structures
- object model classes and functions
- migration functions
- GDB hooks
Co-developed-by: Michael Rolnik
Co-developed-by: Sarah Harris
Signed-off-by: Michael Rolnik
Signed-off-by: Sarah Harris
Signed-off-by: Michael Rolnik
Acked-by: Igor Mammedov
Tested
These were designed to facilitate testing but should provide enough function to
be useful in other contexts.
Only a subset of the functions of each peripheral is implemented, mainly due to
the lack of a standard way to handle electrical connections (like GPIO pins).
Signed-off-by: Sarah Harris
Make AVR support buildable
Signed-off-by: Michael Rolnik
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Aleksandar Markovic
---
configure | 7 +++
default-configs/avr-softmmu.mak | 5 +
target/avr/Makefile.objs| 34 +
3
Signed-off-by: Michael Rolnik
---
qemu-doc.texi | 51 +++
1 file changed, 51 insertions(+)
diff --git a/qemu-doc.texi b/qemu-doc.texi
index 39f950471f..515aacfae9 100644
--- a/qemu-doc.texi
+++ b/qemu-doc.texi
@@ -1741,6 +1741,7 @@ differences
This includes:
- BREAK
- NOP
- SLEEP
- WDR
Signed-off-by: Michael Rolnik
---
target/avr/translate.c | 68 ++
target/avr/insn.decode | 9 ++
2 files changed, 77 insertions(+)
diff --git a/target/avr/translate.c b/target/avr
access instructions are implemented here because some address ranges
actually refer to CPU registers.
Signed-off-by: Michael Rolnik
Tested-by: Philippe Mathieu-Daudé
---
target/avr/helper.h | 29
target/avr/helper.c | 347
2 files changed, 376
This includes:
- LSR, ROR
- ASR
- SWAP
- SBI, CBI
- BST, BLD
- BSET, BCLR
Signed-off-by: Michael Rolnik
---
target/avr/translate.c | 241 +
target/avr/insn.decode | 14 +++
2 files changed, 255 insertions(+)
diff --git a/target
The test is based on
https://github.com/seharris/qemu-avr-tests/tree/master/free-rtos/Demo
demo which. If working correctly, prints 'ABCDEFGHIJKLMNOPQRSTUVWX' out.
it also demostrates that timer and IRQ are working
Signed-off-by: Michael Rolnik
Reviewed-by: Philippe Mathieu-Daudé
Tested
Hi Wainer.
thanks for reviewing.
1. when `self.vm.shutdown()` is not called `self.vm.get_log()` returns
`ERROR: argument of type 'NoneType' is not iterable`
2. I will remove the unnecessary imports
Thanks,
Michael Rolnik
On Mon, Dec 30, 2019 at 7:37 PM Wainer dos Santos Moschetta <
wa
Hi Philippe.
Thank you for joining the effort.
Regards,
Michael Rolnik
On Mon, Dec 30, 2019 at 12:45 AM Philippe Mathieu-Daudé
wrote:
> Hi,
>
> This series add the arduino boards, aiming at removing the
> 'sample' board that doesn't follow any specification.
>
> Sin
Hi Aleksandar.
FreeRTOS demo we use uses avr6, that's why we use avr6.
Regards.
Michael Rolnik
On Mon, Dec 23, 2019 at 11:13 AM Aleksandar Markovic <
aleksandar.m.m...@gmail.com> wrote:
>
>
> On Wednesday, December 18, 2019, Michael Rolnik wrote:
>
>> This series
...@gmail.com> wrote:
>
>
> On Wednesday, December 18, 2019, Michael Rolnik wrote:
>
>> Signed-off-by: Michael Rolnik
>> ---
>
>
> Hi, Michael.
>
> Please avoid empty commit messages.
>
> At the very beginning, there is a line:
>
> + * AVR P
ndar.m.m...@gmail.com> wrote:
>
>>
>>
>> On Saturday, December 21, 2019, Michael Rolnik wrote:
>>
>>> Hi Aleksandar.
>>>
>>> please explain.
>>>
>>>>
>>>>
>> Hi, Michael.
>>
>> I wanted to say:
&g
but this is a sample board that has some ATmega2560 devices and its avr6
core
On Sat, Dec 28, 2019 at 9:38 PM Aleksandar Markovic <
aleksandar.m.m...@gmail.com> wrote:
>
>
> On Saturday, December 28, 2019, Michael Rolnik wrote:
>
>> Hi Aleksandar.
>>
>> Fr
hi all.
are there any news / updates about AVR support?
On Mon, Mar 23, 2020 at 10:14 PM Michael Rolnik wrote:
> thanks Philippe.
>
> On Mon, Mar 23, 2020 at 9:20 PM Philippe Mathieu-Daudé
> wrote:
>
>> On 3/23/20 7:03 PM, Richard Henderson wrote:
>> > On 3/
Hi Philippe.
It's been a while. let me think about it and get back to you. what is your
concern ?
Regards,
Michael Rolnik
On Mon, Mar 23, 2020 at 5:55 PM Philippe Mathieu-Daudé
wrote:
> Hi Michael,
>
> On 1/18/20 8:13 PM, Michael Rolnik wrote:
> > This includes:
> >
thanks Philippe.
On Mon, Mar 23, 2020 at 9:20 PM Philippe Mathieu-Daudé
wrote:
> On 3/23/20 7:03 PM, Richard Henderson wrote:
> > On 3/23/20 10:03 AM, Michael Rolnik wrote:
> >> Hi Philippe.
> >>
> >> It's been a while. let me think about it and get back
Acked-by: Michael Rolnik >
On Mon, Oct 12, 2020 at 8:56 AM sundeep subbaraya
wrote:
> Acked-by: Subbaraya Sundeep
>
> Thanks,
> Sundeep
>
> On Sun, Oct 4, 2020 at 11:55 PM Philippe Mathieu-Daudé
> wrote:
> >
> > These individual contributors have a n
Reviewed-by: Michael Rolnik
On Sat, Oct 10, 2020 at 5:34 PM Heecheol Yang
wrote:
> Add some of these features for AVR GPIO:
>
> - GPIO I/O : PORTx registers
> - Data Direction : DDRx registers
> - DDRx toggling : PINx registers
>
> Following things are not supp
Tested-by: Michael Rolnik
On Fri, Aug 14, 2020 at 7:39 PM Philippe Mathieu-Daudé
wrote:
> In this series we slowly start to use the recently added
> Clock API in the AVR ATmega MCU.
>
> As the Clock Control Unit is not yet modelled, we simply
> connect the XTAL sink to the
e hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef AVR_GPIO_H
> +#define AVR_GPIO_H
> +
> +#include "hw/sysbus.h"
> +#include "qom/object.h"
> +
> +/* Offsets of registers. */
> +#define GPIO_PIN 0x00
> +#define GPIO_DDR 0x01
> +#define GPIO_PORT 0x02
> +
> +#define TYPE_AVR_GPIO "avr-gpio"
> +OBJECT_DECLARE_SIMPLE_TYPE(AVRGPIOState, AVR_GPIO)
> +
> +struct AVRGPIOState {
> +/*< private >*/
> +SysBusDevice parent_obj;
> +
> +/*< public >*/
> +MemoryRegion mmio;
> +
> +uint8_t ddr_val;
> +uint8_t port_val;
> +
> +};
> +
> +#endif /* AVR_GPIO_H */
> --
> 2.17.1
>
>
--
Best Regards,
Michael Rolnik
te *cs)
> env->sregI = 0; /* clear Global Interrupt Flag */
>
> cs->exception_index = -1;
> +if (bql) {
> +qemu_mutex_unlock_iothread();
> +}
> }
>
> int avr_cpu_memory_rw_debug(CPUState *cs, vaddr addr, uint8_t *buf,
> --
> 2.17.1
>
>
--
Best Regards,
Michael Rolnik
Reviewed-by: Michael Rolnik
On Thu, Aug 13, 2020 at 7:50 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 8/12/20 8:53 AM, Thomas Huth wrote:
> > The examples look nicer when using "::" code blocks.
> > Also mention that "-d in_asm&
Tested-by: Michael Rolnik
I mean I got the patch, built and then ran *make check-qtest-avr* and *make
check-acceptance*
On Mon, Jul 20, 2020 at 4:24 PM Michael Rolnik wrote:
> Reviewed-by: Michael Rolnik
>
>
> On Tue, Jul 14, 2020 at 7:42 PM Philippe Mathieu-Daudé
>
Reviewed-by: Michael Rolnik
On Tue, Jul 14, 2020 at 7:42 PM Philippe Mathieu-Daudé
wrote:
> Fix the memory leak reported by Coverity (CID 1430449).
>
> Philippe Mathieu-Daudé (4):
> qemu/osdep: Document os_find_datadir() return value
> qemu/osdep: Reword qemu_get_exec_dir(
ping
On Sun, May 16, 2021 at 1:10 AM Michael Rolnik wrote:
> 1. Initial implementation of AVR WDT
> There are two issues with this implementation so I need your help here
> a. when I configure the WDT to fire an interrupt every 15ms it
> actually happens every 6 instruct
b_end(tb, num_insns);
> +static void avr_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs)
> +{
> +qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
> +log_target_disas(cs, dcbase->pc_first, dcbase->tb->size);
> +}
>
> - tb->size = (ctx->npc - pc_start) * 2;
> -tb->icount = num_insns;
> +static const TranslatorOps avr_tr_ops = {
> +.init_disas_context = avr_tr_init_disas_context,
> +.tb_start = avr_tr_tb_start,
> +.insn_start = avr_tr_insn_start,
> +.breakpoint_check = avr_tr_breakpoint_check,
> +.translate_insn = avr_tr_translate_insn,
> +.tb_stop= avr_tr_tb_stop,
> +.disas_log = avr_tr_disas_log,
> +};
>
> -#ifdef DEBUG_DISAS
> -if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
> -&& qemu_log_in_addr_range(tb->pc)) {
> -FILE *fd;
> -fd = qemu_log_lock();
> -qemu_log("IN: %s\n", lookup_symbol(tb->pc));
> -log_target_disas(cs, tb->pc, tb->size);
> -qemu_log("\n");
> -qemu_log_unlock(fd);
> -}
> -#endif
> +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int
> max_insns)
> +{
> +DisasContext dc;
> +translator_loop(_tr_ops, , cs, tb, max_insns);
> }
>
> void restore_state_to_opc(CPUAVRState *env, TranslationBlock *tb,
> --
> 2.25.1
>
>
--
Best Regards,
Michael Rolnik
Reviewed-by: Michael Rolnik
Tested-by: Michael Rolnik
On Mon, Jun 21, 2021 at 12:50 AM Richard Henderson <
richard.hender...@linaro.org> wrote:
> Signed-off-by: Richard Henderson
> ---
> target/avr/translate.c | 234 ++---
> 1 file chang
Reviewed-by: Michael Rolnik
On Mon, Jun 21, 2021 at 4:34 AM Richard Henderson <
richard.hender...@linaro.org> wrote:
> All of these helpers end with cpu_loop_exit.
>
> Cc: Michael Rolnik
> Signed-off-by: Richard Henderson
> ---
> target/avr/helper.h | 8 -
The whole series.
On Mon, Jun 21, 2021 at 11:33 AM Philippe Mathieu-Daudé
wrote:
> Hi Michael,
>
> On 6/21/21 7:38 AM, Michael Rolnik wrote:
> > Reviewed-by: Michael Rolnik mailto:mrol...@gmail.com
> >>
> > Tested-by: Michael Rolnik mailto:mrol...@gmail
Ok, thanks.
Sent from my cell phone, please ignore typos
On Thu, May 13, 2021, 3:27 PM Pavel Dovgalyuk
wrote:
> On 06.05.2021 00:18, Michael Rolnik wrote:
> > Signed-off-by: Michael Rolnik
> > ---
> > MAINTAINERS | 2 +
> > hw/avr/Kconfig
Signed-off-by: Michael Rolnik
---
MAINTAINERS | 2 +
hw/avr/Kconfig| 1 +
hw/avr/atmega.c | 15 +-
hw/avr/atmega.h | 2 +
hw/watchdog/Kconfig | 3 +
hw/watchdog/avr_wdt.c | 274
. correct RW or RW1C behavior is implemented
2. icount functionality is fixed
3. I still observe something strange, it takes AVR 150 instructions to
simulate 15ms
*** BLURB HERE ***
Michael Rolnik (1):
Implement AVR watchdog timer
MAINTAINERS | 2 +
hw/avr/Kconfig
. correct RW or RW1C behavior is implemented
2. icount functionality is fixed
3. I still observe something strange, it takes AVR 150 instructions to
simulate 15ms
changes since v2
1. use REG8 & FIELD macros to define registers
2. fixing ICOUNT behavior
*** BLURB HERE ***
Michael Rolni
Signed-off-by: Michael Rolnik
---
MAINTAINERS | 2 +
hw/avr/Kconfig| 1 +
hw/avr/atmega.c | 15 +-
hw/avr/atmega.h | 2 +
hw/watchdog/Kconfig | 3 +
hw/watchdog/avr_wdt.c | 279
Reviewed-by: Michael Rolnik
On Tue, Jul 6, 2021 at 9:09 PM Stefan Weil wrote:
> ../target/avr/translate.c: In function ‘gen_jmp_ez’:
> ../target/avr/translate.c:1012:22: error: implicit conversion from ‘enum
> ’ to ‘DisasJumpType’ [-Werror=enum-conversion]
> 1012 | ctx-
Signed-off-by: Michael Rolnik
---
hw/avr/Kconfig| 1 +
hw/avr/atmega.c | 15 ++-
hw/avr/atmega.h | 2 +
hw/watchdog/Kconfig | 3 +
hw/watchdog/avr_wdt.c | 190 ++
hw/watchdog/meson.build
1. Initial implementation of AVR WDT
There are two issues with this implementation so I need your help here
a. when I configure the WDT to fire an interrupt every 15ms it actually
happens every 6 instructions
b. when I specify --icount shift=0 qemu stucks
Michael Rolnik (1
1. Initial implementation of AVR WDT
There are two issues with this implementation so I need your help here
a. when I configure the WDT to fire an interrupt every 15ms it actually
happens every 6 instructions
b. when I specify --icount shift=0 qemu stucks
Michael Rolnik (1
1. Initial implementation of AVR WDT
There are two issues with this implementation so I need your help here
a. when I configure the WDT to fire an interrupt every 15ms it actually
happens every 6 instructions
b. when I specify --icount shift=0 qemu stucks
Michael Rolnik (1
you,
Michael Rolnik
On Mon, May 3, 2021 at 4:36 PM Michael Rolnik wrote:
> Hi Fred.
>
> 1. thanks
> 2. It seems I have forgotten to set those flags.
> 3. 15ms is easy to test 8s will take 533 times longer, so in my case 3200
> instructions which is totally incorrect. I do
Hi Fred.
How can I reproduce it?
Thank you.
Michael Rolnik
Sent from my cell phone, please ignore typos
On Wed, Apr 28, 2021, 5:17 PM Fred Konrad wrote:
> Hi,
>
> I fall on a segfault while running the wdr instruction on AVR:
>
> (gdb) bt
> #0 0xadd0b23a in gd
help with icount.
best regards,
Michael Rolnik
On Mon, May 3, 2021 at 4:15 PM Fred Konrad wrote:
>
>
> Le 5/2/21 à 10:10 PM, Michael Rolnik a écrit :
> > Signed-off-by: Michael Rolnik
> > ---
> > hw/avr/Kconfig| 1 +
> > hw/avr/atmega.c
how long?
On Tue, Mar 23, 2021 at 2:46 PM Dr. David Alan Gilbert
wrote:
> * Michael Rolnik (mrol...@gmail.com) wrote:
> > Signed-off-by: Michael Rolnik
> > ---
> > target/avr/cpu-param.h | 8 +---
> > target/avr/helper.c| 2 --
> > 2 files cha
12 and everything will work fine.
What do you think?
btw, wrote the original comment, you David referred to, when I did not know
that QEMU could map several regions to the same page, which is not true.
That's why I could change 8 to 10.
On Tue, Mar 23, 2021 at 10:11 PM Michael Rolnik wrote:
> ho
Reviewed-by: Michael Rolnik
On Thu, Mar 11, 2021 at 3:55 PM G S Niteesh Babu
wrote:
> Hello,
>
> The following series of the patches add a basic AVR GPIO emulation
> to QEMU. The AVR GPIO emulation patch was originally written by
> Heecheol Yang and was posted on the mailin
how do I test my fix? Is there a procedure?
Thanks,
Michael Rolnik
On Thu, Mar 18, 2021 at 12:45 PM Dr. David Alan Gilbert
wrote:
> * Peter Maydell (peter.mayd...@linaro.org) wrote:
> > On Thu, 18 Mar 2021 at 10:25, Dr. David Alan Gilbert
> > wrote:
> > > Oh yes, just
ok. I will try to fix it.
Regards,
Michael Rolnik
On Thu, Mar 18, 2021 at 11:55 AM Dr. David Alan Gilbert
wrote:
> * Michael Rolnik (mrol...@gmail.com) wrote:
> > Hi Dave.
> >
> > What is the smallest supported page size?
>
> Currently 512 I think; in migration
The previous value of TARGET_PAGE_BITS (8) is a bug. Make it 10
I tested it using the following commands
1. ninja test
2. make check-qtest-avr
3. avocado --show=app run -t arch:avr tests/acceptance/
Michael Rolnik (1):
Set TARGET_PAGE_BITS to be 10 instead of 8 bits
target/avr/cpu-param.h | 8
Signed-off-by: Michael Rolnik
---
target/avr/cpu-param.h | 8 +---
target/avr/helper.c| 2 --
2 files changed, 1 insertion(+), 9 deletions(-)
diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h
index 7ef4e7c679..9765a9d0db 100644
--- a/target/avr/cpu-param.h
+++ b/target/avr
Reviewed-by: Michael Rolnik
On Sat, Mar 13, 2021 at 6:54 PM Philippe Mathieu-Daudé
wrote:
> Hi,
>
> This series contains all the AVR patches I could find on the list.
>
> Niteesh, I fixed minor issues. Do you mind reviewing on top?
>
> Pull request planned for Monday
see migration/ram.c
> RAM_SAVE_FLAG_*- and it's actually tricky to change it, because if
> you change it then it'll break migration compatibility with existing
> qemu's.
>
> Hmm.
>
> Dave
>
> --
> Dr. David Alan Gilbert / dgilb...@redhat.com / Manchester, UK
>
>
--
Best Regards,
Michael Rolnik
I guess we can add some bits TARGET_PAGE_BITS, this will make us to push
some portion of SRAM into the CPU.
Michael Rolnik
On Thu, Mar 18, 2021 at 12:33 AM Peter Maydell
wrote:
> On Wed, 17 Mar 2021 at 20:17, Dr. David Alan Gilbert
> wrote:
> >
> > Hi Michael,
> >
Please review.
On Tue, Mar 23, 2021 at 10:28 PM Michael Rolnik wrote:
> If I set TARGET_PAGE_BITS to 12 this *assert assert(v_l2_levels >= 0);*
> will fail (page_table_config_init function) because
> TARGET_PHYS_ADDR_SPACE_BITS is 24 bits, because AVR has 24 is the longest
> poi
Reviewed-by: Michael Rolnik
On Fri, Sep 24, 2021 at 12:40 PM Philippe Mathieu-Daudé
wrote:
> Restrict has_work() to sysemu.
>
> Reviewed-by: Richard Henderson
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/avr/cpu.c | 2 +-
> 1 file changed, 1 insertion(+), 1
gt; >> ---
> >> target/avr/translate.c | 16 +---
> >> 1 file changed, 5 insertions(+), 11 deletions(-)
> >
> > Reviewed-by: Richard Henderson
>
> Do you mind taking this patch via tcg-next?
>
--
Best Regards,
Michael Rolnik
Reviewed-by: Michael Rolnik
On Mon, Dec 6, 2021 at 12:41 AM Philippe Mathieu-Daudé
wrote:
> TYPE_AVR_CPU inherits TYPE_CPU, which itself inherits TYPE_DEVICE.
> TYPE_DEVICE instances are realized using qdev_realize(), we don't
> need to access QOM internal values.
>
> Signed-o
Reviewed-by: Michael Rolnik
Tested-by: Michael Rolnik
On Wed, Jul 21, 2021 at 9:00 PM Philippe Mathieu-Daudé
wrote:
> +Michael/Alex/Pavel
>
> On 7/21/21 8:41 AM, Richard Henderson wrote:
> > GDB single-stepping is now handled generically.
> >
> > Signe
Reviewed-by: Michael Rolnik
On Tue, Oct 24, 2023 at 2:32 AM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 10/23/23 09:09, Philippe Mathieu-Daudé wrote:
> > Inspired-by: Richard Henderson
> > Signed-off-by: Philippe Mathieu-Daudé
> > ---
> &
Reviewed-by: Michael Rolnik
On Fri, Aug 26, 2022 at 11:55 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> We cannot deliver two interrupts simultaneously;
> the first interrupt handler must execute first.
>
> Signed-off-by: Richard Henderson
> ---
>
Reviewed-by: Michael Rolnik
On Fri, Aug 26, 2022 at 11:55 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> There is no need to go through cc->tcg_ops when
> we know what value that must have.
>
> Signed-off-by: Richard Henderson
> ---
> target/avr/h
Reviewed-by: Michael Rolnik
On Fri, Aug 26, 2022 at 11:55 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> This bit is not saved across interrupts, so we must
> delay delivering the interrupt until the skip has
> been processed.
>
> Resolves: https://gitlab.
Reviewed-by: Michael Rolnik
On Fri, Aug 26, 2022 at 11:55 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> Fixes https://gitlab.com/qemu-project/qemu/-/issues/1118
>
> r~
>
> Richard Henderson (3):
> target/avr: Call avr_cpu_do_interrupt directly
> t
Hi all,
Is there any kind of web UI where I can review it?
I don't find this patch in https://patchew.org/ (there is only 2 year old
version (https://patchew.org/search?q=project%3AQEMU+%22hw%2Favr%22))
Thank you,
Michael Rolnik
On Mon, Sep 12, 2022 at 2:21 PM Heecheol Yang
wrote:
> Add s
Hi Heecheol Yang.
I suggest rebasing your patch to the master.
Regards,
Michael Rolnik
On Sun, Sep 11, 2022 at 7:47 PM Hee-cheol Yang
wrote:
> Hello.
>
> First of all, I am very sorry for my late response for following
> patchworks for AVR gpio.:
>
>- https:
Reviewed-by: Michael Rolnik
On Sat, Nov 19, 2022 at 7:56 AM Pavel Dovgalyuk
wrote:
> Bit vector for features has 64 bits. This patch fixes bit shifts in
> avr_feature and set_avr_feature functions to be 64-bit too.
>
> Signed-off-by: Pavel Dovgalyuk
> ---
> target/avr/cpu.
Reviewed-by: Michael Rolnik
On Wed, Jun 14, 2023 at 3:22 PM Philippe Mathieu-Daudé
wrote:
> On 14/6/23 16:07, Lucas Dietrich wrote:
> > This commit addresses a bug in the AVR interrupt handling code.
> > The modification involves replacing the usage of the ctz32 function
Reviewed-by: Michael Rolnik
On Fri, Jun 9, 2023 at 12:04 AM Adecy wrote:
>
>
> -- Forwarded message -
> De : Adecy
> Date: jeu. 1 juin 2023 à 21:34
> Subject: QEMU AVR Patch - Correct handling of AVR interrupts
> To:
>
>
> Hello,
>
> I wou
Reviewed-by: Michael Rolnik
On Sun, May 14, 2023 at 12:54 AM ~rmsyn wrote:
> From: rmsyn
>
> Adds support for ATmega16u4 and ATmega32u4 MCU definitions.
>
> Defines interrupts, memory layout, and machine types for generic
> ATmega16u4 and ATmega32u4 MCUs.
>
> Signed-of
Hi all,
Previously there was *TARGET_ALIGNED_ONLY* option that caused all memory
accessed to be aligned, now it seems to be removed.
Is there a way to achieve memory access alignment with QEMU v9.0.0 when I
am building a custom target?
--
Best Regards,
Michael Rolnik
Thank you Richard.
On Sun, May 19, 2024 at 6:26 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 5/19/24 16:23, Michael Rolnik wrote:
> > Hi all,
> >
> > Previously there was *TARGET_ALIGNED_ONLY* option that caused all memory
> accessed t
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