On Mon Jun 26, 2023 at 11:35 PM AEST, Cédric Le Goater wrote:
> On 6/23/23 14:37, Cédric Le Goater wrote:
> > On 6/23/23 11:10, Peter Maydell wrote:
> >> On Fri, 23 Jun 2023 at 09:21, Nicholas Piggin wrote:
> >>>
> >>> ppc has always silently i
On Tue Jun 27, 2023 at 7:45 AM AEST, Cédric Le Goater wrote:
> On 6/26/23 14:26, Michael Tokarev wrote:
> > 26.06.2023 08:56, Cédric Le Goater wrote:
> >> From: Nicholas Piggin
> >>
> >> Fix missing env->ca restore when going from L2 back to the hos
On Wed Jun 28, 2023 at 3:38 AM AEST, BALATON Zoltan wrote:
> On Tue, 27 Jun 2023, Nicholas Piggin wrote:
> > checkstop state does not halt the system, interrupts continue to be
> > serviced, and other CPUs run.
> >
> > Stop the machine with vm_stop(), and print a regist
On Wed Jun 28, 2023 at 1:25 AM AEST, Fabiano Rosas wrote:
> Nicholas Piggin writes:
>
> > attn is an implementation-specific instruction that on POWER (and G5/
> > 970) can be enabled with a HID bit (disabled = illegal), and executing
> > it causes the host processor
On Wed Jun 28, 2023 at 3:40 AM AEST, BALATON Zoltan wrote:
> On Mon, 26 Jun 2023, Nicholas Piggin wrote:
> > On Tue Jun 20, 2023 at 8:47 PM AEST, BALATON Zoltan wrote:
> >> On Tue, 20 Jun 2023, Nicholas Piggin wrote:
> >>> On Fri Jun 16, 2023 at 9:03 AM AEST, BAL
adjustment to 0 at minimum.
Signed-off-by: Nicholas Piggin
---
softmmu/icount.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/softmmu/icount.c b/softmmu/icount.c
index 4504433e16..486ea7ef41 100644
--- a/softmmu/icount.c
+++ b/softmmu/icount.c
@@ -259,11 +259,16
an
rebase my patches on yours).
This is specifically to test checkstop due to machine check with
MSR[ME]=0 (other things can potentially case a checkstop). So
maybe rename it powerpc_mcheck_test_checkstop or something like
that?
Mechanically looks okay though, so other than the name,
Reviewed-
interest of having
somebody do some spring cleaning of this code I don't want to nitpick
it, so I won't :)
Acked-by: Nicholas Piggin
>
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc/cpu.h | 1 +
> target/ppc/excp_helper.c | 180 +++---
On Mon Jun 12, 2023 at 8:42 AM AEST, BALATON Zoltan wrote:
> Commit 7a3fe174b12d removed usage of POWERPC_SYSCALL_VECTORED, drop
> the unused define as well.
>
> Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
> ---
> target/ppc/translate.c | 1 -
> 1 fil
On Mon Jun 12, 2023 at 8:42 AM AEST, BALATON Zoltan wrote:
> Use the env_cpu function to get the CPUState for cpu_abort. These are
> only needed in case of fatal errors so this allows to avoid casting
> and storing CPUState in a local variable wnen not needed.
I don't entirely mind keeping cs
On Mon Jun 12, 2023 at 8:42 AM AEST, BALATON Zoltan wrote:
> Most exceptions are raised with nip pointing to the faulting
> instruction but the sc instruction generating a syscall exception
> leaves nip pointing to next instruction. Fix gen_sc to not use
> gen_exception_err() which sets nip back
On Mon Jun 12, 2023 at 8:42 AM AEST, BALATON Zoltan wrote:
> Signed-off-by: BALATON Zoltan
Acked-by: Nicholas Piggin
> ---
> target/ppc/excp_helper.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/exc
ave env already, but I don't mind much either way.
Acked-by: Nicholas Piggin
> ---
> target/ppc/excp_helper.c | 9 -
> 1 file changed, 4 insertions(+), 5 deletions(-)
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index 8298217e78..3783315fdb 100644
On Mon Jun 12, 2023 at 8:42 AM AEST, BALATON Zoltan wrote:
> After previous changes the hypercall handling in 7xx and 74xx
> exception handlers can be folded into one if statement to simpilfy
> this code.
>
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc/excp_helper.c | 26
On Tue Jun 13, 2023 at 11:33 PM AEST, Philippe Mathieu-Daudé wrote:
> Since we *might* have user emulation with softmmu,
> replace the system emulation check by !user emulation one.
>
> Signed-off-by: Philippe Mathieu-Daudé
> Reviewed-by: Richard Henderson
Reviewed-by:
On Tue Jun 13, 2023 at 11:33 PM AEST, Philippe Mathieu-Daudé wrote:
> Missing review: 1, 7, 8
>
> Since v2:
> - Rebased
> - Added R-b tags
> - Rework i386_tr_init_disas_context() patch (Richard)
> - Dropped RFC prefix
>
> This series aims to clarify the CONFIG_[USER|SYSTEM] vs CONFIG_SOFTMMU
>
On Tue Jun 6, 2023 at 11:59 PM AEST, Cédric Le Goater wrote:
> On 6/4/23 01:36, Nicholas Piggin wrote:
> > This adds support for chiptod and core timebase state machine models in
> > the powernv POWER9 and POWER10 models.
> >
> > This does not actually change the time o
On Tue Jun 6, 2023 at 12:57 AM AEST, Cédric Le Goater wrote:
> On 6/4/23 01:36, Nicholas Piggin wrote:
> > diff --git a/hw/ppc/pnv_chiptod.c b/hw/ppc/pnv_chiptod.c
> > new file mode 100644
> > index 00..04ef703e0f
> > --- /dev/null
> > +++ b/hw/ppc
, which should be good
enough for QEMU debugging.
Signed-off-by: Nicholas Piggin
---
Since v1:
- New patch that also uses checkstop function. Works with skiboot.
target/ppc/cpu.h | 2 ++
target/ppc/excp_helper.c | 28
target/ppc/helper.h | 2 ++
target
From: BALATON Zoltan
All powerpc exception handlers share some code when handling machine
check exceptions. Move this to a common function.
Reviewed-by: Nicholas Piggin
Signed-off-by: BALATON Zoltan
[np: adapted to make checkstop generally usable]
Signed-off-by-by: Nicholas Piggin
---
Since
ppc currently silently accepts invalid real address access. Catch
these and turn them into machine checks on POWER9/10 machines.
Signed-off-by: Nicholas Piggin
---
Since v1:
- Only implement this for POWER9/10. Seems like previous IBM processors
may not catch this after all, trying to get info
):
target/ppc: Move common check in machine check handlers to a function
Nicholas Piggin (3):
target/ppc: Machine check on invalid real address access on POWER9/10
target/ppc: Make checkstop actually stop the system
target/ppc: Implement attn instruction on BookS 64-bit processors
target/ppc
checkstop state does not halt the system, interrupts continue to be
serviced, and other CPUs run.
Stop the machine with vm_stop(), and print a register dump too.
Signed-off-by: Nicholas Piggin
---
Since v1:
- Fix loop exit so it stops on the attn instruction, rather than
after it.
target
On Sun Jun 25, 2023 at 5:26 AM AEST, Philippe Mathieu-Daudé wrote:
> The 'kvm_sw_tlb' and 'tlb_dirty' fields introduced in commit
> 93dd5e852c ("kvm: ppc: booke206: use MMU API") are specific
> to KVM and shouldn't be accessed when it is not available.
Reviewed-by: Nicholas
Apple sungem devices are expected to have WOL MMIO registers.
Add a region to prevent transaction failures, and implement the
WOL-disable CSR write because the Linux driver reset writes
this.
Signed-off-by: Nicholas Piggin
---
This fixes the failed MMIO error in the Linux sungem driver reset
On Wed Jun 21, 2023 at 12:26 AM AEST, BALATON Zoltan wrote:
> On Tue, 20 Jun 2023, Nicholas Piggin wrote:
> > powerpc ifetch endianness depends on MSR[LE] so it has to byteswap
> > after cpu_ldl_code(). This corrects DSISR bits in alignment
> > interrupts when running
see the HEAI when running
a nested guest, so that interrupt type can be returned to its KVM
caller.
Fixes: 7cebc5db2eba6 ("target/ppc: Introduce a vhyp framework for nested HV
support")
Signed-off-by: Nicholas Piggin
---
target/ppc/excp_helper.c | 7 +--
1 file changed, 5 insertions(+)
On Fri May 5, 2023 at 9:03 PM AEST, Harsh Prateek Bora wrote:
>
>
> On 5/3/23 06:09, Nicholas Piggin wrote:
> > Arguably this is just shuffling around register accesses, but one nice
> > thing it does is allow the exit to save away the L2 state then switch
> > the e
On Fri May 5, 2023 at 9:09 PM AEST, Harsh Prateek Bora wrote:
>
>
> On 5/3/23 06:09, Nicholas Piggin wrote:
> > Create spapr_nested.c for the nested HV implementation (modulo small
> > pieces in MMU and exception handling).
> >
> This separation of nested code in it
On Fri May 5, 2023 at 8:54 PM AEST, Harsh Prateek Bora wrote:
>
>
> On 5/3/23 06:09, Nicholas Piggin wrote:
> > @@ -1593,12 +1713,14 @@ static target_ulong h_enter_nested(PowerPCCPU *cpu,
> > return H_PARAMETER;
> > }
> >
> > -s
On Sat Apr 29, 2023 at 12:30 AM AEST, Fabiano Rosas wrote:
> Vaibhav Jain writes:
>
> > Hi Fabiano,
> >
> > Thanks for looking into this patch and apologies for the delayed reponse.
> > Fabiano Rosas writes:
> >
> >> Narayana Murty N writes:
> >>
> >>> On PPC64 the HILE(Hypervisor Interrupt
On Tue May 9, 2023 at 7:51 PM AEST, Harsh Prateek Bora wrote:
> On Thu, Mar 23, 2023 at 12:22:37PM +1000, Nicholas Piggin wrote:
> > The hypervisor emulation assistance interrupt modifies HEIR to
> > contain the value of the instruction which caused the exception.
> >
> &
The CTRL register is able to write bit zero, and that is reflected in a
bit field in the register that reflects the state of all threads in the
core.
TCG does not implement SMT, so this just requires mirroring that bit into
the first bit of the thread state field.
Signed-off-by: Nicholas Piggin
by the Alignment interrupt.
Reviewed-by: Fabiano Rosas
Signed-off-by: Nicholas Piggin
---
Since v2: no change.
target/ppc/excp_helper.c | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index bc2be4a726
.
This will allow more information to be passed to the exception
handler in the next patch.
Signed-off-by: Nicholas Piggin
---
Since v2: new patch to deal with bug in patch 6.
target/ppc/mmu-radix64.c | 24
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/target
A store to MMCR0 with PMCjCE=1 fails to update hflags correctly and
results in hflags mismatch:
qemu: fatal: TCG hflags mismatch (current:0x2408003d rebuilt:0x240a003d)
This can be reproduced by running perf on a recent machine.
Signed-off-by: Nicholas Piggin
---
Since v2: new patch
from a load or store instruction (in that case the prefix
bit should be provided).
Reviewed-by: Fabiano Rosas
Signed-off-by: Nicholas Piggin
---
Since v2:
- Fix a bug where ifetch access causing HDSI due to process scoped table
access failing on partition scope translation would go into infinite
System call interrupts in ISA v3.1 CPUs add a LEV indication in SRR1
that corresponds with the LEV field of the instruction that caused the
interrupt.
Signed-off-by: Nicholas Piggin
---
Since v2: new patch.
target/ppc/excp_helper.c | 4
1 file changed, 4 insertions(+)
diff --git a/target
On Mon May 15, 2023 at 8:14 PM AEST, Harsh Prateek Bora wrote:
>
>
> On 5/15/23 14:56, Nicholas Piggin wrote:
> > Some 32-bit SPRs are incorrectly implemented as 64-bits on 64-bit
> > targets.
> >
> > This changes VRSAVE, DSISR, HDSISR, DAWRX0, PIDR, LPIDR, DEX
to implement finer details of SPR implementation (e.g.,
not all bits implemented as simple read/write storage).
Signed-off-by: Nicholas Piggin
---
Since v2: no change.
target/ppc/cpu_init.c| 18 +-
target/ppc/helper_regs.c | 2 +-
target/ppc/misc_helper.c | 4 ++--
target/ppc
The hypervisor emulation assistance interrupt modifies HEIR to
contain the value of the instruction which caused the exception.
Signed-off-by: Nicholas Piggin
---
Since v2:
- Fix ordering of prefix/suffix words in the register, as pointed
out by Mikey.
target/ppc/cpu.h | 1 +
target
powerpc ifetch endianness depends on MSR[LE] so it has to byteswap
after cpu_ldl_code(). This corrects DSISR bits in alignment
interrupts when running in little endian mode.
Reviewed-by: Fabiano Rosas
Signed-off-by: Nicholas Piggin
---
Since v2: no change.
target/ppc/excp_helper.c | 20
Hopefully these are getting close to ready now. There is still the
question about doing better with adding test cases for all this, I
haven't exactly got a good answer yet but I do have kvm-unit-tests
for most at least.
Thanks,
Nick
Nicholas Piggin (9):
target/ppc: Fix width of some 32-bit
On Mon May 15, 2023 at 7:32 PM AEST, Harsh Prateek Bora wrote:
>
>
> On 5/15/23 14:02, Harsh Prateek Bora wrote:
> >>
> >> That would be wrong for the other HSRR fallthroughs above it.
> >>
> > Oh yeh, in that case, may be move it to top of the EXCP_HISI, it would
> > need duplicating one line of
On Mon May 15, 2023 at 10:03 PM AEST, Mark Cave-Ayland wrote:
> On 15/05/2023 10:26, Nicholas Piggin wrote:
>
> > Some 32-bit SPRs are incorrectly implemented as 64-bits on 64-bit
> > targets.
> >
> > This changes VRSAVE, DSISR, HDSISR, DAWRX0, PIDR, LPIDR, DEXCR,
t.
These processors are not widely available, and it's difficult to deal
with all these quirks in qemu +/- KVM, so create a POWER9 DD2.2 CPU
and make it the default POWER9 CPU.
Signed-off-by: Nicholas Piggin
---
This is unchanged since v3, just reposting.
Thanks,
Nick
hw/ppc/pnv.c
a cap to advertise support for AIL-3.
Reviewed-by: David Gibson
Signed-off-by: Nicholas Piggin
---
Since v3:
- Integrated the KVM cap test into this patch since it is in Linux now.
- Removed the KVM fallback heuristic that detects whether AIL-3 might be
supported if the KVM cap could be missing
care
about SMT mode in the target), but for consistency all PVRs should use
the same chip type. We'll go with the SMT4 OpenPOWER type.
Signed-off-by: Nicholas Piggin
---
This is a replacement for
https://lists.gnu.org/archive/html/qemu-ppc/2022-03/msg00227.html
But the chip type is changed to 1 i
On Mon May 15, 2023 at 10:03 PM AEST, Mark Cave-Ayland wrote:
> On 15/05/2023 10:26, Nicholas Piggin wrote:
>
> > Some 32-bit SPRs are incorrectly implemented as 64-bits on 64-bit
> > targets.
> >
> > This changes VRSAVE, DSISR, HDSISR, DAWRX0, PIDR, LPIDR, DEXCR,
On Tue May 16, 2023 at 11:54 AM AEST, Narayana Murty N wrote:
>
> On 5/15/23 12:02, Nicholas Piggin wrote:
> > On Sat Apr 29, 2023 at 12:30 AM AEST, Fabiano Rosas wrote:
> >>>> Could you describe in more detail what is your setup? Specifically
> >>>>
On Tue May 16, 2023 at 5:56 PM AEST, Frederic Barrat wrote:
>
>
> On 15/05/2023 18:02, Nicholas Piggin wrote:
> > POWER9 DD2.1 and earlier had significant limitations when running KVM,
> > including lack of "mixed mode" MMU support (ability to run HPT and RPT
>
On Tue May 16, 2023 at 6:44 PM AEST, Cédric Le Goater wrote:
> On 5/15/23 18:02, Nicholas Piggin wrote:
> > POWER9 DD2.1 and earlier had significant limitations when running KVM,
> > including lack of "mixed mode" MMU support (ability to run HPT and RPT
> > m
On Tue May 16, 2023 at 7:32 PM AEST, Daniel Henrique Barboza wrote:
>
>
> On 5/15/23 06:26, Nicholas Piggin wrote:
> > A store to MMCR0 with PMCjCE=1 fails to update hflags correctly and
> > results in hflags mismatch:
> >
> >qemu: fatal: TCG hflags mis
On Tue May 16, 2023 at 5:02 PM AEST, Mark Cave-Ayland wrote:
> On 15/05/2023 16:19, Nicholas Piggin wrote:
>
> > On Mon May 15, 2023 at 10:03 PM AEST, Mark Cave-Ayland wrote:
> >> On 15/05/2023 10:26, Nicholas Piggin wrote:
> >>
> >>> Some 32-bit SPRs ar
On Tue May 16, 2023 at 6:43 PM AEST, Harsh Prateek Bora wrote:
>
>
> On 5/15/23 21:31, Nicholas Piggin wrote:
> > QEMU's PVR value for POWER9 DD2.0 has chip type 1, which is the SMT4
> > "small core" type that OpenPOWER processors use. QEMU's PVR for all
>
On Tue May 16, 2023 at 6:44 PM AEST, Cédric Le Goater wrote:
> On 5/15/23 18:01, Nicholas Piggin wrote:
> > QEMU's PVR value for POWER9 DD2.0 has chip type 1, which is the SMT4
> > "small core" type that OpenPOWER processors use. QEMU's PVR for all
> > other PO
On Tue May 16, 2023 at 5:58 PM AEST, Frederic Barrat wrote:
>
>
> On 15/05/2023 18:02, Nicholas Piggin wrote:
> > POWER9 DD2.1 and earlier had significant limitations when running KVM,
> > including lack of "mixed mode" MMU support (ability to run HPT and RPT
>
On Tue May 16, 2023 at 7:23 PM AEST, Harsh Prateek Bora wrote:
>
>
> On 5/15/23 21:32, Nicholas Piggin wrote:
> > POWER9 DD2.1 and earlier had significant limitations when running KVM,
> > including lack of "mixed mode" MMU support (ability to run HPT and RPT
>
of
recent snapshots.
Arguably this should be done by the debugger or a program that talks to
QMP, but for setting up simple scenarios and tests, it is convenient to
have this feature.
Signed-off-by: Nicholas Piggin
---
docs/system/replay.rst | 5
include/sysemu/replay.h | 11
qemu
When replaying a trace, it is possible to go from shutdown to
running with a reverse-debugging step. This can be useful if the
problem being debugged triggers a reset or shutdown.
Signed-off-by: Nicholas Piggin
---
include/sysemu/runstate.h | 1 +
replay/replay.c | 2 ++
softmmu
This thing seems to have fallen by the wayside. This gets it working with
the current format, although does not quite implement all events.
Signed-off-by: Nicholas Piggin
---
My python skills are not good. Any help on this or patch 2 is
appreciated.
Thanks,
Nick
scripts/replay-dump.py | 107
Hi,
These are a few small things I have found helpful while trying to
implement and test rr changes. Patch 2 depends on 1, but otherwise
the patches are independent.
Thanks,
Nick
Nicholas Piggin (4):
scripts/replay_dump.sh: Update to current rr record format
tests/avocado: replay_linux.py
This runs replay-dump.py after recording a trace, and fails the test if
the script fails.
replay-dump.py is modified to exit with non-zero if an error is
encountered while parsing.
Signed-off-by: Nicholas Piggin
---
It's possible this could introduce failures to existing test
On Fri Jan 19, 2024 at 10:23 AM AEST, David Gibson wrote:
> On Fri, Jan 19, 2024 at 12:09:36AM +1000, Nicholas Piggin wrote:
> > SAO is a page table attribute that strengthens the memory ordering of
> > accesses. QEMU with MTTCG does not implement this, so clear it in
>
On Fri Jan 19, 2024 at 6:58 PM AEST, Cédric Le Goater wrote:
> Hello Nick,
>
> On 1/18/24 16:06, Nicholas Piggin wrote:
> > This is mostly TCG core emulation improvements and fixes. I
> > got the chiptod model in there because it's intertwined with
> > TFMR SPR.
>
On Fri Jan 19, 2024 at 8:09 AM AEST, Richard Henderson wrote:
> On 1/19/24 02:25, Nicholas Piggin wrote:
> > +/* attn enable check
> > */
> > +static inline int check_attn_none(CPUPPCState *env)
>
> Don't mark
-by: Nicholas Piggin
---
tests/avocado/boot_linux_console.py | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/tests/avocado/boot_linux_console.py
b/tests/avocado/boot_linux_console.py
index 3f0180e1f8..922a9e7b79 100644
--- a/tests/avocado/boot_linux_console.py
+++ b/tests/avocado
the tets harness to avoid it.
Thanks,
Nick
On Thu Jan 18, 2024 at 12:12 AM AEST, Nicholas Piggin wrote:
> Add test for POWER10.
>
> Reviewed-by: Cédric Le Goater
> Signed-off-by: Nicholas Piggin
> ---
> tests/avocado/boot_linux_console.py | 8
> 1 file changed, 8 i
On Tue Sep 26, 2023 at 3:43 AM AEST, Glenn Miles wrote:
> This commit continues adding support for the Branch History
> Rolling Buffer (BHRB) as is provided starting with the P8
> processor and continuing with its successors. This commit
> is limited to the recording and filtering of taken
Calculate the BHRB base from arithmetic on the tcg_env target ptr.
Signed-off-by: Nicholas Piggin
---
Hi Glenn,
I think I have to squash this into the BHRB series. 32-bit host
compile shows up a size mismatch warning... I think it's not quite
right to be using host pointer directly in target
sh Prateek Bora
Signed-off-by: Nicholas Piggin
---
target/ppc/translate/vsx-impl.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/translate/vsx-impl.c.inc
b/target/ppc/translate/vsx-impl.c.inc
index 6db87ab336..0266f09119 100644
--- a/target/ppc/translate/vsx-
On Fri Feb 16, 2024 at 5:42 AM AEST, Richard Henderson wrote:
> On 2/15/24 07:15, Nicholas Piggin wrote:
> > diff --git a/target/ppc/machine.c b/target/ppc/machine.c
> > index 731dd8df35..3541cd83cd 100644
> > --- a/target/ppc/machine.c
> > +++ b/target/ppc/machine.c
>
On Tue Feb 20, 2024 at 12:49 AM AEST, BALATON Zoltan wrote:
> On Mon, 19 Feb 2024, Nicholas Piggin wrote:
> > FreeBSD project provides qcow2 images that work well for testing QEMU.
> > Add pseries tests for HPT and Radix, KVM and TCG. This uses a short
> > term VM image
On Tue Feb 20, 2024 at 12:10 AM AEST, Thomas Huth wrote:
> On 19/02/2024 07.17, Nicholas Piggin wrote:
> > The fastpath in cpu_physical_memory_sync_dirty_bitmap() to test large
> > aligned ranges forgot to bring the TCG TLB up to date after clearing
> > some of the dir
On Tue Feb 20, 2024 at 3:06 AM AEST, Peter Maydell wrote:
> On Mon, 19 Feb 2024 at 08:31, Nicholas Piggin wrote:
> >
> > The following changes since commit da96ad4a6a2ef26c83b15fa95e7fceef5147269c:
> >
> > Merge tag 'hw-misc-20240215' of https://github.com/philmd/qemu
On Fri Feb 16, 2024 at 3:50 AM AEST, Peter Maydell wrote:
> On Thu, 15 Feb 2024 at 17:16, Nicholas Piggin wrote:
> >
> > Calculate the BHRB base from arithmetic on the tcg_env target ptr.
> >
> > Signed-off-by: Nicholas Piggin
> > ---
> > Hi
at the moment is creating a test case for it that does not require
subsequent patches!)
Thanks,
Nick
Nicholas Piggin (3):
accel/tcg: Fix TCG TLB coherency race with physical dirty bit clearing
tcg: add a ll/sc protection facility
target/ppc: Implement reservation protection for larx/stcx
Use the generic llsc protection feature to implement real reservation
protection for larx/stcx.
This is more complicated and quite a bit slower than the cmpxchg
pseudo-reservation, so it's questionable whether it should be merged
or ever made the default.
It could possibly be sped up more by
that TLB are performed without the notdirty_write() call to
set dirty bits (or invalidate tb).
Fix this by checking the physical dirty bitmap while holding the TLB
lock that also covers TLB entry insertion / TLB_NOTDIRTY clearing.
Signed-off-by: Nicholas Piggin
---
Hi Thomas,
This is the other dirty
This uses the cpu physical memory dirty mechanism to provide a LL/SC
protection system, so that a CPU can set llsc protection on a block of
memory, and it can check whether any other CPUs have stored to that
memory in a way that can be done race-free to perform a store
conditional on that check.
On Tue Feb 20, 2024 at 12:10 AM AEST, Thomas Huth wrote:
> On 19/02/2024 07.17, Nicholas Piggin wrote:
> > The fastpath in cpu_physical_memory_sync_dirty_bitmap() to test large
> > aligned ranges forgot to bring the TCG TLB up to date after clearing
> > some of the dir
ok for a one stop solution.
>
> Co-authored-by: Bernhard Beschow
> Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
> ---
> v2:
> Move top level title one level up so subsections will be below it in TOC
>
> MAINTAINERS | 1 +
lly.
>
> Signed-off-by: Saif Abrar
Reviewed-by: Nicholas Piggin
I had a minor comment but NBD for now.
Thanks,
Nick
/ lost updates during migration from a TCG host.
Fix this by exporting an abstracted function to call when dirty bits
have been cleared.
Fixes: aa8dc044772 ("migration: synchronize memory bitmap 64bits at a time")
Signed-off-by: Nicholas Piggin
---
I reproduced this with a kvm-
Cédric Le Goater
Tested-by: Cédric Le Goater
Signed-off-by: Peter Maydell
Signed-off-by: Nicholas Piggin
--
2.42.0
From: Glenn Miles
Create a new powernv machine type, powernv10-rainier, that
will contain rainier-specific devices.
Reviewed-by: Cédric Le Goater
Signed-off-by: Glenn Miles
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv.c | 24 ++--
1 file changed, 22 insertions(+), 2
From: Philippe Mathieu-Daudé
To reduce the use of the term 'softmmu', rename spapr_softmmu.c
to spapr_vhyp_mmu.c.
Reviewed-by: Nicholas Piggin
Signed-off-by: Philippe Mathieu-Daudé
[np: change name]
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Nicholas Piggin
---
hw/ppc/meson.build
-by: Cedric Le Goater
Reviewed-by: Cédric Le Goater
Signed-off-by: Harsh Prateek Bora
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr_irq.c | 6 --
include/hw/ppc/spapr_irq.h | 14 +-
2 files changed, 17 insertions(+), 3 deletions(-)
diff --git a/hw/ppc/spapr_irq.c b/hw/ppc
Signed-off-by: Glenn Miles
Signed-off-by: Nicholas Piggin
---
hw/ppc/Kconfig | 1 +
hw/ppc/pnv.c | 25 +
include/hw/ppc/pnv.h | 1 +
3 files changed, 27 insertions(+)
diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig
index 44263a58c4..8e592e4307 100644
--- a/hw
model where chiplet control registers are implemented.
This commit also implement the read/write method for the powerbus scom
registers
Signed-off-by: Chalapathi V
Signed-off-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
hw/ppc/meson.build | 1 +
hw/ppc/pnv_n1_chiplet.c
Reviewed-by: Cédric Le Goater
Signed-off-by: Glenn Miles
Signed-off-by: Nicholas Piggin
---
hw/misc/Kconfig | 4
hw/misc/meson.build | 1 +
hw/ppc/Kconfig | 1 +
hw/ppc/pnv.c| 6 ++
4 files changed, 12 insertions(+)
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
index
hypervisor interface, called vhyp.
Reviewed-by: Nicholas Piggin
Signed-off-by: Philippe Mathieu-Daudé
[npiggin: Pick a different name, explain it in changelog.]
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr_hcall.c | 4 ++--
hw/ppc/spapr_softmmu.c | 4
t@host build]#
Reviewed-by: Cédric Le Goater
Signed-off-by: Harsh Prateek Bora
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 0d72d286d8..0028ce0b67 100644
--- a/hw/ppc/spapr.c
-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_helper.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index 949ae87f4f..68632bf54e 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -808,13 +808,6
Rather than tlbwe_lo always flushing all TCG TLBs, have it flush just
those corresponding to the old software TLB, and only if it was valid.
Tested-by: BALATON Zoltan
Acked-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_helper.c | 10 --
1 file changed, 8
sh Prateek Bora
Signed-off-by: Nicholas Piggin
---
target/ppc/translate/vsx-impl.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/translate/vsx-impl.c.inc
b/target/ppc/translate/vsx-impl.c.inc
index 6db87ab336..0266f09119 100644
--- a/target/ppc/translate/vsx-
POWER10 is the latest IBM Power machine. Although it is not offered in
"OPAL mode" (i.e., powernv configuration), so there is a case that it
should remain at powernv9, most of the development work is going into
powernv10 at the moment.
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicho
ead TBL on 32-bit.
Change SPR 268 to be called TB on 64-bit implementations.
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
target/ppc/helper_regs.c | 4
target/ppc/ppc-qmp-cmds.c | 4
2 files changed, 8 insertions(+)
diff --git a/target/ppc/helper_regs.c b/target/
Wire the ChipTOD model to powernv9 and powernv10 machines.
Suggested-by-by: Cédric Le Goater
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv.c | 30 ++
include/hw/ppc/pnv_chip.h | 3 +++
2 files changed, 33 insertions
Flushing the TCG TLB pages that cache a software TLB is a common
operation, factor it into its own function.
Tested-by: BALATON Zoltan
Acked-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_helper.c | 24 +---
1 file changed, 13 insertions(+), 11
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