From: Alistair Francis
When the Hypervisor extension is in use we only enable floating point
support when both status and vsstatus have enabled floating point
support.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_helper.c | 3
From: Alistair Francis
Mark both sstatus and vsstatus as dirty (3).
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/translate.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/target/riscv/translate.c b/target
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_helper.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 9e28b19c29..d3b764e694
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_helper.c | 24 ++--
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h| 1 +
target/riscv/cpu_helper.c | 193 ++
2 files changed, 175 insertions(+), 19 deletions(-)
diff --git a
From: Alistair Francis
The hret instruction does not exist in the new spec versions, so remove
it from QEMU.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32.decode | 1 -
target/riscv/insn_trans
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 5 +
target/riscv/cpu.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b27066f6a7..c47d10b739
iewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/translate.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 3ce86adb89..b51ab92068 100644
--- a/target/riscv/translate.c
+++ b/t
ntroller: PCI device 8086:100e
...
BAR1: I/O at 0x [0x003e].
...
It turns out we should set pci_allow_0_address to true to allow 0
PCI address, otherwise pci_bar_address() treats such address as
PCI_BAR_UNMAPPED.
Signed-off-by: Bin Meng
Reviewed-by: Palmer Dabbelt
S
From: Anup Patel
This patch extends CLINT emulation to provide rdtime callback for
TCG. This rdtime callback will be called wheneven TIME CSRs are
read in privileged modes.
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_clint.c
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c| 3 +++
target/riscv/cpu.h| 10 ++
target/riscv/cpu_bits.h | 3 +++
target/riscv/cpu_helper.c | 17 +
target
From: Alistair Francis
Add a helper macro MSTATUS_MPV_ISSET() which will determine if the
MSTATUS_MPV bit is set for both 32-bit and 64-bit RISC-V.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_bits.h | 11
rdtime callback is not
available then the monitor (i.e. OpenSBI) will trap-n-emulate
TIME CSRs in software.
We see 25+% performance improvement in hackbench numbers when
TIME CSRs are not trap-n-emulated.
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
t;, us->serial);
object_property_set_bool(OBJECT(&s->otp), true, "realized", &err);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base);
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 82667b5..7cf742e 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -59,6 +59,7 @@ typedef struct SiFiveUState {
int fdt_size;
bool start_in_flash;
+uint32_t serial;
} SiFiveUState;
enum {
Reviewed-by: Palmer Dabbelt
Thanks. This is in the queue for the soft freeze.
THis would almost certainly cause the exception names to be reported
incorrectly. Covarity found the issue (CID 1420223). As per Peter's
suggestion, I've also added a comma at the end of the list to avoid the issue
reappearing in the future.
Signed-off-by: Palmer Dabbelt
---
ta
On Thu, 05 Mar 2020 08:44:20 PST (-0800), Peter Maydell wrote:
On Tue, 3 Mar 2020 at 00:49, Palmer Dabbelt wrote:
From: Alistair Francis
The v0.5 Hypervisor spec add new execption numbers, let's add support
for those.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signe
support for the new execption numbers")
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index c47d10b739..c0b7023100 100644
--- a/targ
fixes a bug found by Coverity.
------------
Palmer Dabbelt (1):
RISC-V: Add a missing "," in riscv_excp_names
target/riscv/cpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
On Thu, 05 Mar 2020 09:20:31 PST (-0800), phi...@redhat.com wrote:
Cc'ing qemu-trivial@ in case there is a pending PR in progress, it
might get merged quicker.
On Thu, Mar 5, 2020 at 6:19 PM Philippe Mathieu-Daudé wrote:
On 3/5/20 5:48 PM, Palmer Dabbelt wrote:
> THis would almost c
rrent privledge level.
This patch fixes the issue raised in the bug by raising an illegal
instruction if TSR is set and we are in S-Mode.
Signed-off-by: Alistair Francis
@Palmer Dabbelt Ping!
Sorry, I must have missed this. It's in the queue (with the reviews as
collected by patchwork
On Mon, 24 Feb 2020 05:39:44 PST (-0800), bmeng...@gmail.com wrote:
Add two GitLab jobs to build the OpenSBI firmware binaries.
The first job builds a Docker image with the packages requisite
to build OpenSBI, and stores this image in the GitLab registry.
The second job pulls the image from the
On Mon, 24 Feb 2020 05:39:40 PST (-0800), bmeng...@gmail.com wrote:
This series advances the roms/opensbi submodule to the v0.6 release,
and builds and captures platform firmware binaries from that release.
A 32-bit sifive_u bios image has also been added, so that we can have
32-bit test covera
On Wed, 26 Feb 2020 09:55:34 PST (-0800), alistai...@gmail.com wrote:
On Wed, Feb 26, 2020 at 12:54 AM Rajnesh Kanwal
wrote:
Here is the link to the patch
https://lists.nongnu.org/archive/html/qemu-riscv/2020-01/msg00191.html
Ah, it doesn't look like it made it to the QEMU-devel list. Can yo
On Wed, 10 Jun 2020 15:13:49 PDT (-0700), alistai...@gmail.com wrote:
On Thu, May 28, 2020 at 11:13 AM Alistair Francis wrote:
On Thu, May 21, 2020 at 8:57 AM Alistair Francis wrote:
>
> On Wed, May 20, 2020 at 4:08 PM Palmer Dabbelt wrote:
> >
> > On Thu, 14 May 2020 1
On Thu, 18 Jun 2020 16:18:20 PDT (-0700), alistai...@gmail.com wrote:
On Thu, Jun 18, 2020 at 3:42 PM Palmer Dabbelt wrote:
On Wed, 10 Jun 2020 15:13:49 PDT (-0700), alistai...@gmail.com wrote:
> On Thu, May 28, 2020 at 11:13 AM Alistair Francis
wrote:
>>
>> On Thu, May 21,
On Thu, 09 Jul 2020 15:09:18 PDT (-0700), alistai...@gmail.com wrote:
On Thu, Jul 9, 2020 at 3:07 AM Bin Meng wrote:
From: Bin Meng
The reset vector codes are subject to change, e.g.: with recent
fw_dynamic type image support, it breaks oreboot again.
This is a recurring problem, I have an
On Wed, 22 Jul 2020 02:15:24 PDT (-0700), frank.ch...@sifive.com wrote:
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/cpu.c | 24 ++--
target/riscv/cpu.h | 2 --
2 files changed, 6 insertions(+), 20 deletions(-)
diff --git a/target/riscv/cpu.c b/target/ri
On Tue, 24 Sep 2019 11:29:25 PDT (-0700), alistai...@gmail.com wrote:
On Mon, Jun 24, 2019 at 11:21 AM Joel Sing wrote:
On 19-06-17 16:52:44, Richard Henderson wrote:
> On 6/16/19 12:19 PM, Joel Sing wrote:
> > +/*
> > + * Clear the load reservation, since an SC must fail if there is
>
riscv_cpu_set_virt_enabled(env, prev_virt);
+}
return retpc;
}
Reviewed-by: Palmer Dabbelt
);
+return true;
+/* } */
+}
+#endif
+return false;
+}
Reviewed-by: Palmer Dabbelt
riscv_cpu_fp_enabled(CPURISCVState *env)
{
if (*env->mstatus & MSTATUS_FS) {
+if (riscv_cpu_virt_enabled(env) && !(env->vsstatus & MSTATUS_FS)) {
+return false;
+}
return true;
}
Reviewed-by: Palmer Dabbelt
G_USER_ONLY)
+ctx->virt_enabled = riscv_cpu_virt_enabled(env);
+#else
+ctx->virt_enabled = false;
+#endif
ctx->misa = env->misa;
ctx->frm = -1; /* unknown rounding mode */
ctx->ext_ifencei = cpu->cfg.ext_ifencei;
Reviewed-by: Palmer Dabbelt
On Fri, 23 Aug 2019 16:38:44 PDT (-0700), Alistair Francis wrote:
Respect the contents of MSTATUS.MPRV and HSTATUS.SPRV when performing
floating point operations when V=0.
I'm confused as to what this has to do with floating point.
Signed-off-by: Alistair Francis
---
target/riscv/translate
Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/op_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 331cc36232..e87c9115bc 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -93,7
From: ShihPo Hung
remove the check becuase SD bit should summarize FS and XS fields
unconditionally.
Signed-off-by: ShihPo Hung
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 3 +--
target/riscv/translate.c | 2
The following changes since commit 28b58f19d269633b3d14b6aebf1e92b3cd3ab56e:
ui/gtk: Get display refresh rate with GDK version 3.22 or later (2020-01-16
14:03:45 +)
are available in the Git repository at:
g...@github.com:palmer-dabbelt/qemu.git tags/riscv-for-master-5.0-sf1
for you to
From: Pan Nengyuan
Fix a minor memory leak in riscv_sifive_u_soc_realize()
Reported-by: Euler Robot
Signed-off-by: Pan Nengyuan
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 1 +
1 file changed, 1 insertion
ard Henderson
Signed-off-by: ShihPo Hung
Reviewed-by: Richard Henderson
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index e59343e13c..de0a8d893a 100644
--- a/target/riscv/cpu.h
++
From: ShihPo Hung
Signed-off-by: ShihPo Hung
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn_trans/trans_rvd.inc.c | 1 -
target/riscv/insn_trans/trans_rvf.inc.c | 1 -
2 files changed, 2 deletions(-)
diff --git a/target
On Thu, 23 Jan 2020 06:38:07 PST (-0800), Peter Maydell wrote:
On Tue, 21 Jan 2020 at 23:41, Palmer Dabbelt wrote:
The following changes since commit 28b58f19d269633b3d14b6aebf1e92b3cd3ab56e:
ui/gtk: Get display refresh rate with GDK version 3.22 or later (2020-01-16
14:03:45 +)
are
= vd, *a = va, *b = vb;
+d[i] = ssubu8(env, 0, a[i], b[i]);
+}
+
+RVPR(uksub8, 1, 1);
--
2.17.1
The naming on some of these helpers is a bit odd, but given that they're
a mix of the V and P extensions it's probably fine to just leave them
as-is.
Reviewed-by: Palmer Dabbelt
*d = vd, *a = va;
+int32_t shift = sextract32((*(uint32_t *)vb), 0, 4);
+
+if (shift >= 0) {
+do_ksll8(env, vd, va, vb, i);
+} else {
+shift = -shift;
+shift = (shift == 8) ? 7 : shift;
+ d[i] = vssra8(env, 0, a[i], shift);
+}
+}
+
+RVPR(kslra8_u, 1, 1);
Reviewed-by: Palmer Dabbelt
On Fri, 12 Feb 2021 07:02:26 PST (-0800), zhiwei_...@c-sky.com wrote:
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 6
target/riscv/insn32.decode | 6
target/riscv/insn_trans/trans_rvp.c.inc | 7
target/riscv/packed_helper.c|
On Tue, 25 May 2021 22:30:14 PDT (-0700), Palmer Dabbelt wrote:
On Fri, 12 Feb 2021 07:02:26 PST (-0800), zhiwei_...@c-sky.com wrote:
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 6
target/riscv/insn32.decode | 6
target/riscv/insn_trans
On Tue, 25 May 2021 22:43:27 PDT (-0700), zhiwei_...@c-sky.com wrote:
On 5/24/21 9:00 AM, Palmer Dabbelt wrote:
On Mon, 15 Mar 2021 14:22:58 PDT (-0700), alistai...@gmail.com wrote:
On Fri, Feb 12, 2021 at 10:14 AM LIU Zhiwei
wrote:
Signed-off-by: LIU Zhiwei
Acked-by: Alistair Francis
t;, rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 },
{ "lui", rv_codec_u, rv_fmt_rd_imm, NULL, 0, 0, 0 },
{ "auipc", rv_codec_u, rv_fmt_rd_offset, NULL, 0, 0, 0 },
Reviewed-by: Palmer Dabbelt (RISC-V)
Thanks!
,
+ firmware_load_addr, ram_size, NULL);
+
+if (firmware_size > 0) {
+return firmware_load_addr + firmware_size;
}
error_report("could not load firmware '%s'", firmware_filename);
Reviewed-by: Palmer Dabbelt
emory layout agreements that weren't even in specs (or event
meant to be in specs) that have stuck around for quite a while.
Reviewed-by: Palmer Dabbelt
_DEVICE(&s->e_cpus), &error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort);
/*
@@ -792,6 +799,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error
**errp)
static Property sifive_u_soc_props[] = {
DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL),
+DEFINE_PROP_STRING("cpu-type", SiFiveUSoCState, cpu_type),
DEFINE_PROP_END_OF_LIST()
};
Reviewed-by: Palmer Dabbelt
ad_firmware(MachineState *machine,
const char *default_machine_firmware,
hwaddr firmware_load_addr,
Reviewed-by: Palmer Dabbelt
can get a complete list by running
``qemu-system-riscv64 --machine help``, or
``qemu-system-riscv32 --machine help``.
+..
+ This table of contents should be kept sorted alphabetically
+ by the title text of each file, which isn't the same ordering
+ as an alphabetical sort by filename.
+
+..
C-V machines:
diff --git a/MAINTAINERS b/MAINTAINERS
index 8d8b0bf966..c347d49bd2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1359,6 +1359,15 @@ F: include/hw/misc/mchp_pfsoc_dmc.h
F: include/hw/misc/mchp_pfsoc_ioscb.h
F: include/hw/misc/mchp_pfsoc_sysreg.h
+SiFive Machines
+M: Alistair Francis
8b0bf966..c347d49bd2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1359,6 +1359,15 @@ F: include/hw/misc/mchp_pfsoc_dmc.h
F: include/hw/misc/mchp_pfsoc_ioscb.h
F: include/hw/misc/mchp_pfsoc_sysreg.h
+SiFive Machines
+M: Alistair Francis
+M: Bin Meng
+M: Palmer Dabbelt
+L: qemu-ri...@nongnu.org
that I was hoping to have some time to sort out :). I just
gave it a quick look, but
Reviewed-by: Palmer Dabbelt
Acked-by: Palmer Dabbelt
as it certainly seems better than before.
On Thu, 17 Dec 2020 05:58:11 PST (-0800), richard.hender...@linaro.org wrote:
On 12/17/20 12:44 AM, Bin Meng wrote:
What happens if something like ARM big.LITTLE needs to be supported on RISC-V?
I'd say it's the board's job to pass the boot heart.
(Though even big.LITTLE doesn't mix 64 and 32-
On Thu, 17 Dec 2020 13:48:26 PST (-0800), Atish Patra wrote:
Currently, we place the DTB at 2MB from 4GB or end of DRAM which ever is
lesser. However, Linux kernel can address only 1GB of memory for RV32.
Thus, it can not map anything beyond 3GB (assuming 2GB is the starting address).
As a result
On Thu, 17 Dec 2020 14:35:10 PST (-0800), Atish Patra wrote:
On Thu, 2020-12-17 at 14:31 -0800, Palmer Dabbelt wrote:
On Thu, 17 Dec 2020 13:48:26 PST (-0800), Atish Patra wrote:
> Currently, we place the DTB at 2MB from 4GB or end of DRAM which
> ever is
> lesser. However, Linux k
On Thu, 14 Jan 2021 01:49:40 PST (-0800), bmeng...@gmail.com wrote:
On Thu, Jan 14, 2021 at 8:09 AM Alistair Francis wrote:
On Fri, Nov 6, 2020 at 2:36 AM Alex Bennée wrote:
>
>
> Palmer Dabbelt writes:
>
> > On Thu, 22 Oct 2020 17:56:38 PDT (-0700), alistai...@gmail.com
#define MSTATUS_MPP 0x1800
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index 14a5c62dac..88ab850682 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -26,6 +26,7 @@ riscv_ss.add(files(
riscv_softmmu_ss = ss.source_set()
riscv_softmmu_ss.add(files(
+ 'arch_dump.c',
'pmp.c',
'monitor.c',
'machine.c'
Reviewed-by: Palmer Dabbelt
Has anyone tested this with GDB?
Thanks!
e reset vector */
-riscv_setup_rom_reset_vec(machine, s->soc[0], start_addr,
+ riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr,
virt_memmap[VIRT_MROM].base,
virt_memmap[VIRT_MROM].size, kernel_entry,
fdt_load_addr, s->fdt);
Reviewed-by: Palmer Dabbelt
On Mon, 17 Jun 2019 15:38:45 PDT (-0700), richard.hender...@linaro.org wrote:
On 6/14/19 10:11 AM, Alex Bennée wrote:
+++ b/target/riscv/translate.c
@@ -793,7 +793,7 @@ static void riscv_tr_translate_insn(DisasContextBase
*dcbase, CPUState *cpu)
DisasContext *ctx = container_of(dcbase, Dis
On Mon, 17 Jun 2019 18:31:00 PDT (-0700), Alistair Francis wrote:
Based-on:
Now that the RISC-V spec has started to be ratified let's update our
QEMU implementation. There are a few things going on here:
- Add priv version 1.11.0 to QEMU
- This is the ratified version of the Privledge spec
On Wed, 19 Jun 2019 07:19:38 PDT (-0700), alistai...@gmail.com wrote:
On Wed, Jun 19, 2019 at 3:58 AM Palmer Dabbelt wrote:
On Mon, 17 Jun 2019 18:31:00 PDT (-0700), Alistair Francis wrote:
> Based-on:
>
> Now that the RISC-V spec has started to be ratified let's upd
On Wed, 19 Jun 2019 06:42:21 PDT (-0700), bmeng...@gmail.com wrote:
Hi Alistair,
On Tue, Jun 18, 2019 at 1:15 AM Alistair Francis wrote:
On Fri, Jun 14, 2019 at 8:30 AM Bin Meng wrote:
>
> This adds a reset opcode for sifive_test device to trigger a system
> reset for testing purpose.
>
> Si
On Fri, 21 Jun 2019 17:23:44 PDT (-0700), alistai...@gmail.com wrote:
On Thu, Jun 20, 2019 at 7:49 PM Palmer Dabbelt wrote:
On Wed, 19 Jun 2019 07:19:38 PDT (-0700), alistai...@gmail.com wrote:
> On Wed, Jun 19, 2019 at 3:58 AM Palmer Dabbelt wrote:
>>
>> On Mon, 17 Jun 20
On Thu, 20 Jun 2019 22:40:24 PDT (-0700), bmeng...@gmail.com wrote:
Hi Palmer,
On Fri, Jun 21, 2019 at 10:53 AM Palmer Dabbelt wrote:
On Wed, 19 Jun 2019 06:42:21 PDT (-0700), bmeng...@gmail.com wrote:
> Hi Alistair,
>
> On Tue, Jun 18, 2019 at 1:15 AM Alistair Francis wrote:
>
On Mon, Jun 17, 2019 at 4:53 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 6/16/19 12:19 PM, Joel Sing wrote:
> > +/*
> > + * Clear the load reservation, since an SC must fail if there is
> > + * an SC to any address, in between an LR and SC pair.
> > + */
> > +
t way. Unless I'm missing something, I think these two
should do it:
From 6d645eb1e8ba4d16431af40bf04e5c165475bf5a Mon Sep 17 00:00:00 2001
From: Palmer Dabbelt
Date: Mon, 24 Jun 2019 01:59:05 -0700
Subject: [PATCH 1/2] RISC-V: Add support for the Zifencei extension
fence.i has been s
e counters in QEMU never tick (legal according to the spec).
Signed-off-by: Alistair Francis
[Palmer: Fix counter access semantics, change commit message to indicate
the behavior is fully emulated.]
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
diff --git a/target/riscv/cpu_
-
target/riscv/cpu.h| 19 ++---
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c| 13 +++-
.../riscv/insn_trans/trans_privileged.inc.c | 2 +-
6 files changed, 71 insertions(+), 44 deletions(-)
Asid
f the counters.
On Fri, Jun 14, 2019 at 7:52 AM Palmer Dabbelt wrote:
On Tue, 28 May 2019 11:30:20 PDT (-0700), jonat...@fintelia.io wrote:
> Currently mcounteren.TM acts as though it is hardwired to zero, even
though QEMU allows it to be set. This change resolves the issue by allowing
rea
On Mon, 24 Jun 2019 16:16:30 PDT (-0700), alistai...@gmail.com wrote:
On Mon, Jun 24, 2019 at 2:31 AM Palmer Dabbelt wrote:
On Mon, 17 Jun 2019 18:31:25 PDT (-0700), Alistair Francis wrote:
> For completeness let's add Zifencei and Zicsr as command line options,
> even though th
The various CSR instructions have been split out of the base ISA as part
of the ratification process. This patch adds a Zicsr argument, which
disables all the CSR instructions.
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 1 +
target/riscv/csr.c | 5 +
3
fence.i has been split out of the base ISA as part of the ratification
process. This patch adds a Zifencei argument, which disables the
fence.i instruction.
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 1 +
target
riscv/cpu.c| 1 +
target/riscv/cpu.h| 2 ++
target/riscv/cpu_helper.c | 16
target/riscv/pmp.c| 2 +-
5 files changed, 54 insertions(+), 18 deletions(-)
Reviewed-by: Palmer Dabbelt
1 and 4 were already in, so I'm leaving them towards the front of the
On Mon, 24 Jun 2019 16:41:44 PDT (-0700), Atish Patra wrote:
Currently, there is no cpu topology defined in RISC-V.
Define a device tree node that clearly describes the
entire topology. This saves the trouble of scanning individual
cache to figure out the topology.
Here is the linux kernel patch
On Tue, 25 Jun 2019 08:36:28 PDT (-0700), richard.hender...@linaro.org wrote:
On 6/24/19 8:08 PM, Joel Sing wrote:
Regarding the alignment for reservations, the
specification does require this, although I do not recall seeing any enforcement
of this by qemu itself.
Ah, I see it now. Enforceme
On Tue, 25 Jun 2019 08:39:21 PDT (-0700), richard.hender...@linaro.org wrote:
On 6/24/19 8:08 PM, Joel Sing wrote:
From 8ef31a2ce8ef1cbeee92995a0b2994f480e9bb6d Mon Sep 17 00:00:00 2001
From: Joel Sing
Date: Tue, 25 Jun 2019 02:44:24 +1000
Subject: [PATCH] Clear load reservations on qemu riscv
On Tue, 25 Jun 2019 08:20:55 PDT (-0700), alistai...@gmail.com wrote:
On Tue, Jun 25, 2019 at 3:09 AM Palmer Dabbelt wrote:
The various CSR instructions have been split out of the base ISA as part
of the ratification process. This patch adds a Zicsr argument, which
disables all the CSR
everything
will work. They can also override the firmware with their own using
the -bios option. Using "-bios none" will result in no firmware being
loaded (as it is today).
@Palmer Dabbelt can this go in your 4.1 PR? It has been reviewed and tested.
I don't see any reason why not. It&#
On Tue, 27 Aug 2019 18:31:18 PDT (-0700), bmeng...@gmail.com wrote:
Hi Palmer,
On Wed, Aug 28, 2019 at 7:18 AM Palmer Dabbelt wrote:
On Sun, 18 Aug 2019 22:59:54 PDT (-0700), bmeng...@gmail.com wrote:
> On Wed, Aug 14, 2019 at 11:33 PM Bin Meng wrote:
>>
>> This adds 'i
On Tue, 03 Sep 2019 20:41:52 PDT (-0700), bmeng...@gmail.com wrote:
Palmer,
On Wed, Aug 14, 2019 at 5:34 PM Bin Meng wrote:
Hi Palmer,
On Wed, Aug 7, 2019 at 10:53 AM Bin Meng wrote:
>
> On Wed, Aug 7, 2019 at 5:06 AM Philippe Mathieu-Daudé
wrote:
> >
> > On 8/5/19 8:43 AM, Bin Meng wrote
On Thu, 05 Sep 2019 08:25:46 PDT (-0700), bmeng...@gmail.com wrote:
Hi Alistair,
On Thu, Sep 5, 2019 at 3:50 AM Alistair Francis wrote:
On Sat, Aug 31, 2019 at 7:54 PM Bin Meng wrote:
>
> As of today, the QEMU 'sifive_u' machine is a special target that does
> not boot the upstream OpenSBI/U
On Thu, 05 Sep 2019 08:57:44 PDT (-0700), bmeng...@gmail.com wrote:
Hi Palmer,
On Thu, Sep 5, 2019 at 11:55 PM Bin Meng wrote:
This adds a reset opcode for sifive_test device to trigger a system
reset for testing purpose.
Signed-off-by: Bin Meng
Reviewed-by: Palmer Dabbelt
---
Changes
include "qemu/osdep.h"
-#include "hw/hw.h"
#include "hw/sysbus.h"
#include "qemu/module.h"
#include "target/riscv/cpu.h"
Revieweb-by: Palmer Dabbelt
public >*/
+MemoryRegion mmio;
+uint32_t hfxosccfg;
+ uint32_t corepllcfg0;
+uint32_t ddrpllcfg0;
+uint32_t ddrpllcfg1;
+uint32_t gemgxlpllcfg0;
+uint32_t gemgxlpllcfg1;
+uint32_t coreclksel;
+uint32_t devicesreset;
+uint32_t clkmuxstatus;
+} SiFiveUPRCIState;
+
+#endif /* HW_SIFIVE_U_PRCI_H */
Reviewed-by: Palmer Dabbelt
|= env->mstatus & MSTATUS_FS;
+*flags |= TB_FLAGS_MSTATUS_FS;
I thought this was a functional change, but it's not: fp_enabled() checks
mstatus already.
}
#endif
}
Reviewed-by: Palmer Dabbelt
On Fri, 23 Aug 2019 08:21:06 PDT (-0700), Alistair Francis wrote:
The first three patches are ones that I have pulled out of my original
Hypervisor series at an attempt to reduce the number of patches in the
series.
These three patches all make sense without the Hypervisor series so can
be merg
/cpu.h
@@ -67,6 +67,7 @@
#define RVC RV('C')
#define RVS RV('S')
#define RVU RV('U')
+#define RVH RV('H')
/* S extension denotes that Supervisor mode exists, however it is possible
to have a core that support S mode but does not have an MMU and there
Reviewed-by: Palmer Dabbelt
cv_has_ext(env, RVH)) {
+return;
+}
+
+env->virt &= ~VIRT_MODE_MASK;
+env->virt |= enable << VIRT_MODE_SHIFT;
+}
+
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts)
{
CPURISCVState *env = &cpu->env;
Reviewed-by: Palmer Dabbelt
On Fri, 23 Aug 2019 16:37:57 PDT (-0700), Alistair Francis wrote:
Signed-off-by: Alistair Francis
There's really no description of what this does, either in the commit message
or as a comment.
---
target/riscv/cpu.h| 2 ++
target/riscv/cpu_bits.h | 6 ++
target/riscv/cpu_hel
On Fri, 23 Aug 2019 16:38:00 PDT (-0700), Alistair Francis wrote:
Update the CSR permission checking to work correctly when we are in
HS-mode.
Signed-off-by: Alistair Francis
---
target/riscv/csr.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/target/riscv/csr.
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec ", env->stvec);
+if (riscv_has_ext(env, RVH)) {
+qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vstvec ", env->vstvec);
+}
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc", env->mepc);
+qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sepc", env->sepc);
+if (riscv_has_ext(env, RVH)) {
+qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsepc ", env->vsepc);
+}
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause ", env->mcause);
+qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scause ", env->scause);
+if (riscv_has_ext(env, RVH)) {
+qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause);
+}
#endif
for (i = 0; i < 32; i++) {
Reviewed-by: Palmer Dabbelt
write_hgatp
},
+
/* Physical Memory Protection */
[CSR_PMPCFG0 ... CSR_PMPADDR9] = { pmp, read_pmpcfg, write_pmpcfg },
[CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr },
Reviewed-by: Palmer Dabbelt
u, dcbase->pc_first, dcbase->tb->size);
}
Reviewed-by: Palmer Dabbelt
;
+target_ulong vsatp;
+
target_ulong scounteren;
target_ulong mcounteren;
Reviewed-by: Palmer Dabbelt
write_vsip
},
+[CSR_VSATP] = { hmode, read_vsatp, write_vsatp
},
+
/* Physical Memory Protection */
[CSR_PMPCFG0 ... CSR_PMPADDR9] = { pmp, read_pmpcfg, write_pmpcfg },
[CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr },
Reviewed-by: Palmer Dabbelt
The following changes since commit 89ea03a7dc83ca36b670ba7f787802791fcb04b1:
Merge remote-tracking branch 'remotes/huth-gitlab/tags/m68k-pull-2019-09-07'
into staging (2019-09-09 09:48:34 +0100)
are available in the Git repository at:
git://github.com/palmer-dabbelt/qemu.git tags
: Guenter Roeck
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 8313f2605e..ae5a16e636 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
}
-target_ulong mstatus = env->mstatus;
+target_ulong mstatus = *env->mstatus;
target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP);
mstatus = set_field(mstatus,
env->priv_ver >= PRIV_VERSION_1_10_0 ?
@@ -121,7 +121,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong
cpu_pc_deb)
mstatus = set_field(mstatus, MSTATUS_MPIE, 0);
mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
riscv_cpu_set_mode(env, prev_priv);
-env->mstatus = mstatus;
+*env->mstatus = mstatus;
return retpc;
}
@@ -132,7 +132,7 @@ void helper_wfi(CPURISCVState *env)
if (env->priv == PRV_S &&
env->priv_ver >= PRIV_VERSION_1_10_0 &&
-get_field(env->mstatus, MSTATUS_TW)) {
+get_field(*env->mstatus, MSTATUS_TW)) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
} else {
cs->halted = 1;
@@ -147,7 +147,7 @@ void helper_tlb_flush(CPURISCVState *env)
if (!(env->priv >= PRV_S) ||
(env->priv == PRV_S &&
env->priv_ver >= PRIV_VERSION_1_10_0 &&
- get_field(env->mstatus, MSTATUS_TVM))) {
+ get_field(*env->mstatus, MSTATUS_TVM))) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
} else {
tlb_flush(cs);
I don't think this is that bad.
Reviewed-by: Palmer Dabbelt
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