On Tue, Oct 9, 2012 at 11:52 PM, Peter Maydell peter.mayd...@linaro.org wrote:
On 9 October 2012 14:38, Peter Crosthwaite
peter.crosthwa...@petalogix.com wrote:
On Tue, Oct 9, 2012 at 9:41 PM, Peter Maydell peter.mayd...@linaro.org
wrote:
We don't support per-CPU reset right now, and I don't
Mammedov imamm...@redhat.com
[ehabkost: change CPU type declaration to hae TYPE_DEVICE as parent]
Signed-off-by: Igor Mammedov imamm...@redhat.com
Signed-off-by: Eduardo Habkost ehabk...@redhat.com
Acked-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
include/qemu/cpu.h | 6 +++---
qom
device
xilinx_spi: Initial impl. of Xilinx SPI controller
petalogix-ml605: added SPI controller with n25q128
xilinx_spips: Xilinx Zynq SPI cntrlr device model
xilinx_zynq: Added SPI controllers + flashes
MAINTAINERS: Added maintainerships for SSI
Peter Crosthwaite (1
From: Peter A. G. Crosthwaite peter.crosthwa...@petalogix.com
Removed assertion that only one device is attached to the SSI bus.
When multiple devices are attached, all slaves have their transfer function
called for transfers. Each device is responsible for knowing whether or not its
CS is
From: Peter A. G. Crosthwaite peter.crosthwa...@petalogix.com
Slave creation function that can be used to create an SSI slave without
qdev_init() being called. This give machine models a chance to set properties.
Signed-off-by: Peter A. G. Crosthwaite peter.crosthwa...@petalogix.com
Acked-by:
From: Peter A. G. Crosthwaite peter.crosthwa...@petalogix.com
Added a FIFO API that can be used to create and operate byte FIFOs.
Signed-off-by: Peter A. G. Crosthwaite peter.crosthwa...@petalogix.com
---
hw/Makefile.objs |1 +
hw/fifo.c| 78
From: Peter A. G. Crosthwaite peter.crosthwa...@petalogix.com
Removed the explicit SSI mux and wired the CS line directly up to the SSI
devices.
Signed-off-by: Peter A. G. Crosthwaite peter.crosthwa...@petalogix.com
---
hw/ssd0323.c |1 +
hw/ssi-sd.c|1 +
hw/stellaris.c | 94
From: Peter A. G. Crosthwaite peter.crosthwa...@petalogix.com
Added the two SPI controllers to the zynq machine model. Attached two SPI flash
devices to each controller.
Signed-off-by: Peter A. G. Crosthwaite peter.crosthwa...@petalogix.com
Acked-by: Peter Maydell peter.mayd...@linaro.org
---
From: Peter A. G. Crosthwaite peter.crosthwa...@petalogix.com
Added device model for m25p80 style SPI flash family.
Signed-off-by: Peter A. G. Crosthwaite peter.crosthwa...@petalogix.com
---
default-configs/arm-softmmu.mak |1 +
default-configs/microblaze-softmmu.mak |2 +
From: Peter A. G. Crosthwaite peter.crosthwa...@petalogix.com
Added SPI controller to the reference design, with two n25q128 spi-flashes
connected.
Signed-off-by: Peter A. G. Crosthwaite peter.crosthwa...@petalogix.com
Acked-by: Peter Maydell peter.mayd...@linaro.org
---
From: Peter A. G. Crosthwaite peter.crosthwa...@petalogix.com
Allow multiple qdev_init_gpio_in() calls for the one device. The first call will
define GPIOs 0-N-1, the next GPIOs N- ... . Allows different GPIOs to be handled
with different handlers. Needed when two levels of the QOM class heirachy
Added helper function to automatically connect SPI slaves based on the QOM child
nodes of a device. A SSI master device can call this routine to automatically
hook-up all child nodes to its SPI bus.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
Acked-by: Peter Maydell peter.mayd
From: Peter A. G. Crosthwaite peter.crosthwa...@petalogix.com
Added default CS behaviour for SSI slaves. SSI devices can set a property
to enable CS behaviour which will create a GPIO on the device which is the
CS. Tristating of the bus on SSI transfers is implemented.
Signed-off-by: Peter A. G.
From: Peter A. G. Crosthwaite peter.crosthwa...@petalogix.com
Device model for xilinx XPS SPI controller (v2.0)
Signed-off-by: Peter A. G. Crosthwaite peter.crosthwa...@petalogix.com
---
hw/microblaze/Makefile.objs |1 +
hw/xilinx_spi.c | 383
+518,12 @@ M: Paul Brook p...@codesourcery.com
S: Odd Fixes
F: hw/lsi53c895a.c
+SSI
+M: Peter Crosthwaite peter.crosthwa...@petalogix.com
+S: Maintained
+F: hw/ssi.*
+F: hw/m25p80.c
+
USB
M: Gerd Hoffmann kra...@redhat.com
S: Maintained
@@ -565,6 +572,7 @@ F: hw/xilinx_intc.c
F: hw
From: Peter A. G. Crosthwaite peter.crosthwa...@petalogix.com
Added device model for the Xilinx Zynq SPI controller (SPIPS).
Signed-off-by: Peter A. G. Crosthwaite peter.crosthwa...@petalogix.com
Acked-by: Peter Maydell peter.mayd...@linaro.org
---
hw/arm/Makefile.objs |1 +
which should happen before the update.
Fixed the ordering of the two, the old carry is read by r13,RRX before being
updated.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
Reported-by: Vinesh Peringat vine...@xilinx.com
---
target-arm/translate.c |2 +-
1 files changed, 1 insertions
(see the FIXME:s) at the moment but im pushing
for this now as the more conterversial QOM-entangled aspects of this device
model are encapsulated by this series. The device does also fully work for
Linux.
Edgar E. Iglesias (1):
nand: Reset addressing after READSTATUS.
Peter Crosthwaite (6
This field is completely unused. The base address should also be abstracted
away from the device anyway. Removed.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
hw/pflash_cfi01.c |2 --
hw/pflash_cfi02.c |4 +---
2 files changed, 1 insertions(+), 5 deletions(-)
diff
This field is completely unused.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
hw/pflash_cfi01.c |2 --
1 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/hw/pflash_cfi01.c b/hw/pflash_cfi01.c
index 4f3f5f0..ebc8a57 100644
--- a/hw/pflash_cfi01.c
+++ b/hw
or morph into something else with Anthony sysbus purge
so its intended to be a bridging patch until those refactorings go live.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
hw/sysbus.c | 11 ---
hw/sysbus.h |2 ++
2 files changed, 10 insertions(+), 3 deletions
Initial device model for the pl35x series of memory controllers. The SRAM
interface is just implemented as a passthrough using memory regions. NAND
interfaces are modelled.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
default-configs/arm-softmmu.mak |1 +
hw
Add the pl353 memory controller with both NAND and parallel flashes
attached.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
hw/xilinx_zynq.c | 49 +
1 files changed, 41 insertions(+), 8 deletions(-)
diff --git a/hw
From: Edgar E. Iglesias edgar.igles...@gmail.com
Signed-off-by: Edgar E. Iglesias edgar.igles...@gmail.com
---
hw/nand.c |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/hw/nand.c b/hw/nand.c
index 01f3ada..f931d0c 100644
--- a/hw/nand.c
+++ b/hw/nand.c
@@ -478,6
Hi All,
Thanks for the responses. Ill look into further in the near future,
probably starting the the Linker based approaches.
Regards,
Peter
QOMified the pflash_cfi0x so machine models can connect them up in custom ways.
Kept the pflash_cfi0x_register functions as is. They can still be used to
create a flash straight onto system memory.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
hw/pflash_cfi01.c | 142
Support for the Quad SPI flash controller in Xilinx Zynq.
Peter Crosthwaite (3):
m25p80: Support for Quad SPI
xilinx_spips: Generalised to model QSPI
xilinx_zynq: added QSPI controller
hw/m25p80.c | 61 +++-
hw/xilinx_spips.c | 289
-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
hw/m25p80.c | 61 +++---
1 files changed, 57 insertions(+), 4 deletions(-)
diff --git a/hw/m25p80.c b/hw/m25p80.c
index 9a56de8..3895e73 100644
--- a/hw/m25p80.c
+++ b/hw/m25p80.c
@@ -72,6 +72,10
Added the QSPI controller to the Zynq. 4 SPI devices are attached to allow
modelling of the different geometries. E.G. Dual parallel and dual stacked
mode can both be tested with this one arrangement.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
hw/xilinx_zynq.c | 40
-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
hw/xilinx_spips.c | 289 ++--
1 files changed, 255 insertions(+), 34 deletions(-)
diff --git a/hw/xilinx_spips.c b/hw/xilinx_spips.c
index f64a782..538f091 100644
--- a/hw/xilinx_spips.c
+++ b/hw
On Fri, Oct 19, 2012 at 6:06 PM, Peter Maydell peter.mayd...@linaro.org wrote:
On 19 October 2012 07:40, Peter Crosthwaite
peter.crosthwa...@xilinx.com wrote:
Add a variant to sysbus_mmio_map that allow specifying a target memory
region.
The requested device memory region is mapped within
Add more helpful debug information to the cadence UART.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
hw/cadence_uart.c | 11 +++
1 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/hw/cadence_uart.c b/hw/cadence_uart.c
index f8afc4e..483a316 100644
On Fri, Oct 19, 2012 at 8:32 PM, Peter Maydell peter.mayd...@linaro.org wrote:
On 19 October 2012 07:40, Peter Crosthwaite
peter.crosthwa...@xilinx.com wrote:
Add the pl353 memory controller with both NAND and parallel flashes
attached.
Signed-off-by: Peter Crosthwaite peter.crosthwa
On Fri, Oct 19, 2012 at 8:24 PM, Peter Maydell peter.mayd...@linaro.org wrote:
On 19 October 2012 07:40, Peter Crosthwaite
peter.crosthwa...@xilinx.com wrote:
QOMified the pflash_cfi0x so machine models can connect them up in custom
ways.
Kept the pflash_cfi0x_register functions
On Fri, Oct 19, 2012 at 10:18 PM, Edgar E. Iglesias
edgar.igles...@gmail.com wrote:
On Fri, Oct 19, 2012 at 12:59:49PM +0100, Peter Maydell wrote:
On 19 October 2012 07:40, Peter Crosthwaite
peter.crosthwa...@xilinx.com wrote:
From: Edgar E. Iglesias edgar.igles...@gmail.com
Signed-off
in in pflash when debug was turned on (P6)
Removed NAND READ_STATUS address reset patch (fomerly P6)
Peter Crosthwaite (6):
pflash_cfi0x: remove unused base field
pflash_cfi01: remove unused total_len field
pflash_cfi0x: QOMified
hw: Model of Primecell pl35x mem controller
xilinx_zynq: add pl353
This field is completely unused. The base address should also be abstracted
away from the device anyway. Removed.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
hw/pflash_cfi01.c |2 --
hw/pflash_cfi02.c |4 +---
2
QOMified the pflash_cfi0x so machine models can connect them up in custom ways.
Kept the pflash_cfi0x_register functions as is. They can still be used to
create a flash straight onto system memory.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
changed from v1:
Removed union
Add the pl353 memory controller with both NAND and parallel flashes
attached.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
changed from v1:
fixed property names (see patch 3)
hw/xilinx_zynq.c | 50 ++
1 files changed, 42
This DPRINTF was throwing a warning due to a missing cast.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
hw/pflash_cfi01.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/hw/pflash_cfi01.c b/hw/pflash_cfi01.c
index 6164a97..90c111d 100644
--- a/hw
This field is completely unused.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
hw/pflash_cfi01.c |2 --
1 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/hw/pflash_cfi01.c b/hw/pflash_cfi01.c
index 4f3f5f0
Initial device model for the pl35x series of memory controllers. The SRAM
interface is just implemented as a passthrough using memory regions. NAND
interfaces are modelled.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
changed since v1:
use sysbus_mmio_get_region() for SRAM
On Tue, Oct 23, 2012 at 2:12 AM, Peter Maydell peter.mayd...@linaro.org wrote:
On 22 October 2012 08:19, Peter Crosthwaite
peter.crosthwa...@xilinx.com wrote:
Initial device model for the pl35x series of memory controllers. The SRAM
interface is just implemented as a passthrough using memory
On Tue, Oct 23, 2012 at 12:20 AM, Josh Cartwright
josh.cartwri...@ni.com wrote:
Change the cadence_uart such that tx/rx is enabled on reset. Assuming
both are enabled makes debugging early Linux kernel bootup a little bit
easier.
Signed-off-by: Josh Cartwright josh.cartwri...@ni.com
---
Do 16 words per fifo flush. Increases performance and decreases
debug verbosity. This data depth has no real hardware analogue,
so just go with something that has reasonable performance.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
hw/xilinx_spips.c | 11 +++
1
The LQSPI bus attachment supports byte/halfword and misaligned
accesses. Fixed. Refactored the LQSPI cache to be byte-wise
instead of word wise accordingly.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
hw/xilinx_spips.c | 31 +--
1 files
Hi Peter,
This is a corner case bug discovered by U-boot driver for cadence GEM.
Regards,
Peter
Peter Crosthwaite (1):
cadence_uart: Flush queued characters on reset
hw/cadence_uart.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
Reset can be used to empty the rx-fifo. As the fifo full condition is
used to return false from can_receive, queued rx data should be flushed
on reset accordingly.
Cc: Wendy Liang jli...@xilinx.com
Cc: Jason Wu hua...@xilinx.com
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
Refactor axienet to be more QOM friendly.
Peter Crosthwaite (16):
xilinx_axienet: typedef XilinxAXIEnet struct
xilinx_axienet: Defined and use type cast macro
xilinx_axienet: Register reset properly
xilinx_axienet: converted init-realize
xilinx_axidma: typedef XilinxAXIDMA struct
Typedef xilinx_axienets object state struct to shorten the repeated usages of
struct XilinxAXIEnet.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
Reviewed-by: Andreas Färber afaer...@suse.de
Acked-by: Edgar E. Iglesias edgar.igles...@xilinx.com
---
hw/xilinx_axienet.c | 44
Standard QOM cast macro. Replaces usages of FROM_SYSBUS
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
Reviewed-by: Andreas Färber afaer...@suse.de
Acked-by: Edgar E. Iglesias edgar.igles...@xilinx.com
---
hw/xilinx_axienet.c | 11 ---
1 files changed, 8 insertions
Register the reset function and the Device::reset function rather than
explicitly call it from the sysbus::init.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
Reviewed-by: Andreas Färber afaer...@suse.de
Acked-by: Edgar E. Iglesias edgar.igles...@xilinx.com
---
hw
The prescribed transition from SysBusDevice::init to Device::realize. Im going
with Andreas suggestion to move the sysbus foo to Object::init for early IRQ
visibility.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
Reviewed-by: Andreas Färber afaer...@suse.de
Acked-by: Edgar E
Typedef xilinx_axidma's object state struct to shorten the repeated usages of
struct XilinxAXIDMA.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
Acked-by: Edgar E. Iglesias edgar.igles...@xilinx.com
---
hw/xilinx_axidma.c | 16 +---
1 files changed, 9 insertions
Standard QOM cast macro. Replaces usages of FROM_SYSBUS
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
Acked-by: Edgar E. Iglesias edgar.igles...@xilinx.com
---
hw/xilinx_axidma.c | 13 +
1 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/hw
Register the reset function as the Device::reset function rather than
explicitly call it from the sysbus::init.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
Acked-by: Edgar E. Iglesias edgar.igles...@xilinx.com
---
hw/xilinx_axidma.c | 12 +++-
1 files changed, 11
The prescribed transition from SysBusDevice::init to Device::realize. I'm going
with Andreas suggestion to move the sysbus foo to Object::init for early IRQ
visibility.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
Acked-by: Edgar E. Iglesias edgar.igles...@xilinx.com
---
hw
Just attach devices straight to the root machine node, rather than the
unattached node
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
Reviewed-by: Andreas Färber afaer...@suse.de
Acked-by: Edgar E. Iglesias edgar.igles...@xilinx.com
---
Suggested (indirectly) by Andreas if he wants
Explicitly make the ethernet a child of the machine. This is needed to set
and use links pre-realize. Also makes the ethernet initialization consistent
with its peer DMA.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
Reviewed-by: Andreas Färber afaer...@suse.de
Acked-by: Edgar E
differentiate which slave connection they are connected to
by linking to the proxy object rather than the parent.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
changed from v3:
Fixed function name s/axienet_data_stream_push/xilinx_axienet_data_stream_push
changed from v2:
got
differentiate which slave connection they are connected to
by linking to the proxy object rather than the parent.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
changed since v3:
Rebased to occur before flow control patches
hw/microblaze/petalogix_ml605_mmu.c |6 ++-
hw
Add basic flow control to stream. A stream slave may return short, indicating
that it is not capable of accepting any more data at the present time. Polling
or a callback can be used via the can_push() function to determine when the
slave can receive again.
Signed-off-by: Peter Crosthwaite
If there is no DMA buffer descriptor, the DMA halts, not idles.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
Acked-by: Edgar E. Iglesias edgar.igles...@xilinx.com
---
changed from v3:
Fixed for TX path as well as RX
hw/xilinx_axidma.c |4 ++--
1 files changed, 2 insertions
from ethernet can_receive() as appropriate.
If the DMA backs up or is disabled it waits for enablement. When the rx stream
IO
region is touched, the can_push() notify function is called if set.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
hw/xilinx_axidma.c | 49
The uint32_t *app argument doesn't exist in real hardware. It was a hack in
xilinx_axidma/enet to fake the (secondary) control stream connection. Removed
the argument and added the second stream to axienet/dma.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
changed since v3
for any number of address cycles rather than just 3]
Signed-off-by: Wendy Liang jli...@xilinx.com
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
hw/nand.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/hw/nand.c b/hw/nand.c
index de3e502..6362093 100644
Hi Paolo,
On Wed, Apr 3, 2013 at 4:35 PM, Paolo Bonzini pbonz...@redhat.com wrote:
---
Is it expected that this non-blocking condition implies lockup of the
iothread?
No. The idea was to make the loop cheaper when you had a qemu_notify_event()
or bottom half, basically something that
)
Fixed passing of ARFLAGS to dtc submake
Peter Crosthwaite (3):
configure: Put cross compile flags in EXTRA_CFLAGS
dtc: add submodule
configure/Make: Build libfdt from submodule DTC
.gitmodules |3 +++
Makefile| 10 ++
configure | 47
The cross compile CFLAGS are needed to properly build pixman (and any other
submodules). Only the EXTRA_CFLAGS set is passed to submodules not QEMU_CFLAGS,
so put the cross compile flags in EXTRA_CFLAGS instead.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
Changed from v2
Add dtc submodule as a fallback for old distros.
Picking version 1.3.0. as this is the most recently tagged stable version.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
.gitmodules |3 +++
dtc |1 +
2 files changed, 4 insertions(+), 0 deletions(-)
create
directory
and pass in all the needed DTC arguments to make out of tree build happen.
Ideally we fix the DTC make to support out of tree, but did it this way to
avoid commits to DTC.
Signed-off-by: David Holsgrove david.holsgr...@xilinx.com
Signed-off-by: Peter Crosthwaite peter.crosthwa
Trivial code cleanup of the PetaLogix and Zynq machine models.
Peter Crosthwaite (2):
petalogix_ml605_mmu: Cleanup ssi_create_slave()
xilinx_zynq: Cleanup ssi_create_slave
hw/arm/xilinx_zynq.c|3 +--
hw/microblaze/petalogix_ml605_mmu.c |3 +--
2 files changed, 2
With the recent m25p80 cleanup there is no need to use
ssi_create_slave_no_init() anymore. Just use ssi_create_slave().
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
hw/microblaze/petalogix_ml605_mmu.c |3 +--
1 files changed, 1 insertions(+), 2 deletions(-)
diff --git
With the recent m25p80 cleanup there is no need to use
ssi_create_slave_no_init() anymore. Just use ssi_create_slave().
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
hw/arm/xilinx_zynq.c |3 +--
1 files changed, 1 insertions(+), 2 deletions(-)
diff --git a/hw/arm
and MST comments.
Simplified to be more Memory API compatible.
Added Memory API helpers.
Please see discussion already on list and commit msgs for more detail.
Peter A. G. Crosthwaite (2):
xilinx_devcfg: Zynq devcfg device model
xilinx_zynq: added devcfg to machine model
Peter Crosthwaite (3
From: Peter A. G. Crosthwaite peter.crosthwa...@petalogix.com
Signed-off-by: Peter A. G. Crosthwaite peter.crosthwa...@petalogix.com
---
Changed since v1:
Added manual parenting of devcfg node (evil but needed for early access
to canonical path by devcfgs realize fn).
hw/arm/xilinx_zynq.c |
Add memory io handlers that glue the register API to the memory API.
Just translation functions at this stage. Although it does allow for
devices to be created without all-in-one mmio r/w handlers.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
include/exec/register.h | 13
Little macro that just gives you N ones (justified to LSB).
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
include/qemu/bitops.h |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h
index affcc96..da47fc8
From: Peter A. G. Crosthwaite peter.crosthwa...@petalogix.com
Minimal device model for devcfg module of Zynq. DMA capabilities and
interrupt generation supported.
Signed-off-by: Peter A. G. Crosthwaite peter.crosthwa...@petalogix.com
---
Changed since v1:
Rebased against new version of Register
Hi Peter,
On Fri, Apr 5, 2013 at 6:53 PM, Peter Maydell peter.mayd...@linaro.org wrote:
On 5 April 2013 09:43, Peter Crosthwaite peter.crosthwa...@xilinx.com wrote:
Little macro that just gives you N ones (justified to LSB).
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
ops
Verbose debugging info can be enabled/disabled
Useful for defining device register spaces in a data driven way. Cuts
down on a lot of the verbosity and repetition in the switch-case blocks
in the standard foo_mmio_read/write functions.
Signed-off-by: Peter Crosthwaite peter.crosthwa
On Fri, Apr 5, 2013 at 7:26 PM, Peter Maydell peter.mayd...@linaro.org wrote:
On 5 April 2013 09:43, Peter Crosthwaite peter.crosthwa...@xilinx.com wrote:
This API provides some encapsulation of registers and factors our some
common functionality to common code. Bits of device state (usually
Hi Paolo,
On Sat, Apr 6, 2013 at 1:59 AM, Paolo Bonzini pbonz...@redhat.com wrote:
The character backend refactoring introduced an undesirable busy wait.
The busy wait happens if can_read returns zero and there is data available
on the character device's file descriptor. Then, the I/O watch
Hi Anthony,
On Fri, Apr 5, 2013 at 11:46 PM, Anthony Liguori aligu...@us.ibm.com wrote:
The char-flow refactoring introduced a busy-wait that depended on
an action from the VCPU thread. However, the VCPU thread could
never take that action because the busy-wait starved the VCPU thread
of the
timout, (indicating a return to normality). The 1000 iteration
wait now only happens once on the transition from normal operation to
busy-wait starvation.
Anthony's original patch fixed the serial paste bug, but this patch is
also needed to restore performance.
Signed-off-by: Peter Crosthwaite
Hi Edgar,
On Wed, Apr 3, 2013 at 4:50 PM, Edgar E. Iglesias
edgar.igles...@gmail.com wrote:
On Wed, Apr 03, 2013 at 02:09:16PM +1000, Peter Crosthwaite wrote:
Some dodgy casts were making a mess of these msgs.
Hi Peter
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
Fix up the debug printfery m25p80 in various ways. 0 functional diff.
Peter Crosthwaite (4):
m25p80: Fix debug messages.
m25p80: Convert guest errors to LOG_GUEST_ERROR
m25p80.c: Multiple debug verbosity levels
m25p80: Add debug message for no bdrv
hw/m25p80.c | 52
Some dodgy casts were making a mess of these msgs.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
Remove misleading k suffix from erase size message
Use PRIxN macros where appropriate (Edgar review)
hw/m25p80.c | 13 +++--
1 files changed, 7 insertions(+), 6
Some of the debug printfs in m25p80 are really guest errors.
Changed over to qemu_log_mask(LOG_GUEST_ERROR accordingly.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
hw/m25p80.c | 12 +++-
1 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/hw/m25p80.c b
If there is no backing bdrv, let the debugging developer know about it.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
hw/m25p80.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/hw/m25p80.c b/hw/m25p80.c
index d853a2e..efcc7f4 100644
--- a/hw/m25p80
The debug printfs on every page program/read is extremely verbose. Add
a second level of debug for this.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
hw/m25p80.c | 40 +---
1 files changed, 21 insertions(+), 19 deletions(-)
diff --git
Hi Peter,
On Fri, Apr 5, 2013 at 7:49 PM, Peter Crosthwaite
peter.crosthwa...@xilinx.com wrote:
On Fri, Apr 5, 2013 at 7:26 PM, Peter Maydell peter.mayd...@linaro.org
wrote:
On 5 April 2013 09:43, Peter Crosthwaite peter.crosthwa...@xilinx.com
wrote:
This API provides some encapsulation
Hi Paolo,
On Mon, Apr 8, 2013 at 4:49 AM, Paolo Bonzini pbonz...@redhat.com wrote:
Il 06/04/2013 21:00, Amit Shah ha scritto:
On (Fri) 05 Apr 2013 [17:59:33], Paolo Bonzini wrote:
The character backend refactoring introduced an undesirable busy wait.
The busy wait happens if can_read returns
Hi Peter,
On Sat, Apr 6, 2013 at 4:41 AM, Peter Maydell peter.mayd...@linaro.org wrote:
On 3 April 2013 05:27, Peter Crosthwaite peter.crosthwa...@xilinx.com wrote:
The real hardware does not produce interrupts in LQSPI mode. Inhibit
generation of interrupts when the LQ_MODE bit is set
On Sat, Apr 6, 2013 at 4:42 AM, Peter Maydell peter.mayd...@linaro.org wrote:
On 3 April 2013 05:32, Peter Crosthwaite peter.crosthwa...@xilinx.com wrote:
You really need this is you want to track a guest banging on LQSPI.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
Hi Peter,
On Sat, Apr 6, 2013 at 4:46 AM, Peter Maydell peter.mayd...@linaro.org wrote:
On 3 April 2013 05:32, Peter Crosthwaite peter.crosthwa...@xilinx.com wrote:
The LQSPI code currently manipulates the config register to achieve its
ends. Some (agressively designed) drivers assume
On Sat, Apr 6, 2013 at 4:50 AM, Peter Maydell peter.mayd...@linaro.org wrote:
On 3 April 2013 05:32, Peter Crosthwaite peter.crosthwa...@xilinx.com wrote:
QSPI has a bigger FIFO than the regular SPI controller. Differentiate
between the two with correct FIFO sizes for each.
Signed-off
Hi Peter,
On Sat, Apr 6, 2013 at 4:53 AM, Peter Maydell peter.mayd...@linaro.org wrote:
On 3 April 2013 05:32, Peter Crosthwaite peter.crosthwa...@xilinx.com wrote:
Invalidate the LQSPI cached page when transitioning into LQSPI mode.
Otherwise there is a possibility that the controller
Hi Peter,
On Sat, Apr 6, 2013 at 4:59 AM, Peter Maydell peter.mayd...@linaro.org wrote:
On 3 April 2013 05:33, Peter Crosthwaite peter.crosthwa...@xilinx.com wrote:
The QSPI controller was using byte-wide stripes when striping across
the two flashes in dual parallel mode. The real hardware
On Sat, Apr 6, 2013 at 5:01 AM, Peter Maydell peter.mayd...@linaro.org wrote:
On 3 April 2013 05:33, Peter Crosthwaite peter.crosthwa...@xilinx.com wrote:
The LQSPI bus attachment supports byte/halfword and misaligned
accesses. Fixed. Refactored the LQSPI cache to be byte-wise
instead of word
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