x27;t currently implement the architectural
interrupt handling.
Add a "do nothing" implementation of cpu_exec_hook for Tricore,
assert on startup that the CPU does provide the hook, and remove
the runtime NULL check before calling it.
Signed-off-by: Peter Maydell
---
accel/tcg
The QC, N, Z, C, V bits live in the FPSR, not the FPCR. Rename the
macros that define these bits accordingly.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20240628142347.1283015-8-peter.mayd...@linaro.org
---
target/arm/cpu.h | 17
which
takes a mask of which bits to update.
(We could do the same for FPSR, but we leave that until we actually
are likely to need it.)
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20240628142347.1283015-10-peter.mayd...@linaro.org
---
target/arm/vfp_helper.c
From: Richard Henderson
Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
Message-id: 20240709000610.382391-4-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 33 ++
target/arm/tcg/translate-a64.c | 604
tests/qtest/stm32l4x5_usart-test.c)
checks that USART1_IRQ in the CPU is pending when expected so it
confirms that the connection through the EXTI still works.
Signed-off-by: Inès Varhol
Reviewed-by: Peter Maydell
Message-id: 20240707085927.122867-4-ines.var...@telecom-paris.fr
Signed-off-by:
AArch64 register, and define them
symbolically rather than as hex values. (This latter requires
defining some extra macros for bits which we haven't previously
defined.)
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20240628142347.1283015-9-peter.mayd...@linar
tem-aarch64 -display \
none -machine accel=qtest, -m 512M -machine realview-pb-a8 -qtest stdio
writeq 0x1000b024 0xf800
EOF
Suggested-by: Peter Maydell
Signed-off-by: Zheyu Ma
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20240702155752.3022007-1-zheyum...@gmail.com
Signed-off-by: Peter Mayde
ndling for direct interrupts (interrupts without configurable edge).
Signed-off-by: Inès Varhol
Message-id: 20240707085927.122867-3-ines.var...@telecom-paris.fr
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
hw/misc/stm32l4x5_exti.c | 7 +++
1 file changed, 7 insertions(+)
diff
The M-profile FPSCR LTPSIZE is bits [18:16]; this is the same
field as A-profile FPSCR Len, not Stride. Correct the comment
in vfp_get_fpscr().
We also implemented M-profile FPSCR.QC, but forgot to delete
a TODO comment from vfp_set_fpscr(); remove it now.
Signed-off-by: Peter Maydell
Reviewed
dle direct interrupts
hw/arm: In STM32L4x5 SOC, connect USART devices to EXTI
Peter Maydell (12):
target/arm: Correct comments about M-profile FPSCR
target/arm: Make vfp_get_fpscr() call vfp_get_{fpcr, fpsr}
target/arm: Make vfp_set_fpscr() call vfp_set_{fpcr, fpsr}
target/ar
ey're only 32 bit registers).
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20240628142347.1283015-7-peter.mayd...@linaro.org
---
target/arm/cpu.h | 7 +++
target/arm/tcg/translate.h| 3 +--
target/arm/tcg/mve_helper.c
From: Richard Henderson
Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
Message-id: 20240709000610.382391-3-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 9 ++
target/arm/tcg/translate-a64.c | 150
n the high
half of either register.
(We won't ever send the new migration subsection until we add support
for a CPU feature which enables setting overlapping FPCR bits, like
FEAT_AFP.)
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20240628142347.1283015-5-peter.mayd
al to the source file it's defined in.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
---
target/riscv/internals.h | 3 +++
target/alpha/cpu.c | 1 +
target/avr/cpu.c | 1 +
target/cris/cpu.c | 2 ++
target/hppa/cpu.c | 1 +
target
away then.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20240628142347.1283015-4-peter.mayd...@linaro.org
---
target/arm/cpu.h| 22 +
target/arm/vfp_helper.c | 100 ++--
2 files changed, 78 insertions(+), 44
2.3018932-1-zheyum...@gmail.com
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
hw/misc/bcm2835_thermal.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/misc/bcm2835_thermal.c b/hw/misc/bcm2835_thermal.c
index ee7816b8a5d..0c49c088a79 100644
--- a/hw/misc/bcm2835_thermal
From: Richard Henderson
Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
Message-id: 20240709000610.382391-2-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 22
target/arm/tcg/translate-a64.c | 184
From: Richard Henderson
Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
Message-id: 20240709000610.382391-6-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 5 ++
target/arm/tcg/translate-a64.c | 127
From: Richard Henderson
Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
Message-id: 20240709000610.382391-5-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 5 ++
target/arm/tcg/translate-a64.c | 86
From: Richard Henderson
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
Message-id: 20240709000610.382391-7-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 3 ++
target/arm/tcg/translate-a64.c
Now that all targets set TCGCPUOps::cpu_exec_halt, we can make it
mandatory and remove the fallback handling that calls cpu_has_work.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
---
include/hw/core/tcg-cpu-ops.h | 9 ++---
accel/tcg/cpu-exec.c | 11
commit consolidates
constants `EXTI_NUM_INTERRUPT_OUT_LINES` (40) and
`EXTI_NUM_GPIO_EVENT_IN_LINES` (16) into `EXTI_NUM_LINES` (40).
Signed-off-by: Inès Varhol
Reviewed-by: Peter Maydell
Message-id: 20240707085927.122867-2-ines.var...@telecom-paris.fr
Signed-off-by: Peter Maydell
---
include/hw
We already have a load_cpu_field_low32() to load the low half of a
64-bit CPU struct field to a TCGv_i32; however we haven't yet needed
the store equivalent. We'll want that in the next patch, so
implement it.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/cpu.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 4c656bdbb76..a12859fc533 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3354,8 +3354,8 @@ extern
is correct, but it's perhaps a little
confusing. We would also like to make setting the cpu_exec_halt
method mandatory.
Initialize arm_v7m_tcg_ops cpu_exec_halt to the same function we use
for A-profile. (On M-profile we never set up the wfxt timer so there
is no change in behaviour her
ion for getting FPCR bits.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20240628142347.1283015-3-peter.mayd...@linaro.org
---
target/arm/cpu.h| 24 +++-
target/arm/vfp_helper.c | 34 ++
2 files changed, 37 in
On Tue, 2 Jul 2024 at 19:15, Zheyu Ma wrote:
>
> Hi Mark,
>
> On Mon, Jul 1, 2024 at 10:49 PM Mark Cave-Ayland
> wrote:
>>
>> On 30/06/2024 14:04, Zheyu Ma wrote:
>> What would happen if the source data plus length goes beyond the end of the
>> framebuffer but the destination lies completely wit
On Thu, 11 Jul 2024 at 12:54, Michael S. Tsirkin wrote:
>
> On Thu, Jul 11, 2024 at 11:52:03AM +0200, Mauro Carvalho Chehab wrote:
> > From: Jonathan Cameron
> >
> > Creates a GED - Generic Event Device and set a GPIO to
> > be used or error injection.
> >
> > Signed-off-by: Jonathan Cameron
> >
On Thu, 11 Jul 2024 at 08:25, Ani Sinha wrote:
>
> load_image_gzipped() does not seem to be used anywhere. Remove it.
>
> Signed-off-by: Ani Sinha
> ---
Reviewed-by: Peter Maydell
thanks
-- PMM
On Wed, 10 Jul 2024 at 18:35, Marcin Juszkiewicz
wrote:
>
> Neoverse-V1 TRM says that NumSets are [27:13] not :32 like in code.
NumSets in fields [27:13] is the 32-bit CCSIDR_EL1 format
(i.e. what you have when FEAT_CCIDX is not implemented).
The make_ccsidr64() function provides the 64-bit CCSID
On Tue, 9 Jul 2024 at 01:06, Richard Henderson
wrote:
>
> [Sorry about the @qemu.prg typo; resend for anyone replying.]
>
> A small set, but better than waiting for a larger set.
> It's a good stopping point, finishing the convertion of
>
> disas_simd_three_reg_diff
> disas_simd_scalar_three_r
On Wed, 10 Jul 2024 at 09:02, hellord wrote:
>
>
>>
>>
>> On Tue, Jul 9, 2024 at 10:39 PM Peter Maydell
>> wrote:
>> Is there a particular reason to use 128MB here? If the
>> runtime only fails on 4GB or more, maybe we should use
>> a larger MAX_C
On Mon, 8 Jul 2024 at 14:24, junjiehua wrote:
>
> when building elf2dump with x86_64-w64-mingw32-gcc, fwrite is imported from
> msvcrt.dll. However, the implementation of msvcrt.dll!fwrite is buggy:
> it enters an infinite loop when the size of a single write exceeds 4GB.
> This patch addresses th
On Tue, 9 Jul 2024 at 01:07, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
thanks
-- PMM
On Tue, 9 Jul 2024 at 01:07, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/tcg/translate-a64.c | 604 ++---
> target/arm/tcg/a64.decode | 33 ++
> 2 files changed, 138 insertions(+), 499 deletions(-)
On Tue, 9 Jul 2024 at 01:06, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/tcg/translate-a64.c | 127 +++--
> target/arm/tcg/a64.decode | 5 ++
> 2 files changed, 61 insertions(+), 71 deletions(-)
>
On Tue, 9 Jul 2024 at 01:08, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/tcg/translate-a64.c | 150 +
> target/arm/tcg/a64.decode | 9 ++
> 2 files changed, 87 insertions(+), 72 deletions(-)
Reviewed
On Tue, 9 Jul 2024 at 01:07, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/tcg/translate-a64.c | 184 -
> target/arm/tcg/a64.decode | 22
> 2 files changed, 156 insertions(+), 50 deletions(-)
On Tue, 9 Jul 2024 at 01:07, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/tcg/translate-a64.c | 86 +-
> target/arm/tcg/a64.decode | 5 ++
> 2 files changed, 48 insertions(+), 43 deletions(-)
Reviewed
emu-project/qemu/-/issues/2419
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 223eac3cac2..f873e8bc8b9 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/t
looking at the code: the LDAPR-register form incorrectly uses the
stricter check_atomic_align() rather than check_ordered_align()
(a bug that's been present since we added the FEAT_LSE2 support).
thanks
-- PMM
Peter Maydell (2):
target/arm: Fix handling of LDAPR/STLR with negative offset
targe
0b ("target/arm: Relax ordered/atomic alignment checks for
LSE2")
Signed-off-by: Peter Maydell
---
target/arm/tcg/translate-a64.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 6c07aeaf3bd..5ea204d50
On Tue, 9 Jul 2024 at 11:53, Alex Bennée wrote:
>
> Manos Pitsidianakis writes:
> > +msrv = {
> > + 'rustc': '1.77.2',
> > + 'cargo': '1.77.2',
> > + 'bindgen': '0.69.4',
> > +}
>
> This is still pretty bleeding edge (it even tripped up on the
> .cargo/bin/cargo I have installed). This needs t
On Mon, 8 Jul 2024 at 19:18, Roman Kiryanov wrote:
>
> void* pointer arithmetic is a GCC extentension
> which could not be available in other build tools
> (e.g. C++). This changes removes this assumption.
>
> Signed-off-by: Roman Kiryanov
We had the question on a previous "make this C++
compati
On Mon, 8 Jul 2024 at 08:49, Nicholas Piggin wrote:
>
> On Sun Jul 7, 2024 at 9:46 AM AEST, David Gibson wrote:
> > On Sat, Jul 06, 2024 at 11:37:08AM +0100, Peter Maydell wrote:
> > > On Fri, 5 Jul 2024 at 06:13, David Gibson
> > > wrote:
> > > > Huh..
ed-by: BALATON Zoltan
Signed-off-by: Peter Maydell
---
Does this help? I wrote the text and know what the functions do
to start with so it's a bit tricky for me to see where the docs
don't state things as clearly as they ought to do...
---
include/hw/qdev-core.h | 17 +
On Fri, 5 Jul 2024 at 01:32, BALATON Zoltan wrote:
>
> On Thu, 4 Jul 2024, Bernhard Beschow wrote:
> > Makes the code more comprehensible, matches the datasheet and the piix4
> > device
> > model.
> >
> > Signed-off-by: Bernhard Beschow
> > ---
> > hw/isa/vt82c686.c | 2 +-
> > hw/mips/fuloong2
On Sun, 7 Jul 2024 at 09:59, Inès Varhol wrote:
>
> STM32L4x5 EXTI was handling only configurable interrupts
> (such as those coming from STM32L4x5 SYSCFG which was the
> only device connected to the EXTI).
> This patch adds support for direct line interrupts and
> connects the existing STM32L4x5
0);
> +}
> +
> +int main(void)
> +{
> +static const struct sigaction sa = {
> +.sa_flags = SA_SIGINFO,
> +.sa_sigaction = sigsegv
> +};
> +size_t size;
> +int r;
> +
> +size = getpagesize();
> +ptr = mmap(NULL, size, PROT_READ | PROT_WRITE,
> + MAP_ANON | MAP_PRIVATE, -1, 0);
> +assert(ptr != MAP_FAILED);
> +
> +test();
> +
> +r = sigaction(SIGSEGV, &sa, NULL);
> +assert(r == 0);
> +r = mprotect(ptr, size, PROT_NONE);
> +assert(r == 0);
> +
> +test();
> +abort();
> +}
A few comments in this test program to explain what it's
doing would be helpful.
Otherwise
Reviewed-by: Peter Maydell
thanks
-- PMM
e they're a function where
the caller needs to be quite careful about what they're doing
(e.g. not to use them in a way that the memmove or memset
would cross a page boundary if other guest register state needs
to be kept in sync with the reported fault address), but I
can't think of a useful non-architecture-specific warning that
would be worth putting in the doc comments.
Reviewed-by: Peter Maydell
thanks
-- PMM
On Wed, 3 Jul 2024 at 00:43, Richard Henderson
wrote:
>
> While looking into Zoltan's attempt to speed up ppc64 DCBZ
> (data cache block set to zero), I wondered what AArch64 was
> doing differently. It turned out that Arm is the only user
> of tlb_vaddr_to_host.
riscv also seems to use it in ve
Thu Jul 4, 2024 at 10:15 PM AEST, Peter Maydell wrote:
> > > > > On Sat, 29 Jun 2024 at 04:17, David Gibson
> > > > > wrote:
> > > > > >
> > > > > > On Fri, Jun 28, 2024 at 04:20:02PM +0100, Peter Maydell wrote:
> > > &g
On Fri, 5 Jul 2024 at 12:46, Bernhard Beschow wrote:
> Am 27. Mai 2024 17:49:26 UTC schrieb Bernhard Beschow :
> >Am 27. Mai 2024 16:20:44 UTC schrieb Richard Henderson
> >:
> >>On 5/27/24 08:29, Bernhard Beschow wrote:
> >>> I think the kernel's output indicates that the MMU is active:
> >>>
> >
On Tue, 18 Jun 2024 at 21:32, Richard Henderson
wrote:
>
> On 6/18/24 13:15, Philippe Mathieu-Daudé wrote:
> > On 18/6/24 22:06, Richard Henderson wrote:
> >> Fails testing:
> >>
> >> https://gitlab.com/qemu-project/qemu/-/jobs/7129004955
> >>
> >> qemu-system-tricore: ../accel/tcg/cpu-exec.c:1082
On Tue, 2 Jul 2024 at 16:49, Richard Henderson
wrote:
>
> In a completely artifical memset benchmark object_dynamic_cast_assert
> dominates the profile, even above guest address resolution and
> the underlying host memset.
>
> Signed-off-by: Richard Henderson
Applied to target-arm.next, thanks
On Tue, 2 Jul 2024 at 16:41, Zheyu Ma wrote:
>
> The current implementation of bcm2835_thermal_ops sets
> impl.max_access_size and valid.min_access_size to 4, but leaves
> impl.min_access_size and valid.max_access_size unset, defaulting to 1.
> This causes issues when the memory system is presente
On Tue, 2 Jul 2024 at 17:18, Philippe Mathieu-Daudé wrote:
>
> On 2/7/24 17:57, Zheyu Ma wrote:
> > In pl011_get_baudrate(), when we calculate the baudrate we can
> > accidentally divide by zero. This happens because although (as the
> > specification requires) we treat UARTIBRD = 0 as invalid, we
On Fri, 28 Jun 2024 at 17:50, Richard Henderson
wrote:
>
> On 6/28/24 09:37, Philippe Mathieu-Daudé wrote:
> > On 28/6/24 16:31, Richard Henderson wrote:
> >> On 6/19/24 05:49, Philippe Mathieu-Daudé wrote:
> >>> Merge gdbstub64.c in gdbstub.c and remove uses of
> >>> target specific TARGET_AARCH6
On Sat, 29 Jun 2024 at 04:17, David Gibson wrote:
>
> On Fri, Jun 28, 2024 at 04:20:02PM +0100, Peter Maydell wrote:
> > On Thu, 27 Jun 2024 at 14:39, Akihiko Odaki
> > wrote:
> > >
> > > FDT properties are aligned by 4 bytes, not 8 bytes.
>
t; -X86MachineState *x86ms = X86_MACHINE(obj);;
> +X86MachineState *x86ms = X86_MACHINE(obj);
>
> visit_type_OnOffAuto(v, name, &x86ms->pit, errp);
> }
> --
> 2.34.1
Reviewed-by: Peter Maydell
thanks
-- PMM
On Thu, 4 Jul 2024 at 09:33, Zhao Liu wrote:
>
> Fix the superfluous trailing semicolon in target/hexagon/imported/mmvec/
> ext.idef.
>
> Cc: Brian Cain
> Signed-off-by: Zhao Liu
> ---
> target/hexagon/imported/mmvec/ext.idef | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --gi
ir(domain, type, protocol, sv);
> if (ret == 0) {
> qemu_set_cloexec(sv[0]);
> qemu_set_cloexec(sv[1]);
> --
> 2.34.1
>
Reviewed-by: Peter Maydell
thanks
-- PMM
s->value = g_new0(StatsValue, 1);;
> +stats->value = g_new0(StatsValue, 1);
>
> if ((pdesc->flags & KVM_STATS_UNIT_MASK) == KVM_STATS_UNIT_BOOLEAN) {
> stats->value->u.boolean = *stats_data;
Reviewed-by: Peter Maydell
thanks
-- PMM
On Wed, 3 Jul 2024 at 22:32, Zheyu Ma wrote:
>
> The sifive_plic_read function in hw/intc/sifive_plic.c had a potential
> heap-buffer-overflow issue when reading from the pending_base region.
> This occurred because the code did not check if the calculated word index
> was within valid bounds befo
umber of ways, with the two
> -main methods being email and IRC
> +main methods being email and IRC:
>
> * `<mailto:qemu-devel@nongnu.org>`_
> * `<https://lists.nongnu.org/mailman/listinfo/qemu-devel>`_
> --
> 2.34.1
(cc'ing qemu-trivial)
Reviewed-by: Peter Maydell
thanks
-- PMM
On Tue, 2 Jul 2024 at 16:50, Philippe Mathieu-Daudé wrote:
> Personally I consider accepting access of
>
>.valid.min_access_size > .impl.min_access_size
>
> as a bug in the memory core layer, whether being
> unaligned or not.
Mmm. You could make an argument for
.valid: min_access_size = 4,
Signed-off-by: Peter Maydell
---
hw/misc/zynq_slcr.c | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c
index 3412ff099ea..ad814c3a79b 100644
--- a/hw/misc/zynq_slcr.c
+++ b/hw/misc/zynq_slcr.c
@@ -24,6 +24,8
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240625183536.1672454-10-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 4
target/arm/tcg/translate-a64.c | 36
From: Richard Henderson
Input denormals cause the Javascript inexact bit
(output to Z) to be set.
Cc: qemu-sta...@nongnu.org
Fixes: 6c1f6f2733a ("target/arm: Implement ARMv8.3-JSConv")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2375
Reviewed-by: Peter Maydell
Sig
From: Rayhan Faizel
The OTP device registers are currently stubbed. For now, the device
houses the OTP rows which will be accessed directly by other peripherals.
Signed-off-by: Rayhan Faizel
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
include/hw/nvram/bcm2835_otp.h | 68
Inès Varhol
Message-id: 20240629104454.366283-1-ines.var...@telecom-paris.fr
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
tests/qtest/stm32l4x5_syscfg-test.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/tests/qtest/stm32l4x5_syscfg-t
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240625183536.1672454-7-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 3 +++
target/arm/tcg/translate-a64.c | 35
From: Richard Henderson
MLA, MLS, SQDMULH, SQRDMULH, were converted with 8db93dcd3def
and f80701cb44d, and this code should have been removed then.
Signed-off-by: Richard Henderson
Message-id: 20240625183536.1672454-14-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
Reviewed-by
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240625183536.1672454-11-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/translate-a64.c | 52 +-
1 file changed, 26 insertions(+), 26
From: Gustavo Romero
Fix comment indentation adding a missing space.
Signed-off-by: Gustavo Romero
Reviewed-by: Richard Henderson
Message-id: 20240624180915.4528-2-gustavo.rom...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/cpu64.c | 2 +-
1 file changed, 1 insertion(+), 1
: Richard Henderson
Message-id: 20240624180915.4528-4-gustavo.rom...@linaro.org
Signed-off-by: Peter Maydell
---
docs/system/arm/emulation.rst | 1 +
target/arm/tcg/cpu32.c| 6 +++---
target/arm/tcg/cpu64.c| 2 +-
3 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/docs
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240625183536.1672454-5-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/helper.h| 10 ++
target/arm/tcg/a64.decode | 16 +++
target/arm/tcg/translate
From: Richard Henderson
Signed-off-by: Richard Henderson
Message-id: 20240625183536.1672454-13-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
Reviewed-by: Peter Maydell
---
target/arm/tcg/a64.decode | 6 +
target/arm/tcg/translate-a64.c | 238
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240625183536.1672454-12-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 3 +++
target/arm/tcg/translate-a64.c | 33
-ines.var...@telecom-paris.fr
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
include/hw/misc/stm32l4x5_exti.h | 2 ++
hw/misc/stm32l4x5_exti.c | 28 +---
2 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/include/hw/misc/stm32l4x5_exti.h
From: Rayhan Faizel
Replace stubbed OTP memory region with the new OTP device.
Signed-off-by: Rayhan Faizel
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
include/hw/arm/bcm2835_peripherals.h | 3 ++-
hw/arm/bcm2835_peripherals.c | 13 -
2 files changed, 14
From: Patrick Leis
Signed-off-by: Patrick Leis
Message-id: 20240626211623.3510701-1-vent...@google.com
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 19f67dc5d21
Henderson
Message-id: 20240624180915.4528-3-gustavo.rom...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/cpu.h | 2 ++
target/arm/tcg/cpu32.c | 31 ---
2 files changed, 30 insertions(+), 3 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240625183536.1672454-8-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 2 ++
target/arm/tcg/translate-a64.c | 20 +---
2 files
From: Sai Pavan Boddu
Read boot-mode value as machine property and propagate that to
SLCR.BOOT_MODE register.
Signed-off-by: Sai Pavan Boddu
Acked-by: Edgar E. Iglesias
Reviewed-by: Francisco Iglesias
Message-id: 20240621125906.1300995-3-sai.pavan.bo...@amd.com
Signed-off-by: Peter Maydell
u/-/issues/2376
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240625183536.1672454-2-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/vec_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/tcg/vec_
lue before and after each
QTest, this commit toggles back the irq lines that were changed at the
end of each problematic test. Most QTests were already doing this.
Signed-off-by: Inès Varhol
Message-id: 20240629110800.539969-3-ines.var...@telecom-paris.fr
Reviewed-by: Peter Maydell
Signed-off
.
Signed-off-by: Marcin Juszkiewicz
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Message-id: 20240620-b4-new-firmware-v3-1-29a3a2f1b...@linaro.org
Signed-off-by: Peter Maydell
---
tests/avocado/machine_aarch64_sbsaref.py | 14 +++---
1 file changed, 7 insertions
From: Nicolin Chen
The caller of smmu_iommu_mr wants to get sdev for smmuv3_flush_config().
Do it directly instead of bridging with an iommu mr pointer.
Signed-off-by: Nicolin Chen
Message-id: 20240619002218.926674-1-nicol...@nvidia.com
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
From: Sai Pavan Boddu
Added the supported device list and an example command.
Signed-off-by: Sai Pavan Boddu
Reviewed-by: Edgar E. Iglesias
Reviewed-by: Francisco Iglesias
Message-id: 20240621125906.1300995-4-sai.pavan.bo...@amd.com
Signed-off-by: Peter Maydell
---
MAINTAINERS
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240625183536.1672454-9-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 2 +
target/arm/tcg/translate-a64.c | 77
: Peter Maydell
Signed-off-by: Peter Maydell
---
include/hw/arm/raspberrypi-fw-defs.h | 2 +
include/hw/misc/bcm2835_property.h | 2 +
hw/arm/bcm2835_peripherals.c | 2 +
hw/misc/bcm2835_property.c | 87
4 files changed, 93 insertions(+)
diff
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240625183536.1672454-6-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 7 +
target/arm/tcg/translate-a64.c | 54
From: Richard Henderson
The inner loop, bounded by eltspersegment, must not be
larger than the outer loop, bounded by elements.
Cc: qemu-sta...@nongnu.org
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240625183536.1672454-3-richard.hender...@linaro.org
Signed-off
mware-v3-2-29a3a2f1b...@linaro.org
Signed-off-by: Peter Maydell
---
tests/avocado/machine_aarch64_sbsaref.py | 2 --
1 file changed, 2 deletions(-)
diff --git a/tests/avocado/machine_aarch64_sbsaref.py
b/tests/avocado/machine_aarch64_sbsaref.py
index e854ec6a1af..e920bbf08c1 100644
The following changes since commit b6d32a06fc0984e537091cba08f2e1ed9f775d74:
Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into
staging (2024-06-30 16:12:24 -0700)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-targ
n big-endian.
>
> Signed-off-by: Philippe Mathieu-Daudé
> Tested-by: Cédric Le Goater
> ---
> RFC because I'm surprised this has been unnoticed for 17 years
> (commit a1bb27b1e9 "initial SD card emulation", April 2007).
>
> Cc: Peter Maydell
> ---
> h
off-by: Philippe Mathieu-Daudé
> Tested-by: Cédric Le Goater
> ---
> RFC because I'm surprised this has been unnoticed for 17 years
> (commit a1bb27b1e9 "initial SD card emulation", April 2007).
>
> Cc: Peter Maydell
> ---
> hw/sd/sd.c | 2 +-
> 1 file chan
On Mon, 1 Jul 2024 at 16:07, Konstantin Ryabitsev
wrote:
>
> On Mon, Jul 01, 2024 at 09:00:48PM GMT, Akihiko Odaki wrote:
> > > > Signed-off-by: Akihiko Odaki
> > >
> > > PS: you don't need to put a signed-off-by line on the cover
> > > letter, only in the individual patches.
> >
> > I have been
On Mon, 24 Jun 2024 at 17:20, Marcin Juszkiewicz
wrote:
>
> FreeBSD has longer support cycle for stable release (14.x EoL in 2028)
> than OpenBSD (7.3 we used is already EoL). Also bugfixes are backported
> so we can stay on 14.x for longer. Tests done on OpenBSD will now be
> done using FreeBSD.
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