Re: [PATCH 2/3] target/arm: Always add pmu property

On Mon, 1 Jul 2024 at 13:17, Akihiko Odaki wrote: > > On 2024/07/01 20:54, Peter Maydell wrote: > > On Sat, 29 Jun 2024 at 13:51, Akihiko Odaki > > wrote: > >> > >> kvm-steal-time and sve properties are added for KVM even if the > >> correspondi

Re: [PATCH] Remove inclusion of hw/hw.h from files that don't need it

On Mon, 1 Jul 2024 at 14:27, Thomas Huth wrote: > > hw/hw.h only contains the prototype of hw_error() nowadays, so > files that don't use this function don't need to include this > header. > > Signed-off-by: Thomas Huth Reviewed-by: Peter Maydell thanks -- PMM

Re: [PATCH] hw/misc/bcm2835_thermal: Handle invalid address accesses gracefully

On Mon, 1 Jul 2024 at 12:18, Philippe Mathieu-Daudé wrote: > > Hi Zheyu, > > On 30/6/24 17:14, Zheyu Ma wrote: > > This commit handles invalid address accesses gracefully in both read and > > write > > functions. Instead of asserting and aborting, it logs an error message and > > returns > > a n

Re: [PATCH 2/2] hw/isa/vt82c686.c: Embed i8259 irq in device state instead of allocating

On Sat, 29 Jun 2024 at 21:01, BALATON Zoltan wrote: > > To avoid a warning about unfreed qemu_irq embed the i8259 irq in the > device state instead of allocating it. > > Signed-off-by: BALATON Zoltan > --- > hw/isa/vt82c686.c | 7 --- > 1 file changed, 4 insertions(+), 3 deletions(-) > > dif

Re: [PATCH 1/2] hw: Move declaration of IRQState to header and add init function

On Sat, 29 Jun 2024 at 21:01, BALATON Zoltan wrote: > > To allow embedding a qemu_irq in a struct move its definition to the > header and add a function to init it in place without allocating it. > > Signed-off-by: BALATON Zoltan Yes, I think this makes sense, and I'm not quite sure why we don't

Re: [PATCH] hw/usb: Fix memory leak in musb_reset()

On Sun, 30 Jun 2024 at 17:33, Zheyu Ma wrote: > > The musb_reset function was causing a memory leak by not properly freeing > the memory associated with USBPacket instances before reinitializing them. > This commit addresses the memory leak by adding calls to usb_packet_cleanup > for each USBPacke

Re: [PATCH] hw/char/pl011: ensure UARTIBRD register is 16-bit

On Sun, 30 Jun 2024 at 18:00, Zheyu Ma wrote: > > The PL011 TRM says that "The 16-bit integer is written to the Integer Baud > Rate > Register, UARTIBRD". Updated the handling of the UARTIBRD register to ensure > only 16-bit values are written to it. Thanks for this patch. I think we could impr

Re: [PATCH 2/3] target/arm: Always add pmu property

On Sat, 29 Jun 2024 at 13:51, Akihiko Odaki wrote: > > kvm-steal-time and sve properties are added for KVM even if the > corresponding features are not available. Always add pmu property too. > > Signed-off-by: Akihiko Odaki > --- > target/arm/cpu.c | 3 ++- > 1 file changed, 2 insertions(+), 1

Re: [PATCH 0/2] hw/misc: Fix STM32L4x5 EXTI interrupts

On Sat, 29 Jun 2024 at 12:08, Inès Varhol wrote: > > STM32L4x5 EXTI was incorrectly expecting alternating interrupts. > This patch adds a new field to track IRQ levels to actually > *detect* edges. > It also corrects existing QTests which were modifying the IRQ lines' > levels. > > Signed-off-by:

Re: [PATCH] tests/qtest: Fix STM32L4x5 SYSCFG irq line 15 state assumption

On Sat, 29 Jun 2024 at 11:46, Inès Varhol wrote: > > The QTest `test_irq_pin_multiplexer` makes the assumption that the > reset state of irq line 15 is low, which is false since STM32L4x5 GPIO > was implemented (the reset state of pin GPIOA15 is high because there's > pull-up and it results in the

Re: [PATCH 0/4] Drop ifdef for macOS versions older than 12.0

the vendor itself drops > > support, whichever comes first. > > macOS 12.0 was released 2021: > https://www.apple.com/newsroom/2021/10/macos-monterey-is-now-available/ Further, we have already dropped support for macos < 12 in the ui/cocoa.m code in commit 2d27c91e2b72ac. For th

Re: [PATCH v3 1/2] tests/avocado: update firmware for sbsa-ref

On Mon, 1 Jul 2024 at 07:49, Marcin Juszkiewicz wrote: > > W dniu 30.06.2024 o 16:37, Ard Biesheuvel pisze: > > On Thu, 20 Jun 2024 at 12:20, Marcin Juszkiewicz > > wrote: > >> > >> Update firmware to have graphics card memory fix from EDK2 commit > >> c1d1910be6e04a8b1a73090cf2881fb698947a6e: >

Re: [PATCH] virtio: remove virtio_tswap16s() call in vring_packed_event_read()

ic void vring_packed_event_read(VirtIODevice *vdev, > /* Make sure flags is seen before off_wrap */ > smp_rmb(); > e->off_wrap = virtio_lduw_phys_cached(vdev, cache, off_off); > -virtio_tswap16s(vdev, &e->flags); > } Reviewed-by: Peter Maydell thanks -- PMM

Re: [PATCH v6 06/11] target/arm: Factor out code for setting MTE TCF0 field

On Fri, 28 Jun 2024 at 19:13, Gustavo Romero wrote: > Re-reading it after your clarifications makes it clear, but the first time > Phil pointed it out the phrases: > > "[...] since the .c file will have already included it." and > "Headers should normally include everything they need beyond osdep.

Re: [PATCH 4/9] target/arm: Support migration when FPSR/FPCR won't fit in the FPSCR

On Fri, 28 Jun 2024 at 17:01, Richard Henderson wrote: > > On 6/28/24 07:23, Peter Maydell wrote: > > To support FPSR and FPCR bits that don't exist in the AArch32 FPSCR > > view of floating point control and status (such as the FEAT_AFP ones), > > we need to make su

Re: [PATCH] hw/ide/macio.c: switch from using qemu_allocate_irq() to qdev input GPIOs

b54da6b31..869b66055b 100644 > --- a/include/hw/misc/macio/macio.h > +++ b/include/hw/misc/macio/macio.h > @@ -92,6 +92,11 @@ struct MACIOIDEState { > uint32_t irq_reg; > }; > > +#define MACIO_IDE_PMAC_NIRQS 2 > + > +#define MACIO_IDE_PMAC_DMA_IRQ 0 > +#define MACIO_IDE

Re: [PATCH v2 15/15] tests/qtest: Free GThread

On Thu, 27 Jun 2024 at 14:41, Akihiko Odaki wrote: > > These GThreads are never referenced. > > Signed-off-by: Akihiko Odaki > --- Reviewed-by: Peter Maydell thanks -- PMM

Re: [PATCH v2 12/15] tests/qtest: Free old machine variable name

t; qemu_var = g_strdup(var); > > /* new qemu, clear the cache */ > > -- > 2.45.2 Reviewed-by: Peter Maydell thanks -- PMM

Re: [PATCH v2 06/15] ppc/vof: Fix unaligned FDT property access

*(uint32_t *)(mem0_reg + sizeof(uint32_t) * > ac)); > } I did wonder if there was a better way to do what this is doing, but neither we (in system/device_tree.c) nor libfdt seem to provide one. Reviewed-by: Peter Maydell thanks -- PMM

Re: [PATCH v2 01/15] cpu: Free cpu_ases

On Thu, 27 Jun 2024 at 14:39, Akihiko Odaki wrote: > > This fixes LeakSanitizer warnings. > > Signed-off-by: Akihiko Odaki > --- > hw/core/cpu-common.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c > index f131cde2c038..a3073c17d098 100644 >

Re: [PATCH] hw/usb/hcd-ohci: Set transfer error code with no dev

On Sat, 22 Jun 2024 at 13:57, Ryan Wendland wrote: > > When a usb device is disconnected the transfer service functions bails > before appropraite transfer error flags are set. (typo: "appropriate") > This patch sets the appropriate condition code OHCI_CC_DEVICENOTRESPONDING > when a device is d

Re: [Bug Report] Possible Missing Endianness Conversion

On Tue, 25 Jun 2024 at 08:18, Stefano Garzarella wrote: > > On Mon, Jun 24, 2024 at 04:19:52PM GMT, Peter Maydell wrote: > >On Mon, 24 Jun 2024 at 16:11, Stefano Garzarella wrote: > >> > >> CCing Jason. > >> > >> On Mon, Jun 24, 2024 at 4:30 P

Re: [PATCH v4 0/3] Add boot-mode property for zynq

On Fri, 21 Jun 2024 at 13:59, Sai Pavan Boddu wrote: > > Add a way to update the boot-mode via machine properties. > > Changes for V2: > Make boot-mode property work with string, > Fixed few code style issues, > Added zynq board doc. > Changes for V3: > Mentioned about zynq doc in

Re: [PATCH] MAINTAINERS: Update my family name

On Wed, 26 Jun 2024 at 22:16, Patrick Leis wrote: > > Signed-off-by: Patrick Leis > --- > MAINTAINERS | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/MAINTAINERS b/MAINTAINERS > index 19f67dc5d2..13255d4a3b 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -2496,7 +249

Re: [PATCH v3 0/3] target/arm: Enable FEAT_Debugv8p8 for -cpu max

On Mon, 24 Jun 2024 at 19:09, Gustavo Romero wrote: > > Enable FEAT_Debugv8p8 on Arm max CPU. > > v2: > - Revert to the original comment above call to aa32_max_features() > > v3: > - Added feature entry to docs/system/arm/emulation.rst > - Explicitly set t=0 before using it to set DBGDEVID reg.

Re: [PATCH v2 00/13] target/arm: AdvSIMD conversion, part 2

On Tue, 25 Jun 2024 at 19:41, Richard Henderson wrote: > > Convert another hand-full of instructions, plus fixes > for two issues that are related. > > Applied to target-arm.next, thanks. -- PMM

[PATCH 3/9] target/arm: Make vfp_set_fpscr() call vfp_set_{fpcr, fpsr}

away then. Signed-off-by: Peter Maydell --- target/arm/cpu.h| 22 + target/arm/vfp_helper.c | 100 ++-- 2 files changed, 78 insertions(+), 44 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 68a9922f88e..0a570afcab4 100644

[PATCH 8/9] target/arm: Rename FPSR_MASK and FPCR_MASK and define them symbolically

AArch64 register, and define them symbolically rather than as hex values. (This latter requires defining some extra macros for bits which we haven't previously defined.) Signed-off-by: Peter Maydell --- target/arm/cpu.h| 41 ++--- target/arm/mach

[PATCH 7/9] target/arm: Rename FPCR_ QC, NZCV macros to FPSR_

The QC, N, Z, C, V bits live in the FPSR, not the FPCR. Rename the macros that define these bits accordingly. Signed-off-by: Peter Maydell --- target/arm/cpu.h | 17 ++--- target/arm/tcg/mve_helper.c | 8 target/arm/tcg/translate-m-nocp.c | 16

[PATCH 0/9] target/arm: Refactor FPCR/FPSR handling to prepare for FEAT_AFP

sr fields, rather than in vfp.xregs[ARM_VFP_FPSCR] * we make sure that writes to FPSCR leave bits in FPCR that aren't in FPSCR alone The series also has a bit of tidyup of some of the macro naming etc. thanks -- PMM Peter Maydell (9): target/arm: Correct comments about M-pr

[PATCH 2/9] target/arm: Make vfp_get_fpscr() call vfp_get_{fpcr, fpsr}

ion for getting FPCR bits. Signed-off-by: Peter Maydell --- target/arm/cpu.h| 24 +++- target/arm/vfp_helper.c | 34 ++ 2 files changed, 37 insertions(+), 21 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 3841359d0

[PATCH 6/9] target/arm: Store FPSR and FPCR in separate CPU state fields

ey're only 32 bit registers). Signed-off-by: Peter Maydell --- target/arm/cpu.h | 7 +++ target/arm/tcg/translate.h| 3 +-- target/arm/tcg/mve_helper.c | 12 ++-- target/arm/tcg/translate-m-nocp.c | 6 +++--- target/arm/tcg/translate-vfp.c| 2

[PATCH 9/9] target/arm: Allow FPCR bits that aren't in FPSCR

which takes a mask of which bits to update. (We could do the same for FPSR, but we leave that until we actually are likely to need it.) Signed-off-by: Peter Maydell --- target/arm/vfp_helper.c | 54 ++--- 1 file changed, 34 insertions(+), 20 deletions(-) diff

[PATCH 1/9] target/arm: Correct comments about M-profile FPSCR

The M-profile FPSCR LTPSIZE is bits [18:16]; this is the same field as A-profile FPSCR Len, not Stride. Correct the comment in vfp_get_fpscr(). We also implemented M-profile FPSCR.QC, but forgot to delete a TODO comment from vfp_set_fpscr(); remove it now. Signed-off-by: Peter Maydell

[PATCH 4/9] target/arm: Support migration when FPSR/FPCR won't fit in the FPSCR

n the high half of either register. (We won't ever send the new migration subsection until we add support for a CPU feature which enables setting overlapping FPCR bits, like FEAT_AFP.) Signed-off-by: Peter Maydell --- target/arm/machine.c | 134 ++-

[PATCH 5/9] target/arm: Implement store_cpu_field_low32() macro

We already have a load_cpu_field_low32() to load the low half of a 64-bit CPU struct field to a TCGv_i32; however we haven't yet needed the store equivalent. We'll want that in the next patch, so implement it. Signed-off-by: Peter Maydell --- target/arm/tcg/translate-a32.h | 7 +

Re: linux-user cannot allocate stack memory on riscv64 host due to non-zero guest_base

On Thu, 27 Jun 2024 at 15:27, Andreas Schwab wrote: > Perhaps you should refrain from attacking the volunteers that report > bugs. I think the tone of your previous email was extremely terse and didn't actually answer the question, which is quite easy to misinterpret as hostility. We're all tryi

Re: [PATCH 02/14] hw/ide: Free macio-ide IRQs

On Wed, 26 Jun 2024 at 12:09, Akihiko Odaki wrote: > > This suppresses LeakSanitizer warnings. > > Signed-off-by: Akihiko Odaki > --- > hw/ide/macio.c | 9 + > 1 file changed, 9 insertions(+) > > diff --git a/hw/ide/macio.c b/hw/ide/macio.c > index aca90d04f0e8..d8fbc1a17ba6 100644 > ---

Re: [PATCH 03/14] hw/isa/vt82c686: Free irqs

On Wed, 26 Jun 2024 at 12:08, Akihiko Odaki wrote: > > This suppresses LeakSanitizer warnings. > > Signed-off-by: Akihiko Odaki > --- > hw/isa/vt82c686.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c > index 8582ac0322eb..189b487

Re: [RFC PATCH v3 5/5] DO NOT MERGE: replace TYPE_PL011 with x-pl011-rust in arm virt machine

On Tue, 25 Jun 2024 at 20:15, Daniel P. Berrangé wrote: > > On Wed, Jun 26, 2024 at 12:18:55AM +0800, Zhao Liu wrote: > > Hi Manos, > > > > On Wed, Jun 19, 2024 at 11:14:02PM +0300, Manos Pitsidianakis wrote: > > > Date: Wed, 19 Jun 2024 23:14:02 +0300 > > > From: Manos Pitsidianakis > > > Subjec

Re: [PATCH 13/13] target/arm: Delete dead code from disas_simd_indexed

On Tue, 25 Jun 2024 at 15:18, Richard Henderson wrote: > > On 6/25/24 05:41, Peter Maydell wrote: > > On Tue, 25 Jun 2024 at 06:09, Richard Henderson > > wrote: > >> > >> The last insns in this block, MLA and MLS, were converted > >> with f80701cb44d

Re: [PULL 00/46] virtio: features,fixes

On Tue, 4 Jun 2024 at 20:06, Michael S. Tsirkin wrote: > > virtio: features,fixes > > A bunch of improvements: > - vhost dirty log is now only scanned once, not once per device > - virtio and vhost now support VIRTIO_F_NOTIFICATION_D

Re: [PATCH 10/13] target/arm: Add data argument to do_fp3_vector

On Tue, 25 Jun 2024 at 06:10, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/tcg/translate-a64.c | 52 +- > 1 file changed, 26 insertions(+), 26 deletions(-) Reviewed-by: Peter Maydell thanks -- PMM

Re: [PATCH 09/13] target/arm: Convert BFMMLA, SMMLA, UMMLA, USMMLA to decodetree

On Tue, 25 Jun 2024 at 06:09, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/tcg/a64.decode | 4 > target/arm/tcg/translate-a64.c | 36 -- > 2 files changed, 12 insertions(+), 28 deletions(-) >

Re: [PATCH 07/13] target/arm: Convert BFDOT to decodetree

On Tue, 25 Jun 2024 at 06:09, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/tcg/a64.decode | 2 ++ > target/arm/tcg/translate-a64.c | 20 +--- > 2 files changed, 7 insertions(+), 15 deletions(-) Reviewed-by: Peter Maydell thanks -- PMM

Re: [PATCH 11/13] target/arm: Convert FCADD to decodetree

On Tue, 25 Jun 2024 at 06:09, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/tcg/a64.decode | 3 +++ > target/arm/tcg/translate-a64.c | 33 ++--- > 2 files changed, 13 insertions(+), 23 deletions(-) >

Re: [PATCH 13/13] target/arm: Delete dead code from disas_simd_indexed

tcg_op, tcg_idx); > -} else { > -gen_helper_neon_qrdmulh_s32(tcg_res, tcg_env, > - tcg_op, tcg_idx); > -} > -break; Otherwise Reviewed-by: Peter Maydell thanks -- PMM

Re: [PATCH 05/13] target/arm: Convert SDOT, UDOT to decodetree

On Tue, 25 Jun 2024 at 06:10, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/tcg/a64.decode | 7 + > target/arm/tcg/translate-a64.c | 54 ++ > 2 files changed, 35 insertions(+), 26 deletions(-) >

Re: [PATCH 08/13] target/arm: Convert BFMLALB, BFMLALT to decodetree

On Tue, 25 Jun 2024 at 06:10, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/tcg/a64.decode | 2 + > target/arm/tcg/translate-a64.c | 77 +- > 2 files changed, 31 insertions(+), 48 deletions(-) > Revie

Re: [PATCH 04/13] target/arm: Convert SQRDMLAH, SQRDMLSH to decodetree

/arm/tcg/vec_helper.c| 72 ++++ Reviewed-by: Peter Maydell thanks -- PMM

Re: [PATCH 06/13] target/arm: Convert SUDOT, USDOT to decodetree

On Tue, 25 Jun 2024 at 06:09, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/tcg/a64.decode | 3 +++ > target/arm/tcg/translate-a64.c | 35 -- > 2 files changed, 11 insertions(+), 27 deletions(-) Reviewed

Re: [PATCH 12/13] target/arm: Convert FCMLA to decodetree

On Tue, 25 Jun 2024 at 06:09, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/tcg/a64.decode | 5 + > target/arm/tcg/translate-a64.c | 241 ++--- > 2 files changed, 76 insertions(+), 170 deletions(-) > > diff --git a/target/arm/

Re: [PATCH 03/13] target/arm: Fix FJCVTZS vs flush-to-zero

+ "cset %1, eq" > + : "=r"(r), "=r"(z) > + : "r"(0x0100L), /* FZ = 1 */ > + "w"(0xfcff00L)); /* denormal */ > + > +assert(r == 0); > +assert(z == 0); > +return 0; > +} Otherwise Reviewed-by: Peter Maydell (If these are the only issues in the patchset I'll fix them up when I apply it.) thanks -- PMM

Re: [PATCH 02/13] target/arm: Fix SQDMULH (by element) with Q=0

On Tue, 25 Jun 2024 at 06:09, Richard Henderson wrote: > > The inner loop, bounded by eltspersegment, must not be > larger than the outer loop, bounded by elements. > > Cc: qemu-sta...@nongnu.org > Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell thanks -- PMM

Re: [PATCH 01/13] target/arm: Fix VCMLA Dd, Dn, Dm[idx]

gt; (indexed)") > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2376 > Signed-off-by: Richard Henderson > --- Reviewed-by: Peter Maydell thanks -- PMM

Re: [PATCH 1/1] include/qemu: Provide a C++ compatible version of typeof_strip_qual

On Tue, 25 Jun 2024 at 10:27, Peter Maydell wrote: > > On Tue, 25 Jun 2024 at 07:19, Philippe Mathieu-Daudé > wrote: > > > > On 25/6/24 08:05, Paolo Bonzini wrote: > > > > > > > > > Il mar 25 giu 2024, 04:32 Roman Kiryanov > > <mailto:

Re: [PATCH 1/1] include/qemu: Provide a C++ compatible version of typeof_strip_qual

On Tue, 25 Jun 2024 at 07:19, Philippe Mathieu-Daudé wrote: > > On 25/6/24 08:05, Paolo Bonzini wrote: > > > > > > Il mar 25 giu 2024, 04:32 Roman Kiryanov > > ha scritto: > > > > Hi Philippe, thank you for looking. > > > > On Mon, Jun 24, 2024 at 7:27 PM Philippe

Re: [PATCH 1/2] qom: Rename Object::class into Object::klass

On Tue, 25 Jun 2024 at 03:20, Philippe Mathieu-Daudé wrote: > Since you are posting different C++ enablement cleanups, > I suggest you add a section in our docs/devel/style.rst > requesting to keep headers C++ compatible, by not using > C++ reserved keywords, etc... > > In particular because the m

Re: [QEMU PATCH v2 1/1] hw/arm: FW first ARM processor error injection

On Mon, 24 Jun 2024 at 16:40, wrote: > > From: Shiju Jose > > Add support for QEMU based FW first ARM processor error injection. > +++ b/hw/arm/arm_error_inject_stubs.c > @@ -0,0 +1,22 @@ > +/* > + * ARM Processor errors QMP stubs > + * > + * Copyright(C) 2024 Huawei LTD. > + * > + * This work

Re: [Bug Report] Possible Missing Endianness Conversion

On Mon, 24 Jun 2024 at 16:11, Stefano Garzarella wrote: > > CCing Jason. > > On Mon, Jun 24, 2024 at 4:30 PM Xoykie wrote: > > > > The virtio packed virtqueue support patch[1] suggests converting > > endianness by lines: > > > > virtio_tswap16s(vdev, &e->off_wrap); > > virtio_tswap16s(vdev, &e->f

Re: linux-user crash in python test

On Mon, 24 Jun 2024 at 15:20, Andreas Schwab wrote: > > $ /usr/bin/python3.11 -m unittest -v > test.test_signal.StressTest.test_stress_modifying_handlers > test_stress_modifying_handlers > (test.test_signal.StressTest.test_stress_modifying_handlers) ... ok > > ---

Re: [PATCH v1 1/2] aspeed/soc: fix coverity issue

On Mon, 24 Jun 2024 at 14:58, Cédric Le Goater wrote: > > On 6/24/24 2:18 PM, Peter Maydell wrote: > > On Wed, 19 Jun 2024 at 10:35, Jamin Lin wrote: > >> > >> Fix coverity defect: DIVIDE_BY_ZERO. > >> > >> Signed-off-by: Jamin Lin > >&g

Re: [RFC PATCH 1/1] hw/arm: FW first ARM processor error injection.

On Fri, 21 Jun 2024 at 17:52, shiju.jose--- via wrote: > > From: Shiju Jose > > diff --git a/hw/arm/arm_error_inject.c b/hw/arm/arm_error_inject.c > new file mode 100644 > index 00..953a9d6705 > --- /dev/null > +++ b/hw/arm/arm_error_inject.c > @@ -0,0 +1,49 @@ > +/* > + * CXL Type 3 (

Re: [PATCH] hw/arm/smmu-common: Replace smmu_iommu_mr with smmu_find_sdev

On Wed, 19 Jun 2024 at 01:22, Nicolin Chen wrote: > > The caller of smmu_iommu_mr wants to get sdev for smmuv3_flush_config(). > > Do it directly instead of bridging with an iommu mr pointer. > > Signed-off-by: Nicolin Chen > --- > hw/arm/smmu-common.c | 8 ++-- > hw/arm/smmuv3.c

Re: [PATCH v3 0/2] tests/avocado: make sbsa-ref working with >1 core

ange drops "-smp 1" from CI to make sure we test default setup > of sbsa-ref. > > Previous firmware worked with 1 cpu by pure luck probably. > > To: qemu-devel@nongnu.org > Cc: qemu-...@nongnu.org, > Cc: Peter Maydell , > Cc: Leif Lindholm , > Cc: Radoslaw Biern

Re: [PATCH v2 2/2] target/arm: Enable FEAT_Debugv8p8 for -cpu max

On Fri, 21 Jun 2024 at 15:39, Gustavo Romero wrote: > > Enable FEAT_Debugv8p8 for max CPU. This feature is out of scope for QEMU > since it concerns the external debug interface for JTAG, but is > mandatory in Armv8.8 implementations, hence it is reported as supported > in the ID registers. > > Si

Re: [PATCH v2 1/2] target/arm: Move initialization of debug ID registers

On Fri, 21 Jun 2024 at 15:39, Gustavo Romero wrote: > > Move the initialization of the debug ID registers to aa32_max_features, > which is used to set the 32-bit ID registers. This ensures that the > debug ID registers are consistently set for the max CPU in a single > place. > > Signed-off-by: Gu

Re: [PATCH v1 1/2] aspeed/soc: fix coverity issue

On Wed, 19 Jun 2024 at 10:35, Jamin Lin wrote: > > Fix coverity defect: DIVIDE_BY_ZERO. > > Signed-off-by: Jamin Lin > --- > hw/arm/aspeed_ast27x0.c | 6 ++ > 1 file changed, 6 insertions(+) > > diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c > index b6876b4862..d14a46df6f 100

Re: [PATCH] hw/ufs: Fix potential bugs in MMIO read|write

register region. We also updated (uint8_t *) to (uint32_t *) to > represent we are accessing the MMIO registers by dword-sized only. > > [1] > https://lore.kernel.org/qemu-devel/cafeaca82l-wznhmw0x+dr40bhm-evq2zh4dg4pdqop4xxdp...@mail.gmail.com/ > > Cc: Jeuk Kim > Reporte

Re: [PATCH v3 0/3] Initial support for One-Time Programmable Memory (OTP) in BCM2835

On Mon, 24 Jun 2024 at 10:12, Rayhan Faizel wrote: > > Hi, > > The patch series is still not merged. Oops, sorry about that -- not sure how it got lost. I have applied it to target-arm.next for real this time... -- PMM

[PULL 17/18] hw/usb/hcd-ohci: Fix ohci_service_td: accept zero-length TDs where CBP=BE+1

From: David Hubbard This changes the way the ohci emulation handles a Transfer Descriptor with "Buffer End" set to "Current Buffer Pointer" - 1, specifically in the case of a zero-length packet. The OHCI spec 4.3.1.2 Table 4-2 specifies td.cbp to be zero for a zero-length pa

[PULL 06/18] scripts/coverity-scan/COMPONENTS.md: Fix 'char' component

tching our current sources. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 20240604145934.1230583-3-peter.mayd...@linaro.org --- scripts/coverity-scan/COMPONENTS.md | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/scripts/coverity-scan/COMPON

[PULL 04/18] hw/arm/xilinx_zynq: Fix IRQ/FIQ routing

-brains.de Signed-off-by: Peter Maydell --- hw/arm/xilinx_zynq.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 7f7a3d23fbe..c79661bbc1b 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -252,10 +252,11 @@ s

[PULL 08/18] scripts/coverity-scan/COMPONENTS.md: Fix monitor component

Update the 'monitor' component: * qapi/ and monitor/ are now subdirectories * add job-qmp.c Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 20240604145934.1230583-5-peter.mayd...@linaro.org --- scripts/coverity-scan/COMPONENTS.md | 2 +- 1 file

[PULL 00/18] target-arm queue

d (1): hw/usb/hcd-ohci: Fix ohci_service_td: accept zero-length TDs where CBP=BE+1 Edgar E. Iglesias (1): hw/intc/arm_gic: Fix deactivation of SPI lines Marcin Juszkiewicz (1): hw/arm/sbsa-ref: switch to 1GHz timer frequency Peter Maydell (8): scripts/coverity-scan/COMPON

[PULL 13/18] hw/arm/virt: Rename VIRT_UART and VIRT_SECURE_UART to VIRT_UART[01]

We're going to make the second UART not always a secure-only device. Rename the constants VIRT_UART and VIRT_SECURE_UART to VIRT_UART0 and VIRT_UART1 accordingly. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 20240610162343.2131524-3-peter.mayd...@linar

[PULL 07/18] scripts/coverity-scan/COMPONENTS.md: Add crypto headers in host/include to the crypto component

host/include/*/host/crypto/ are relatively new headers; add them to the crypto component. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 20240604145934.1230583-4-peter.mayd...@linaro.org --- scripts/coverity-scan/COMPONENTS.md | 2 +- 1 file changed, 1 insertion

[PULL 03/18] hw/intc/arm_gic: Fix deactivation of SPI lines

CTIVER. Reported-by: Julien Grall Signed-off-by: Edgar E. Iglesias Message-id: 20240605143044.2029444-2-edgar.igles...@gmail.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/intc/gic_internal.h | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/hw/intc

[PULL 14/18] hw/arm/virt: allow creation of a second NonSecure UART

Signed-off-by: Peter Maydell Tested-by: Laszlo Ersek Reviewed-by: Philippe Mathieu-Daudé Message-id: 20240610162343.2131524-4-peter.mayd...@linaro.org --- docs/system/arm/virt.rst | 6 +- include/hw/arm/virt.h| 1 + hw/arm/virt-acpi-build.c | 12 hw/arm/virt.c

[PULL 18/18] hw/arm/sbsa-ref: Enable CPU cluster on ARM sbsa machine

Reviewed-by: Leif Lindholm Message-id: 20240607103825.1295328-2-xiongyining1...@phytium.com.cn Tested-by: Marcin Juszkiewicz Signed-off-by: Peter Maydell --- docs/system/arm/sbsa.rst | 4 hw/arm/sbsa-ref.c| 11 ++- 2 files changed, 14 insertions(+), 1 deletion(-) diff

[PULL 12/18] hw/arm/virt: Add serial aliases in DTB

two UARTs in the DTB when one is for the Secure world and one for the Non-Secure world, so this isn't really a problem. However if we want to add a second NS UART we'll need the aliases to ensure guests pick the right one. Signed-off-by: Peter Maydell Reviewed-by: Phil

[PULL 02/18] hw/arm/sbsa-ref: switch to 1GHz timer frequency

: 20240531093729.220758-2-marcin.juszkiew...@linaro.org Signed-off-by: Peter Maydell --- hw/arm/sbsa-ref.c | 12 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index e884692f07f..87884400e30 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa

[PULL 16/18] hw/misc: Set valid access size for Exynos4210 RNG

ted-by: Philippe Mathieu-Daudé Signed-off-by: Zheyu Ma Message-id: 20240618163701.3204975-1-zheyum...@gmail.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/misc/exynos4210_rng.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/misc/exynos4210_rng.c b/hw/misc/exynos4210

[PULL 05/18] scripts/coverity-scan/COMPONENTS.md: Update paths to match gitlab CI

hopefully avoid the need to change them again in future if the build path changes again. This change was made with a search-and-replace of (/qemu)? to .*/qemu . Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 20240604145934.1230583-2-peter.mayd...@linaro.org --

[PULL 11/18] hw/usb/hcd-dwc2: Handle invalid address access in read and write functions

e file=null-co://,if=none,format=raw,id=disk0 -device \ usb-storage,port=1,drive=disk0 -qtest stdio readl 0x3f980dfb EOF Signed-off-by: Zheyu Ma Reviewed-by: Paul Zimmerman Message-id: 20240618135610.3109175-1-zheyum...@gmail.com Signed-off-by: Peter Maydell --- hw/usb/hcd-dwc2.c | 9 +++--

[PULL 10/18] hw/timer/a9gtimer: Handle QTest mode in a9_gtimer_get_current_cpu

t; EOF | qemu-system-aarch64 -display \ none -machine accel=qtest, -m 512M -machine npcm750-evb -qtest stdio writel 0xf03fe20c 0x26d7468c EOF Signed-off-by: Zheyu Ma Reviewed-by: Philippe Mathieu-Daudé Message-id: 20240618144009.3137806-1-zheyum...@gmail.com Signed-off-by: Peter Maydell --- hw

[PULL 15/18] hw/arm/virt: Avoid unexpected warning from Linux guest on host with Fujitsu CPUs

mark it as dma-coherent. Signed-off-by: Zhenyu Zhang Reviewed-by: Gavin Shan Reviewed-by: Donald Dutile Message-id: 20240612020506.307793-1-zheny...@redhat.com [PMM: tweaked commit message] Signed-off-by: Peter Maydell --- hw/arm/virt.c | 11 +++ 1 file changed, 11 insertions(+) di

[PULL 09/18] scripts/coverity-scan/COMPONENTS.md: Include libqmp in testlibs

Add libqmp to the testlibs component. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 20240604145934.1230583-6-peter.mayd...@linaro.org --- scripts/coverity-scan/COMPONENTS.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/coverity-scan

[PULL 01/18] hw/net/can/xlnx-versal-canfd: Fix sorting of the tx queue

using their index and transmit the message at the lowest index first. Signed-off-by: Shiva sagar Myana Reviewed-by: Francisco Iglesias Message-id: 20240603051732.3334571-1-shivasagar.my...@amd.com Signed-off-by: Peter Maydell --- hw/net/can/xlnx-versal-canfd.c | 5 - 1 file changed, 4

command line syntax for connecting a chardev to a CPU

Arm CPUs have a "debug communications channel" which on real hardware is basically a way to talk to the debugger on the other end of a JTAG connection; Linux supports using this as a console. This patchseries: https://patchew.org/QEMU/20240614093026.328271-1-sai.pavan.bo...@amd.com/ proposes imple

Re: [PATCH] hw/usb/hcd-ohci: Fix ohci_service_td: accept valid TDs

On Fri, 21 Jun 2024 at 17:24, Cord Amfmgm wrote: > > > On Fri, Jun 21, 2024 at 10:21 AM Peter Maydell > wrote: >> Thanks; I've picked up this patch for target-arm.next (as with >> your previous one for hcd-ohci, adjusting the Author and >> Signed-off-

Re: [PATCH RFC 3/3] target/arm/debug_helper: Add fieldoffset for MDCCSR_EL0 reg

On Fri, 14 Jun 2024 at 10:30, Sai Pavan Boddu wrote: > > MDCCSR_EL0 is aarch64 varient of DBGDSCRint, so utilize the same cpreg > offset. > > Signed-off-by: Sai Pavan Boddu > --- > target/arm/debug_helper.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/arm/debug

Re: [PATCH RFC 1/3] target/arm: Add dcc uart support

On Fri, 14 Jun 2024 at 10:30, Sai Pavan Boddu wrote: > > DCC is a debug port to transfer some data between debugger and > processor, we are using this feature to connect a chardev device. > Chardev frontends should be named as "dcc" inorder to connect > to this interface. > > Signed-off-by: Sai Pa

Re: [PATCH RFC 0/3] Add DCC uart console support

On Fri, 14 Jun 2024 at 10:30, Sai Pavan Boddu wrote: > > This patch series attaches a chardev to arm Debug Communication channel > registers, > As each cpu has it own DBGDTRTX/RX register just tried to hook each cpu > with chardev iff we find a chardev with id "dcc". > > ex: > Below chardev

Re: [PATCH v5 1/1] hw/arm/sbsa-ref: Enable CPU cluster on ARM sbsa machine

On Fri, 7 Jun 2024 at 11:38, Xiong Yining wrote: > > Enable CPU cluster support on SbsaQemu platform, so that users can > specify a 4-level CPU hierarchy sockets/clusters/cores/threads. And > this topology can be passed to the firmware through /cpus/topology > Device Tree. > > Signed-off-by: Xiong

Re: [PATCH] hw/usb/hcd-ohci: Fix ohci_service_td: accept valid TDs

On Wed, 12 Jun 2024 at 20:36, Alex Bennée wrote: > > Cord Amfmgm writes: > > > On Wed, Jun 12, 2024 at 9:21 AM Alex Bennée wrote: > > > > David Hubbard writes: > > > > > From: Cord Amfmgm > > > > > > This changes the way the ohci emulation handles a Transfer Descriptor > > with > > > "Cu

Re: [PATCH] hw/misc/stm32l4x5_rcc: Add validation for MCOPRE and MCOSEL values

On Fri, 21 Jun 2024 at 16:03, Philippe Mathieu-Daudé wrote: > > On 18/6/24 15:55, Zheyu Ma wrote: > > This commit adds validation checks for the MCOPRE and MCOSEL values in > > the rcc_update_cfgr_register function. If the MCOPRE value exceeds > > 0b100 or the MCOSEL value exceeds 0b111, an error

Re: [PATCH v3] hw/misc: Set valid access size for Exynos4210 RNG

On Tue, 18 Jun 2024 at 17:37, Zheyu Ma wrote: > > The Exynos4210 RNG module requires 32-bit (4-byte) accesses to its registers. > According to the User Manual Section 25.3[1], the registers for RNG operations > are 32-bit. This change ensures that the memory region operations for the > RNG module

Re: [PATCH] Add zh_TW Traditional Chinese translation

On Fri, 21 Jun 2024 at 13:50, Peter Dave Hello wrote: > On Wednesday, April 24th, 2024 at AM 2:20, Peter Dave Hello > wrote: > > Thank you for all your help; I wonder if the copyright can just > > belong to this project because the copyright to me personally in the > > open source world just to

Re: [PATCH v3] hw/arm/virt: Avoid unexpected warning from Linux guest on host with Fujitsu CPUs

On Wed, 12 Jun 2024 at 03:05, Zhenyu Zhang wrote: > > Multiple warning messages and corresponding backtraces are observed when Linux > guest is booted on the host with Fujitsu CPUs. One of them is shown as below. > > [0.032443] [ cut here ] > [0.032446] uart-pl011 9

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