[Qemu-devel] [PATCH 06/10] bitops: Write bitops_flsl in terms of clzl

Signed-off-by: Richard Henderson --- include/qemu/bitops.h | 29 + 1 file changed, 1 insertion(+), 28 deletions(-) diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h index 8b88791..b50629b 100644 --- a/include/qemu/bitops.h +++ b/include/qemu/bitops.h

[Qemu-devel] [PATCH v2 00/10] Cleanup bitops vs host-utils

Version 1 merely tried to adjust bitops_flsl, here I instead eliminate it all from bitops.h, and standardizes on the routines from host-utils.h. r~ Richard Henderson (10): host-utils: Add host long specific aliases for clz, ctz, ctpop host-utils: Fix coding style and add comments hbitmap

[Qemu-devel] [PATCH 04/10] bitops: Use non-bitops ctzl

The use of ctz has already eliminated zero, and thus the difference in edge conditions between the two routines is irrelevant. Signed-off-by: Richard Henderson --- util/bitops.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/bitops.c b/util/bitops.c index 7b853cf

[Qemu-devel] [PATCH 05/10] memory: Use non-bitops ctzl

A memory size of zero is invalid, and so that edge condition does not occur. Signed-off-by: Richard Henderson --- memory.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/memory.c b/memory.c index cd7d5e0..92a2196 100644 --- a/memory.c +++ b/memory.c @@ -855,7 +855,7

[Qemu-devel] [PATCH 09/10] bitops: Replace bitops_ctol with ctzl

The is the only remaining user. Signed-off-by: Richard Henderson --- util/bitops.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/bitops.c b/util/bitops.c index 50b4a81..e72237a 100644 --- a/util/bitops.c +++ b/util/bitops.c @@ -109,7 +109,7 @@ found_first

Re: [Qemu-devel] 3 new x86 instructions

On 02/14/2013 05:38 AM, Torbjorn Granlund wrote: > I now updated x86-next in order to get support for adox/adcx. Hmm. I'm not quite sure what the state of that branch is atm. I know I started splitting out work into other branches as will be required by the eventual merge; perhaps I didn't put t

Re: [Qemu-devel] [PATCH v2 00/10] Cleanup bitops vs host-utils

On 02/14/2013 01:43 AM, Peter Maydell wrote: > I was hoping we'd be able to get rid of host-utils.h instead, > since "Utility compute operations used by translated code" is > now a completely irrelevant categorisation... I suppose an 11th patch could move the code back to bitops.h, but I much pref

[Qemu-devel] [RFC] Disassembler options going forward

On 02/13/2013 06:28 PM, Anthony Liguori wrote: > QEMU is GPLv2 only so we can't take GPLv3 code. We're stuck on binutils > code that predates the v3 relicense. Ok, this is something that's going to bite us more and more. We need *some* solution that allows us to disassemble current cpus. What we

Re: [Qemu-devel] [PATCH moxie 3/5] Moxie target code

On 02/13/2013 02:26 PM, Anthony Green wrote: > +typedef struct CPUMoxieState { > + > + > + uint32_t flags; /* general execution flags */ > + uint32_t gregs[16]; /* general registers */ > + uint32_t sregs[256]; /* special registers */ > + uint32_t pc; > + uint32

Re: [Qemu-devel] [PATCH moxie 3/5] Moxie target code

On 02/14/2013 03:19 PM, Richard Henderson wrote: >> > +tcg_gen_brcond_i32(TCG_COND_EQ, REG(a), REG(b), label_equal); >> > + >> &

[Qemu-devel] [PATCH v2 0/3] Improve 64-bit widening multiply

Version 2 is a simple rebase and conflict fix in the tests/Makefile. r~ Richard Henderson (3): host-utils: Use __int128_t for mul[us]64 host-utils: Improve mulu64 and muls64 tests: Add unit tests for mulu64 and muls64 configure | 20 ++ include/qemu/host-utils.h

[Qemu-devel] [PATCH 1/3] host-utils: Use __int128_t for mul[us]64

get native multiplication on ia64 and s390x hosts. With minor improvements to gcc we can get it for ppc64 as well. Signed-off-by: Richard Henderson --- configure | 20 include/qemu/host-utils.h | 17 - util/host-utils.c | 4 ++-- 3

[Qemu-devel] [PATCH 3/3] tests: Add unit tests for mulu64 and muls64

Signed-off-by: Richard Henderson --- tests/Makefile | 6 - tests/test-mul64.c | 70 ++ 2 files changed, 75 insertions(+), 1 deletion(-) create mode 100644 tests/test-mul64.c diff --git a/tests/Makefile b/tests/Makefile index a2d62b8

[Qemu-devel] [PATCH 2/3] host-utils: Improve mulu64 and muls64

The new formulation makes better use of add-with-carry type insns that the host may have. Use gcc's sign adjustment trick to avoid having to perform a 128-bit negation. Signed-off-by: Richard Henderson --- util/host-utils.c | 92 +++ 1

Re: [Qemu-devel] fixing qemu busy wait

On 2013-02-15 03:12, Orr Dvory wrote: when debugging with qemu(user mode), qemu waits in infinite loop to read a signal from gdb (when it waits on breakpoint for example). I added sleeps to reduce the cpu usage from 100% to about ~0%. Wouldn't it be better to toggle the O_NONBLOCK state of the

Re: [Qemu-devel] [PATCH] Replace all setjmp()/longjmp() with sigsetjmp()/siglongjmp()

ed to be run under QEMU's Linux emulation, so they have neither the portability nor the multithreading issues to deal with. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson r~

Re: [Qemu-devel] Undefined reference to 'ffs' when building for win64

On 2013-02-18 01:52, Kevin Wolf wrote: On Fri, Feb 15, 2013 at 10:16:11PM +0100, Stefan Weil wrote: It looks like most (but not all) versions of gcc emit built-in code for ffs() even for compilations without optimisation. I have to provide additional compiler options (e.g. -fno-builtin-ffs) to g

[Qemu-devel] [PATCH 00/24] Modernize tcg/ppc64

. r~ Richard Henderson (24): disas: Disassemble all ppc insns for the host tcg-ppc64: Use TCGReg everywhere tcg-ppc64: Introduce and use tcg_out_rlw tcg-ppc64: Introduce and use tcg_out_ext32u tcg-ppc64: Introduce and use tcg_out_shli64 tcg-ppc64: Introduce and use tcg_out_shri64 tcg-

[Qemu-devel] [PATCH 01/24] disas: Disassemble all ppc insns for the host

Signed-off-by: Richard Henderson --- disas.c | 1 + 1 file changed, 1 insertion(+) diff --git a/disas.c b/disas.c index a46faee..c0ac7ec 100644 --- a/disas.c +++ b/disas.c @@ -322,6 +322,7 @@ void disas(FILE *out, void *code, unsigned long size) s.info.mach = bfd_mach_x86_64

[Qemu-devel] [PATCH 23/24] tcg-ppc64: Implement movcond

Signed-off-by: Richard Henderson --- tcg/ppc64/tcg-target.c | 59 ++ tcg/ppc64/tcg-target.h | 4 ++-- 2 files changed, 61 insertions(+), 2 deletions(-) diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index df4be3b..ca81456 100644

[Qemu-devel] [PATCH 14/24] tcg-ppc64: Streamline qemu_ld/st insn selection

Using a table to look up insns of the right width and sign. Include support for the Power 2.05 LDBRX and STDBRX insns included in e.g. Power6. Signed-off-by: Richard Henderson --- tcg/ppc64/tcg-target.c | 166 + 1 file changed, 56 insertions

[Qemu-devel] [PATCH 19/24] tcg-ppc64: Implement deposit

Signed-off-by: Richard Henderson --- tcg/ppc64/tcg-target.c | 12 tcg/ppc64/tcg-target.h | 4 ++-- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index a1be15a..2b9309d 100644 --- a/tcg/ppc64/tcg-target.c +++ b/tcg

[Qemu-devel] [PATCH 21/24] tcg-ppc64: Use TCGType throughout compares

The optimization/bug being fixed is that tcg_out_cmp was not applying the right type to loading a constant, in the case it can't be implemented directly. Rather than recomputing the TCGType enum from the arch64 bool, pass around the original TCGType throughout. Signed-off-by: Richard Hend

[Qemu-devel] [PATCH 15/24] tcg-ppc64: Implement rotates

Signed-off-by: Richard Henderson --- tcg/ppc64/tcg-target.c | 39 +++ tcg/ppc64/tcg-target.h | 4 ++-- 2 files changed, 41 insertions(+), 2 deletions(-) diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index 4a55ae7..a08ad90 100644 --- a/tcg

[Qemu-devel] [PATCH 24/24] tcg-ppc64: Use getauxval for ISA detection

Glibc 2.16 includes an easy way to get feature bits previously buried in /proc or the program startup auxiliary vector. Use it. Signed-off-by: Richard Henderson --- configure | 18 ++ tcg/ppc64/tcg-target.c | 20 +++- 2 files changed, 37 insertions

[Qemu-devel] [PATCH 12/24] tcg-ppc64: Improve and_i32 with constant

Use RLWINM Signed-off-by: Richard Henderson --- tcg/ppc64/tcg-target.c | 50 +- 1 file changed, 49 insertions(+), 1 deletion(-) diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index 9718ef6..ad6db6c 100644 --- a/tcg/ppc64/tcg

[Qemu-devel] [PATCH 11/24] tcg-ppc64: Tidy or and xor patterns.

Handle constants in common code; we'll want to reuse that later. Signed-off-by: Richard Henderson --- tcg/ppc64/tcg-target.c | 55 -- 1 file changed, 31 insertions(+), 24 deletions(-) diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-tar

[Qemu-devel] [PATCH 10/24] tcg-ppc64: Improve constant add and sub ops.

Use SUBFIC to implement subtraction with constant op1. Improve constant addition -- previously we'd emit useless addis with 0. Use new constraints to force the driver to pull full 64-bit constants into a register. Signed-off-by: Richard Henderson --- tcg/ppc64/tcg-target.c

[Qemu-devel] [PATCH 05/24] tcg-ppc64: Introduce and use tcg_out_shli64

Signed-off-by: Richard Henderson --- tcg/ppc64/tcg-target.c | 13 - 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index 84e30ad..9199ac4 100644 --- a/tcg/ppc64/tcg-target.c +++ b/tcg/ppc64/tcg-target.c @@ -456,6 +456,11

[Qemu-devel] [PATCH 13/24] tcg-ppc64: Improve and_i64 with constant

Use RLDICL and RLDICR. Signed-off-by: Richard Henderson --- tcg/ppc64/tcg-target.c | 64 +++--- 1 file changed, 50 insertions(+), 14 deletions(-) diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index ad6db6c..51a5545 100644 --- a/tcg

[Qemu-devel] [PATCH 09/24] tcg-ppc64: Rearrange integer constant constraints

We'll need a zero, and Z makes more sense for that. Make sure we have a full compliment of signed and unsigned 16 and 32-bit tests. Signed-off-by: Richard Henderson --- tcg/ppc64/tcg-target.c | 43 +-- 1 file changed, 33 insertions(+), 10 dele

[Qemu-devel] [PATCH 04/24] tcg-ppc64: Introduce and use tcg_out_ext32u

Signed-off-by: Richard Henderson --- tcg/ppc64/tcg-target.c | 15 ++- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index 3587d0e..84e30ad 100644 --- a/tcg/ppc64/tcg-target.c +++ b/tcg/ppc64/tcg-target.c @@ -451,6

[Qemu-devel] [PATCH 07/24] tcg-ppc64: Cleanup tcg_out_movi

The test for using movi32 was sub-optimal for TCG_TYPE_I32, comparing a signed 32-bit quantity against an unsigned 32-bit quantity. When possible, use addi+oris for 32-bit unsigned constants. Otherwise, standardize on addi+oris+ori instead of addis+ori+rldicl. Signed-off-by: Richard Henderson

[Qemu-devel] [PATCH 06/24] tcg-ppc64: Introduce and use tcg_out_shri64

Signed-off-by: Richard Henderson --- tcg/ppc64/tcg-target.c | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index 9199ac4..82e1da7 100644 --- a/tcg/ppc64/tcg-target.c +++ b/tcg/ppc64/tcg-target.c @@ -461,6 +461,11

[Qemu-devel] [PATCH 17/24] tcg-ppc64: Implement bswap64

Signed-off-by: Richard Henderson --- tcg/ppc64/tcg-target.c | 35 +++ tcg/ppc64/tcg-target.h | 2 +- 2 files changed, 36 insertions(+), 1 deletion(-) diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index 723cc77..576effc 100644 --- a/tcg/ppc64/tcg

[Qemu-devel] [PATCH 03/24] tcg-ppc64: Introduce and use tcg_out_rlw

Signed-off-by: Richard Henderson --- tcg/ppc64/tcg-target.c | 72 ++ 1 file changed, 20 insertions(+), 52 deletions(-) diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index 762ca1b..3587d0e 100644 --- a/tcg/ppc64/tcg-target.c +++ b

[Qemu-devel] [PATCH 18/24] tcg-ppc64: Implement compound logicals

Mostly copied from the ppc32 port. Signed-off-by: Richard Henderson --- tcg/ppc64/tcg-target.c | 34 ++ tcg/ppc64/tcg-target.h | 20 ++-- 2 files changed, 44 insertions(+), 10 deletions(-) diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg

[Qemu-devel] [PATCH 02/24] tcg-ppc64: Use TCGReg everywhere

Signed-off-by: Richard Henderson --- tcg/ppc64/tcg-target.c | 36 +--- 1 file changed, 21 insertions(+), 15 deletions(-) diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index 833fe0c..762ca1b 100644 --- a/tcg/ppc64/tcg-target.c +++ b/tcg/ppc64/tcg

[Qemu-devel] [PATCH 22/24] tcg-ppc64: Rewrite setcond

lable. Signed-off-by: Richard Henderson --- tcg/ppc64/tcg-target.c | 264 + 1 file changed, 181 insertions(+), 83 deletions(-) diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index bb5cd8a..df4be3b 100644 --- a/tcg/ppc64/tcg-target.c +++

[Qemu-devel] [PATCH 08/24] tcg-ppc64: Introduce and use TAI and SAI

Signed-off-by: Richard Henderson --- tcg/ppc64/tcg-target.c | 138 +++-- 1 file changed, 66 insertions(+), 72 deletions(-) diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index a4951c5..31b0cb7 100644 --- a/tcg/ppc64/tcg-target.c +++ b

[Qemu-devel] [PATCH 16/24] tcg-ppc64: Implement bswap16 and bswap32

Signed-off-by: Richard Henderson --- tcg/ppc64/tcg-target.c | 43 +++ tcg/ppc64/tcg-target.h | 18 ++ 2 files changed, 53 insertions(+), 8 deletions(-) diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index a08ad90..723cc77

[Qemu-devel] [PATCH 20/24] tcg-ppc64: Use I constraint for mul

The mul_i32 pattern was loading non-16-bit constants into a register, when we can get the middle-end to do that for us. The mul_i64 pattern was not considering that MULLI takes 64-bit inputs. Signed-off-by: Richard Henderson --- tcg/ppc64/tcg-target.c | 24 1 file

Re: [Qemu-devel] 3 new x86 instructions

On 2013-02-14 05:38, Torbjorn Granlund wrote: Richard Henderson writes: Yes, and "-cpu Haswell" will enable the BMI extensions. I have used git://repo.or.cz/qemu/rth.git x86-next checked out around 15 January for a while now. The host system is Debian GNU/Linux amd64 and th

[Qemu-devel] [PATCH 23/57] target-i386: convert gen_compute_eflags_c to TCG

-off-by: Paolo Bonzini Signed-off-by: Richard Henderson --- target-i386/translate.c | 109 +++- 1 file changed, 98 insertions(+), 11 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index 06aa7bf..ea1b003 100644 --- a/target

[Qemu-devel] [PATCH 52/57] target-i386: Implement SHLX, SARX, SHRX

Signed-off-by: Richard Henderson --- target-i386/translate.c | 31 +++ 1 file changed, 31 insertions(+) diff --git a/target-i386/translate.c b/target-i386/translate.c index 51016fe..c1a2886 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -4174,6

[Qemu-devel] [PATCH 31/57] target-i386: inline gen_prepare_cc_slow

Signed-off-by: Paolo Bonzini Signed-off-by: Richard Henderson --- target-i386/translate.c | 91 + 1 file changed, 46 insertions(+), 45 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index b081fc0..0b88eae 100644 --- a

[Qemu-devel] [PATCH 02/57] test-i386: make it compile with a recent gcc

From: Paolo Bonzini Signed-off-by: Paolo Bonzini Signed-off-by: Richard Henderson --- tests/tcg/test-i386.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/tcg/test-i386.c b/tests/tcg/test-i386.c index b18fe20..b05572b 100644 --- a/tests/tcg/test-i386.c +++ b

[Qemu-devel] [PATCH 56/57] target-i386: Implement tzcnt and fix lzcnt

We weren't computing flags for lzcnt at all. At the same time, adjust the implementation of bsf/bsr to avoid the local branch, using movcond instead. Signed-off-by: Richard Henderson --- target-i386/helper.h | 5 ++- target-i386/int_helper.c | 11 ++- target-i386/translate.c

[Qemu-devel] [PATCH 36/57] target-i386: use gen_op for cmps/scas

Replace low-level ops with a higher-level "cmp %al, (A0)" in the case of scas, and "cmp T0, (A0)" in the case of cmps. Signed-off-by: Paolo Bonzini Signed-off-by: Richard Henderson --- target-i386/translate.c | 20 ++-- 1 file changed, 6 insertions(+), 1

[Qemu-devel] [PATCH 41/57] target-i386: Make helper_cc_compute_{all, c} const

Pass the data in explicitly, rather than indirectly via env. This avoids all sorts of unnecessary register spillage. Signed-off-by: Richard Henderson --- target-i386/cc_helper.c | 12 target-i386/helper.h| 4 ++-- target-i386/translate.c | 31 +++ 3

[Qemu-devel] [PATCH 49/57] target-i386: Implement BZHI

Signed-off-by: Richard Henderson --- target-i386/translate.c | 27 +++ 1 file changed, 27 insertions(+) diff --git a/target-i386/translate.c b/target-i386/translate.c index 2322d5c..2bb8d9f 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -4072,6

[Qemu-devel] [PATCH 37/57] target-i386: introduce gen_jcc1_noeob

to prepare for the introduction of src2. Signed-off-by: Paolo Bonzini Signed-off-by: Richard Henderson --- target-i386/translate.c | 27 ++- 1 file changed, 22 insertions(+), 5 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index f8d5e68

[Qemu-devel] [PATCH 39/57] target-i386: optimize flags checking after sub using CC_SRCT

...jbe... Signed-off-by: Paolo Bonzini Signed-off-by: Richard Henderson --- target-i386/translate.c | 46 +++--- 1 file changed, 31 insertions(+), 15 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index

[Qemu-devel] [PATCH 42/57] target-i386: Use CC_SRC2 for ADC and SBB

Add another slot in ENV and store two of the three inputs. This lets us do less work when carry-out is not needed, and avoids the unpredictable CC_OP after translating these insns. Signed-off-by: Richard Henderson --- target-i386/cc_helper.c | 40 ++-- target-i386

[Qemu-devel] [PATCH 43/57] target-i386: Tidy prefix parsing

Avoid duplicating switch statement between 32 and 64-bit modes. Signed-off-by: Richard Henderson --- target-i386/translate.c | 134 +++- 1 file changed, 52 insertions(+), 82 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c

[Qemu-devel] [PATCH 03/57] target-i386: use OT_* consistently

From: Paolo Bonzini Reviewed-by: Blue Swirl Signed-off-by: Paolo Bonzini Signed-off-by: Richard Henderson --- target-i386/translate.c | 88 +++-- 1 file changed, 49 insertions(+), 39 deletions(-) diff --git a/target-i386/translate.c b/target-i386

[Qemu-devel] [PATCH 08/57] target-i386: move eflags computation closer to gen_op_set_cc_op

ng the flags. Finally, always follow gen_compute_eflags(cpu_cc_src) by setting s->cc_op and discarding cpu_cc_dst. Signed-off-by: Paolo Bonzini Signed-off-by: Richard Henderson --- target-i386/translate.c | 19 --- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git

[Qemu-devel] [PATCH 48/57] target-i386: Implement BLSR, BLSMSK, BLSI

Do all of group 17 at one time for ease. Signed-off-by: Richard Henderson --- target-i386/cc_helper.c | 18 +++ target-i386/cc_helper_template.h | 18 +++ target-i386/cpu.h| 5 + target-i386/helper.c | 7 +- target-i386

[Qemu-devel] [PATCH 45/57] target-i386: Implement MOVBE

Signed-off-by: Richard Henderson --- target-i386/cpu.c | 16 +-- target-i386/translate.c | 122 ++-- 2 files changed, 110 insertions(+), 28 deletions(-) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index dfcf86e..0f19533 100644 --- a

[Qemu-devel] [PATCH 32/57] target-i386: cleanup temporary macros for CCPrepare

From: Paolo Bonzini Signed-off-by: Paolo Bonzini Signed-off-by: Richard Henderson --- target-i386/translate.c | 86 ++--- 1 file changed, 39 insertions(+), 47 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index 0b88eae

[Qemu-devel] [PATCH 17/57] target-i386: add helper functions to get other flags

From: Paolo Bonzini Introduce new functions to extract PF, SF, OF, ZF in addition to CF. These provide single entry points for optimizing accesses to a single flag. Reviewed-by: Blue Swirl Signed-off-by: Paolo Bonzini Signed-off-by: Richard Henderson --- target-i386/translate.c | 48

[Qemu-devel] [PATCH 47/57] target-i386: Implement BEXTR

Signed-off-by: Richard Henderson --- target-i386/translate.c | 40 1 file changed, 40 insertions(+) diff --git a/target-i386/translate.c b/target-i386/translate.c index 01ff131..d742fe3 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c

[Qemu-devel] [PATCH 27/57] target-i386: optimize setcc instructions

From: Paolo Bonzini Reconstruct the arguments for complex conditions involving CC_OP_SUBx (BE, L, LE). In the others do it via setcond and gen_setcc_slow (which is not that slow in many cases). Signed-off-by: Paolo Bonzini Signed-off-by: Richard Henderson --- target-i386/translate.c | 95

[Qemu-devel] [PATCH 19/57] target-i386: no need to flush out cc_op before gen_eob

This makes code more similar to the other callers of gen_eob, especially loopz/loopnz/jcxz. Signed-off-by: Paolo Bonzini Signed-off-by: Richard Henderson --- target-i386/translate.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/target-i386/translate.c b/target-i386

[Qemu-devel] [PATCH 35/57] target-i386: kill cpu_T3

From: Paolo Bonzini It is almost unused, and it is simpler to pass a TCG value directly to gen_shiftd_rm_T1_T3. This value is then written to t2 without going through a temporary register. Signed-off-by: Paolo Bonzini Signed-off-by: Richard Henderson --- target-i386/translate.c | 19

[Qemu-devel] [PATCH 50/57] target-i386: Implement MULX

Signed-off-by: Richard Henderson --- target-i386/helper.h | 1 + target-i386/int_helper.c | 7 +++ target-i386/translate.c | 39 +++ 3 files changed, 47 insertions(+) diff --git a/target-i386/helper.h b/target-i386/helper.h index 4c46ab1..d750754

[Qemu-devel] [PATCH 24/57] target-i386: change gen_setcc_slow_T0 to gen_setcc_slow

From: Paolo Bonzini Do not hard code the destination register. Reviewed-by: Blue Swirl Signed-off-by: Paolo Bonzini Signed-off-by: Richard Henderson --- target-i386/translate.c | 39 --- 1 file changed, 20 insertions(+), 19 deletions(-) diff --git a

[Qemu-devel] [PATCH 04/57] target-i386: introduce gen_ext_tl

From: Paolo Bonzini Introduce a function that abstracts extracting an 8, 16, 32 or 64-bit value with or without sign, generalizing gen_extu and gen_exts. Reviewed-by: Blue Swirl Signed-off-by: Paolo Bonzini Signed-off-by: Richard Henderson --- target-i386/translate.c | 146

[Qemu-devel] [PATCH 09/57] target-i386: compute eflags outside rcl/rcr helper

ove cc_tmp and just modify cc_src from within the helper. Finally, always follow gen_compute_eflags(cpu_cc_src) by setting s->cc_op and discarding cpu_cc_dst. Signed-off-by: Paolo Bonzini Signed-off-by: Richard Henderson --- target-i386/cpu.h | 1 - target-i386/shift_helper_temp

[Qemu-devel] [PATCH 38/57] target-i386: Update cc_op before TCG branches

Placing the CC_OP_DYNAMIC at the join is less effective than before the branch, as the branch will have forced global registers to their home locations. This way we have a chance to discard CC_SRC2 before it gets stored. Signed-off-by: Richard Henderson --- target-i386/translate.c | 8

[Qemu-devel] [PATCH] tcg-optimize: Fold sub r,0,x to neg r,x

Signed-off-by: Richard Henderson --- tcg/optimize.c | 33 - 1 file changed, 32 insertions(+), 1 deletion(-) I noticed this while looking at other dumps. This seems like it should be considered independently of the other patch series. r~ diff --git a/tcg

[Qemu-devel] [PATCH 06/57] target-i386: drop cc_op argument of gen_jcc1

ned-off-by: Richard Henderson --- target-i386/translate.c | 33 ++--- 1 file changed, 18 insertions(+), 15 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index 9ac66b9..48a3255 100644 --- a/target-i386/translate.c +++ b/target-i386/translat

[Qemu-devel] [PATCH 28/57] target-i386: introduce CCPrepare

.] Signed-off-by: Paolo Bonzini Signed-off-by: Richard Henderson --- target-i386/translate.c | 147 ++-- 1 file changed, 93 insertions(+), 54 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index 5c9211f..06f0fbc 100644 --- a

[Qemu-devel] [PATCH 46/57] target-i386: Implement ANDN

As this is the first of the BMI insns to be implemented, this carries quite a bit more baggage than normal. Signed-off-by: Richard Henderson --- target-i386/cpu.c | 10 +- target-i386/translate.c | 19 +-- 2 files changed, 22 insertions(+), 7 deletions(-) diff

[Qemu-devel] [PATCH 54/57] target-i386: Implement ADX extension

Signed-off-by: Richard Henderson --- target-i386/cc_helper.c | 30 + target-i386/cpu.c | 4 +- target-i386/cpu.h | 4 ++ target-i386/helper.c| 4 ++ target-i386/translate.c | 109 ++-- 5 files changed, 146 insertions

[Qemu-devel] [PATCH 20/57] target-i386: Move CC discards to set_cc_op

This gets us universal coverage, rather than scattering discards around at various places. As a bonus, we do not emit redundant discards e.g. between sequential logic insns. Signed-off-by: Richard Henderson --- target-i386/translate.c | 48 +++- 1

[Qemu-devel] [PATCH 51/57] target-i386: Implement PDEP, PEXT

Signed-off-by: Richard Henderson --- target-i386/helper.h | 3 +++ target-i386/int_helper.c | 32 target-i386/translate.c | 36 3 files changed, 71 insertions(+) diff --git a/target-i386/helper.h b/target-i386/helper.h

[Qemu-devel] [PATCH 12/57] target-i386: factor gen_op_set_cc_op/tcg_gen_discard_tl around computing flags

in gen_compute_eflags, rather than doing it all over the place. Signed-off-by: Paolo Bonzini Signed-off-by: Richard Henderson --- target-i386/translate.c | 103 +--- 1 file changed, 37 insertions(+), 66 deletions(-) diff --git a/target-i386/translate.c b/tar

[Qemu-devel] [PATCH 05/57] target-i386: factor setting of s->cc_op handling for string functions

From: Paolo Bonzini Set it to the appropriate CC_OP_SUBx constant in gen_scas/gen_cmps. In the repz case it can be overridden to CC_OP_DYNAMIC after generating the code. Signed-off-by: Paolo Bonzini Signed-off-by: Richard Henderson --- target-i386/translate.c | 9 + 1 file changed, 5

[Qemu-devel] [PATCH 14/57] target-i386: Introduce set_cc_op

This will provide a good hook into which we can consolidate all of the cc variable discards. Signed-off-by: Richard Henderson --- target-i386/translate.c | 134 +--- 1 file changed, 69 insertions(+), 65 deletions(-) diff --git a/target-i386

[Qemu-devel] [PATCH 13/57] target-i386: Name the cc_op enumeration

Signed-off-by: Richard Henderson --- target-i386/cpu.h | 4 ++-- target-i386/translate.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target-i386/cpu.h b/target-i386/cpu.h index cd35cd5..8c4c605 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -582,7

[Qemu-devel] [PATCH 11/57] target-i386: use gen_jcc1 to compile loopz

From: Paolo Bonzini Signed-off-by: Paolo Bonzini Signed-off-by: Richard Henderson --- target-i386/translate.c | 8 +--- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index 64564e0..6fcd0f6 100644 --- a/target-i386

Re: [Qemu-devel] 3 new x86 instructions

On 02/19/2013 12:40 PM, Torbjorn Granlund wrote: > The apparent symptom is that an > > adox (%rdi,%rcx,8), %r9 > > where the 8 bytes at the memory location contains just zeros, > and r9 is some random value, results in OF being set. Interesting. > I only have Intel's 327831.pdf document whi

[Qemu-devel] [PATCH 34/57] target-i386: expand cmov via movcond

Signed-off-by: Richard Henderson --- target-i386/translate.c | 45 - 1 file changed, 20 insertions(+), 25 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index 4b0a701..9d5467d 100644 --- a/target-i386/translate.c +++ b

[Qemu-devel] [PATCH 18/57] target-i386: do not compute eflags multiple times consecutively

the callers. Reviewed-by: Blue Swirl Signed-off-by: Paolo Bonzini Signed-off-by: Richard Henderson --- target-i386/translate.c | 72 - 1 file changed, 36 insertions(+), 36 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c

[Qemu-devel] [PATCH 33/57] target-i386: introduce gen_cmovcc1

From: Paolo Bonzini Signed-off-by: Richard Henderson --- target-i386/translate.c | 72 ++--- 1 file changed, 38 insertions(+), 34 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index c83b56f..4b0a701 100644 --- a/target

[Qemu-devel] [PATCH 16/57] target-i386: Use gen_update_cc_op everywhere

All of the conditional calls to gen_op_set_cc_op go away, and gen_op_set_cc_op itself gets inlined into its only remaining caller. Signed-off-by: Richard Henderson --- target-i386/translate.c | 177 1 file changed, 57 insertions(+), 120 deletions

[Qemu-devel] [PATCH 07/57] target-i386: move carry computation for inc/dec closer to gen_op_set_cc_op

From: Paolo Bonzini This ensures the invariant that cpu_cc_op matches s->cc_op when calling the helpers. The next patches need this because gen_compute_eflags and gen_compute_eflags_c will take care of setting cpu_cc_op. Signed-off-by: Paolo Bonzini Signed-off-by: Richard Hender

[Qemu-devel] [PATCH 01/57] test-i386: QEMU_PACKED is not defined here

From: Paolo Bonzini Signed-off-by: Paolo Bonzini Signed-off-by: Richard Henderson --- tests/tcg/test-i386.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tests/tcg/test-i386.c b/tests/tcg/test-i386.c index 6dc730d..b18fe20 100644 --- a/tests/tcg/test-i386.c +++ b

[Qemu-devel] [PATCH 10/57] target-i386: clean up sahf

From: Paolo Bonzini Discard CC_DST and set s->cc_op immediately after computing EFLAGS. Signed-off-by: Paolo Bonzini Signed-off-by: Richard Henderson --- target-i386/translate.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target-i386/translate.c b/target-i

[Qemu-devel] [PATCH 55/57] target-i386: Use clz/ctz for bsf/bsr helpers

And mark the helpers as NO_RWG_SE. Signed-off-by: Richard Henderson --- target-i386/helper.h | 6 +++--- target-i386/int_helper.c | 45 +++-- 2 files changed, 14 insertions(+), 37 deletions(-) diff --git a/target-i386/helper.h b/target-i386/helper.h

[Qemu-devel] [PATCH 30/57] target-i386: use CCPrepare to generate conditional jumps

From: Paolo Bonzini This simplifies all the jump generation code. CCPrepare allows the code to create an efficient brcond always, so there is no need to duplicate the setcc and jcc code. Signed-off-by: Paolo Bonzini Signed-off-by: Richard Henderson --- target-i386/translate.c | 119

[Qemu-devel] [PATCH 44/57] target-i386: Decode the VEX prefixes

No actual required uses of these encodings yet. Signed-off-by: Richard Henderson --- target-i386/translate.c | 68 ++--- 1 file changed, 64 insertions(+), 4 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index e5cda94

[Qemu-devel] [PATCH 57/57] target-i386: Add CC_OP_CLR

Special case xor with self. We need not even store the known zero into cc_src. Signed-off-by: Richard Henderson --- target-i386/cc_helper.c | 3 +++ target-i386/cpu.h | 2 ++ target-i386/helper.c| 2 ++ target-i386/translate.c | 17 ++--- 4 files changed, 21 insertions

[Qemu-devel] [PATCH 29/57] target-i386: introduce gen_prepare_cc

operations will still go through CC computation in a single-bit temporary, followed by a brcond if the temporary is nonzero. Signed-off-by: Paolo Bonzini Signed-off-by: Richard Henderson --- target-i386/translate.c | 91 +++-- 1 file changed, 42

[Qemu-devel] [PATCH 40/57] target-i386: Don't reference ENV through most of cc helpers

In preparation for making this a const helper. By using the proper types in the parameters to the helper functions, we get to avoid quite a lot of subsequent casting. Signed-off-by: Richard Henderson --- target-i386/cc_helper.c | 217 ++ target-i386

[Qemu-devel] [PATCH 26/57] target-i386: optimize setle

And allow gen_setcc_slow to operate on cpu_cc_src. Signed-off-by: Paolo Bonzini Signed-off-by: Richard Henderson --- target-i386/translate.c | 15 ++- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index dab6983

[Qemu-devel] [PATCH 22/57] target-i386: use inverted setcond when computing NS or NZ

. I'm not doing it yet. Reviewed-by: Blue Swirl Signed-off-by: Paolo Bonzini Signed-off-by: Richard Henderson --- target-i386/translate.c | 49 +++-- 1 file changed, 31 insertions(+), 18 deletions(-) diff --git a/target-i386/translate.c b/target

[Qemu-devel] [PATCH 21/57] target-i386: do not call helper to compute ZF/SF

Bonzini Signed-off-by: Richard Henderson --- target-i386/translate.c | 37 +++-- 1 file changed, 31 insertions(+), 6 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index a767b50..026fbd6 100644 --- a/target-i386/translate.c +++ b/target-i386

[Qemu-devel] [PATCH 25/57] target-i386: optimize setbe

This is looking at EFLAGS, but it can do so more efficiently with setcond. Reviewed-by: Blue Swirl Signed-off-by: Paolo Bonzini Signed-off-by: Richard Henderson --- target-i386/translate.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/target-i386/translate.c b

<    1   2   3   4   5   6   7   8   9   10   >