In preference to the older helpers. Loads only in this patch.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 84 ++---
1 file changed, 31 insertions(+), 53 deletions(-)
diff --git a/target-i386/translate.c b/target
In preference to the older helpers. Stores only in this patch.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 75 ++---
1 file changed, 34 insertions(+), 41 deletions(-)
diff --git a/target-i386/translate.c b/target
For the known MO_32/MO_64 cases, we don't need to extend a 32-bit temp
into a 64-bit temp before storing into the hardware register.
We do need the extension for the MO_8/MO_16 cases, in order for the
deposit_tl operation to work, so leave those alone.
Signed-off-by: Richard Henderson r
Always perform a sign-extending load. In the extremely unlikely
case that we've used an 0x66 prefix, the extension to 64-bits is
unnecessary but not wrong; the store will still examine only 16 bits.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 6 +-
1 file
Propagate the definitions into all users. In two cases, this allows
us to share code between the 32-bit and 64-bit immediate moves.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 26 +++---
1 file changed, 3 insertions(+), 23 deletions
Change the domain of the parameter and update all callers.
Which lets us defer completely to gen_op_mov_reg_v.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 32
1 file changed, 8 insertions(+), 24 deletions(-)
diff --git
Propagate the definitions into all users.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 16 +++-
1 file changed, 3 insertions(+), 13 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index bda9ff4..2fa222b 100644
Unify the code across stack pointer widths. Fix the note about
not updating ESP before the potential exception.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 29 +++--
1 file changed, 15 insertions(+), 14 deletions(-)
diff --git
Change the domain of the parameter and update all callers.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index e3b24aa
We can use the MO_SIGN bit to tidy the reg-reg switch statement
as well as pass it on to gen_op_ld_v, eliminating one call.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 23 ---
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git
Use gen_lea_v_seg for centralized segment base knowledge. Unify
code across 32- and 64-bit. Fix note about must save state
before using the out-of-line helpers.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/helper.h | 4 ---
target-i386/seg_helper.c | 68
Changing the domain to TCGMemOp makes it easier to interoperate
with other portions of the rest of the translator.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 180 +++-
1 file changed, 87 insertions(+), 93 deletions
Propagate its definition into all users.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 6b7c89e..f07fca0 100644
--- a/target-i386
believe the tcg optimizer improvements that Aurelien has
posted (but not committed) would clean those up.
r~
Richard Henderson (61):
exec: Delay CPU_LOG_TB_CPU until we actually execute a TB
target-i386: Push DisasContext into load/store helpers
target-i386: Stop encoding
On 11/07/2013 08:53 PM, Alex Bennée wrote:
r...@twiddle.net writes:
All references to cpu_T are done with a constant index. It aids
readability to decompose the array into two scalar variables.
snip
I'm not necessarily disagreeing with the readability argument but does
this make any
On 11/07/2013 06:31 AM, Tom Musta wrote:
}
\
+
\
+if (r2sp) {
\
+
On 11/08/2013 09:28 AM, Richard Henderson wrote:
On 11/07/2013 06:31 AM, Tom Musta wrote:
}
\
+
\
+if (r2sp
On 11/08/2013 09:30 AM, Richard Henderson wrote:
On 11/08/2013 09:28 AM, Richard Henderson wrote:
On 11/07/2013 06:31 AM, Tom Musta wrote
On 11/07/2013 06:31 AM, Tom Musta wrote:
The single-precision scalar arithmetic instructions all interpret the most
significant 64 bits of a VSR as a single precision floating point number
stored in double precision format (similar to the standard PowerPC floating
point single precision
On 11/12/2013 01:13 AM, Claudio Fontana wrote:
+/* C3.2 Branches, exception generating and system instructions */
+static void disas_b_exc_sys(DisasContext *s, uint32_t insn)
+{
+switch (extract32(insn, 25, 7)) {
+case 0x0a: case 0x4a: /* Unconditional branch (immediate) */
+
) = abcf0002
+lea (%%ecx) = abc90004
+lea (%%edx) = abc50008
+lea (%%esi) = abdd0010
+lea (%%edi) = abed0020
In addition, reduce ifdeffery and minimize the number of TCG ops
produced during address computation.
Signed-off-by: Richard Henderson r...@twiddle.net
-devel/2013-11/msg01312.html
Reviewed-by: Richard Henderson r...@twiddle.net
r~
On 11/13/2013 03:04 AM, Anthony Liguori wrote:
On Tue, Nov 12, 2013 at 8:08 AM, Peter Maydell peter.mayd...@linaro.org
wrote:
On 12 November 2013 15:58, Paolo Bonzini pbonz...@redhat.com wrote:
I don't really see a reason why QEMU should give clang more weight than
Windows or Mac OS X.
I'm
On 11/13/2013 08:53 AM, Paolo Bonzini wrote:
Il 12/11/2013 19:54, Richard Henderson ha scritto:
For what it's worth, I think BOTH of the patches that have been posted
should be applied. That is, the patch that does (X || 1) - (1 || X),
and the patch that adds the stub.
Frankly I'd have
On 11/14/2013 06:49 AM, Tom Musta wrote:
I have reviewed the code and the spec and I cannot see a flaw. The sequence
is
effectively this:
- float64_muladd - performs proper FMA for 64 bit numbers)
- float64_to_float32 - converts to single precision, including proper
rounding
-
On 11/16/2013 08:12 PM, Martin T wrote:
So I'm thinking there must be some other place where cpu_ldq_data() gets
defined which does something else, however, I haven't been able to find it
searching through the sources.
It's constructed via macro glue. See include/exec/softmmu_exec.h.
r~
On 11/18/2013 11:55 PM, Michael Matz wrote:
I think we need to either explicitly convert the tcg_shift to a
TCGv_i32, or we need to use an open coded version of the rotr_i64 that
inserts at (32 - n) instead of (64 - n)
What do you think?
I think converting tcg_shift might eventually
hw/i386/acpi-build.c:294:5: error: implicit declaration of function
‘g_string_vprintf’ [-Werror=implicit-function-declaration]
g_string_vprintf(s, format, args);
Introduced in 2.14.
hw/i386/acpi-build.c:427:5: error: implicit declaration of function
‘g_array_get_element_size’
Acked-by: Aurelien Jarno aurel...@aurel32.net
Signed-off-by: Richard Henderson r...@twiddle.net
---
tcg/ia64/tcg-target.c | 173 ++
1 file changed, 91 insertions(+), 82 deletions(-)
diff --git a/tcg/ia64/tcg-target.c b/tcg/ia64/tcg-target.c
index
15:57:59 +1000)
Richard Henderson (13):
tcg-ia64: Use TCGMemOp within qemu_ldst routines
tcg-ia64: Use shortcuts for nop insns
tcg-ia64: Handle constant calls
tcg-ia64: Simplify brcond
tcg-ia64: Move AREG0
Acked-by: Aurelien Jarno aurel...@aurel32.net
Signed-off-by: Richard Henderson r...@twiddle.net
---
tcg/ia64/tcg-target.c | 63 +++
1 file changed, 28 insertions(+), 35 deletions(-)
diff --git a/tcg/ia64/tcg-target.c b/tcg/ia64/tcg-target.c
index
.
If we pack the compare and the branch together in the same bundle, then
there's no longer any room for non-zero constants. At which point we
can eliminate half the function by not handling them.
Acked-by: Aurelien Jarno aurel...@aurel32.net
Signed-off-by: Richard Henderson r...@twiddle.net
---
tcg
holding the return address elsewhere.
Choose R33 for tidiness.
Acked-by: Aurelien Jarno aurel...@aurel32.net
Signed-off-by: Richard Henderson r...@twiddle.net
---
tcg/ia64/tcg-target.c | 13 ++---
tcg/ia64/tcg-target.h | 4 ++--
2 files changed, 8 insertions(+), 9 deletions(-)
diff --git
When performing an operation with two input registers, we'd leave
the stop bit (and thus an extra cycle) that's only needed when one
or the other input is a constant.
Acked-by: Aurelien Jarno aurel...@aurel32.net
Signed-off-by: Richard Henderson r...@twiddle.net
---
tcg/ia64/tcg-target.c | 17
Acked-by: Aurelien Jarno aurel...@aurel32.net
Signed-off-by: Richard Henderson r...@twiddle.net
---
tcg/ia64/tcg-target.c | 32
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/tcg/ia64/tcg-target.c b/tcg/ia64/tcg-target.c
index 2f630f4..afcb1ad
We can and/or/xor/andcm small constants, saving one cycle.
Acked-by: Aurelien Jarno aurel...@aurel32.net
Signed-off-by: Richard Henderson r...@twiddle.net
---
tcg/ia64/tcg-target.c | 64 +++
1 file changed, 34 insertions(+), 30 deletions(-)
diff
We can subtract from more small constants that just 0 with one insn,
and we can add the negative for most small constants.
Acked-by: Aurelien Jarno aurel...@aurel32.net
Signed-off-by: Richard Henderson r...@twiddle.net
---
tcg/ia64/tcg-target.c | 25 +++--
1 file changed, 23
Being able to extend from 64-bits (with a mov) simplifies
a few places where the conditional breaks the train of thought.
Acked-by: Aurelien Jarno aurel...@aurel32.net
Signed-off-by: Richard Henderson r...@twiddle.net
---
tcg/ia64/tcg-target.c | 54
Acked-by: Aurelien Jarno aurel...@aurel32.net
Signed-off-by: Richard Henderson r...@twiddle.net
---
tcg/ia64/tcg-target.c | 35 ---
1 file changed, 16 insertions(+), 19 deletions(-)
diff --git a/tcg/ia64/tcg-target.c b/tcg/ia64/tcg-target.c
index 322955b..2f630f4
Using only indirect calls results in 3 bundles (one to load the
descriptor address), and 4 stop bits. By looking through the
descriptor to the constants, we can perform the call with 2
bundles and only 1 stop bit.
Acked-by: Aurelien Jarno aurel...@aurel32.net
Signed-off-by: Richard Henderson r
There's no need to go through the full opcode-to-insn function call
to generate nops. This makes the source a bit more readable.
Acked-by: Aurelien Jarno aurel...@aurel32.net
Signed-off-by: Richard Henderson r...@twiddle.net
---
tcg/ia64/tcg-target.c | 251
Avoids a wasted cycle loading up small constants.
Simplify the code assuming the tcg optimizer is going to work
and don't expect the first operand of the add to be constant.
Acked-by: Aurelien Jarno aurel...@aurel32.net
Signed-off-by: Richard Henderson r...@twiddle.net
---
tcg/ia64/tcg-target.c
Ping?
r~
On 09/20/2013 05:58 AM, Richard Henderson wrote:
We previously allocated 32-bits per temp for the next_free_temp entry.
We now allocate 4 bits per temp across the 4 bitmaps.
Using a linked list meant that if a translator is tweeked, resulting in
temps being freed in a different
Ping.
r~
On 10/29/2013 03:30 AM, Richard Henderson wrote:
Ping.
r~
On 10/17/2013 08:29 AM, Richard Henderson wrote:
Changes from v2:
* Rebase for trivial conflicts
* Fix codingstyle errors
* Drop the static fallback code
* Use getauxval for AT_EXECFD
r~
Richard
On 11/19/2013 05:47 AM, Clemens Kolbitsch wrote:
Getting around this is not trivial, so if it's a new issue, does anyone have
an
idea how to approach it most meaningfully? I was thinking about detecting this
very specific case and marking the TB for re-translation only after the TB is
On 11/19/2013 11:40 PM, Tom Musta wrote:
+/* NOTE: in order to get accurate results, we must first round back */
\
+/* to single precision and use the fused multiply add routine */
\
+/* for 32-bit floats. */
\
+
On 11/20/2013 09:54 PM, Paolo Bonzini wrote:
The fix is to make the pause instruction do cpu_loop_exit.
Cc: Richard Henderson r...@twiddle.net
Reported-by: Luigi Rizzo ri...@iet.unipi.it
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
Reviewed-by: Richard Henderson r...@twiddle.net
.
Signed-off-by: Bobby Bingham koor...@koorogi.info
Reviewed-by: Richard Henderson r...@twiddle.net
r~
On 11/25/2013 09:48 PM, Michael S. Tsirkin wrote:
g_string_vprintf was only introduced in 2.24 so switch to vsnprintf
instead. A bit uglier but name size is fixed at 4 bytes here so it's
easy.
You list 2.24 here,
-GString *s = g_string_new();
+/* It would be nicer to use
On 11/25/2013 09:48 PM, Michael S. Tsirkin wrote:
+#if GLIB_CHECK_VERSION(2, 14, 0)
+assert(g_array_get_element_size(table) == 1);
+#endif
https://developer.gnome.org/glib/2.28/glib-Arrays.html#g-array-get-element-size
says Since 2.22, not 2.14.
r~
On 11/26/2013 06:31 AM, Michael S. Tsirkin wrote:
On Tue, Nov 26, 2013 at 06:24:53AM +1000, Richard Henderson wrote:
On 11/25/2013 09:48 PM, Michael S. Tsirkin wrote:
g_string_vprintf was only introduced in 2.24 so switch to vsnprintf
instead. A bit uglier but name size is fixed at 4 bytes
On 11/26/2013 06:54 AM, Michael S. Tsirkin wrote:
+char s[] = ;
char s[5];
Then do something like
char s[sizeof()];
so that the actual initialization doesn't happen.
Why? As an optimization?
How about failing to pessimize?
With your initialization you're forcing the
On 11/26/2013 07:02 AM, Michael S. Tsirkin wrote:
In any case it's too late to play with cosmetic changes for 1.7.
We can revisit for 1.8.
I beg your pardon? I didn't realize your patch had already been applied. And
since it has mistakes that require respin anyway, why can't we change this
On 11/26/2013 07:01 AM, Michael S. Tsirkin wrote:
Can you confirm this works?
I can confirm that with this follow-on I can once again build on RHEL 5.3.
r~
On 11/27/2013 12:56 AM, Claudio Fontana wrote:
On 09/27/2013 09:42 PM, Richard Henderson wrote:
On 09/26/2013 05:48 PM, Alexander Graf wrote:
+if (setflags) {
+tcg_dst = cpu_reg(dest);
+} else {
+tcg_dst = cpu_reg_sp(dest);
+}
Never sp for logicals
On 11/27/2013 08:41 PM, Xin Tong wrote:
I am trying to implement a out-of-line TLB lookup for QEMU softmmu-x86-64 on
x86-64 machine, potentially for better instruction cache performance, I have a
few questions.
1. I see that tcg_out_qemu_ld_slow_path/tcg_out_qemu_st_slow_path are
The previous placement could result in duplicate logging while
still processing interrupts.
Signed-off-by: Richard Henderson r...@twiddle.net
---
cpu-exec.c | 36 +++-
1 file changed, 19 insertions(+), 17 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index
Now that we don't combine mem_index with operand size info,
we don't need to encode it. Which tidies many places that
access it.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 67 ++---
1 file changed, 25 insertions
Changes v1-v2:
* Rebased on master, with one of the patches already applied to 1.7.
r~
Richard Henderson (60):
exec: Delay CPU_LOG_TB_CPU until we actually execute a TB
target-i386: Push DisasContext into load/store helpers
target-i386: Stop encoding DisasContext.mem_index
target
Propagate its definition into all users.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 77 +++--
1 file changed, 36 insertions(+), 41 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index
Rather than add s-mem_index into a combined size+mem_index
argument, pass the context down. This will allow cleaning
up s-mem_index later.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 331 +---
1 file changed, 170
In preference to the older helpers. Loads only in this patch.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 84 ++---
1 file changed, 31 insertions(+), 53 deletions(-)
diff --git a/target-i386/translate.c b/target
Propagate its definition into all users.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 15 +--
1 file changed, 5 insertions(+), 10 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 8e231b3..c64203e 100644
--- a/target
In preference to the older helpers. Stores only in this patch.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 75 ++---
1 file changed, 34 insertions(+), 41 deletions(-)
diff --git a/target-i386/translate.c b/target
We can use the MO_SIGN bit to tidy the reg-reg switch statement
as well as pass it on to gen_op_ld_v, eliminating one call.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 23 ---
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git
Replace its users by gen_op_ld_v with the MO_SIGN bit set.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 13 -
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 586e5af..8c3d7ae
Propagate its definition into all users.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 23 +--
1 file changed, 9 insertions(+), 14 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index c64203e..586e5af 100644
Always perform a sign-extending load. In the extremely unlikely
case that we've used an 0x66 prefix, the extension to 64-bits is
unnecessary but not wrong; the store will still examine only 16 bits.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 6 +-
1 file
Propagate its definition into all users.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index d3fc8f3..b28663b 100644
--- a/target-i386
We can now use tcg_gen_qemu_st_i32 directly to avoid the extension.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 34 +-
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/target-i386/translate.c b/target-i386
Fold the bswap into the memory operation.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 40 +---
1 file changed, 5 insertions(+), 35 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 45a00ba
Propagate its definition into all users.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 17 ++---
1 file changed, 6 insertions(+), 11 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 51ee579..6f88ed9 100644
Too many places have the same test vs OR_TMP0 to indicate
a write back to memory. Hoist that to a subroutine.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 85 ++---
1 file changed, 24 insertions(+), 61 deletions
The reg_ptr and offset_ptr outputs are universally unused.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 146 +++-
1 file changed, 69 insertions(+), 77 deletions(-)
diff --git a/target-i386/translate.c b/target-i386
For the 16 and 32-bit cases, we don't need to truncate via
a temporary register.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index
Propagate the definitions into all users. In two cases, this allows
us to share code between the 32-bit and 64-bit immediate moves.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 17 ++---
1 file changed, 2 insertions(+), 15 deletions(-)
diff --git
By inspection, obviously we should be storing T[1] not T[0].
This could only happen for x86_64 in 64-bit mode with 0x66
prefix to call insn -- i.e. never.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
Replace it with tcg_gen_ext16u_tl. In four places we can combine that
with a previous move into cpu_T[0], and in one place we can infer that
the zero-extension has already happened via the previous load.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 43
For the known MO_32/MO_64 cases, we don't need to extend a 32-bit temp
into a 64-bit temp before storing into the hardware register.
We do need the extension for the MO_8/MO_16 cases, in order for the
deposit_tl operation to work, so leave those alone.
Signed-off-by: Richard Henderson r
should be.
This does require adding some default cases to some switch statements,
to avoid the 'unhandled enumeration value' warning that would result
from the change of type.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 120
We can now use tcg_gen_qemu_ld_i32 directly to avoid the truncation.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 39 +++
1 file changed, 19 insertions(+), 20 deletions(-)
diff --git a/target-i386/translate.c b/target-i386
Propagate the definitions into all users. The only time that
gen_op_movl_T1_imu was used, the input was type 'unsigned',
so the replacement works identically.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 30 ++
1 file changed, 10
Propagate the definition of gen_op_movl_T0_im to all users.
The function gen_op_movl_T0_imu was unused.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 32 ++--
1 file changed, 10 insertions(+), 22 deletions(-)
diff --git a/target-i386
Unlike the addr32, there was no bug. But we can use the same
technique to reduce the number of TCG ops.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 34 --
1 file changed, 16 insertions(+), 18 deletions(-)
diff --git a/target
Replace it with its definition.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 009529e..bb45c2b 100644
--- a/target-i386/translate.c
Replace it with its definition.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 20 +---
1 file changed, 9 insertions(+), 11 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 236d0a7..009529e 100644
--- a/target
Reduce ifdefs, share more code between paths, reduce the number of TCG
ops generated.
Add forgotten zero-extension in the TARGET_X86_64, !CODE64, ss32 case.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 106 +++-
1
Having segs[].base as a register significantly improves code
generation for real and protected modes, particularly for TBs
that have multiple memory references where the segment base
can be held in a hard register through the TB.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386
Replace it with tcg_gen_ext16u_tl, and in two cases merge with a
previous move from cpu_regs.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 33 +
1 file changed, 13 insertions(+), 20 deletions(-)
diff --git a/target-i386
Centralize computation of a MO_SIZE for the stack pointer.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 43 ++-
1 file changed, 18 insertions(+), 25 deletions(-)
diff --git a/target-i386/translate.c b/target-i386
I.e. gen_push_v, gen_pop_T0, gen_stack_A0.
More centralization of handling of segment bases.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 49 +++--
1 file changed, 15 insertions(+), 34 deletions(-)
diff --git
Replace with its definition.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 7f2c718..62a2cbc 100644
--- a/target-i386/translate.c
+++ b
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 87 -
1 file changed, 36 insertions(+), 51 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 07dac7c..5a5c8b6 100644
--- a/target-i386
Add forgotten zero-extension in the TARGET_X86_64, !CODE64, ss32 case;
use this new function to implement gen_string_movl_A0_EDI,
gen_string_movl_A0_ESI, gen_add_A0_ds_seg.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 159
to gen_op_mov_reg_v.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 76 ++---
1 file changed, 22 insertions(+), 54 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 31f0d02..087f0a2 100644
--- a/target
Centralize handling of segment bases.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 82 ++---
1 file changed, 23 insertions(+), 59 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index
Merge gen_op_addl_A0_im and gen_op_addq_A0_im into gen_add_A0_im
and clean up the ifdef.
Replace the one remaining user of gen_op_addl_A0_im with gen_add_A0_im.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 27 +--
1 file changed, 5
And make the destination argument explicit.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 9052907..fcf4c67 100644
Unify the code across stack pointer widths. Fix the note about
not updating ESP before the potential exception.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 29 +++--
1 file changed, 15 insertions(+), 14 deletions(-)
diff --git
No longer used.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-i386/translate.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 62a2cbc..19cabf6 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
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