- xsnmaddmdp, xvnmaddmdp, xvnmaddmsp
- xsnmsubadp, xvnmsubadp, xvnmsubasp
- xsnmsubmdp, xvnmsubmdp, xvnmsubmsp
V2: reworked implementation per comments from Richard Henderson and
Peter Maydell.
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed-by: Richard Henderson address@hidden
---
target
This patch adds the VSX floating point compare vector instructions:
- xvcmpeqdp[.], xvcmpgedp[.], xvcmpgtdp[.]
- xvcmpeqsp[.], xvcmpgesp[.], xvcmpgtsp[.]
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed-by: Richard Henderson address@hidden
---
target-ppc/fpu_helper.c | 57
This patch adds the VSX floating point multiply instructions defined
by V2.06 of the PowerPC ISA: xsmuldp, xvmuldp, xvmulsp.
V2: re-implemented VSX_MUL macro.
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed-by: Richard Henderson address@hidden
---
target-ppc/fpu_helper.c | 46
This patch adds the VSX scalar floating point compare ordered
and unordered instructions.
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed-by: Richard Henderson address@hidden
---
target-ppc/fpu_helper.c | 39 +++
target-ppc/helper.h |2
This patch adds the VSX Round to Floating Point Integer instructions:
- xsrdpi, xsrdpic, xsrdpim, xsrdpip, xsrdpiz
- xvrdpi, xvrdpic, xvrdpim, xvrdpip, xvrdpiz
- xvrspi, xvrspic, xvrspim, xvrspip, xvrspiz
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed-by: Richard Henderson address
, xvcvuxddp, xvcvuxwdp
- xvcvsxdsp, xscvsxwsp, xvcvuxdsp, xvcvuxwsp
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed-by: Richard Henderson address@hidden
---
target-ppc/fpu_helper.c | 107 +++
target-ppc/helper.h | 22 ++
target-ppc
as well as one might
think. Therefore specific routines for comparing 64 and 32
bit floating point numbers are implemented in the PowerPC
helper code.
V2: consolidated into a single macro, using the softfloat
float*_max/float*_min routines.
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed
On 12/18/2013 9:52 AM, Peter Maydell wrote:
On 18 December 2013 15:31, Tom Musta tommu...@gmail.com wrote:
OK makes sense. I will fold the bug fix back into this series and
re-publish.
If you can keep all the softfloat patches in one PPC series
and all at the beginning of the series
functions.
- assorted style fixes
V3: re-submitting due to patch corruption.
V4: Folded in softfloat bug fixes per Peter Maydell's request.
Tom Musta (22):
softfloat: Fix float64_to_uint64
softfloat: Add float32_to_uint64()
softfloat: Fix float64_to_uint64_round_to_zero
softfloat: Fix
On 12/18/2013 9:52 AM, Peter Maydell wrote:
On 18 December 2013 15:31, Tom Musta tommu...@gmail.com wrote:
OK makes sense. I will fold the bug fix back into this series and
re-publish.
If you can keep all the softfloat patches in one PPC series
and all at the beginning of the series
This patch adds the fcfids, fcfidu and fcfidus instructions which
were introduced in Power ISA 2.06. A common macro is provided to
eliminated redudant code, and the existing fcfid instruction is
re-implemented to use this macro.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc
-by: Tom Musta tommu...@gmail.com
---
target-ppc/fpu_helper.c | 122 +--
target-ppc/helper.h |4 ++
target-ppc/translate.c | 12 +
3 files changed, 50 insertions(+), 88 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc
helper is modified to correctly handle some of
the boundary cases (NaNs and the inexact flag).
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/fpu_helper.c | 12 ++--
target-ppc/translate_init.c |2 ++
2 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/target
-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate_init.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 7bb9bbc..ec65bf4 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
in aligment check for lharx (caught by Richard).
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c | 50 +++
1 files changed, 24 insertions(+), 26 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 3344fa9
This patch adds the Load Floating Point as Integer Word and
Zero Indexed (lfiwzx) instruction which was introduced in
Power ISA 2.06.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c | 15 +++
1 files changed, 15 insertions(+), 0 deletions(-)
diff --git
This patch adds the Floating Point Test for Divide instruction which
was introduced in Power ISA 2.06.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/fpu_helper.c | 56 ++
target-ppc/helper.h |2 +
target-ppc/translate.c | 17
This patch adds the Floating Point Test for Square Root instruction
which was introduced in Power ISA 2.06.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/fpu_helper.c | 31 +++
target-ppc/helper.h |1 +
target-ppc/translate.c | 14
This patch adds the VSX instructions that convert between floating
point formats: xscvdpsp, xscvspdp, xvcvdpsp, xvcvspdp.
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed-by: Richard Henderson address@hidden
---
target-ppc/fpu_helper.c | 46
This patch adds the Bit Permute Doubleword (bpermd) instruction,
which was introduced in Power ISA 2.06 as part of the base 64-bit
architecture.
V2: Addressing stylistic comments from Richard Henderson.
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed-by: Richard Henderson address@hidden
This patch adds a flag for base instruction additions to Power ISA
2.06B. The flag will be used to identify/select basic Book I and
Book II instructions that were newly added in that revision of the
architecture. The flag will not be used for VSX or Altivec.
Signed-off-by: Tom Musta tommu
This patch adds the Divide Doubleword Extended instructions.
The implementation builds on the unsigned helper provided in
the previous patch.
V2: Updated to use the host-utils 128 bit divide.
Signed-off-by: Tom Musta tommu...@gmail.com
---
include/qemu/host-utils.h | 14 ++
target
This patch adds the VSX floating point square root instructions
defined by V2.06 of the PowerPC ISA: xssqrtdp, xvsqrtdp, xvsqrtsp.
V2: re-implemented the VSX_SQRT macro.
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed-by: Richard Henderson address@hidden
---
target-ppc/fpu_helper.c | 44
Peter Maydell. softloat changes have been
moved back to the VSX stage 3 patch series.
Tom Musta (14):
target-ppc: Add Flag for Power ISA V2.06
target-ppc: Add ISA2.06 bpermd Instruction
target-ppc: Add ISA2.06 divdeu[o] Instructions
target-ppc: Add ISA2.06 divde[o] Instructions
target-ppc
This patch addes the Signed and Unsigned Divide Word Extended
instructions which were introduced in Power ISA 2.06.
V2: Eliminating extraneous code in the overflow case per comments
from Richard Henderson. Fixed corner case bug in divweu (check
for (RA) = (RB)).
Signed-off-by: Tom Musta tommu
into host-utils per Richard
Henderson's suggestion.
Signed-off-by: Tom Musta tommu...@gmail.com
---
include/qemu/host-utils.h | 14 ++
target-ppc/helper.h |1 +
target-ppc/int_helper.c | 27 +++
target-ppc/translate.c| 20
This patch adds the VSX floating point reciprocal estimate instructions
defined by V2.06 of the PowerPC ISA: xsredp, xvredp, xvresp.
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed-by: Richard Henderson address@hidden
---
target-ppc/fpu_helper.c | 35
This patch adds the VSX floating point test for software square
root instructions defined by V2.06 of the PowerPC ISA: xstsqrtdp,
xvtsqrtdp, xvtsqrtsp.
V2: (a) using locally implemented ppc_float*_get_unbiased_exp
routines (b) eliminated dependency on float*_is_denormal().
Signed-off-by: Tom
.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c | 88 ++-
1 files changed, 41 insertions(+), 47 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index c3d0ebe..27eef84 100644
--- a/target-ppc/translate.c
This patch adds the floating point addition and subtraction
instructions defined by V2.06 of the PowerPC ISA: xssubdp,
xvsubdp and xvsubsp.
V2: re-implemented helper macro and combined add and substract.
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed-by: Richard Henderson address@hidden
On 12/18/2013 4:37 PM, Alexander Graf wrote:
Am 18.12.2013 um 23:11 schrieb Scott Wood scottw...@freescale.com:
On Wed, 2013-12-18 at 23:09 +0100, Alexander Graf wrote:
On 18.12.2013, at 23:02, Scott Wood scottw...@freescale.com wrote:
On Mon, 2013-12-09 at 09:46 -0600, Tom Musta wrote
On 12/20/2013 4:01 AM, Alexander Graf wrote:
The recent VSX patches broken compilation of QEMU when configurated
with --enable-debug, as it was treating target long TCG variables
as i64 which is not true for 32bit targets.
This patch fixes all the places that the compiler has found to use
On 12/19/2013 4:11 PM, Peter Maydell wrote:
On 18 December 2013 20:19, Tom Musta tommu...@gmail.com wrote:
The comment preceding the float64_to_uint64 routine suggests that
the implementation is broken. And this is, indeed, the case.
This patch properly implements the conversion of a 64-bit
On 12/19/2013 3:31 PM, Peter Maydell wrote:
On 18 December 2013 20:19, Tom Musta tommu...@gmail.com wrote:
This patch adds the float32_to_uint64() routine, which converts a
32-bit floating point number to an unsigned 64 bit number.
This contribution can be licensed under either the softfloat
On 12/23/2013 12:10 PM, Alexander Graf wrote:
On 23.12.2013, at 19:08, Andreas Färber afaer...@suse.de wrote:
Am 20.12.2013 02:00, schrieb Alexander Graf:
Alex, we now have those meaningless-without-context commit messages in
qemu.git history. I'm pretty sure I asked the contributor
On 12/31/2013 7:35 AM, Peter Maydell wrote:
We need Tom Musta's softfloat patches too, so I have included them
here. Note that two of these still have outstanding issues identified
in code review : see the notes in their commit messages (and I haven't
applied my signed-off-by line to them).
This patch adds the float32_to_uint64() routine, which converts a
32-bit floating point number to an unsigned 64 bit number.
This contribution can be licensed under either the softfloat-2a or -2b
license.
Signed-off-by: Tom Musta tommu...@gmail.com
---
V2: Reduced patch to just this single
rounding of small negatives in float32_to_uint64
- simplification of max/min instructions using new softfloat routines.
- assorted commentary changes.
Tom Musta (22):
softfloat: Fix float64_to_uint64
softfloat: Add float32_to_uint64()
softfloat: Fix float64_to_uint64_round_to_zero
the invalid exception flag is raised (but
not the inexact flag).
This contribution can be licensed under either the softfloat-2a or -2b
license.
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed-by: Peter Maydell address@hidden
---
V4: Correct commit commentary. Corrected code to properly
the softfloat-2a or -2b
license.
Signed-off-by: Tom Musta tommu...@gmail.com
---
V2: Added softfloat license statement.
V3: Modified to meet QEMU coding conventions.
V4: Fixed incorrect handling of small negatives, which, if rounded
up to zero should not set the inexact flag.
V5: Clarified handling
the float64_to_uint64 routine.
This contribution can be licensed under either the softfloat-2a or -2b
license.
Signed-off-by: Tom Musta tommu...@gmail.com
---
fpu/softfloat.c | 12 +---
1 files changed, 5 insertions(+), 7 deletions(-)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
This patch adds the VSX floating point square root instructions
defined by V2.06 of the PowerPC ISA: xssqrtdp, xvsqrtdp, xvsqrtsp.
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed-by: Richard Henderson address@hidden
---
V2: re-implemented the VSX_SQRT macro.
target-ppc/fpu_helper.c | 44
.
This contribution can be licensed under either the softfloat-2a or -2b
license.
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed-by: Peter Maydell addresshidden
---
V4: Fixed handling of stickiness of the inexact bit per comments from
Peter Maydell.
fpu/softfloat.c | 15 +++
1 files changed, 7
This patch adds the floating point addition and subtraction
instructions defined by V2.06 of the PowerPC ISA: xssubdp,
xvsubdp and xvsubsp.
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed-by: Richard Henderson address@hidden
---
V2: re-implemented helper macro and combined add and substract
This patch adds the VSX floating point reciprocal estimate instructions
defined by V2.06 of the PowerPC ISA: xsredp, xvredp, xvresp.
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed-by: Richard Henderson address@hidden
---
target-ppc/fpu_helper.c | 35
of the FPRF
field is made conditional via a parameter.
All invocations of this routine in existing instructions are
modified to pass 1 and thus retain their current behavior.
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed-by: Richard Henderson address@hidden
---
target-ppc/fpu_helper.c | 103
This patch adds the VSX floating point multiply instructions defined
by V2.06 of the PowerPC ISA: xsmuldp, xvmuldp, xvmulsp.
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed-by: Richard Henderson address@hidden
---
V2: re-implemented VSX_MUL macro.
target-ppc/fpu_helper.c | 46
This patch adds the VSX floating point divide instructions defined
by V2.06 of the PowerPC ISA: xsdivdp, xvdivdp, xvdivsp.
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed-by: Richard Henderson address@hidden
---
V2: re-implemented the VSX_DIV macro.
target-ppc/fpu_helper.c | 49
This patch adds the VSX floating point reciprocal square root
estimate instructions defined by V2.06 of the PowerPC ISA: xsrsqrtedp,
xvrsqrtedp, xvrsqrtesp.
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed-by: Richard Henderson address@hidden
---
V2: re-implemented VSX_RSQRTE macro.
target
as well as one might
think. Therefore specific routines for comparing 64 and 32
bit floating point numbers are implemented in the PowerPC
helper code.
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed-by: Richard Henderson address@hidden
---
V2: consolidated into a single macro, using
This patch adds the VSX floating point test for software square
root instructions defined by V2.06 of the PowerPC ISA: xstsqrtdp,
xvtsqrtdp, xvtsqrtsp.
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed-by: Richard Henderson address@hidden
---
V2: (a) using locally implemented ppc_float
This patch adds the VSX Round to Floating Point Integer instructions:
- xsrdpi, xsrdpic, xsrdpim, xsrdpip, xsrdpiz
- xvrdpi, xvrdpic, xvrdpim, xvrdpip, xvrdpiz
- xvrspi, xvrspic, xvrspim, xvrspip, xvrspiz
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed-by: Richard Henderson address
, xvcvuxddp, xvcvuxwdp
- xvcvsxdsp, xscvsxwsp, xvcvuxdsp, xvcvuxwsp
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed-by: Richard Henderson address@hidden
---
target-ppc/fpu_helper.c | 107 +++
target-ppc/helper.h | 22 ++
target-ppc
This patch adds the VSX scalar floating point compare ordered
and unordered instructions.
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed-by: Richard Henderson address@hidden
---
target-ppc/fpu_helper.c | 39 +++
target-ppc/helper.h |2
This patch adds the VSX instructions that convert between floating
point formats: xscvdpsp, xscvspdp, xvcvdpsp, xvcvspdp.
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed-by: Richard Henderson address@hidden
---
target-ppc/fpu_helper.c | 45
This patch adds the VSX floating point compare vector instructions:
- xvcmpeqdp[.], xvcmpgedp[.], xvcmpgtdp[.]
- xvcmpeqsp[.], xvcmpgesp[.], xvcmpgtsp[.]
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed-by: Richard Henderson address@hidden
---
target-ppc/fpu_helper.c | 58
This patch adds the VSX floating point test for software divide
instructions defined by V2.06 of the PowerPC ISA: xstdivdp, xvtdivdp,
and xvtdivsp.
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed-by: Richard Henderson address@hidden
---
V2: added ppc_float*_get_unbiased_exp() routines
This patch adds general support that will be used by the VSX helper
routines:
- a union describing the various VSR subfields.
- access routines to get and set VSRs
- VSX decoders
- a general routine to generate a handler that invokes a VSX
helper.
Signed-off-by: Tom Musta tommu
- xsnmaddmdp, xvnmaddmdp, xvnmaddmsp
- xsnmsubadp, xvnmsubadp, xvnmsubasp
- xsnmsubmdp, xvnmsubmdp, xvnmsubmsp
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed-by: Richard Henderson address@hidden
---
V2: reworked implementation per comments from Richard Henderson and
Peter Maydell.
target
This patch refactors the stxsdx instruction. Reusable code is
extracted into a macro which will be used in subsequent patches
in this series.
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed-by: Richard Henderson r...@twiddle.net
---
target-ppc/translate.c | 27
This patch adds the scalar load instructions introduced in ISA
V2.07:
- Load VSX Scalar as Integer Word Algebraic Indexd (lxsiwax)
- Load VSX Scalar as Integer Word and Zero Indexed (lxsiwzx)
- Load VSX Scalar Single-Precision Indexed (lxsspx)
Signed-off-by: Tom Musta tommu...@gmail.com
This patch adds two store scalar instructions:
- Store VSX Scalar as Integer Word Indexed (stxsiwx)
- Store VSX Scalar Single-Precision Indexed (stxsspx)
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed-by: Richard Henderson r...@twiddle.net
---
V5: Updated to address tcg-debug
.
V4: Changed fused multiply/add to use helper_frsp (inadvertently re-injected
when I used an earlier patch).
V5: Fixed tcg compilation problems.
Tom Musta (14):
target-ppc: VSX Stage 4: Add VSX 2.07 Flag
target-ppc: VSX Stage 4: Refactor lxsdx
target-ppc: VSX Stage 4: Add lxsiwax, lxsiwzx
This patch adds a flag to identify those VSX instructions that are
new to Power ISA V2.07. The flag is added to the Power 8 processor
initialization so that the P8 models understand how to decode and
emulate instructions in this category.
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed
This patch refactors the lxsdx generator. Resuable code is isolated
into a macro. The macro will be used in subsequent patches in this
series to implement other scalar load instructions.
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed-by: Richard Henderson r...@twiddle.net
---
target-ppc
This patch adds the VSX Scalar Square Root Single Precision (xssqrtsp)
instruction.
The existing VSX_SQRT() macro is modified to support rounding of the
intermediate double-precision result to single-precision.
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed-by: Richard Henderson r
This patch adds the VSX Scalar Add Single-Precision (xsaddsp) and
VSX Scalar Subtract Single-Precision (xssubsp) instructions.
The existing VSX_ADD_SUB macro is modified to support the rounding
of the (intermediate) result to single-precision.
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed
This patch adds the VSX Scalar Reciprocal Square Root Estimate
Single Precision (xsrsqrtesp) instruction.
The existing VSX_RSQRTE() macro is modified to support rounding
of the intermediate double-precision result to single precision.
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed
This patch adds the VSX Scalar Reciprocal Estimate Single Precision
(xsresp) instruction.
The existing VSX_RE macro is modified to support rounding of the
intermediate double precision result to single precision.
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed-by: Richard Henderson r
This patch adds the VSX Scalar Multiply Single-Precision (xsmulsp)
instruction.
The existing VSX_MUL macro is modified to support rounding of the
intermediate result to single precision.
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed-by: Richard Henderson r...@twiddle.net
---
V2: Updated
This patch adds the VSX Scalar Divide Single Precision (xsdivsp)
instruction.
The existing VSX_DIV macro is modified to support rounding of the
intermediate double precision result to single precision.
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed-by: Richard Henderson r...@twiddle.net
point conversion macro (VSX_CVT_INT_TO_FP)
is modified to support the rounding of the intermediate floating point
result to single precision.
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed-by: Richard Henderson r...@twiddle.net
---
V2: updated conversion to single precision range.
target
This patchs adds the VSX Logical instructions that are new with
ISA V2.07:
- VSX Logical Equivalence (xxleqv)
- VSX Logical NAND (xxlnand)
- VSX Logical ORC (xxlorc)
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed-by: Richard Henderson r...@twiddle.net
---
V5: Changes to address tcg
On 12/27/2013 6:30 PM, Scott Wood wrote:
These instructions are phased-in on embedded, and unlike bpermd are not
present on e5500/e6500 which are 64-bit ISA 2.06 implementations.
Wasn't the conclusion in a previous thread to use separate flags for
these instruction groups?
-Scott
Scott:
On 12/24/2013 10:02 AM, Richard Henderson wrote:
I'll also note that frin can't properly be implemented with
float_round_nearest_even because it doesn't round to even.
Good catch. I should be able to use Peter's ties away rounding
mode patches.
helpers to avoid double rounding.
- Corrected frin to use nearest ties away rounding mode instead of
nearest ties to even.
- Updated (new) Power7+ model to include all newly added instruction flags.
- Assorted comments from Richard Henderson, Peter Maydell and Scott Wood.
Tom Musta (22
This patch addes the Unsigned Divide Word Extended instructions
which were introduced in Power ISA 2.06B.
Signed-off-by: Tom Musta tommu...@gmail.com
---
V2: Eliminating extraneous code in the overflow case per comments
from Richard Henderson. Fixed corner case bug in divweu (check
for (RA
.
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed-by: Richard Henderson address@hidden
---
V2: Moved the 128-bit divide routine into host-utils per Richard
Henderson's suggestion.
V4: Use the newly added PPC2_DIVE_ISA206 flag. Modified helper
macro which will be common for divde[u] and divwe[u
This patch adds a flag for the Divide Extended instructions that
were introduced in Power ISA V2.06B. The flag is added to the
Power7 and Power8 models.
Signed-off-by: Tom Musta tommu...@gmail.com
---
V4: Split into new and separate patch. Added flag to Power7+
model.
target-ppc/cpu.h
This patch adds the Divide Doubleword Extended instructions.
The implementation builds on the unsigned helper provided in
the previous patch.
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed-by: Richard Henderson address@hidden
---
V2: Updated to use the host-utils 128 bit divide.
V4: Using
This patch adds a flag for the floating point conversion instructions
introduced in Power ISA 2.06B.
Signed-off-by: Tom Musta tommu...@gmail.com
---
V4: Split single flag into multiple flags per discussion with
Alex Graf and Scott Wood. Added to Power7+ config.
target-ppc/cpu.h
This patch adds the fcfids, fcfidu and fcfidus instructions which
were introduced in Power ISA 2.06B. A common macro is provided to
eliminate repetitious code, and the existing fcfid instruction is
refactored to use this macro.
Signed-off-by: Tom Musta tommu...@gmail.com
---
V4: Using the newly
tiesAway rounding mode.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Message-Id: 1389013881-15726-16-git-send-email-peter.mayd...@linaro.org
Reviewed-by: Tom Musta tommu...@gmail.com
Reviewed-by: Richard Henderson r...@twiddle.net
---
fpu/softfloat.c | 405
This patch adds the byte and halfword variants of the Store Conditional
instructions. A common macro is introduced and the existing implementations
of stwcx. and stdcx. are refactored to use this macro.
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed-by: Richard Henderson address@hidden
This patch adds the Floating Point Test for Divide instruction which
was introduced in Power ISA 2.06B.
Signed-off-by: Tom Musta tommu...@gmail.com
---
V4: Using the newly added PPC2_FP_TST_ISA206 flag. Modified helper
signature per Richard Henderson's review.
target-ppc/fpu_helper.c | 56
This patch adds a flag for Floating Point Test instructions that were
introduced in Power ISA V2.06B.
Signed-off-by: Tom Musta tommu...@gmail.com
---
V4: Split single flag into multiple flags per discussion with
Alex Graf and Scott Wood. Added flag to Power7+ model.
target-ppc/cpu.h
This patch adds the Floating Point Test for Square Root instruction
which was introduced in Power ISA 2.06.
Signed-off-by: Tom Musta tommu...@gmail.com
---
V4: Using the newly added PPC2_FP_TST_ISA206 flag. Modified helper
signature per Richard Henderson's review.
target-ppc/fpu_helper.c
This patch adds the Load Floating Point as Integer Word and
Zero Indexed (lfiwzx) instruction which was introduced in
Power ISA 2.06.
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed-by: Richard Henderson address@hidden
---
V4: Using the PPC2_FP_CVT_ISA206 flag.
target-ppc/translate.c
-off-by: Tom Musta tommu...@gmail.com
Reviewed-by: Richard Henderson address@hidden
---
target-ppc/translate_init.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index bcaee6c..a83c964 100644
--- a/target-ppc
(fctidu)
- Floating Convert to Integer Doubleword Unsigned with Round
Toward Zero (fctiduz)
A common macro is developed to eliminate repetitious code. Existing
instructions
are also refactoried to use this macro (fctiw, fctiwz, fctid, fctidz).
Signed-off-by: Tom Musta tommu...@gmail.com
helper is modified to correctly handle some of
the boundary cases (NaNs and the inexact flag).
Signed-off-by: Tom Musta tommu...@gmail.com
---
V4: frin changed to use ties away rounding mode per Richard Henderson's
review. Modified NaN handling. Proper handling of stickiness of
the inexact flag
This patch adds the Bit Permute Doubleword (bpermd) instruction,
which was introduced in Power ISA 2.06 as part of the base 64-bit
architecture.
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed-by: Richard Henderson address@hidden
---
V2: Addressing stylistic comments from Richard Henderson
This patch addes the signed Divide Word Extended instructions
which were introduced in Power ISA 2.06B.
Signed-off-by: Tom Musta tommu...@gmail.com
---
V2: Eliminating extraneous code in the overflow case per comments
from Richard Henderson. Fixed corner case bug in divweu (check
for (RA) = (RB
the rounding operation naturally causes
the exact tie to round up in magnitude.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Message-Id: 1389013881-15726-17-git-send-email-peter.mayd...@linaro.org
Reviewed-by: Tom Musta tommu...@gmail.com
Reviewed-by: Richard Henderson r...@twiddle.net
---
fpu
This patch adds the byte and halfword variants of the Load and
Reserve instructions. Since there is much commonality among
all forms of Load and Reserve, a macro is provided and the existing
implementations of lwarx and ldarx are refactoried to use this
macro.
Signed-off-by: Tom Musta tommu
This patch adds a flag for the atomic instructions introduced
in Power ISA V2.06B.
Signed-off-by: Tom Musta tommu...@gmail.com
---
V4: Split into new and separate patch. Added to Power7+ model.
target-ppc/cpu.h|5 -
target-ppc/translate_init.c |9 ++---
2 files
-by: Peter Maydell peter.mayd...@linaro.org
Message-Id: 1389013881-15726-14-git-send-email-peter.mayd...@linaro.org
Reviewed-by: Tom Musta tommu...@gmail.com
Reviewed-by: Richard Henderson r...@twiddle.net
---
fpu/softfloat.c | 209 +--
1 files
...@linaro.org
Reviewed-by: Richard Henderson r...@twiddle.net
Reviewed-by: Tom Musta tommu...@gmail.com
---
fpu/softfloat.c | 105 ++
1 files changed, 66 insertions(+), 39 deletions(-)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 2c598ca..f95c964
Arggh.
I relied on Power ISA Book I Section 7.6.1 as a definitive list of VSX
instructions. Unfortunately it is not complete.
I will publish soon V6 of this series to add in some ISA 2.07 VSX
instructions that I missed:
- mfvsr*, mtvsr*
- fmrg[eo]w
- xsrsp
- xscvdpspn, xscvspdpn
This patch adds a flag to identify those VSX instructions that are
new to Power ISA V2.07. The flag is added to the Power 8 processor
initialization so that the P8 models understand how to decode and
emulate instructions in this category.
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed
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