Add SHA_NI feature bit. Its spec can be found at:
https://software.intel.com/sites/default/files/managed/39/c5/325462-sdm-vol-1-2abcd-3abcd.pdf
Signed-off-by: Yi Sun <yi.y@linux.intel.com>
---
target-i386/cpu.c | 2 +-
target-i386/cpu.h | 1 +
2 files changed, 2 insertions(+), 1 de
On 16-12-14 13:17:12, Paolo Bonzini wrote:
>
>
> On 14/12/2016 03:50, Yi Sun wrote:
> > Add SHA_NI feature bit. Its spec can be found at:
> > https://software.intel.com/sites/default/files/managed/39/c5/325462-sdm-vol-1-2abcd-3abcd.pdf
> >
> > Signed-off-by:
rio to break migration? From latest
qemu integrated scalable mode patches to an old qemu without scalable
mode?
The changes look good to me. Thanks for the fix!
Reviewed-by: Yi Sun
> The normal way should be that we use something like
> VMSTATE_UINT32_TEST() or subsections for the new vms
.
---
Liu, Yi L (2):
intel_iommu: scalable mode emulation
intel_iommu: add 256 bits qi_desc support
Yi Sun (1):
intel_iommu: add scalable-mode option to make scalable mode work
hw/i386/intel_iommu.c | 540 ++---
hw/i386/intel_iommu_internal.
to support scalable mode.
Signed-off-by: Liu, Yi L
[Yi Sun is co-developer to contribute much to refine the whole commit.]
Signed-off-by: Yi Sun
---
v2:
- remove unnecessary macros.
- rename macros to capital.
- make 're->hi' assignment be unconditional to simplify codes.
patch set:
https://www.spinics.net/lists/kernel/msg2985279.html
Signed-off-by: Liu, Yi L
Signed-off-by: Yi Sun
---
v2:
- rename "scalable-mode" to "x-scalable-mode".
- remove caching_mode check when scalable_mode is set.
- check dma_drain check when scalable_
From: "Liu, Yi L"
Per Intel(R) VT-d 3.0, the qi_desc is 256 bits in Scalable
Mode. This patch adds emulation of 256bits qi_desc.
Signed-off-by: Liu, Yi L
[Yi Sun is co-developer to rebase and refine the patch.]
Signed-off-by: Yi Sun
---
v2:
- modify s-o-b position.
to support scalable mode.
Signed-off-by: Liu, Yi L
[Yi Sun is co-developer to contribute much to refine the whole commit.]
Signed-off-by: Yi Sun
---
RFC v2->v1
- revert unnecessary rename in 'vtd_ce_present".
- use 'ce_size' to judge if it is scalable mode in
'vtd_get_conte
On 19-03-05 12:48:36, Peter Xu wrote:
> On Tue, Mar 05, 2019 at 11:24:24AM +0800, Yi Sun wrote:
> > On 19-03-05 11:09:34, Peter Xu wrote:
> > > On Tue, Mar 05, 2019 at 10:34:52AM +0800, Yi Sun wrote:
> > > > Intel vt-d rev3.0 [1] introduces a new translation mode
On 19-03-05 13:36:12, Peter Xu wrote:
> On Tue, Mar 05, 2019 at 01:15:53PM +0800, Yi Sun wrote:
>
> [...]
>
> > > > w/o passthr
> > > > -device intel-iommu \
> > > > -netdev tap,id=net1,vhost=off|on \
> > > > -device virt
On 19-03-05 11:09:34, Peter Xu wrote:
> On Tue, Mar 05, 2019 at 10:34:52AM +0800, Yi Sun wrote:
> > Intel vt-d rev3.0 [1] introduces a new translation mode called
> > 'scalable mode', which enables PASID-granular translations for
> > first level, second level, nested a
- move 's->dma_drain' check from 'vtd_init' to 'vtd_decide_config'.
---
Liu, Yi L (2):
intel_iommu: scalable mode emulation
intel_iommu: add 256 bits qi_desc support
Yi Sun (1):
intel_iommu: add scalable-mode option to make scalable mode work
hw/i386/int
patch set:
https://www.spinics.net/lists/kernel/msg2985279.html
Signed-off-by: Liu, Yi L
Signed-off-by: Yi Sun
---
RFC v2->v1:
- move 's->dma_drain' check from 'vtd_init' to 'vtd_decide_config'.
---
hw/i386/intel_iommu.c | 25 +
hw/i386/intel_iommu
From: "Liu, Yi L"
Per Intel(R) VT-d 3.0, the qi_desc is 256 bits in Scalable
Mode. This patch adds emulation of 256bits qi_desc.
Signed-off-by: Liu, Yi L
[Yi Sun is co-developer to rebase and refine the patch.]
Signed-off-by: Yi Sun
Reviewed-by: Peter Xu
---
RFC v2->v1
On 19-03-01 14:59:00, Peter Xu wrote:
> On Thu, Feb 28, 2019 at 09:47:56PM +0800, Yi Sun wrote:
> > From: "Liu, Yi L"
> >
> > Per Intel(R) VT-d 3.0, the qi_desc is 256 bits in Scalable
> > Mode. This patch adds emulation of 256bits qi_desc.
> >
>
On 19-03-01 14:52:19, Peter Xu wrote:
> On Thu, Feb 28, 2019 at 09:47:55PM +0800, Yi Sun wrote:
> > From: "Liu, Yi L"
> >
> > Intel(R) VT-d 3.0 spec introduces scalable mode address translation to
> > replace extended context mode. This patch extends current
On 19-03-01 15:07:34, Peter Xu wrote:
> On Thu, Feb 28, 2019 at 09:47:54PM +0800, Yi Sun wrote:
> > Intel vt-d rev3.0 [1] introduces a new translation mode called
> > 'scalable mode', which enables PASID-granular translations for
> > first level, second level, nested a
On 19-03-01 15:04:14, Peter Xu wrote:
[...]
> > @@ -3540,6 +3555,15 @@ static void vtd_init(IntelIOMMUState *s)
> > s->cap |= VTD_CAP_CM;
> > }
> >
> > +/* TODO: read cap/ecap from host to decide which cap to be exposed. */
> > +if (s->scalable_mode) {
> > +if
On 19-02-12 14:46:29, Peter Xu wrote:
[...]
> > diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> > index 3664a00..447fdf3 100644
> > --- a/hw/i386/intel_iommu.c
> > +++ b/hw/i386/intel_iommu.c
> > @@ -2492,6 +2492,17 @@ static bool vtd_process_inv_desc(IntelIOMMUState *s)
> >
On 19-02-15 13:39:05, Peter Xu wrote:
> On Fri, Feb 15, 2019 at 01:22:34PM +0800, Yi Sun wrote:
>
> [...]
>
> > > > +/* TODO: read cap/ecap from host to decide which cap to be
> > > > exposed. */
> > > > +if (s->sca
On 19-02-11 18:37:41, Peter Xu wrote:
> On Wed, Jan 30, 2019 at 01:09:10PM +0800, Yi Sun wrote:
> > Intel vt-d rev3.0 [1] introduces a new translation mode called
> > 'scalable mode', which enables PASID-granular translations for
> > first level, second level, nested a
On 19-02-11 18:12:13, Peter Xu wrote:
> On Wed, Jan 30, 2019 at 01:09:11PM +0800, Yi Sun wrote:
> > From: "Liu, Yi L"
> >
> > Intel(R) VT-d 3.0 spec introduces scalable mode address translation to
> > replace extended context mode. This patch extends current
On 19-02-12 14:27:28, Peter Xu wrote:
> On Wed, Jan 30, 2019 at 01:09:12PM +0800, Yi Sun wrote:
> > From: "Liu, Yi L"
> >
> > Per Intel(R) VT-d 3.0, the qi_desc is 256 bits in Scalable
> > Mode. This patch adds emulation of 256bits qi_desc.
> >
>
On 19-02-14 11:24:35, Peter Xu wrote:
> On Thu, Feb 14, 2019 at 09:52:04AM +0800, Yi Sun wrote:
>
> [...]
>
> > > > > > /* Fetch an Invalidation Descriptor from the Invalidation Queue */
> > > > > > -static bool vtd_get_inv_desc(dma_addr_t base
On 19-02-13 18:42:24, Peter Xu wrote:
> On Wed, Feb 13, 2019 at 05:00:41PM +0800, Yi Sun wrote:
>
> [...]
>
> > > >
> > > > /* context entry operations */
> > > > #define vtd_get_ce_size(s, ce) \
> > > > @@ -65,6 +66
to support scalable mode.
[Yi Sun is co-developer to contribute much to refine the whole commit.]
Signed-off-by: Yi Sun
Signed-off-by: Liu, Yi L
---
hw/i386/intel_iommu.c | 528 ++---
hw/i386/intel_iommu_internal.h | 43 +++-
hw/i386/trace-events
From: "Liu, Yi L"
Per Intel(R) VT-d 3.0, the qi_desc is 256 bits in Scalable
Mode. This patch adds emulation of 256bits qi_desc.
[Yi Sun is co-developer to rebase and refine the patch.]
Signed-off-by: Yi Sun
Signed-off-by: Liu, Yi L
---
hw/i386/intel_iommu.c
/00/LC3-SIOV-final.pdf
Liu, Yi L (2):
intel_iommu: scalable mode emulation
intel_iommu: add 256 bits qi_desc support
Yi Sun (1):
intel_iommu: add scalable-mode option to make scalable mode work
hw/i386/intel_iommu.c | 732 -
hw/i386
patch set:
https://www.spinics.net/lists/kernel/msg2985279.html
Signed-off-by: Liu, Yi L
Signed-off-by: Yi Sun
---
hw/i386/intel_iommu.c | 22 ++
hw/i386/intel_iommu_internal.h | 6 ++
include/hw/i386/intel_iommu.h | 3 ++-
3 files changed, 30 insert
Should directly read DMAR_RTADDR_REG but not using 's->root'.
Because 's->root' is modified in 'vtd_root_table_setup()' so
that the first 12 bits are omitted. This causes the guest
iommu debugfs cannot show pasid tables.
Signed-off-by: Yi Sun
---
hw/i386/intel_iommu.c | 7 +++
f0, notifier->end=0x
Skip this notification but not coredump makes everything
work well.
Signed-off-by: Yi Sun
---
memory.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/memory.c b/memory.c
index 06484c2bff..62ad0f3377 100644
--- a/memory.c
+++ b
On 20-03-02 22:36:39, Yan Zhao wrote:
> On Tue, Mar 03, 2020 at 11:11:14AM +0800, Yi Sun wrote:
> > It is too strict to use assert to make qemu coredump if
> > the notification does not overlap with registered range.
> > Skip it is fine enough.
> >
> > During tes
this commit can optimize the downtime. But we observed
that the dirty log stop cannot be executed if user inputs "quit" in qemu
monitor after migration completes. Have you considered such case before?
Any suggestion? Thanks!
BRs,
Yi Sun
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