[PATCH RFC 5/9] target/riscv: Implement kvm_arch_put_registers

Put GPR CSR and FP registers by kvm by KVM_SET_ONE_REG ioctl Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/kvm.c | 136 - 1 file changed, 135 insertions(+), 1 deletion(-) diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c

[PATCH RFC 3/9] target/riscv: Implement function kvm_arch_init_vcpu

Get isa info from kvm while kvm init. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/kvm.c | 26 +- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 8c386d9acf..3e8f8e7185 100644

[PATCH RFC 4/9] target/riscv: Implement kvm_arch_get_registers

Get GPR CSR and FP registers from kvm by KVM_GET_ONE_REG ioctl. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/kvm.c | 144 - 1 file changed, 143 insertions(+), 1 deletion(-) diff --git a/target/riscv/kvm.c b/target/riscv

[PATCH RFC 2/9] target/riscv: Add target/riscv/kvm.c to place the public kvm interface

Add target/riscv/kvm.c to place kvm_arch_* function needed by kvm/kvm-all.c. Meanwhile, add riscv64 kvm support to configure. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- configure | 1 + target/riscv/Makefile.objs | 1 + target/riscv/kvm.c | 128

[PATCH RFC 7/9] hw/riscv: PLIC update external interrupt by KVM when kvm enabled

Only support supervisor external interrupt currently. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- hw/riscv/sifive_plic.c | 31 ++- target/riscv/kvm.c | 19 +++ target/riscv/kvm_riscv.h | 1 + 3 files changed, 42 insertions(+), 9

[PATCH RFC 8/9] target/riscv: Handler KVM_EXIT_RISCV_SBI exit

Use char-fe handler console sbi call, which implement early console io while apply 'earlycon=sbi' into kernel parameters. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/kvm.c | 54 +- 1 file changed, 53 insertions(+), 1

[PATCH RFC 1/9] linux-header: Update linux/kvm.h

Update linux/kvm.h to commit b9a6e4cd9 on https://github.com/kvm-riscv/linux. Only use this header file, so do not update all linux headers. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- linux-headers/linux/kvm.h | 8 1 file changed, 8 insertions(+) diff --git a/linux

[PATCH RFC 6/9] target/riscv: Support start kernel directly by KVM

Get kernel and fdt start address in virt.c, and pass them to KVM when cpu reset.In addition,add kvm_riscv.h to place riscv specific interface. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- hw/riscv/virt.c | 15 +-- target/riscv/cpu.c | 4 target

[PATCH RFC 0/9] Add riscv64 kvm accel support

mat=raw,id=hd0 \ -device virtio-blk-device,drive=hd0 \ -append "root=/dev/vda rw console=ttyS0 earlycon=sbi" Yifei Jiang (9): linux-header: Update linux/kvm.h target/riscv: Add target/riscv/kvm.c to place the public kvm interface target/riscv: Implement functio

[PATCH RFC 9/9] target/riscv: add host riscv64 cpu type

Currently, host cpu is inherited simply. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/cpu.c | 5 + target/riscv/cpu.h | 1 + 2 files changed, 6 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3c3264869f..11557719cf 100644 --- a/target

[PATCH RFC v2 7/9] hw/riscv: PLIC update external interrupt by KVM when kvm enabled

Only support supervisor external interrupt currently. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- hw/riscv/sifive_plic.c | 31 ++- target/riscv/kvm.c | 19 +++ target/riscv/kvm_riscv.h | 1 + 3 files changed, 42 insertions(+), 9

[PATCH RFC v2 6/9] target/riscv: Support start kernel directly by KVM

Get kernel and fdt start address in virt.c, and pass them to KVM when cpu reset. In addition, add kvm_riscv.h to place riscv specific interface. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- hw/riscv/virt.c | 16 +--- target/riscv/cpu.c | 4 target

[PATCH RFC v2 8/9] target/riscv: Handler KVM_EXIT_RISCV_SBI exit

Use char-fe handler console sbi call, which implement early console io while apply 'earlycon=sbi' into kernel parameters. The common SBI interface sbi_ecall_interface.h is introduced from https://github.com/riscv/opensbi/blob/master/include/sbi/sbi_ecall_interface.h. Signed-off-by: Yifei Jiang

[PATCH RFC v2 5/9] target/riscv: Implement kvm_arch_put_registers

Put GPR CSR and FP registers to kvm by KVM_SET_ONE_REG ioctl Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/kvm.c | 136 - 1 file changed, 135 insertions(+), 1 deletion(-) diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c

[PATCH RFC v2 9/9] target/riscv: add host cpu type

Currently, host cpu is inherited simply. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/cpu.c | 6 ++ target/riscv/cpu.h | 1 + 2 files changed, 7 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6a6af13ab9..e5b42c3a54 100644 --- a/target

[PATCH RFC v2 4/9] target/riscv: Implement kvm_arch_get_registers

Get GPR CSR and FP registers from kvm by KVM_GET_ONE_REG ioctl. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/kvm.c | 144 - 1 file changed, 143 insertions(+), 1 deletion(-) diff --git a/target/riscv/kvm.c b/target/riscv

[PATCH RFC v2 0/9] Add riscv kvm accel support

img,format=raw,id=hd0 \ -device virtio-blk-device,drive=hd0 \ -append "root=/dev/vda rw console=ttyS0 earlycon=sbi" Changes since RFC v1 1、Add separate SBI ecall interface header. 2、Add riscv32 kvm accel support. Yifei Jiang (9): linux-header: Update linux/kvm.h targ

[PATCH RFC v2 3/9] target/riscv: Implement function kvm_arch_init_vcpu

Get isa info from kvm while kvm init. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/kvm.c | 26 +- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 8c386d9acf..3e8f8e7185 100644

[PATCH RFC v2 2/9] target/riscv: Add target/riscv/kvm.c to place the public kvm interface

Add target/riscv/kvm.c to place kvm_arch_* function needed by kvm/kvm-all.c. Meanwhile, add kvm support in configure file. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- configure | 1 + target/riscv/Makefile.objs | 1 + target/riscv/kvm.c | 128

[PATCH RFC v2 1/9] linux-header: Update linux/kvm.h

Update linux/kvm.h to commit b9a6e4cd9 on https://github.com/kvm-riscv/linux. Only use this header file, so do not update all linux headers. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- linux-headers/linux/kvm.h | 8 1 file changed, 8 insertions(+) diff --git a/linux

[PATCH 0/2] avoid integer overflow

the constant default type is "int", when the constant is shifted to the left, it may exceed 32 bits, resulting in integer overflowing. So constant type need change to "long" Yifei Jiang (2): tcg: avoid integer overflow accel/tcg: avoid integer overflow accel/tcg/cputl

[PATCH 2/2] accel/tcg: avoid integer overflow

ed using 32-bit arithmetic, and then used in a context that expects an expression of type "target_ulong" (64 bits, unsigned). 1525if (addr & ((1 << a_bits) - 1)) { Signed-off-by: Yifei Jiang Signed-off-by: Mingwang Li Reported-by: Euler Robot --- accel/tcg/cputlb.c

[PATCH 1/2] tcg: avoid integer overflow

ed using 32-bit arithmetic, and then used in a context that expects an expression of type "int64_t" (64 bits, signed). tcg_gen_muli_i64(t, t, (1 << nbit) - 1); Signed-off-by: Yifei Jiang Signed-off-by: Mingwang Li Reported-by: Euler Robot --- tcg/tcg-op-gvec.c | 18

[PATCH V2 0/5] Support RISC-V migration

/riscv/machine.c. 2. Regenerate some state of PMP at post_load hook. Yifei Jiang (5): target/riscv: Add basic vmstate description of CPU target/riscv: Add PMP state description target/riscv: Add H extension state description target/riscv: Add V extension state description target/riscv: Add

[PATCH V2 2/5] target/riscv: Add PMP state description

() and pmp_update_rule_nums() to update 'vmstate_pmp_addr' and 'num_rules' respectively. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/machine.c | 50 ++ target/riscv/pmp.c | 29 ++-- target/riscv/pmp.h | 2 ++ 3

[PATCH V2 4/5] target/riscv: Add V extension state description

In the case of supporting V extension, add V extension description to vmstate_riscv_cpu. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin Reviewed-by: Richard Henderson --- target/riscv/machine.c | 25 + 1 file changed, 25 insertions(+) diff --git a/target/riscv

[PATCH V2 3/5] target/riscv: Add H extension state description

In the case of supporting H extension, add H extension description to vmstate_riscv_cpu. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/machine.c | 51 ++ 1 file changed, 51 insertions(+) diff --git a/target/riscv/machine.c b

[PATCH V2 1/5] target/riscv: Add basic vmstate description of CPU

Add basic CPU state description to the newly created machine.c Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/cpu.c | 7 target/riscv/cpu.h | 4 +++ target/riscv/machine.c | 77 target/riscv/meson.build | 3

[PATCH V2 5/5] target/riscv: Add sifive_plic vmstate

Add sifive_plic vmstate for supporting sifive_plic migration. Current vmstate framework only supports one structure parameter as num field to describe variable length arrays, so introduce num_enables. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- hw/intc/sifive_plic.c | 26

[PATCH V2] target/riscv: raise exception to HS-mode at get_physical_address

must be handled by HS-mode. So introduce TRANSLATE_STAGE2_FAIL so that riscv_cpu_tlb_fill could distinguish and raise it to HS-mode. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/cpu.h| 1 + target/riscv/cpu_helper.c | 17 +++-- 2 files changed, 16

[PATCH V3] target/riscv: raise exception to HS-mode at get_physical_address

must be handled by HS-mode. So introduce TRANSLATE_STAGE2_FAIL so that riscv_cpu_tlb_fill could distinguish and raise it to HS-mode. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/cpu.h| 10 +++--- target/riscv/cpu_helper.c | 35

[PATCH RFC v3 04/14] target/riscv: Implement kvm_arch_get_registers

Get GPR CSR and FP registers from kvm by KVM_GET_ONE_REG ioctl. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/kvm.c | 150 - 1 file changed, 149 insertions(+), 1 deletion(-) diff --git a/target/riscv/kvm.c b/target/riscv

[PATCH RFC v3 03/14] target/riscv: Implement function kvm_arch_init_vcpu

Get isa info from kvm while kvm init. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/kvm.c | 26 +- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 8c386d9acf..7983f43f3f 100644

[PATCH RFC v3 13/14] target/riscv: Implement virtual time adjusting with vm state changing

We hope that virtual time adjusts with vm state changing. When a vm is stopped, guest virtual time should stop counting and kvm_timer should be stopped. When the vm is resumed, guest virtual time should continue to count and kvm_timer should be restored. Signed-off-by: Yifei Jiang Signed-off

[PATCH RFC v3 05/14] arget/riscv: Implement kvm_arch_put_registers

Put GPR CSR and FP registers to kvm by KVM_SET_ONE_REG ioctl Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/kvm.c | 142 - 1 file changed, 141 insertions(+), 1 deletion(-) diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c

[PATCH RFC v3 08/14] target/riscv: Handler KVM_EXIT_RISCV_SBI exit

Use char-fe handler console sbi call, which implement early console io while apply 'earlycon=sbi' into kernel parameters. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/kvm.c | 42 - target/riscv/sbi_ecall_interface.h | 72

[PATCH RFC v3 02/14] target/riscv: Add target/riscv/kvm.c to place the public kvm interface

Add target/riscv/kvm.c to place kvm_arch_* function needed by kvm/kvm-all.c. Meanwhile, add kvm support in configure file. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin Reviewed-by: Alistair Francis --- configure| 1 + target/riscv/kvm.c | 128

[PATCH RFC v3 11/14] target/riscv: Support riscv cpu vmstate

Describe gpr, fpr and csr in vmstate_riscv_cpu. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/cpu.c | 20 ++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d8c32a8f84..b698f4adbb 100644

[PATCH RFC v3 06/14] target/riscv: Support start kernel directly by KVM

Get kernel and fdt start address in virt.c, and pass them to KVM when cpu reset. In addition, add kvm_riscv.h to place riscv specific interface. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- hw/riscv/virt.c | 8 target/riscv/cpu.c | 4 target/riscv

[PATCH RFC v3 01/14] linux-header: Update linux/kvm.h

Update linux-headers/linux/kvm.h from https://github.com/kvm-riscv/linux. Only use this header file, so here do not update all linux headers by update-linux-headers.sh until above KVM series is accepted. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- linux-headers/linux/kvm.h | 8

[PATCH RFC v3 00/14] Add riscv kvm accel support

on support. Changes since RFC v1 1. Add separate SBI ecall interface header. 2. Add riscv32 kvm accel support. Yifei Jiang (14): linux-header: Update linux/kvm.h target/riscv: Add target/riscv/kvm.c to place the public kvm interface target/riscv: Implement function kvm_arch_init_vcpu tar

[PATCH RFC v3 14/14] target/riscv: Support virtual time context synchronization

Add virtual time context description to vmstate_riscv_cpu. After cpu being loaded, virtual time context is updated to KVM. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/cpu.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/target/riscv/cpu.c b/target

[PATCH RFC v3 10/14] target/riscv: Add sifive_plic vmstate

Add sifive_plic vmstate for supporting sifive_plic migration. Current vmstate framework only supports one structure parameter as num field to describe variable length arrays, so introduce num_enables. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- hw/riscv/sifive_plic.c | 24

[PATCH RFC v3 12/14] target/riscv: Add kvm_riscv_get/put_regs_timer

== 0. It's better to adapt in KVM, but it doesn't matter that adaping in QEMU. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/cpu.h | 6 target/riscv/kvm.c | 72 ++ 2 files changed, 78 insertions(+) diff --git a/target

[PATCH RFC v3 07/14] hw/riscv: PLIC update external interrupt by KVM when kvm enabled

Only support supervisor external interrupt currently. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- hw/riscv/sifive_plic.c | 31 ++- target/riscv/kvm.c | 19 +++ target/riscv/kvm_riscv.h | 1 + 3 files changed, 42 insertions(+), 9

[PATCH RFC v3 09/14] target/riscv: Add host cpu type

Currently, host cpu is inherited simply. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/cpu.c | 6 ++ target/riscv/cpu.h | 1 + 2 files changed, 7 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 266e70cc47..d8c32a8f84 100644 --- a/target

[PATCH] target/riscv: raise exception to HS-mode at get_physical_address

must be handled by HS-mode. So introduce TRANSLATE_STAGE2_FAIL so that riscv_cpu_tlb_fill could distinguish and raise it to HS-mode. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/cpu.h| 1 + target/riscv/cpu_helper.c | 12 ++-- 2 files changed, 11

[PATCH 1/5] target/riscv: Add basic vmstate description of CPU

Add basic CPU state description to the newly created machine.c Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/cpu.c | 7 - target/riscv/cpu.h | 4 +++ target/riscv/machine.c | 59 target/riscv/meson.build | 3

[PATCH 5/5] target/riscv: Add sifive_plic vmstate

Add sifive_plic vmstate for supporting sifive_plic migration. Current vmstate framework only supports one structure parameter as num field to describe variable length arrays, so introduce num_enables. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- hw/intc/sifive_plic.c | 26

[PATCH 3/5] target/riscv: Add H extention state description

In the case of supporting H extention, add H extention description to vmstate_riscv_cpu. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/machine.c | 51 ++ 1 file changed, 51 insertions(+) diff --git a/target/riscv/machine.c b

[PATCH 2/5] target/riscv: Add PMP state description

In the case of supporting PMP feature, add PMP state description to vmstate_riscv_cpu. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/machine.c | 49 ++ 1 file changed, 49 insertions(+) diff --git a/target/riscv/machine.c b/target

[PATCH 4/5] target/riscv: Add V extention state description

In the case of supporting V extention, add V extention description to vmstate_riscv_cpu. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/machine.c | 25 + 1 file changed, 25 insertions(+) diff --git a/target/riscv/machine.c b/target/riscv

[PATCH 0/5] Support RISC-V migration

found that tcg accelerated migration can be supported with a few changes. Most of the devices have already implemented the migration interface, so, to achieve the tcg accelerated migration, we just need to add vmstate of both cpu and sifive_plic. Yifei Jiang (5): target/riscv: Add basic vmstate

[PATCH V3 1/6] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit

mstatus/mstatush and vsstatus/vsstatush are two halved for RISCV32. This patch expands mstatus and vsstatus to uint64_t instead of target_ulong so that it can be saved as one unit and reduce some ifdefs in the code. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/cpu.c

[PATCH V3 3/6] target/riscv: Add PMP state description

() and pmp_update_rule_nums() to update 'vmstate_pmp_addr' and 'num_rules' respectively. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/machine.c | 50 ++ target/riscv/pmp.c | 29 ++-- target/riscv/pmp.h | 2 ++ 3

[PATCH V3 4/6] target/riscv: Add H extension state description

In the case of supporting H extension, add H extension description to vmstate_riscv_cpu. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/machine.c | 47 ++ 1 file changed, 47 insertions(+) diff --git a/target/riscv/machine.c b

[PATCH V3 5/6] target/riscv: Add V extension state description

In the case of supporting V extension, add V extension description to vmstate_riscv_cpu. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin Reviewed-by: Richard Henderson --- target/riscv/machine.c | 25 + 1 file changed, 25 insertions(+) diff --git a/target/riscv

[PATCH V3 0/6] Support RISC-V migration

declaration to internals.h. 2. Merge m/vsstatus and m/vsstatush into one uint64_t unit. Changes since v1: 1. Add license head to target/riscv/machine.c. 2. Regenerate some state of PMP at post_load hook. Yifei Jiang (6): target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit target

[PATCH V3 6/6] target/riscv: Add sifive_plic vmstate

Add sifive_plic vmstate for supporting sifive_plic migration. Current vmstate framework only supports one structure parameter as num field to describe variable length arrays, so introduce num_enables. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- hw/intc/sifive_plic.c | 26

[PATCH V3 2/6] target/riscv: Add basic vmstate description of CPU

Add basic CPU state description to the newly created machine.c Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/cpu.c | 8 + target/riscv/internals.h | 4 +++ target/riscv/machine.c | 74 target/riscv/meson.build | 3

[PATCH V4 1/6] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit

mstatus/mstatush and vsstatus/vsstatush are two halved for RISCV32. This patch expands mstatus and vsstatus to uint64_t instead of target_ulong so that it can be saved as one unit and reduce some ifdefs in the code. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin Signed-off-by: Alistair

[PATCH V4 0/6] Support RISC-V migration

. Changes since v1: 1. Add license head to target/riscv/machine.c. 2. Regenerate some state of PMP at post_load hook. Yifei Jiang (6): target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit target/riscv: Add basic vmstate description of CPU target/riscv: Add PMP state

[PATCH V4 6/6] target/riscv: Add sifive_plic vmstate

Add sifive_plic vmstate for supporting sifive_plic migration. Current vmstate framework only supports one structure parameter as num field to describe variable length arrays, so introduce num_enables. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin Reviewed-by: Alistair Francis --- hw

[PATCH V4 2/6] target/riscv: Add basic vmstate description of CPU

Add basic CPU state description to the newly created machine.c Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 8 + target/riscv/internals.h | 4 +++ target/riscv/machine.c | 74

[PATCH V4 4/6] target/riscv: Add H extension state description

In the case of supporting H extension, add H extension description to vmstate_riscv_cpu. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin Reviewed-by: Alistair Francis --- target/riscv/machine.c | 47 ++ 1 file changed, 47 insertions(+) diff --git

[PATCH V4 5/6] target/riscv: Add V extension state description

In the case of supporting V extension, add V extension description to vmstate_riscv_cpu. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/machine.c | 25 + 1 file changed, 25 insertions

[PATCH V4 3/6] target/riscv: Add PMP state description

() and pmp_update_rule_nums() to update 'vmstate_pmp_addr' and 'num_rules' respectively. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin Reviewed-by: Alistair Francis --- target/riscv/machine.c | 50 ++ target/riscv/pmp.c | 29

[PATCH] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap

_names. So introduce riscv_cpu_get_trap_name to get the trap cause name. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/cpu.c| 11 +++ target/riscv/cpu.h| 1 + target/riscv/cpu_helper.c | 4 ++-- 3 files changed, 14 insertions(+), 2 deletions(-)

[PATCH] target/riscv: Fix the bug of HLVX/HLV/HSV

s.SUM is ignored." But get_physical_address() doesn't ignore sstatus.SUM, when HLVX/HLV/HSV accesses guest userspace memory. So this patch fixes it. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/cpu_helper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)

[PATCH RFC v4 05/15] target/riscv: Implement kvm_arch_put_registers

Put GPR CSR and FP registers to kvm by KVM_SET_ONE_REG ioctl Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/kvm.c | 142 - 1 file changed, 141 insertions(+), 1 deletion(-) diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c

[PATCH RFC v4 15/15] target/riscv: Add time frequency migration support

will be abort. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/machine.c | 8 1 file changed, 8 insertions(+) diff --git a/target/riscv/machine.c b/target/riscv/machine.c index ef2d5395a8..6955542fef 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c

[PATCH RFC v4 12/15] target/riscv: Support virtual time context synchronization

Add virtual time context description to vmstate_riscv_cpu. After cpu being loaded, virtual time context is updated to KVM. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/machine.c | 14 ++ 1 file changed, 14 insertions(+) diff --git a/target/riscv/machine.c

[PATCH RFC v4 08/15] target/riscv: Handle KVM_EXIT_RISCV_SBI exit

Use char-fe to handle console sbi call, which implement early console io while apply 'earlycon=sbi' into kernel parameters. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/kvm.c | 42 - target/riscv/sbi_ecall_interface.h | 72

[PATCH RFC v4 03/15] target/riscv: Implement function kvm_arch_init_vcpu

Get isa info from kvm while kvm init. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/kvm.c | 27 ++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 8c386d9acf..86660ba81b 100644

[PATCH RFC v4 09/15] target/riscv: Add host cpu type

Currently, host cpu is inherited simply. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/cpu.c | 6 ++ target/riscv/cpu.h | 1 + 2 files changed, 7 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index faee98a58c..439dc89ee7 100644 --- a/target

[PATCH RFC v4 11/15] target/riscv: Implement virtual time adjusting with vm state changing

We hope that virtual time adjusts with vm state changing. When a vm is stopped, guest virtual time should stop counting and kvm_timer should be stopped. When the vm is resumed, guest virtual time should continue to count and kvm_timer should be restored. Signed-off-by: Yifei Jiang Signed-off

[PATCH RFC v4 00/15] Add riscv kvm accel support

v2 - Fix checkpatch error at target/riscv/sbi_ecall_interface.h. - Add riscv migration support. Changes since RFC v1 - Add separate SBI ecall interface header. - Add riscv32 kvm accel support. Yifei Jiang (15): linux-header: Update linux/kvm.h target/riscv: Add target/riscv/kvm.c to place the

[PATCH RFC v4 04/15] target/riscv: Implement kvm_arch_get_registers

Get GPR CSR and FP registers from kvm by KVM_GET_ONE_REG ioctl. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/kvm.c | 150 - 1 file changed, 149 insertions(+), 1 deletion(-) diff --git a/target/riscv/kvm.c b/target/riscv

[PATCH RFC v4 01/15] linux-header: Update linux/kvm.h

Update linux-headers/linux/kvm.h from https://github.com/avpatel/linux/tree/riscv_kvm_v15. Only use this header file, so here do not update all linux headers by update-linux-headers.sh before above KVM series is accepted. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- linux-headers

[PATCH RFC v4 14/15] target/riscv: Synchronize vcpu's frequency with KVM

If vcpu's frequency is specified by cpu option 'frequency', it will be set into KVM by KVM_SET_ONE_REG ioctl. Otherwise, vcpu's frequency will follow KVM by KVM_GET_ONE_REG ioctl. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/kvm.c | 17 + 1 file changed

[PATCH RFC v4 07/15] hw/riscv: PLIC update external interrupt by KVM when kvm enabled

Only support supervisor external interrupt currently. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- hw/intc/sifive_plic.c| 31 ++- target/riscv/kvm.c | 19 +++ target/riscv/kvm_riscv.h | 1 + 3 files changed, 42 insertions(+), 9

[PATCH RFC v4 10/15] target/riscv: Add kvm_riscv_get/put_regs_timer

Add kvm_riscv_get/put_regs_timer to synchronize virtual time context from KVM. To set register of RISCV_TIMER_REG(state) will occur a error from KVM on kvm_timer_state == 0. It's better to adapt in KVM, but it doesn't matter that adaping in QEMU. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng

[PATCH RFC v4 13/15] target/riscv: Introduce dynamic time frequency for virt machine

Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- hw/riscv/virt.c| 18 ++ target/riscv/cpu.c | 3 +++ target/riscv/cpu.h | 2 ++ 3 files changed, 19 insertions(+), 4 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 47b7018193..788a7237b6 100644 ---

[PATCH RFC v4 06/15] target/riscv: Support start kernel directly by KVM

Get kernel and fdt start address in virt.c, and pass them to KVM when cpu reset. In addition, add kvm_riscv.h to place riscv specific interface. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- hw/riscv/virt.c | 8 target/riscv/cpu.c | 4 target/riscv

[PATCH RFC v4 02/15] target/riscv: Add target/riscv/kvm.c to place the public kvm interface

Add target/riscv/kvm.c to place kvm_arch_* function needed by kvm/kvm-all.c. Meanwhile, add kvm support in meson.build file. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin Reviewed-by: Alistair Francis --- meson.build | 2 + target/riscv/kvm.c | 128

[PATCH 1/1] target-riscv: support QMP dump-guest-memory

Add the support needed for creating prstatus elf notes. Now elf notes only contains user_regs. This allows us to use QMP dump-guest-memory. Signed-off-by: Yifei Jiang Signed-off-by: Mingwang Li --- target/riscv/arch_dump.c | 189 +++ target/riscv/cpu.c

[PATCH 0/1] target-riscv: support QMP dump-guest-memory

0x000485b3 0x00090633 0x8020: 0x046358fd 0x1d630118 0x08171305 0x0813 0x8030: 0x48854868 0x0118282f 0x12081463 0x0297 0x8040: 0x48428293 0x0317 0xfbc30313 0x0062b023 ... Yifei Jiang (1): target-riscv: support QM

[PATCH v2 1/1] target-riscv: support QMP dump-guest-memory

Add the support needed for creating prstatus elf notes. Now elf notes only contains user_regs. This allows us to use QMP dump-guest-memory. Signed-off-by: Yifei Jiang Signed-off-by: Mingwang Li --- target/riscv/arch_dump.c | 189 +++ target/riscv/cpu.c

[PATCH v2 0/1] target-riscv: support QMP dump-guest-memory

e for RISC-V linux user. Yifei Jiang (1): target-riscv: support QMP dump-guest-memory target/riscv/arch_dump.c | 189 +++ target/riscv/cpu.c | 2 + target/riscv/cpu.h | 4 + target/riscv/cpu_bits.h | 1 + target/riscv/meson.build | 1 + 5 f

[PATCH v3 1/1] target-riscv: support QMP dump-guest-memory

Add the support needed for creating prstatus elf notes. Now elf notes only contains user_regs. This allows us to use QMP dump-guest-memory. Signed-off-by: Yifei Jiang Signed-off-by: Mingwang Li --- target/riscv/arch_dump.c | 202 +++ target/riscv/cpu.c

[PATCH v3 0/1] target-riscv: support QMP dump-guest-memory

s since v1 1. Fix the build failure for RISC-V linux user. Yifei Jiang (1): target-riscv: support QMP dump-guest-memory target/riscv/arch_dump.c | 202 +++ target/riscv/cpu.c | 2 + target/riscv/cpu.h | 4 + target/riscv/cpu_bits.h | 1 +

[PATCH v4 1/1] target-riscv: support QMP dump-guest-memory

Add the support needed for creating prstatus elf notes. This allows us to use QMP dump-guest-memory. Now ELF notes of RISC-V only contain prstatus elf notes. Signed-off-by: Yifei Jiang Signed-off-by: Mingwang Li Reviewed-by: Alistair Francis Reviewed-by: Andrew Jones Reviewed-by: Palmer

[PATCH v4 0/1] target-riscv: support QMP dump-guest-memory

ion and code comments Changes since v2 1. Add build-bugs. Changes since v1 1. Fix the build failure for RISC-V linux user. Yifei Jiang (1): target-riscv: support QMP dump-guest-memory target/riscv/arch_dump.c | 202 +++ target/riscv/cpu.c | 2 + target

[PATCH RFC v5 03/12] target/riscv: Implement function kvm_arch_init_vcpu

Get isa info from kvm while kvm init. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/kvm.c | 27 ++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 687dd4b621..0d924be33f 100644

[PATCH RFC v5 02/12] target/riscv: Add target/riscv/kvm.c to place the public kvm interface

Add target/riscv/kvm.c to place kvm_arch_* function needed by kvm/kvm-all.c. Meanwhile, add kvm support in meson.build file. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin Reviewed-by: Alistair Francis --- meson.build | 2 + target/riscv/kvm.c | 133

[PATCH RFC v5 01/12] linux-header: Update linux/kvm.h

Update linux-headers/linux/kvm.h from https://github.com/avpatel/linux/tree/riscv_kvm_v17. Only use this header file, so here do not update all linux headers by update-linux-headers.sh until above KVM series is accepted. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- linux-headers

[PATCH RFC v5 09/12] target/riscv: Add host cpu type

'host' type cpu is set isa to RVXLEN simply, more isa info will obtain from KVM in kvm_arch_init_vcpu() Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/cpu.c | 9 + target/riscv/cpu.h | 1 + 2 files changed, 10 insertions(+) diff --git a/target/riscv/cpu.c b

[PATCH RFC v5 12/12] target/riscv: Support virtual time context synchronization

Add virtual time context description to vmstate_riscv_cpu. After cpu being loaded, virtual time context is updated to KVM. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/machine.c | 14 ++ 1 file changed, 14 insertions(+) diff --git a/target/riscv/machine.c

[PATCH RFC v5 10/12] target/riscv: Add kvm_riscv_get/put_regs_timer

Add kvm_riscv_get/put_regs_timer to synchronize virtual time context from KVM. To set register of RISCV_TIMER_REG(state) will occur a error from KVM on kvm_timer_state == 0. It's better to adapt in KVM, but it doesn't matter that adaping in QEMU. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng

[PATCH RFC v5 00/12] Add riscv kvm accel support

Changes since RFC v2 - Fix checkpatch error at target/riscv/sbi_ecall_interface.h. - Add riscv migration support. Changes since RFC v1 - Add separate SBI ecall interface header. - Add riscv32 kvm accel support. Yifei Jiang (12): linux-header: Update linux/kvm.h target/riscv: Add target/

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