[Qemu-devel] [PATCH] target-ppc: SPR_BOOKE_ESR not set on FP exceptions

2017-06-21 Thread Aaron Larson
Properly set the book E exception syndrome register when a floating point exception occurs. Currently on a book E processor, the POWERPC_EXCP_FP exception handler fails to set "env->spr[SPR_BOOKE_ESR] = ESR_FP;" as required by the book E specification. Signed-off-by: Aaron

[Qemu-devel] [PATCH v3] target-ppc: Enable open-pic timers to count and generate interrupts

2017-06-05 Thread Aaron Larson
h comments. - Simplify clock frequency logic and commentary. - Remove camelCase variables. - Timer objects now created at init rather than lazily. Signed-off-by: Aaron Larson <alar...@ddci.com> --- hw/intc/openpic.c | 117 +++--- 1 file changed

[Qemu-devel] [PATCH] target-ppc: Fix openpic timer read register offset

2017-06-02 Thread Aaron Larson
es between the functions. Signed-off-by: Aaron Larson <alar...@ddci.com> --- hw/intc/openpic.c | 22 ++ 1 file changed, 10 insertions(+), 12 deletions(-) diff --git a/hw/intc/openpic.c b/hw/intc/openpic.c index 4349e45..f966d06 100644 --- a/hw/intc/openpic.c +++ b/h

[Qemu-devel] [PATCH v2] target-ppc: Enable open-pic timers to count and generate interrupts

2017-05-02 Thread Aaron Larson
Previous QEMU open-pic implemented the 4 open-pic timers including all timer registers, but the timers did not "count" or generate any interrupts. The patch makes the timers both count and generate interrupts. The timer clock frequency is fixed at 100MHZ. Signed-off-by: Aaron La

[Qemu-devel] Subject: [PATCH] target-ppc: Add global timer group A to open-pic.

2017-04-21 Thread Aaron Larson
Add global timer group A to open-pic. This patch is still somewhat dubious because I'm not sure how to determine what QEMU wants for the timer frequency. Suggestions solicited. Signed-off-by: Aaron Larson <alar...@ddci.com> --- hw/intc/openpic.c

[Qemu-devel] Subject: [PATCH] target-ppc: Add global timer group A to open-pic.

2017-04-21 Thread Aaron Larson
Add global timer group A to open-pic. This patch is still somewhat dubious because I'm not sure how to determine what QEMU wants for the timer frequency. Suggestions solicited. Signed-off-by: Aaron Larson <alar...@ddci.com> --- hw/intc/openpic.c

[Qemu-devel] [Bug 1587535] Re: Incorrect MAS1_TSIZE_SHIFT in ppce500_spin.c causes incorrectly sized TLB.

2016-06-30 Thread Aaron Larson
Patch accepted. Commit title is: Eliminate redundant and incorrect function booke206_page_size_to_tlb ** Changed in: qemu Status: New => Fix Committed -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU.

[Qemu-devel] [PATCH v2] target-ppc: Eliminate redundant and incorrect function booke206_page_size_to_tlb

2016-06-28 Thread Aaron Larson
W> adjusting it got missed. Commit 2bd9543cd3 did update the SW> equivalent code in ppce500_mpc8544ds.c, which now resides in SW> hw/ppc/e500.c and has been changed to not assume a power-of-2 SW> size. The ppce500_spin version should be eliminated. Signed-off-by: Aaron Larson

[Qemu-devel] [PATCH] target-ppc: gen_pause for instructions: yield, mdoio, mdoom, miso

2016-06-24 Thread Aaron Larson
ge program priority, providing a slight "future proofing". Signed-off-by: Aaron Larson <alar...@ddci.com> --- target-ppc/translate.c | 15 --- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 2f1c591..c4559

[Qemu-devel] [PATCH] target-ppc: Eliminate redundant and incorrect function booke206_page_size_to_tlb

2016-06-24 Thread Aaron Larson
Eliminate redundant and incorrect booke206_page_size_to_tlb function from ppce500_spin.c in preference to previously existing but newly exported definition from e500.c Signed-off-by: Aaron Larson <alar...@ddci.com> --- hw/ppc/e500.c | 2 +- hw/ppc/e500.h | 2 ++

[Qemu-devel] [PATCH] target-ppc: ppce500_spin.c uses SPR_PIR, should use SPR_BOOKE_PIR

2016-06-23 Thread Aaron Larson
ppce500_spin.c uses SPR_PIR to initialize the spin table, however on Book E processors the correct SPR is SPR_BOOKE_PIR. Signed-off-by: Aaron Larson <alar...@ddci.com> --- hw/ppc/ppce500_spin.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ppc/ppce500_spin.c b/

[Qemu-devel] [PATCH] target-ppc: Correct ppc3500_spin initial TLB size

2016-06-17 Thread Aaron Larson
. Simply changing MAS1_TSIZE_SHIFT from 7 to 8 is not appropriate since the macro is used elsewhere. Signed-off-by: Aaron Larson <alar...@ddci.com> --- hw/ppc/ppce500_spin.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/ppc/ppce500_spin.c b/hw/ppc/ppce500_spin.c

[Qemu-devel] [Bug 1587535] [NEW] Incorrect MAS1_TSIZE_SHIFT in ppce500_spin.c causes incorrectly sized TLB.

2016-05-31 Thread Aaron Larson
Public bug reported: When e500 PPC is booted multi-core, the non-boot cores are started via the spin table. ppce500_spin.c:spin_kick() calls mmubooke_create_initial_mapping() to allocate a 64MB TLB entry, but the created TLB entry is only 256KB. The root cause is that the function computing the