On Thu, Oct 27, 2022 at 11:58:54AM +0100, Jonathan Cameron wrote:
> On Wed, 26 Oct 2022 16:47:18 -0400
> Gregory Price wrote:
>
> > On Wed, Oct 26, 2022 at 08:13:24PM +, Adam Manzanares wrote:
> > > On Tue, Oct 25, 2022 at 08:47:33PM -0400, Gregory Price wr
On Tue, Oct 25, 2022 at 08:47:33PM -0400, Gregory Price wrote:
> Submitted as an extention to the multi-feature branch maintained
> by Jonathan Cameron at:
>
On Fri, Apr 01, 2022 at 02:30:34PM +0100, Jonathan Cameron wrote:
> On Thu, 31 Mar 2022 22:13:20 +
> Adam Manzanares wrote:
>
> > On Wed, Mar 30, 2022 at 06:48:48PM +0100, Jonathan Cameron wrote:
> > > On Tue, 29 Mar 2022 18:13:59 +0000
> > > Adam Manzanare
On Wed, Mar 30, 2022 at 06:48:48PM +0100, Jonathan Cameron wrote:
> On Tue, 29 Mar 2022 18:13:59 +
> Adam Manzanares wrote:
>
> > On Fri, Mar 18, 2022 at 03:05:53PM +, Jonathan Cameron wrote:
> > > From: Ben Widawsky
> > >
> > > A CXL devic
On Wed, Mar 30, 2022 at 01:15:58PM +0100, Jonathan Cameron wrote:
> On Tue, 29 Mar 2022 12:53:51 -0700
> Davidlohr Bueso wrote:
>
> > On Tue, 29 Mar 2022, Adam Manzanares wrote:
> > >> +typedef struct cxl_device_state {
> > >> +MemoryRegion device_
FIELD(CXL_DEV_MAILBOX_STS, BG_OP, 0, 1)
> +FIELD(CXL_DEV_MAILBOX_STS, ERRNO, 32, 16)
> +FIELD(CXL_DEV_MAILBOX_STS, VENDOR_ERRNO, 48, 16)
> +
8.2.8.4.7
> +REG64(CXL_DEV_BG_CMD_STS, 0x18)
> +FIELD(CXL_DEV_BG_CMD_STS, BG, 0, 16)
Should we call this OP since it is implied that we are BG given the register?
> +FIELD(CXL_DEV_BG_CMD_STS, DONE, 16, 7)
NUM_DONE? since this is a percentage.
> +FIELD(CXL_DEV_BG_CMD_STS, ERRNO, 32, 16)
Isn't this a RET_CODE since it is only valid if previous field is 100%
> +FIELD(CXL_DEV_BG_CMD_STS, VENDOR_ERRNO, 48, 16)
VENDOR_RET_CODE since the same rule for the previous field applies here.
> +
> +REG32(CXL_DEV_CMD_PAYLOAD, 0x20)
> +
> +#endif
> --
> 2.32.0
>
>
+cc Dave, Klaus, Tong
Other than the minor issues raised.
Looks good.
Reviewed by: Adam Manzanares
10);
> +
> +/*
> + * CXL 2.0 devices must implement certain DVSEC IDs, and can [optionally]
> + * implement others.
> + *
> + * CXL 2.0 Device: 0, [2], 5, 8
> + * CXL 2.0 RP: 3, 4, 7, 8
> + * CXL 2.0 Upstream Port: [2], 7, 8
> + * CXL 2.0 Downstream Port: 3, 4, 7, 8
> + */
> +
> +/* CXL 2.0 - 8.1.5 (ID 0003) */
> +struct cxl_dvsec_port_extensions {
> +struct dvsec_header hdr;
> +uint16_t status;
> +uint16_t control;
> +uint8_t alt_bus_base;
> +uint8_t alt_bus_limit;
> +uint16_t alt_memory_base;
> +uint16_t alt_memory_limit;
> +uint16_t alt_prefetch_base;
> +uint16_t alt_prefetch_limit;
> +uint32_t alt_prefetch_base_high;
> +uint32_t alt_prefetch_base_low;
Limit high?
> +uint32_t rcrb_base;
> +uint32_t rcrb_base_high;
> +};
> +QEMU_BUILD_BUG_ON(sizeof(struct cxl_dvsec_port_extensions) != 0x28);
> +
> +#define PORT_CONTROL_OFFSET 0xc
> +#define PORT_CONTROL_UNMASK_SBR 1
> +#define PORT_CONTROL_ALT_MEMID_EN4
> +
> +/* CXL 2.0 - 8.1.6 GPF DVSEC (ID 0004) */
> +struct cxl_dvsec_port_gpf {
> +struct dvsec_header hdr;
> +uint16_t rsvd;
> +uint16_t phase1_ctrl;
> +uint16_t phase2_ctrl;
> +};
> +QEMU_BUILD_BUG_ON(sizeof(struct cxl_dvsec_port_gpf) != 0x10);
> +
> +/* CXL 2.0 - 8.1.8/8.2.1.3 Flexbus DVSEC (ID 0007) */
> +struct cxl_dvsec_port_flexbus {
> +struct dvsec_header hdr;
> +uint16_t cap;
> +uint16_t ctrl;
> +uint16_t status;
> +uint32_t rcvd_mod_ts_data_phase1;
> +};
> +QEMU_BUILD_BUG_ON(sizeof(struct cxl_dvsec_port_flexbus) != 0x14);
> +
> +/* CXL 2.0 - 8.1.9 Register Locator DVSEC (ID 0008) */
> +struct cxl_dvsec_register_locator {
> +struct dvsec_header hdr;
> +uint16_t rsvd;
> +uint32_t reg0_base_lo;
> +uint32_t reg0_base_hi;
> +uint32_t reg1_base_lo;
> +uint32_t reg1_base_hi;
> +uint32_t reg2_base_lo;
> +uint32_t reg2_base_hi;
> +};
> +QEMU_BUILD_BUG_ON(sizeof(struct cxl_dvsec_register_locator) != 0x24);
> +
> +/* BAR Equivalence Indicator */
> +#define BEI_BAR_10H 0
> +#define BEI_BAR_14H 1
> +#define BEI_BAR_18H 2
> +#define BEI_BAR_1cH 3
> +#define BEI_BAR_20H 4
> +#define BEI_BAR_24H 5
> +
> +/* Register Block Identifier */
> +#define RBI_EMPTY 0
> +#define RBI_COMPONENT_REG (1 << 8)
> +#define RBI_BAR_VIRT_ACL (2 << 8)
> +#define RBI_CXL_DEVICE_REG (3 << 8)
> +
> +#endif
> --
> 2.32.0
>
>
+cc (Klaus, Dave, Tong)
Other than the minor cleanups/nits.
Looks good.
Reviewed by: Adam Manzanares
PCI_DEVICE, TYPE_PCI_DEVICE)
>
> +/*
> + * Implemented by devices that can be plugged on CXL buses. In the spec,
> this is
> + * actually a "CXL Component, but we name it device to match the PCI naming.
> + */
> +#define INTERFACE_CXL_DEVICE "cxl-device"
> +
> /* Implemented by devices that can be plugged on PCI Express buses */
> #define INTERFACE_PCIE_DEVICE "pci-express-device"
>
> --
> 2.32.0
>
>
Looks good.
Reviewed by: Adam Manzanares
