On Mon, 29 Jun 2020 at 09:15, Andrew Jones wrote:
>
> On Sun, Jun 28, 2020 at 04:04:58PM +0100, Beata Michalska wrote:
> > On ARMv7 & ARMv8 some load/store instructions might trigger a data abort
> > exception with no valid ISS info to be decoded. The lack of decode info
ling those by requesting KVM to inject external
dabt into the quest.
Signed-off-by: Beata Michalska
Reviewed-by: Andrew Jones
---
target/arm/kvm.c | 52
1 file changed, 52 insertions(+)
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index eef
instruction.
Add support for handling that case.
[
Fixed-by: 018f22f95e8a
('KVM: arm: Fix DFSR setting for non-LPAE aarch32 guests')
Fixed-by: 21aecdbd7f3a
('KVM: arm: Make inject_abt32() inject an external abort instead')
]
Signed-off-by: Beata Michalska
Ac
easonable and what's effective:
aborting qemu when running on buggy host kernel
v2:
- Improving/re-phrasing messaging
- Dropping messing around with forced sync (@see [PATCH v2 1/2])
and PC alignment
Beata Michalska (2):
target/arm: kvm: Handle DABT with no valid ISS
target/ar
ling those by requesting KVM to inject external
dabt into the quest.
Signed-off-by: Beata Michalska
---
target/arm/kvm.c | 57 +++-
1 file changed, 56 insertions(+), 1 deletion(-)
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index eef3bbd..2dd
instruction.
Add support for handling that case.
[
Fixed-by: 018f22f95e8a
('KVM: arm: Fix DFSR setting for non-LPAE aarch32 guests')
Fixed-by: 21aecdbd7f3a
('KVM: arm: Make inject_abt32() inject an external abort instead')
]
Signed-off-by: Beata Michalska
-
27;s effective:
aborting qemu when running on buggy host kernel
v2:
- Improving/re-phrasing messaging
- Dropping messing around with forced sync (@see [PATCH v2 1/2])
and PC alignment
Beata Michalska (2):
target/arm: kvm: Handle DABT with no valid ISS
target/arm: kvm: Handle misconfigured
Hi Peter,
Hi Andrew
Thanks for quick review.
I have pushed the updated version.
BR
Beata
On Fri, 26 Jun 2020 at 13:59, Peter Maydell wrote:
>
> On Fri, 26 Jun 2020 at 10:01, Andrew Jones wrote:
> > nit: How about using '= {0}' when declaring the variable, rather than this
> > memset?
>
> We pr
instruction.
Add support for handling that case.
[
Fixed-by: 018f22f95e8a
('KVM: arm: Fix DFSR setting for non-LPAE aarch32 guests')
Fixed-by: 21aecdbd7f3a
('KVM: arm: Make inject_abt32() inject an external abort instead')
]
Signed-off-by: Beata Michalska
-
ling those by requesting KVM to inject external
dabt into the quest.
Signed-off-by: Beata Michalska
---
target/arm/kvm.c | 58 +++-
1 file changed, 57 insertions(+), 1 deletion(-)
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index eef3bbd..3ea
ng/re-phrasing messaging
- Dropping messing around with forced sync (@see [PATCH v2 1/2])
and PC alignment
Beata Michalska (2):
target/arm: kvm: Handle DABT with no valid ISS
target/arm: kvm: Handle misconfigured dabt injection
target/arm/cpu.h | 2 ++
target/arm/
instruction.
Add support for handling that case.
[
Fixed-by: 018f22f95e8a
('KVM: arm: Fix DFSR setting for non-LPAE aarch32 guests')
Fixed-by: 21aecdbd7f3a
('KVM: arm: Make inject_abt32() inject an external abort instead')
]
Signed-off-by: Beata Michalska
-
ling those by requesting KVM to inject external
dabt into the quest.
Signed-off-by: Beata Michalska
---
target/arm/kvm.c | 59 +++-
1 file changed, 58 insertions(+), 1 deletion(-)
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index eef3bbd..265
nels):
little bit of trade-off between what's reasonable and what's effective:
aborting qemu when running on buggy host kernel
v2:
- Improving/re-phrasing messaging
- Dropping messing around with forced sync (@see [PATCH v2 1/2])
and PC alignment
Beata Michalska (2):
target/ar
Hi Andrew,
Thanks for the feedback.
On Tue, 16 Jun 2020 at 09:33, Andrew Jones wrote:
>
> Hi Beata,
>
> I see Peter just picked this up, so I'm a bit late getting to it. I do
> have a couple comments below though.
>
> Thanks,
> drew
>
> On Fri, May 29, 2020 a
instruction.
Add support for handling that case.
[
Fixed-by: 018f22f95e8a
('KVM: arm: Fix DFSR setting for non-LPAE aarch32 guests')
Fixed-by: 21aecdbd7f3a
('KVM: arm: Make inject_abt32() inject an external abort instead')
]
Signed-off-by: Beata Michalska
-
ling those by requesting KVM to inject external
dabt into the quest.
Signed-off-by: Beata Michalska
---
target/arm/cpu.h | 2 ++
target/arm/kvm.c | 64 +++-
target/arm/kvm_arm.h | 11 +
3 files changed, 76 insertions(+), 1 dele
nable and what's effective:
aborting qemu when running on buggy host kernel
v2:
- Improving/re-phrasing messaging
- Dropping messing around with forced sync (@see [PATCH v2 1/2])
and PC alignment
Beata Michalska (2):
target/arm: kvm: Handle DABT with no valid ISS
target/ar
On Fri, 8 May 2020 at 07:33, Paolo Bonzini wrote:
>
> On 08/05/20 08:24, Philippe Mathieu-Daudé wrote:
> > It is not clear if dccvap_writefn() really needs
> > memory_region_writeback() or could use memory_region_msync().
>
> Indeed, I don't understand the code and why it matters that
> mr->dirty_
On Fri, 17 Apr 2020 at 14:10, Andrew Jones wrote:
>
> On Fri, Apr 17, 2020 at 11:39:25AM +0100, Peter Maydell wrote:
> > On Mon, 23 Mar 2020 at 11:32, Beata Michalska
> > wrote:
> > >
> > > On ARMv7 & ARMv8 some load/store instructions might trigger a data
On Tue, 7 Apr 2020 at 12:24, Peter Maydell wrote:
>
> On Fri, 3 Apr 2020 at 09:44, Andrew Jones wrote:
> >
> > On Mon, Mar 23, 2020 at 11:32:27AM +0000, Beata Michalska wrote:
> > > Injecting external data abort through KVM might trigger
> > > an issue o
On Fri, 3 Apr 2020 at 09:44, Andrew Jones wrote:
>
> On Mon, Mar 23, 2020 at 11:32:27AM +, Beata Michalska wrote:
> > Injecting external data abort through KVM might trigger
> > an issue on kernels that do not get updated to include the KVM fix.
> > For those and aarc
On Mon, 23 Mar 2020 at 18:44, Richard Henderson
wrote:
>
> On 3/23/20 4:32 AM, Beata Michalska wrote:
> > uint8_t ext_dabt_pending; /* Request for injecting ext DABT */
> > +uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */
>
> Is there a
Hi,
On Mon, 23 Mar 2020 at 12:44, Andrew Jones wrote:
>
> On Mon, Mar 23, 2020 at 11:32:26AM +, Beata Michalska wrote:
> > On ARMv7 & ARMv8 some load/store instructions might trigger a data abort
> > exception with no valid ISS info to be decoded. The lack of decod
ween what's reasonable and what's effective:
aborting qemu when running on buggy host kernel
v2:
- Improving/re-phrasing messaging
- Dropping messing around with forced sync (@see [PATCH v2 1/2])
and PC alignment
Beata Michalska (2):
target/arm: kvm: Handle DABT with no valid ISS
t
ling those by requesting KVM to inject external
dabt into the quest.
Signed-off-by: Beata Michalska
---
target/arm/cpu.h | 2 ++
target/arm/kvm.c | 54
target/arm/kvm_arm.h | 11 +++
3 files changed, 67 insertions(+)
diff --g
instruction.
Add support for handling that case.
[
Fixed-by: 018f22f95e8a
('KVM: arm: Fix DFSR setting for non-LPAE aarch32 guests')
Fixed-by: 21aecdbd7f3a
('KVM: arm: Make inject_abt32() inject an external abort instead')
]
Signed-off-by: Beata Michalska
-
On Thu, 12 Mar 2020 at 10:25, Andrew Jones wrote:
>
> On Thu, Mar 12, 2020 at 12:34:01AM +, Beata Michalska wrote:
> > On ARMv7 & ARMv8 some load/store instructions might trigger a data abort
> > exception with no valid ISS info to be decoded. The lack of decode info
On Thu, 12 Mar 2020 at 16:33, Peter Maydell wrote:
>
> On Thu, 12 Mar 2020 at 00:34, Beata Michalska
> wrote:
> >
> > KVM_SET_VCPU_EVENTS might actually lead to vcpu registers being modified.
> > As such this should be the last step of sync to avoid potential overwrit
ling those by requesting KVM to inject external
dabt into the quest.
Signed-off-by: Beata Michalska
---
target/arm/cpu.h | 3 ++
target/arm/kvm.c | 81
target/arm/kvm32.c | 26 +
target/arm/kvm64.c
KVM_SET_VCPU_EVENTS might actually lead to vcpu registers being modified.
As such this should be the last step of sync to avoid potential overwriting
of whatever changes KVM might have done.
Signed-off-by: Beata Michalska
---
target/arm/kvm32.c | 15 ++-
target/arm/kvm64.c | 15
bug (for small range of affected kernels):
little bit of trade-off between what's reasonable and what's effective:
aborting qemu when running on buggy host kernel
v2:
- Improving/re-phrasing messaging
- Dropping messing around with forced sync (@see [PATCH v2 1/2])
and PC ali
On Fri, 7 Feb 2020 at 08:20, Andrew Jones wrote:
>
> On Thu, Feb 06, 2020 at 09:48:05PM +, Beata Michalska wrote:
> > On Wed, 5 Feb 2020 at 16:57, Andrew Jones wrote:
> > >
> > > On Wed, Jan 29, 2020 at 08:24:41PM +, Beata Michalska wrote:
> >
On Tue, 4 Feb 2020 at 10:34, Andrew Jones wrote:
>
> On Wed, Jan 29, 2020 at 08:24:40PM +, Beata Michalska wrote:
> > KVM_SET_VCPU_EVENTS might actually lead to vcpu registers being modified.
> > As such this should be the last step of sync to avoid potential overwriti
On Wed, 5 Feb 2020 at 16:57, Andrew Jones wrote:
>
> On Wed, Jan 29, 2020 at 08:24:41PM +, Beata Michalska wrote:
> > On ARMv7 & ARMv8 some load/store instructions might trigger a data abort
> > exception with no valid ISS info to be decoded. The lack of decode info
1/2])
and PC alignment
Beata Michalska (2):
target/arm: kvm: Inject events at the last stage of sync
target/arm: kvm: Handle DABT with no valid ISS
target/arm/cpu.h | 2 ++
target/arm/kvm.c | 96
target/arm/kvm32.c
ling those by requesting KVM to inject external
dabt into the quest.
Signed-off-by: Beata Michalska
---
target/arm/cpu.h | 2 ++
target/arm/kvm.c | 96
target/arm/kvm32.c | 3 ++
target/arm/kvm64.c | 3 ++
target/arm/kvm_arm.h
KVM_SET_VCPU_EVENTS might actually lead to vcpu registers being modified.
As such this should be the last step of sync to avoid potential overwriting
of whatever changes KVM might have done.
Signed-off-by: Beata Michalska
---
target/arm/kvm32.c | 20 ++--
target/arm/kvm64.c | 20
Hi Klaus,
On Thu, 19 Dec 2019 at 13:09, Klaus Jensen wrote:
>
> For now, support the Data Block, Segment and Last Segment descriptor
> types.
>
> See NVM Express 1.3d, Section 4.4 ("Scatter Gather List (SGL)").
>
> Signed-off-by: Klaus Jensen
> Acked-by: Fam Zheng
> ---
> block/nvme.c
Hi Klaus,
On Thu, 19 Dec 2019 at 13:09, Klaus Jensen wrote:
>
> This refactors how the device issues asynchronous block backend
> requests. The NvmeRequest now holds a queue of NvmeAIOs that are
> associated with the command. This allows multiple aios to be issued for
> a command. Only when all r
Hi Klaus,
On Thu, 19 Dec 2019 at 13:09, Klaus Jensen wrote:
>
> Handling DMA errors gracefully is required for the device to pass the
> block/011 test ("disable PCI device while doing I/O") in the blktests
> suite.
>
> With this patch the device passes the test by retrying "critical"
> transfers
On Tue, 7 Jan 2020 at 14:28, Peter Maydell wrote:
>
> On Fri, 20 Dec 2019 at 20:27, Beata Michalska
> wrote:
> >
> > On ARMv7 & ARMv8 some load/store instructions might trigger a data abort
> > exception with no valid ISS info to be decoded. The lack of decode in
On Mon, 6 Jan 2020 at 17:15, Peter Maydell wrote:
>
> On Fri, 20 Dec 2019 at 20:27, Beata Michalska
> wrote:
> >
> > On ARMv7 & ARMv8 some load/store instructions might trigger a data abort
> > exception with no valid ISS info to be decoded. The lack of decode in
d in dabt with no valid ISS decoding info.
This still leaves QEMU to handle the case, but at least now, it can enable
further debugging of the encountered issue by being more verbose
in a (hopefully) useful way.
Beata Michalska (1):
target/arm: kvm: Handle DABT with no valid ISS
accel/kvm
ling those by requesting KVM to inject external
dabt into the quest.
Signed-off-by: Beata Michalska
---
accel/kvm/kvm-all.c| 15 +++
accel/stubs/kvm-stub.c | 4 ++
include/sysemu/kvm.h | 1 +
target/arm/cpu.h | 3 +-
target/arm/kvm.c
Hi Anthony,
On Thu, 19 Dec 2019 at 15:42, Anthony PERARD wrote:
>
> Hi,
>
> Commit bd108a44bc29 ("migration: ram: Switch to ram block writeback")
> breaks migration on Xen. We have:
> ramblock_ptr: Assertion `offset_in_ramblock(block, offset)' failed.
>
> I've track it down to qemu_ram_writebac
Hi Anthony,
On Thu, 19 Dec 2019 at 15:43, Anthony PERARD wrote:
>
> It is possible that a ramblock doesn't have memory that QEMU can
> access, this is the case with the Xen hypervisor.
>
> In order to avoid to trigger an assert, only call ramblock_ptr() when
> needed in qemu_ram_writeback(). This
On Sat, 7 Dec 2019 at 09:33, gengdongjiu wrote:
>
>
>
> On 2019/11/22 23:47, Beata Michalska wrote:
> > Hi,
> >
> > On Mon, 11 Nov 2019 at 01:48, Xiang Zheng wrote:
> >>
> >> From: Dongjiu Geng
> >>
> >> Add a SIGBUS signal ha
On Wed, 27 Nov 2019 at 13:03, Igor Mammedov wrote:
>
> On Wed, 27 Nov 2019 20:47:15 +0800
> Xiang Zheng wrote:
>
> > Hi Beata,
> >
> > Thanks for you review!
> >
> > On 2019/11/22 23:47, Beata Michalska wrote:
> > > Hi,
> >
Hi
On Wed, 27 Nov 2019 at 12:47, Xiang Zheng wrote:
>
> Hi Beata,
>
> Thanks for you review!
>
YAW
> On 2019/11/22 23:47, Beata Michalska wrote:
> > Hi,
> >
> > On Mon, 11 Nov 2019 at 01:48, Xiang Zheng wrote:
> >>
> >> From: Dongjiu Geng
On Mon, 25 Nov 2019 at 06:21, Klaus Birkelund wrote:
>
> On Tue, Nov 12, 2019 at 03:25:18PM +, Beata Michalska wrote:
> > Hi Klaus,
> >
> > On Tue, 15 Oct 2019 at 11:57, Klaus Jensen wrote:
> > > +static uint16_t nvme_map_sgl(NvmeCtrl *n, QEMUSGList *qsg,
On Thu, 21 Nov 2019 at 11:57, Klaus Birkelund wrote:
>
> On Tue, Nov 12, 2019 at 03:25:06PM +, Beata Michalska wrote:
> > Hi Klaus,
> >
> > On Tue, 15 Oct 2019 at 11:55, Klaus Jensen wrote:
> > > @@ -341,19 +344,18 @@ static uint16_t nvme_dma_write_prp
On Wed, 20 Nov 2019 at 09:39, Klaus Birkelund wrote:
>
> On Tue, Nov 12, 2019 at 03:23:43PM +, Beata Michalska wrote:
> > Hi Klaus,
> >
> > On Tue, 15 Oct 2019 at 11:57, Klaus Jensen wrote:
> > >
> > > Instead of handling both QSGs and IOVs
On Tue, 19 Nov 2019 at 19:51, Klaus Birkelund wrote:
>
> On Tue, Nov 12, 2019 at 03:04:59PM +, Beata Michalska wrote:
> > Hi Klaus,
> >
> > On Tue, 15 Oct 2019 at 11:49, Klaus Jensen wrote:
> > > @@ -1188,6 +1326,9 @@ stati
On Mon, 18 Nov 2019 at 09:48, Klaus Birkelund wrote:
>
> On Tue, Nov 12, 2019 at 03:05:06PM +, Beata Michalska wrote:
> > Hi Klaus,
> >
> > On Tue, 15 Oct 2019 at 11:52, Klaus Jensen wrote:
> > >
> > > +static uint16_t nvme_iden
Hi,
On Mon, 18 Nov 2019 at 12:50, gengdongjiu wrote:
>
> Hi,Igor,
>Thanks for you review and time.
>
> >
> >> +/*
> >> + * Type:
> >> + * Generic Hardware Error Source version 2(GHESv2 - Type 10)
> >> + */
> >> +build_append_int_noprefix(table_data,
> >> ACPI_GHES_SOURCE_
Hi Xiang,
On Mon, 11 Nov 2019 at 01:48, Xiang Zheng wrote:
>
> From: Dongjiu Geng
>
> This patch implements APEI GHES Table generation via fw_cfg blobs. Now
> it only supports ARMv8 SEA, a type of GHESv2 error source. Afterwards,
> we can extend the supported types if needed. For the CPER sectio
Hi,
On Mon, 11 Nov 2019 at 01:48, Xiang Zheng wrote:
>
> From: Dongjiu Geng
>
> Add a SIGBUS signal handler. In this handler, it checks the SIGBUS type,
> translates the host VA delivered by host to guest PA, then fills this PA
> to guest APEI GHES memory, then notifies guest according to the SI
Hi,
On Fri, 15 Nov 2019 at 16:54, Igor Mammedov wrote:
>
> On Mon, 11 Nov 2019 09:40:47 +0800
> Xiang Zheng wrote:
>
> > From: Dongjiu Geng
> >
> > Add a SIGBUS signal handler. In this handler, it checks the SIGBUS type,
> > translates the host VA delivered by host to guest PA, then fills this
both to be actually the same so there is no
distinction between the two. If none is available (there is no backing store
for given memory) both will result in Data Cache Clean up to the point of
coherency. Otherwise sync for the specified range shall be performed.
Signed-off-by: Beata Michalska
Switch to ram block writeback for pmem migration.
Signed-off-by: Beata Michalska
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Acked-by: Dr. David Alan Gilbert
---
migration/ram.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/migration/ram.c b/migration
Add an option to trigger memory writeback to sync given memory region
with the corresponding backing store, case one is available.
This extends the support for persistent memory, allowing syncing on-demand.
Signed-off-by: Beata Michalska
---
exec.c | 36
Add probe_read alongside the write probing equivalent.
Signed-off-by: Beata Michalska
Reviewed-by: Alex Bennée
---
include/exec/exec-all.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index d85e610..350c4b4 100644
--- a/include
IG_POSIX switch + additional comments
- Fixed length alignment
- Dropped treating the DC CVAP/CVADP as special case
and moved those to conditional registration
- Dropped needless locking for grabbing mem region
Beata Michalska (4):
tcg: cputlb: Add probe_read
Memory: Enable w
Hi Klaus,
On Wed, 13 Nov 2019 at 06:12, Klaus Birkelund wrote:
>
> On Tue, Nov 12, 2019 at 03:04:38PM +, Beata Michalska wrote:
> > Hi Klaus
> >
>
> Hi Beata,
>
> Thank you very much for your thorough reviews! I'll start going through
> them one by one :
Hi Klaus,
On Tue, 15 Oct 2019 at 11:57, Klaus Jensen wrote:
>
> For now, support the Data Block, Segment and Last Segment descriptor
> types.
>
> See NVM Express 1.3d, Section 4.4 ("Scatter Gather List (SGL)").
>
> Signed-off-by: Klaus Jensen
> ---
> block/nvme.c | 18 +-
> hw/block/n
Hi Klaus,
On Tue, 15 Oct 2019 at 11:55, Klaus Jensen wrote:
>
> This refactors how the device issues asynchronous block backend
> requests. The NvmeRequest now holds a queue of NvmeAIOs that are
> associated with the command. This allows multiple aios to be issued for
> a command. Only when all r
Hi Klaus,
On Tue, 15 Oct 2019 at 11:50, Klaus Jensen wrote:
>
> Signed-off-by: Klaus Jensen
> ---
> hw/block/nvme-ns.c | 2 +-
> hw/block/nvme-ns.h | 4 +++-
> hw/block/nvme.c| 1 +
> 3 files changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/hw/block/nvme-ns.c b/hw/block/nvme-ns.c
>
Hi Klaus,
On Tue, 15 Oct 2019 at 11:57, Klaus Jensen wrote:
>
> Instead of handling both QSGs and IOVs in multiple places, simply use
> QSGs everywhere by assuming that the request does not involve the
> controller memory buffer (CMB). If the request is found to involve the
> CMB, convert the QSG
Hi Klaus,
On Tue, 15 Oct 2019 at 11:49, Klaus Jensen wrote:
>
> Required for compliance with NVMe revision 1.2.1. See NVM Express 1.2.1,
> Section 5.2 ("Asynchronous Event Request command").
>
> Mostly imported from Keith's qemu-nvme tree. Modified to not enqueue
> events if something of the same
Hi Klaus,
On Tue, 15 Oct 2019 at 11:52, Klaus Jensen wrote:
>
> Add the new Namespace Identification Descriptor List (CNS 03h) and track
> creation of queues to enable the controller to return Command Sequence
> Error if Set Features is called for Number of Queues after any queues
> have been cre
Hi Klaus
On Tue, 15 Oct 2019 at 11:42, Klaus Jensen wrote:
>
> Required for compliance with NVMe revision 1.2.1 or later. See NVM
> Express 1.2.1, Section 5.11 ("Identify command"), Figure 90 and Section
> 7.9 ("NVMe Qualified Names").
>
> This also bumps the supported version to 1.2.1.
>
> Signe
Hi Klaus
On Tue, 15 Oct 2019 at 11:41, Klaus Jensen wrote:
>
> Required for compliance with NVMe revision 1.2.1. See NVM Express 1.2.1,
> Section 5.1 ("Abort command").
>
> The Abort command is a best effort command; for now, the device always
> fails to abort the given command.
>
> Signed-off-by
Hi Klaus,
On Tue, 15 Oct 2019 at 11:45, Klaus Jensen wrote:
>
> Add support for the Get Log Page command and basic implementations
> of the mandatory Error Information, SMART/Health Information and
> Firmware Slot Information log pages.
>
> In violation of the specification, the SMART/Health Inf
On Wed, 6 Nov 2019 at 12:20, Richard Henderson
wrote:
>
> On 11/6/19 12:40 AM, Beata Michalska wrote:
> > +void qemu_ram_writeback(RAMBlock *block, ram_addr_t start, ram_addr_t
> > length)
> > +{
> > +void *addr = ramblock_ptr(block, start);
> > +
> &g
both to be actually the same so there is no
distinction between the two. If none is available (there is no backing store
for given memory) both will result in Data Cache Clean up to the point of
coherency. Otherwise sync for the specified range shall be performed.
Signed-off-by: Beata Michalska
Switch to ram block writeback for pmem migration.
Signed-off-by: Beata Michalska
Reviewed-by: Richard Henderson
Acked-by: Dr. David Alan Gilbert
---
migration/ram.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/migration/ram.c b/migration/ram.c
index 5078f94..38070f1
Add an option to trigger memory writeback to sync given memory region
with the corresponding backing store, case one is available.
This extends the support for persistent memory, allowing syncing on-demand.
Signed-off-by: Beata Michalska
---
exec.c | 43
Add probe_read alongside the write probing equivalent.
Signed-off-by: Beata Michalska
Reviewed-by: Alex Bennée
---
include/exec/exec-all.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index d85e610..350c4b4 100644
--- a/include
CVADP as special case
and moved those to conditional registration
- Dropped needless locking for grabbing mem region
Beata Michalska (4):
tcg: cputlb: Add probe_read
Memory: Enable writeback for given memory region
migration: ram: Switch to ram block writeback
target/arm: Add sup
ed on or off, getting all vector lengths the host CPU supports
> when on. We'll add the other SVE CPU properties in later patches.
>
> Signed-off-by: Andrew Jones
> Reviewed-by: Richard Henderson
> Reviewed-by: Eric Auger
Reviewed-by: Beata Michalska
Thanks,
BR
ry time.
> For 'vfp' and 'neon' this will require some refactoring to share a
> validation function between the QMP query and the CPU realize
> functions.
>
> Signed-off-by: Andrew Jones
> Reviewed-by: Richard Henderson
> Reviewed-by: Eric Auger
> ---
Revi
Hi Andrew,
On Tue, 22 Oct 2019 at 14:43, Andrew Jones wrote:
>
> On Mon, Oct 21, 2019 at 04:07:14PM +0100, Beata Michalska wrote:
> > Indeed, the patch got bit messed-up. Apologies for that as well.
> > I have been testing manually but I did try the test you have provided
&g
ing in a nice
> LOC reduction.
>
> Signed-off-by: Andrew Jones
> Reviewed-by: Richard Henderson
> Reviewed-by: Eric Auger
Reviewed-by: Beata Michalska
Thanks.
BR
Beata
> ---
> docs/arm-cpu-features.rst | 168 +++--
> include/qe
s
> Reviewed-by: Richard Henderson
> Reviewed-by: Eric Auger
Reviewed-by: Beata Michalska
Thanks
BR
Beata
> ---
> target/arm/kvm.c | 20 +++-
> target/arm/kvm32.c | 6 +-
> target/arm/kvm64.c | 6 +-
> 3 files changed, 25 insertions(+), 7 del
Add the 'sve=on|off'
> property to give it that flexibility. We also rename
> cpu_max_get/set_sve_vq to cpu_max_get/set_sve_max_vq in order for them
> to follow the typical *_get/set_ pattern.
>
> Signed-off-by: Andrew Jones
> Reviewed-by: Richard Henderson
> R
On Wed, 16 Oct 2019 at 17:16, Andrew Jones wrote:
>
> On Wed, Oct 16, 2019 at 04:16:57PM +0100, Beata Michalska wrote:
> > On Wed, 16 Oct 2019 at 14:50, Andrew Jones wrote:
> > >
> > > On Wed, Oct 16, 2019 at 02:24:50PM +0100, Beata Michalska wrote:
> > >
On Wed, 16 Oct 2019 at 14:50, Andrew Jones wrote:
>
> On Wed, Oct 16, 2019 at 02:24:50PM +0100, Beata Michalska wrote:
> > On Tue, 15 Oct 2019 at 12:56, Beata Michalska
> > wrote:
> > >
> > > On Tue, 15 Oct 2019 at 11:56, Andrew Jones wrote:
> > >
On Tue, 15 Oct 2019 at 12:56, Beata Michalska
wrote:
>
> On Tue, 15 Oct 2019 at 11:56, Andrew Jones wrote:
> >
> > On Tue, Oct 15, 2019 at 10:59:16AM +0100, Beata Michalska wrote:
> > > On Tue, 1 Oct 2019 at 14:04, Andrew Jones wrote:
> > &g
On Tue, 15 Oct 2019 at 11:56, Andrew Jones wrote:
>
> On Tue, Oct 15, 2019 at 10:59:16AM +0100, Beata Michalska wrote:
> > On Tue, 1 Oct 2019 at 14:04, Andrew Jones wrote:
> > > +
> > > +obj = object_new(object_class_get_name(oc));
> > > +
> >
On Tue, 1 Oct 2019 at 14:04, Andrew Jones wrote:
>
> Add support for the query-cpu-model-expansion QMP command to Arm. We
> do this selectively, only exposing CPU properties which represent
> optional CPU features which the user may want to enable/disable.
> Additionally we restrict the list of qu
On Tue, 1 Oct 2019 at 14:04, Andrew Jones wrote:
>
> Introduce cpu properties to give fine control over SVE vector lengths.
> We introduce a property for each valid length up to the current
> maximum supported, which is 2048-bits. The properties are named, e.g.
> sve128, sve256, sve384, sve512, ..
On Tue, 24 Sep 2019 at 02:16, Alex Bennée wrote:
>
>
> Beata Michalska writes:
>
> > ARMv8.2 introduced support for Data Cache Clean instructions
> > to PoP (point-of-persistence) - DC CVAP and PoDP (point-of-deep-persistence)
> > - DV CVADP. Both specify concep
On Tue, 24 Sep 2019 at 17:30, Richard Henderson
wrote:
>
> On 9/10/19 2:56 AM, Beata Michalska wrote:
> > +void qemu_ram_writeback(RAMBlock *block, ram_addr_t start, ram_addr_t
> > length);
> > +
> > +/* Clear whole block of mem */
> >
On Tue, 24 Sep 2019 at 17:28, Richard Henderson
wrote:
>
> On 9/10/19 2:56 AM, Beata Michalska wrote:
> > +int main(void) {
> > +#if defined(_POSIX_MAPPED_FILES) && _POSIX_MAPPED_FILES > 0 \
> > +&& defined(_POSIX_SYNCHRONIZED_IO) && _POSIX_SY
On Tue, 24 Sep 2019 at 01:00, Alex Bennée wrote:
>
>
> Beata Michalska writes:
>
> > Add an option to trigger memory writeback to sync given memory region
> > with the corresponding backing store, case one is available.
> > This extends the support for persiste
On Tue, 24 Sep 2019 at 18:22, Richard Henderson
wrote:
>
> On 9/10/19 2:56 AM, Beata Michalska wrote:
> > @@ -2229,7 +2229,8 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t
> > cpregid)
> > #define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300)
>
On Tue, 24 Sep 2019 at 00:54, Alex Bennée wrote:
>
>
> Beata Michalska writes:
>
> > ARMv8.2 introduced support for Data Cache Clean instructions
> > to PoP (point-of-persistence) - DC CVAP and PoDP (point-of-deep-persistence)
> > - DV CVADP. Both specify concep
On Wed, 11 Sep 2019 at 11:36, Dr. David Alan Gilbert
wrote:
>
> * Beata Michalska (beata.michal...@linaro.org) wrote:
> > On Tue, 10 Sep 2019 at 14:16, Dr. David Alan Gilbert
> > wrote:
> > >
> > > * Beata Michalska (beata.michal...@linaro.org) wrote:
>
On Tue, 10 Sep 2019 at 14:16, Dr. David Alan Gilbert
wrote:
>
> * Beata Michalska (beata.michal...@linaro.org) wrote:
> > On Tue, 10 Sep 2019 at 12:26, Dr. David Alan Gilbert
> > wrote:
> > >
> > > * Beata Michalska (beata.michal...@linaro.org) wrote:
>
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