Ping...
On 1/22/2024 4:55 PM, Binbin Wu wrote:
Gentle ping...
Please help to review and consider applying the patch series. (The KVM
part has been merged).
On 1/12/2024 2:00 PM, Binbin Wu wrote:
Linear-address masking (LAM) [1], modifies the checking that is
applied to
*64-bit* linear
Ping...
Hi Paolo,
do you have time to have a look at this patchset?
On 1/22/2024 4:55 PM, Binbin Wu wrote:
Gentle ping...
Please help to review and consider applying the patch series. (The KVM
part has been merged).
On 1/12/2024 2:00 PM, Binbin Wu wrote:
Linear-address masking (LAM) [1
Gentle ping...
Please help to review and consider applying the patch series. (The KVM
part has been merged).
On 1/12/2024 2:00 PM, Binbin Wu wrote:
Linear-address masking (LAM) [1], modifies the checking that is applied to
*64-bit* linear addresses, allowing software to use of the untranslated
is not allowed to be set in TCG.
- gdbstub
x86_cpu_gdb_write_register() will call cpu_x86_update_cr4() to update cr4.
Mask out LAM bit on CR4 if vcpu doesn't support LAM.
- x86_cpu_reset_hold() doesn't need special handling.
Signed-off-by: Binbin Wu
Tested-by: Xuelian Guo
---
target/i386/cpu.h| 7
Binbin Wu (1):
target/i386: add control bits support for LAM
Robert Hoo (1):
target/i386: add support for LAM in CPUID enumeration
target/i386/cpu.c| 2 +-
target/i386/cpu.h| 9 -
target/i386/helper.c | 4
3 files changed, 13 insertions(+), 2 deletions(-)
base-commit
CPIUD bit
will not be added to TCG_7_1_EAX_FEATURES.
More info can be found in Intel ISE Chapter "LINEAR ADDRESS MASKING(LAM)"
https://cdrdv2.intel.com/v1/dl/getContent/671368
Signed-off-by: Robert Hoo
Co-developed-by: Binbin Wu
Signed-off-by: Binbin Wu
Tested-by: Xuelian Guo
Reviewed-b
On 12/28/2023 4:51 PM, Xiaoyao Li wrote:
On 7/21/2023 4:08 PM, Binbin Wu wrote:
LAM uses CR3[61] and CR3[62] to configure/enable LAM on user pointers.
LAM uses CR4[28] to configure/enable LAM on supervisor pointers.
For CR3 LAM bits, no additional handling needed:
- TCG
LAM
CPIUD bit will not
be added to TCG_7_1_EAX_FEATURES.
More info can be found in Intel ISE Chapter "LINEAR ADDRESS MASKING (LAM)"
https://cdrdv2.intel.com/v1/dl/getContent/671368
Signed-off-by: Robert Hoo
Co-developed-by: Binbin Wu
Signed-off-by: Binbin Wu
---
target/i386/cpu.c | 2 +-
t
.
- Add handling of LAM control bits. (Xiaoyao)
v2:
- https://lists.gnu.org/archive/html/qemu-devel/2023-05/msg07842.html
Binbin Wu (1):
target/i386: add control bits support for LAM
Robert Hoo (1):
target/i386: add support for LAM in CPUID enumeration
target/i386/cpu.c | 2 +-
target/i386/cpu.h
is not
allowed to be set in TCG.
- gdbstub
x86_cpu_gdb_write_register() will call cpu_x86_update_cr4() to update cr4.
Allow gdb
to set the LAM bit to CR4, if vcpu doesn't support LAM, KVM_SET_SREGS will
fail.
- x86_cpu_reset_hold() doesn't need special handling.
Signed-off-by: Binbin Wu
On 5/31/2023 11:45 AM, Xiaoyao Li wrote:
On 5/31/2023 9:32 AM, Binbin Wu wrote:
From: Robert Hoo
Linear Address Masking (LAM) is a new Intel CPU feature, which allows
software
to use of the untranslated address bits for metadata.
The bit definition:
CPUID.(EAX=7,ECX=1):EAX[26]
Add CPUID
DRESS MASKING (LAM)"
https://cdrdv2.intel.com/v1/dl/getContent/671368
Signed-off-by: Robert Hoo
Co-developed-by: Binbin Wu
Signed-off-by: Binbin Wu
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/
Linear-address masking (LAM) [1], modifies the checking that is applied to
*64-bit* linear addresses, allowing software to use of the untranslated address
bits for metadata and masks the metadata bits before using them as linear
addresses to access memory.
When the feature is virtualized and
On 12/2/2022 2:13 PM, Chao Peng wrote:
In confidential computing usages, whether a page is private or shared is
necessary information for KVM to perform operations like page fault
handling, page zapping etc. There are other potential use cases for
per-page memory attributes, e.g. to make
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