RE: [PATCH v6] Hexagon: add PC alignment check and exception
> -Original Message-
> From: Matheus Bernardino (QUIC)
> Sent: Friday, May 3, 2024 11:53 AM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Sid Manning ;
> a...@rev.ng; a...@rev.ng; ltaylorsimp...@gmail.com;
> richard.hender...@linaro.org; Laurent Vivier
> Subject: [PATCH v6] Hexagon: add PC alignment check and exception
>
> The Hexagon Programmer's Reference Manual says that the exception 0x1e
> should be raised upon an unaligned program counter. Let's implement that
> and also add some tests.
>
> Signed-off-by: Matheus Tavares Bernardino
> Reviewed-by: Richard Henderson
> Reviewed-by: Taylor Simpson
> ---
> Changes in v6:
> - The multi COF test defines a new section for the unaligned label to
> make it more robust.
> - Instead of a nop in the undesired test branch, we use a trap for
> SYS_EXIT
>
Reviewed-by: Brian Cain
> target/hexagon/cpu.h | 7 ++
> target/hexagon/cpu_bits.h | 4 ++
> target/hexagon/macros.h | 3 -
> linux-user/hexagon/cpu_loop.c | 4 ++
> target/hexagon/op_helper.c| 9 ++-
> tests/tcg/hexagon/unaligned_pc.c | 107 ++
> tests/tcg/hexagon/Makefile.target | 2 +
> 7 files changed, 128 insertions(+), 8 deletions(-)
> create mode 100644 tests/tcg/hexagon/unaligned_pc.c
>
> diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
> index 3eef58fe8f..764f3c38cc 100644
> --- a/target/hexagon/cpu.h
> +++ b/target/hexagon/cpu.h
> @@ -134,6 +134,10 @@ struct ArchCPU {
>
> FIELD(TB_FLAGS, IS_TIGHT_LOOP, 0, 1)
>
> +G_NORETURN void hexagon_raise_exception_err(CPUHexagonState *env,
> +uint32_t exception,
> +uintptr_t pc);
> +
> static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc,
> uint64_t *cs_base, uint32_t *flags)
> {
> @@ -144,6 +148,9 @@ static inline void
> cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc,
> hex_flags = FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1);
> }
> *flags = hex_flags;
> +if (*pc & PCALIGN_MASK) {
> +hexagon_raise_exception_err(env, HEX_EXCP_PC_NOT_ALIGNED, 0);
> +}
> }
>
> typedef HexagonCPU ArchCPU;
> diff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h
> index 96fef71729..4279281a71 100644
> --- a/target/hexagon/cpu_bits.h
> +++ b/target/hexagon/cpu_bits.h
> @@ -20,9 +20,13 @@
>
> #include "qemu/bitops.h"
>
> +#define PCALIGN 4
> +#define PCALIGN_MASK (PCALIGN - 1)
> +
> #define HEX_EXCP_FETCH_NO_UPAGE 0x012
> #define HEX_EXCP_INVALID_PACKET 0x015
> #define HEX_EXCP_INVALID_OPCODE 0x015
> +#define HEX_EXCP_PC_NOT_ALIGNED 0x01e
> #define HEX_EXCP_PRIV_NO_UREAD 0x024
> #define HEX_EXCP_PRIV_NO_UWRITE 0x025
>
> diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
> index 1376d6ccc1..f375471a98 100644
> --- a/target/hexagon/macros.h
> +++ b/target/hexagon/macros.h
> @@ -22,9 +22,6 @@
> #include "hex_regs.h"
> #include "reg_fields.h"
>
> -#define PCALIGN 4
> -#define PCALIGN_MASK (PCALIGN - 1)
> -
> #define GET_FIELD(FIELD, REGIN) \
> fEXTRACTU_BITS(REGIN, reg_field_info[FIELD].width, \
> reg_field_info[FIELD].offset)
> diff --git a/linux-user/hexagon/cpu_loop.c b/linux-user/hexagon/cpu_loop.c
> index 7f1499ed28..d41159e52a 100644
> --- a/linux-user/hexagon/cpu_loop.c
> +++ b/linux-user/hexagon/cpu_loop.c
> @@ -60,6 +60,10 @@ void cpu_loop(CPUHexagonState *env)
> env->gpr[0] = ret;
> }
> break;
> +case HEX_EXCP_PC_NOT_ALIGNED:
> +force_sig_fault(TARGET_SIGBUS, TARGET_BUS_ADRALN,
> +env->gpr[HEX_REG_R31]);
> +break;
> case EXCP_ATOMIC:
> cpu_exec_step_atomic(cs);
> break;
> diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
> index da10ac5847..ae5a605513 100644
> --- a/target/hexagon/op_helper.c
> +++ b/target/hexagon/op_helper.c
> @@ -36,10 +36,9 @@
> #define SF_MANTBITS23
>
> /* Exceptions processing helpers */
> -static G_NORETURN
> -void do_raise_exception_err(CPUHexagonState *env,
> -uint32_t exception,
> -uintptr_t pc)
> +G_NORETURN void hexagon_raise_exception_err(CPUHexagonState *env,
> +uint32_t exception,
> +uintptr_t pc)
> {
> CPUState *cs = env_cpu(env);
> qemu_
[PULL 10/15] Hexagon (target/hexagon) Mark has_pred_dest in trans functions
From: Taylor Simpson
Check that the value matches opcode_wregs
Signed-off-by: Taylor Simpson
Reviewed-by: Brian Cain
Message-Id: <20240307032327.4799-5-ltaylorsimp...@gmail.com>
Signed-off-by: Brian Cain
---
target/hexagon/decode.c | 3 +++
target/hexagon/gen_trans_funcs.py | 5 +
target/hexagon/insn.h | 1 +
3 files changed, 9 insertions(+)
diff --git a/target/hexagon/decode.c b/target/hexagon/decode.c
index a4d8500fea..84a3899556 100644
--- a/target/hexagon/decode.c
+++ b/target/hexagon/decode.c
@@ -366,6 +366,9 @@ static void decode_shuffle_for_execution(Packet *packet)
for (flag = false, i = 0; i < last_insn + 1; i++) {
int opcode = packet->insn[i].opcode;
+g_assert(packet->insn[i].has_pred_dest ==
+ (strstr(opcode_wregs[opcode], "Pd4") ||
+ strstr(opcode_wregs[opcode], "Pe4")));
if ((strstr(opcode_wregs[opcode], "Pd4") ||
strstr(opcode_wregs[opcode], "Pe4")) &&
GET_ATTRIB(opcode, A_STORE) == 0) {
diff --git a/target/hexagon/gen_trans_funcs.py
b/target/hexagon/gen_trans_funcs.py
index 1201172dda..9f86b4edbd 100755
--- a/target/hexagon/gen_trans_funcs.py
+++ b/target/hexagon/gen_trans_funcs.py
@@ -70,6 +70,7 @@ def mark_which_imm_extended(f, tag):
## insn->regno[2] = args->Rt;
## insn->new_read_idx = -1;
## insn->dest_idx = 0;
+## insn->has_pred_dest = false;
## return true;
## }
##
@@ -88,6 +89,7 @@ def gen_trans_funcs(f):
new_read_idx = -1
dest_idx = -1
+has_pred_dest = "false"
for regno, (reg_type, reg_id, *_) in enumerate(regs):
reg = hex_common.get_register(tag, reg_type, reg_id)
f.write(code_fmt(f"""\
@@ -98,6 +100,8 @@ def gen_trans_funcs(f):
# dest_idx should be the first destination, so check for -1
if reg.is_written() and dest_idx == -1:
dest_idx = regno
+if reg_type == "P" and reg.is_written() and not reg.is_read():
+has_pred_dest = "true"
if len(imms) != 0:
mark_which_imm_extended(f, tag)
@@ -121,6 +125,7 @@ def gen_trans_funcs(f):
f.write(code_fmt(f"""\
insn->new_read_idx = {new_read_idx};
insn->dest_idx = {dest_idx};
+insn->has_pred_dest = {has_pred_dest};
"""))
f.write(textwrap.dedent(f"""\
return true;
diff --git a/target/hexagon/insn.h b/target/hexagon/insn.h
index a770379958..24dcf7fe9f 100644
--- a/target/hexagon/insn.h
+++ b/target/hexagon/insn.h
@@ -41,6 +41,7 @@ struct Instruction {
uint32_t new_value_producer_slot:4;
int32_t new_read_idx;
int32_t dest_idx;
+bool has_pred_dest;
bool part1; /*
* cmp-jumps are split into two insns.
--
2.25.1
[PULL 14/15] Hexagon (target/hexagon) Remove gen_shortcode.py
From: Taylor Simpson
This data structure is not used
Signed-off-by: Taylor Simpson
Reviewed-by: Brian Cain
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20240307032327.4799-9-ltaylorsimp...@gmail.com>
Signed-off-by: Brian Cain
---
target/hexagon/README | 1 -
target/hexagon/gen_shortcode.py | 63 -
target/hexagon/meson.build | 10 --
target/hexagon/opcodes.c| 7
4 files changed, 81 deletions(-)
delete mode 100755 target/hexagon/gen_shortcode.py
diff --git a/target/hexagon/README b/target/hexagon/README
index 224a3f9206..7ffd517d70 100644
--- a/target/hexagon/README
+++ b/target/hexagon/README
@@ -46,7 +46,6 @@ header files in /target/hexagon
gen_printinsn.py-> printinsn_generated.h.inc
gen_op_attribs.py -> op_attribs_generated.h.inc
gen_helper_protos.py-> helper_protos_generated.h.inc
-gen_shortcode.py-> shortcode_generated.h.inc
gen_tcg_funcs.py-> tcg_funcs_generated.c.inc
gen_tcg_func_table.py -> tcg_func_table_generated.c.inc
gen_helper_funcs.py -> helper_funcs_generated.c.inc
diff --git a/target/hexagon/gen_shortcode.py b/target/hexagon/gen_shortcode.py
deleted file mode 100755
index deb94446c4..00
--- a/target/hexagon/gen_shortcode.py
+++ /dev/null
@@ -1,63 +0,0 @@
-#!/usr/bin/env python3
-
-##
-## Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights
Reserved.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, see <http://www.gnu.org/licenses/>.
-##
-
-import sys
-import re
-import string
-import hex_common
-
-
-def gen_shortcode(f, tag):
-f.write(f"DEF_SHORTCODE({tag}, {hex_common.semdict[tag]})\n")
-
-
-def main():
-hex_common.read_semantics_file(sys.argv[1])
-hex_common.read_attribs_file(sys.argv[2])
-hex_common.calculate_attribs()
-tagregs = hex_common.get_tagregs()
-tagimms = hex_common.get_tagimms()
-
-with open(sys.argv[3], "w") as f:
-f.write("#ifndef DEF_SHORTCODE\n")
-f.write("#define DEF_SHORTCODE(TAG,SHORTCODE)/* Nothing */\n")
-f.write("#endif\n")
-
-for tag in hex_common.tags:
-## Skip the priv instructions
-if "A_PRIV" in hex_common.attribdict[tag]:
-continue
-## Skip the guest instructions
-if "A_GUEST" in hex_common.attribdict[tag]:
-continue
-## Skip the diag instructions
-if tag == "Y6_diag":
-continue
-if tag == "Y6_diag0":
-continue
-if tag == "Y6_diag1":
-continue
-
-gen_shortcode(f, tag)
-
-f.write("#undef DEF_SHORTCODE\n")
-
-
-if __name__ == "__main__":
-main()
diff --git a/target/hexagon/meson.build b/target/hexagon/meson.build
index b3a0944d3b..988e7489ba 100644
--- a/target/hexagon/meson.build
+++ b/target/hexagon/meson.build
@@ -42,21 +42,11 @@ hexagon_ss.add(semantics_generated)
#
# Step 2
# We use Python scripts to generate the following files
-# shortcode_generated.h.inc
# tcg_func_table_generated.c.inc
# printinsn_generated.h.inc
# op_attribs_generated.h.inc
# opcodes_def_generated.h.inc
#
-shortcode_generated = custom_target(
-'shortcode_generated.h.inc',
-output: 'shortcode_generated.h.inc',
-depends: [semantics_generated],
-depend_files: [hex_common_py, attribs_def],
-command: [python, files('gen_shortcode.py'), semantics_generated,
attribs_def, '@OUTPUT@'],
-)
-hexagon_ss.add(shortcode_generated)
-
tcg_func_table_generated = custom_target(
'tcg_func_table_generated.c.inc',
output: 'tcg_func_table_generated.c.inc',
diff --git a/target/hexagon/opcodes.c b/target/hexagon/opcodes.c
index 02ae9cf787..c8bde2f9e9 100644
--- a/target/hexagon/opcodes.c
+++ b/target/hexagon/opcodes.c
@@ -37,13 +37,6 @@ const char * const opcode_names[] = {
};
-const char * const opcode_short_semantics[] = {
-#define DEF_SHORTCODE(TAG, SHORTCODE) [TAG] = #SHORTCODE,
-#include "shortcode_generated.h.inc"
-#undef DEF_SHORTCODE
-NULL
-};
-
DECLARE_BITMAP(opcode_attribs[XX_LAST_OPCODE], A_ZZ_LASTATTRIB);
static void init_attribs(int tag, ...)
--
2.25.1
[PULL 05/15] Hexagon (target/hexagon) Pass SP explicitly to helpers that need it
From: Taylor Simpson
Rather than reading SP from the env, pass it explicitly
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
Tested-by: Anton Johansson
Reviewed-by: Brian Cain
Message-Id: <20240214042726.19290-3-ltaylorsimp...@gmail.com>
Signed-off-by: Brian Cain
---
target/hexagon/attribs_def.h.inc | 3 ++-
target/hexagon/hex_common.py | 11 +++
target/hexagon/macros.h | 2 +-
3 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/target/hexagon/attribs_def.h.inc b/target/hexagon/attribs_def.h.inc
index 87942d46f4..9e3a05f882 100644
--- a/target/hexagon/attribs_def.h.inc
+++ b/target/hexagon/attribs_def.h.inc
@@ -1,5 +1,5 @@
/*
- * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights
Reserved.
+ * Copyright(c) 2019-2024 Qualcomm Innovation Center, Inc. All Rights
Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -117,6 +117,7 @@ DEF_ATTRIB(IMPLICIT_READS_P1, "Reads the P1 register", "",
"")
DEF_ATTRIB(IMPLICIT_READS_P2, "Reads the P2 register", "", "")
DEF_ATTRIB(IMPLICIT_READS_P3, "Reads the P3 register", "", "")
DEF_ATTRIB(IMPLICIT_WRITES_USR, "May write USR", "", "")
+DEF_ATTRIB(IMPLICIT_READS_SP, "Reads the SP register", "", "")
DEF_ATTRIB(COMMUTES, "The operation is communitive", "", "")
DEF_ATTRIB(DEALLOCRET, "dealloc_return", "", "")
DEF_ATTRIB(DEALLOCFRAME, "deallocframe", "", "")
diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
index 63d18f73ad..03c9ce1d8a 100755
--- a/target/hexagon/hex_common.py
+++ b/target/hexagon/hex_common.py
@@ -101,6 +101,7 @@ def calculate_attribs():
add_qemu_macro_attrib('fLSBNEW1', 'A_IMPLICIT_READS_P1')
add_qemu_macro_attrib('fLSBNEW1NOT', 'A_IMPLICIT_READS_P1')
add_qemu_macro_attrib('fREAD_P3', 'A_IMPLICIT_READS_P3')
+add_qemu_macro_attrib('fREAD_SP', 'A_IMPLICIT_READS_SP')
# Recurse down macros, find attributes from sub-macros
macroValues = list(macros.values())
@@ -201,6 +202,10 @@ def need_p0(tag):
return "A_IMPLICIT_READS_P0" in attribdict[tag]
+def need_sp(tag):
+return "A_IMPLICIT_READS_SP" in attribdict[tag]
+
+
def need_slot(tag):
if (
"A_CVI_SCATTER" not in attribdict[tag]
@@ -1144,6 +1149,12 @@ def helper_args(tag, regs, imms):
"hex_pred[0]",
"uint32_t P0"
))
+if need_sp(tag):
+args.append(HelperArg(
+"i32",
+"hex_gpr[HEX_REG_SP]",
+"uint32_t SP"
+))
if need_slot(tag):
args.append(HelperArg(
"i32",
diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
index aedc863fab..feb798c6c0 100644
--- a/target/hexagon/macros.h
+++ b/target/hexagon/macros.h
@@ -343,7 +343,7 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val, int
shift)
#define fREAD_LR() (env->gpr[HEX_REG_LR])
-#define fREAD_SP() (env->gpr[HEX_REG_SP])
+#define fREAD_SP() (SP)
#define fREAD_LC0 (env->gpr[HEX_REG_LC0])
#define fREAD_LC1 (env->gpr[HEX_REG_LC1])
#define fREAD_SA0 (env->gpr[HEX_REG_SA0])
--
2.25.1
[PULL 15/15] Hexagon (target/hexagon) Remove hex_common.read_attribs_file
From: Taylor Simpson The attribinfo data structure is not used Adjust the command-line arguments to the python scripts Add hex_common.read_common_files for TCG/helper generation scripts Signed-off-by: Taylor Simpson Reviewed-by: Brian Cain Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20240307032327.4799-10-ltaylorsimp...@gmail.com> Signed-off-by: Brian Cain --- target/hexagon/gen_analyze_funcs.py | 19 +- target/hexagon/gen_helper_funcs.py | 21 ++- target/hexagon/gen_helper_protos.py | 19 +- target/hexagon/gen_idef_parser_funcs.py | 5 ++-- target/hexagon/gen_op_attribs.py| 5 ++-- target/hexagon/gen_opcodes_def.py | 4 +-- target/hexagon/gen_printinsn.py | 5 ++-- target/hexagon/gen_tcg_func_table.py| 5 ++-- target/hexagon/gen_tcg_funcs.py | 21 ++- target/hexagon/hex_common.py| 35 +++-- target/hexagon/meson.build | 31 +++--- 11 files changed, 52 insertions(+), 118 deletions(-) diff --git a/target/hexagon/gen_analyze_funcs.py b/target/hexagon/gen_analyze_funcs.py index 81e1d9cfa3..54bac19724 100755 --- a/target/hexagon/gen_analyze_funcs.py +++ b/target/hexagon/gen_analyze_funcs.py @@ -78,24 +78,7 @@ def gen_analyze_func(f, tag, regs, imms): def main(): -hex_common.read_semantics_file(sys.argv[1]) -hex_common.read_attribs_file(sys.argv[2]) -hex_common.read_overrides_file(sys.argv[3]) -hex_common.read_overrides_file(sys.argv[4]) -## Whether or not idef-parser is enabled is -## determined by the number of arguments to -## this script: -## -## 5 args. -> not enabled, -## 6 args. -> idef-parser enabled. -## -## The 6:th arg. then holds a list of the successfully -## parsed instructions. -is_idef_parser_enabled = len(sys.argv) > 6 -if is_idef_parser_enabled: -hex_common.read_idef_parser_enabled_file(sys.argv[5]) -hex_common.calculate_attribs() -hex_common.init_registers() +hex_common.read_common_files() tagregs = hex_common.get_tagregs() tagimms = hex_common.get_tagimms() diff --git a/target/hexagon/gen_helper_funcs.py b/target/hexagon/gen_helper_funcs.py index 9cc3d69c49..e9685bff2f 100755 --- a/target/hexagon/gen_helper_funcs.py +++ b/target/hexagon/gen_helper_funcs.py @@ -1,7 +1,7 @@ #!/usr/bin/env python3 ## -## Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved. +## Copyright(c) 2019-2024 Qualcomm Innovation Center, Inc. All Rights Reserved. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -102,24 +102,7 @@ def gen_helper_function(f, tag, tagregs, tagimms): def main(): -hex_common.read_semantics_file(sys.argv[1]) -hex_common.read_attribs_file(sys.argv[2]) -hex_common.read_overrides_file(sys.argv[3]) -hex_common.read_overrides_file(sys.argv[4]) -## Whether or not idef-parser is enabled is -## determined by the number of arguments to -## this script: -## -## 5 args. -> not enabled, -## 6 args. -> idef-parser enabled. -## -## The 6:th arg. then holds a list of the successfully -## parsed instructions. -is_idef_parser_enabled = len(sys.argv) > 6 -if is_idef_parser_enabled: -hex_common.read_idef_parser_enabled_file(sys.argv[5]) -hex_common.calculate_attribs() -hex_common.init_registers() +hex_common.read_common_files() tagregs = hex_common.get_tagregs() tagimms = hex_common.get_tagimms() diff --git a/target/hexagon/gen_helper_protos.py b/target/hexagon/gen_helper_protos.py index f8578d5033..fd2bfd0f36 100755 --- a/target/hexagon/gen_helper_protos.py +++ b/target/hexagon/gen_helper_protos.py @@ -52,24 +52,7 @@ def gen_helper_prototype(f, tag, tagregs, tagimms): def main(): -hex_common.read_semantics_file(sys.argv[1]) -hex_common.read_attribs_file(sys.argv[2]) -hex_common.read_overrides_file(sys.argv[3]) -hex_common.read_overrides_file(sys.argv[4]) -## Whether or not idef-parser is enabled is -## determined by the number of arguments to -## this script: -## -## 5 args. -> not enabled, -## 6 args. -> idef-parser enabled. -## -## The 6:th arg. then holds a list of the successfully -## parsed instructions. -is_idef_parser_enabled = len(sys.argv) > 6 -if is_idef_parser_enabled: -hex_common.read_idef_parser_enabled_file(sys.argv[5]) -hex_common.calculate_attribs() -hex_common.init_registers() +hex_common.read_common_files() tagregs = hex_common.get_tagregs() tagimms = hex_common.get_tagimms() diff --git a/target/hexagon/gen_idef_parser_funcs.py b/target/hexagon/gen_idef_parser_funcs.py index 550a48cb7b..eb494abba8 100644 --- a/target/hexagon/gen_idef_par
[PULL 06/15] Hexagon (target/hexagon) Only pass env to generated helper when needed
From: Taylor Simpson
Currently, we pass env to every generated helper. When the semantics of
the instruction only depend on the arguments, this is unnecessary and
adds extra overhead to the helper call.
We add the TCG_CALL_NO_RWG_SE flag to any non-HVX helpers that don't get
the ptr to env.
The A2_nop and SA1_setin1 instructions end up with no arguments. This
results in a "old-style function definition" error from the compiler, so
we write overrides for them.
With this change, the number of helpers with env argument is
idef-parser enabled:329 total, 23 with env
idef-parser disabled: 1543 total, 550 with env
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
Tested-by: Anton Johansson
Message-Id: <20240214042726.19290-4-ltaylorsimp...@gmail.com>
Signed-off-by: Brian Cain
---
target/hexagon/gen_helper_protos.py | 12 ++--
target/hexagon/gen_tcg.h| 5 -
target/hexagon/hex_common.py| 23 ++-
3 files changed, 32 insertions(+), 8 deletions(-)
diff --git a/target/hexagon/gen_helper_protos.py
b/target/hexagon/gen_helper_protos.py
index c82b0f54e4..f8578d5033 100755
--- a/target/hexagon/gen_helper_protos.py
+++ b/target/hexagon/gen_helper_protos.py
@@ -1,7 +1,7 @@
#!/usr/bin/env python3
##
-## Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights
Reserved.
+## Copyright(c) 2019-2024 Qualcomm Innovation Center, Inc. All Rights
Reserved.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
@@ -40,7 +40,15 @@ def gen_helper_prototype(f, tag, tagregs, tagimms):
declared.append(arg.proto_arg)
arguments = ", ".join(declared)
-f.write(f"DEF_HELPER_{len(declared) - 1}({tag}, {arguments})\n")
+
+## Add the TCG_CALL_NO_RWG_SE flag to helpers that don't take the env
+## argument and aren't HVX instructions. Since HVX instructions take
+## pointers to their arguments, they will have side effects.
+if hex_common.need_env(tag) or hex_common.is_hvx_insn(tag):
+f.write(f"DEF_HELPER_{len(declared) - 1}({tag}, {arguments})\n")
+else:
+f.write(f"DEF_HELPER_FLAGS_{len(declared) - 1}({tag}, "
+f"TCG_CALL_NO_RWG_SE, {arguments})\n")
def main():
diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index 1c4391b415..3fc1f4e281 100644
--- a/target/hexagon/gen_tcg.h
+++ b/target/hexagon/gen_tcg.h
@@ -1,5 +1,5 @@
/*
- * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights
Reserved.
+ * Copyright(c) 2019-2024 Qualcomm Innovation Center, Inc. All Rights
Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -1369,3 +1369,6 @@
gen_helper_raise_exception(tcg_env, excp); \
} while (0)
#endif
+
+#define fGEN_TCG_A2_nop(SHORTCODE) do { } while (0)
+#define fGEN_TCG_SA1_setin1(SHORTCODE) tcg_gen_movi_tl(RdV, -1)
diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
index 03c9ce1d8a..c09b48bb36 100755
--- a/target/hexagon/hex_common.py
+++ b/target/hexagon/hex_common.py
@@ -206,6 +206,18 @@ def need_sp(tag):
return "A_IMPLICIT_READS_SP" in attribdict[tag]
+def is_hvx_insn(tag):
+return "A_CVI" in attribdict[tag]
+
+
+def need_env(tag):
+return ("A_STORE" in attribdict[tag] or
+"A_LOAD" in attribdict[tag] or
+"A_CVI_GATHER" in attribdict[tag] or
+"A_CVI_SCATTER" in attribdict[tag] or
+"A_IMPLICIT_WRITES_USR" in attribdict[tag])
+
+
def need_slot(tag):
if (
"A_CVI_SCATTER" not in attribdict[tag]
@@ -1085,11 +1097,12 @@ def helper_args(tag, regs, imms):
args = []
## First argument is the CPU state
-args.append(HelperArg(
-"env",
-"tcg_env",
-"CPUHexagonState *env"
-))
+if need_env(tag):
+args.append(HelperArg(
+"env",
+"tcg_env",
+"CPUHexagonState *env"
+))
## For predicated instructions, we pass in the destination register
if is_predicated(tag):
--
2.25.1
[PULL 11/15] Hexagon (tests/tcg/hexagon) Test HVX .new read from high half of pair
From: Taylor Simpson
Make sure the decoding of HVX .new is correctly handling this case
Signed-off-by: Taylor Simpson
Reviewed-by: Brian Cain
Message-Id: <20240307032327.4799-6-ltaylorsimp...@gmail.com>
Signed-off-by: Brian Cain
---
tests/tcg/hexagon/hvx_misc.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/tests/tcg/hexagon/hvx_misc.c b/tests/tcg/hexagon/hvx_misc.c
index b45170acd1..1fe14b5158 100644
--- a/tests/tcg/hexagon/hvx_misc.c
+++ b/tests/tcg/hexagon/hvx_misc.c
@@ -1,5 +1,5 @@
/*
- * Copyright(c) 2021-2023 Qualcomm Innovation Center, Inc. All Rights
Reserved.
+ * Copyright(c) 2021-2024 Qualcomm Innovation Center, Inc. All Rights
Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -231,6 +231,7 @@ static void test_masked_store(bool invert)
static void test_new_value_store(void)
{
void *p0 = buffer0;
+void *p1 = buffer1;
void *pout = output;
asm("{\n\t"
@@ -242,6 +243,19 @@ static void test_new_value_store(void)
expect[0] = buffer0[0];
check_output_w(__LINE__, 1);
+
+/* Test the .new read from the high half of a pair */
+asm("v7 = vmem(%0 + #0)\n\t"
+"v12 = vmem(%1 + #0)\n\t"
+"{\n\t"
+"v5:4 = vcombine(v12, v7)\n\t"
+"vmem(%2 + #0) = v5.new\n\t"
+"}\n\t"
+: : "r"(p0), "r"(p1), "r"(pout) : "v4", "v5", "v7", "v12", "memory");
+
+expect[0] = buffer1[0];
+
+check_output_w(__LINE__, 1);
}
static void test_max_temps()
--
2.25.1
[PULL 07/15] Hexagon (target/hexagon) Add is_old/is_new to Register class
From: Taylor Simpson
Signed-off-by: Taylor Simpson
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Brian Cain
Message-Id: <20240307032327.4799-2-ltaylorsimp...@gmail.com>
Signed-off-by: Brian Cain
---
target/hexagon/hex_common.py | 12
1 file changed, 12 insertions(+)
diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
index c09b48bb36..f6f187968a 100755
--- a/target/hexagon/hex_common.py
+++ b/target/hexagon/hex_common.py
@@ -428,10 +428,18 @@ def is_readwrite(self):
class OldSource(Source):
def reg_tcg(self):
return f"{self.regtype}{self.regid}V"
+def is_old(self):
+return True
+def is_new(self):
+return False
class NewSource(Source):
def reg_tcg(self):
return f"{self.regtype}{self.regid}N"
+def is_old(self):
+return False
+def is_new(self):
+return True
class ReadWrite:
def reg_tcg(self):
@@ -444,6 +452,10 @@ def is_read(self):
return True
def is_readwrite(self):
return True
+def is_old(self):
+return True
+def is_new(self):
+return False
class GprDest(Register, Single, Dest):
def decl_tcg(self, f, tag, regno):
--
2.25.1
[PULL 02/15] Hexagon (target/hexagon) Enable more short-circuit packets (scalar core)
From: Taylor Simpson
Look for read-after-write instead of overlap of reads and writes
Here is an example with overalp but no read-after-write:
0x000200fc: 0x38103876 { R0 = add(R0,R1); R6 = add(R6,R7) }
BEFORE:
000200fc
mov_i32 loc2,$0x0
mov_i32 loc2,r0
add_i32 loc3,loc2,r1
mov_i32 loc2,loc3
mov_i32 loc4,$0x0
mov_i32 loc4,r6
add_i32 loc5,loc4,r7
mov_i32 loc4,loc5
mov_i32 r0,loc2
mov_i32 r6,loc4
AFTER:
000200fc
add_i32 loc2,r0,r1
mov_i32 r0,loc2
add_i32 loc3,r6,r7
mov_i32 r6,loc3
We can also short-circuit packets with .new values by reading from the
real destination instead of the temporary.
0x00020100: 0x78005ff3 { R19 = #0xff
0x00020104: 0x2002e204 if (cmp.eq(N19.new,R2)) jump:t PC+8 }
BEFORE:
00020100
mov_i32 pc,$0x20108
mov_i32 loc8,$0x0
mov_i32 loc8,$0xff
setcond_i32 loc10,loc8,r2,eq
mov_i32 loc6,loc10
mov_i32 r19,loc8
add_i32 pkt_cnt,pkt_cnt,$0x2
add_i32 insn_cnt,insn_cnt,$0x4
brcond_i32 loc6,$0x0,eq,$L1
goto_tb $0x0
mov_i32 pc,$0x20108
exit_tb $0x7fbb5440
set_label $L1
goto_tb $0x1
exit_tb $0x7fbb5441
set_label $L0
exit_tb $0x7fbb5443
AFTER:
00020100
mov_i32 pc,$0x20108
mov_i32 r19,$0xff
setcond_i32 loc7,r19,r2,eq
mov_i32 loc4,loc7
add_i32 pkt_cnt,pkt_cnt,$0x2
add_i32 insn_cnt,insn_cnt,$0x4
brcond_i32 loc4,$0x0,eq,$L1
goto_tb $0x0
mov_i32 pc,$0x20108
exit_tb $0x7f976440
set_label $L1
goto_tb $0x1
exit_tb $0x7f976441
set_label $L0
exit_tb $0x7f976443
Signed-off-by: Taylor Simpson
Reviewed-by: Brian Cain
Message-Id: <20240201103340.119081-3-ltaylorsimp...@gmail.com>
Signed-off-by: Brian Cain
---
target/hexagon/translate.c | 21 -
target/hexagon/translate.h | 13 +++--
2 files changed, 11 insertions(+), 23 deletions(-)
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index 47a870f42d..8d42ebd91c 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -1,5 +1,5 @@
/*
- * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights
Reserved.
+ * Copyright(c) 2019-2024 Qualcomm Innovation Center, Inc. All Rights
Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -396,20 +396,8 @@ static bool need_commit(DisasContext *ctx)
}
}
-/* Check for overlap between register reads and writes */
-for (int i = 0; i < ctx->reg_log_idx; i++) {
-int rnum = ctx->reg_log[i];
-if (test_bit(rnum, ctx->regs_read)) {
-return true;
-}
-}
-
-/* Check for overlap between predicate reads and writes */
-for (int i = 0; i < ctx->preg_log_idx; i++) {
-int pnum = ctx->preg_log[i];
-if (test_bit(pnum, ctx->pregs_read)) {
-return true;
-}
+if (ctx->read_after_write) {
+return true;
}
/* Check for overlap between HVX reads and writes */
@@ -468,6 +456,7 @@ static void analyze_packet(DisasContext *ctx)
{
Packet *pkt = ctx->pkt;
ctx->has_hvx_helper = false;
+ctx->read_after_write = false;
for (int i = 0; i < pkt->num_insns; i++) {
Insn *insn = >insn[i];
ctx->insn = insn;
@@ -492,11 +481,9 @@ static void gen_start_packet(DisasContext *ctx)
ctx->next_PC = next_PC;
ctx->reg_log_idx = 0;
bitmap_zero(ctx->regs_written, TOTAL_PER_THREAD_REGS);
-bitmap_zero(ctx->regs_read, TOTAL_PER_THREAD_REGS);
bitmap_zero(ctx->predicated_regs, TOTAL_PER_THREAD_REGS);
ctx->preg_log_idx = 0;
bitmap_zero(ctx->pregs_written, NUM_PREGS);
-bitmap_zero(ctx->pregs_read, NUM_PREGS);
ctx->future_vregs_idx = 0;
ctx->tmp_vregs_idx = 0;
ctx->vreg_log_idx = 0;
diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h
index f06d71fc53..d5e7f49ad8 100644
--- a/target/hexagon/translate.h
+++ b/target/hexagon/translate.h
@@ -38,12 +38,10 @@ typedef struct DisasContext {
int reg_log[REG_WRITES_MAX];
int reg_log_idx;
DECLARE_BITMAP(regs_written, TOTAL_PER_THREAD_REGS);
-DECLARE_BITMAP(regs_read, TOTAL_PER_THREAD_REGS);
DECLARE_BITMAP(predicated_regs, TOTAL_PER_THREAD_REGS);
int preg_log[PRED_WRITES_MAX];
int preg_log_idx;
DECLARE_BITMAP(pregs_written, NUM_PREGS);
-DECLARE_BITMAP(pregs_read, NUM_PREGS);
uint8_t store_width[STORES_MAX];
bool s1_store_processed;
int future_vregs_idx;
@@ -68,6 +66,7 @@ typedef struct DisasContext {
bool is_tight_loop;
bool short_circuit;
bool has_hvx_helper;
+bool read_after_write;
TCGv new_value[TOTAL_PER_THREAD_REGS];
TCGv new_pred_value[NUM_PREGS];
TCGv pred_written;
@@ -88,13 +87,14 @@ static inline void ctx_log_pred_write(DisasContext *ctx,
int pnum)
static inline void ctx_log_pred_read
[PULL 13/15] Hexagon (target/hexagon) Remove gen_op_regs.py
From: Taylor Simpson
Signed-off-by: Taylor Simpson
Reviewed-by: Brian Cain
Message-Id: <20240307032327.4799-8-ltaylorsimp...@gmail.com>
Signed-off-by: Brian Cain
---
target/hexagon/README | 1 -
target/hexagon/gen_op_regs.py | 125 --
target/hexagon/meson.build| 14 +---
3 files changed, 2 insertions(+), 138 deletions(-)
delete mode 100755 target/hexagon/gen_op_regs.py
diff --git a/target/hexagon/README b/target/hexagon/README
index c1d8c8d0ab..224a3f9206 100644
--- a/target/hexagon/README
+++ b/target/hexagon/README
@@ -43,7 +43,6 @@ target/hexagon/gen_semantics.c. This step produces
That file is consumed by the following python scripts to produce the indicated
header files in /target/hexagon
gen_opcodes_def.py -> opcodes_def_generated.h.inc
-gen_op_regs.py -> op_regs_generated.h.inc
gen_printinsn.py-> printinsn_generated.h.inc
gen_op_attribs.py -> op_attribs_generated.h.inc
gen_helper_protos.py-> helper_protos_generated.h.inc
diff --git a/target/hexagon/gen_op_regs.py b/target/hexagon/gen_op_regs.py
deleted file mode 100755
index 7b7b33895a..00
--- a/target/hexagon/gen_op_regs.py
+++ /dev/null
@@ -1,125 +0,0 @@
-#!/usr/bin/env python3
-
-##
-## Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights
Reserved.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, see <http://www.gnu.org/licenses/>.
-##
-
-import sys
-import re
-import string
-import hex_common
-
-
-##
-## Generate the register and immediate operands for each instruction
-##
-def calculate_regid_reg(tag):
-def letter_inc(x):
-return chr(ord(x) + 1)
-
-ordered_implregs = ["SP", "FP", "LR"]
-srcdst_lett = "X"
-src_lett = "S"
-dst_lett = "D"
-retstr = ""
-mapdict = {}
-for reg in ordered_implregs:
-reg_rd = 0
-reg_wr = 0
-if ("A_IMPLICIT_WRITES_" + reg) in hex_common.attribdict[tag]:
-reg_wr = 1
-if reg_rd and reg_wr:
-retstr += srcdst_lett
-mapdict[srcdst_lett] = reg
-srcdst_lett = letter_inc(srcdst_lett)
-elif reg_rd:
-retstr += src_lett
-mapdict[src_lett] = reg
-src_lett = letter_inc(src_lett)
-elif reg_wr:
-retstr += dst_lett
-mapdict[dst_lett] = reg
-dst_lett = letter_inc(dst_lett)
-return retstr, mapdict
-
-
-def calculate_regid_letters(tag):
-retstr, mapdict = calculate_regid_reg(tag)
-return retstr
-
-
-def strip_reg_prefix(x):
-y = x.replace("UREG.", "")
-y = y.replace("MREG.", "")
-return y.replace("GREG.", "")
-
-
-def main():
-hex_common.read_semantics_file(sys.argv[1])
-hex_common.read_attribs_file(sys.argv[2])
-hex_common.init_registers()
-tagregs = hex_common.get_tagregs(full=True)
-tagimms = hex_common.get_tagimms()
-
-with open(sys.argv[3], "w") as f:
-for tag in hex_common.tags:
-regs = tagregs[tag]
-rregs = []
-wregs = []
-regids = ""
-for regtype, regid, _, numregs in regs:
-reg = hex_common.get_register(tag, regtype, regid)
-if reg.is_read():
-if regid[0] not in regids:
-regids += regid[0]
-rregs.append(regtype + regid + numregs)
-if reg.is_written():
-wregs.append(regtype + regid + numregs)
-if regid[0] not in regids:
-regids += regid[0]
-for attrib in hex_common.attribdict[tag]:
-if hex_common.attribinfo[attrib]["rreg"]:
-rregs.append(strip_reg_prefix(attribinfo[attrib]["rreg"]))
-if hex_common.attribinfo[attrib]["wreg"]:
-wregs.append(strip_reg_prefix(attribinfo[attrib]["wreg"]))
-regids += calculate_regid_letters(tag)
-f.write(
-f'REGINFO({tag},"{regids}",\t/*RD:*/\t"{",".join(rregs)}&q
[PULL 04/15] Hexagon (target/hexagon) Pass P0 explicitly to helpers that need it
From: Taylor Simpson Rather than reading P0 from the env, pass it explicitly Signed-off-by: Taylor Simpson Reviewed-by: Anton Johansson Tested-by: Anton Johansson Reviewed-by: Brian Cain Message-Id: <20240214042726.19290-2-ltaylorsimp...@gmail.com> Signed-off-by: Brian Cain --- target/hexagon/hex_common.py | 10 ++ target/hexagon/macros.h | 4 ++-- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py index 9e7f613e3c..63d18f73ad 100755 --- a/target/hexagon/hex_common.py +++ b/target/hexagon/hex_common.py @@ -197,6 +197,10 @@ def get_tagimms(): return dict(zip(tags, list(map(compute_tag_immediates, tags +def need_p0(tag): +return "A_IMPLICIT_READS_P0" in attribdict[tag] + + def need_slot(tag): if ( "A_CVI_SCATTER" not in attribdict[tag] @@ -1134,6 +1138,12 @@ def helper_args(tag, regs, imms): "tcg_constant_tl(ctx->next_PC)", "target_ulong next_PC" )) +if need_p0(tag): +args.append(HelperArg( +"i32", +"hex_pred[0]", +"uint32_t P0" +)) if need_slot(tag): args.append(HelperArg( "i32", diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h index 1376d6ccc1..aedc863fab 100644 --- a/target/hexagon/macros.h +++ b/target/hexagon/macros.h @@ -1,5 +1,5 @@ /* - * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved. + * Copyright(c) 2019-2024 Qualcomm Innovation Center, Inc. All Rights Reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -358,7 +358,7 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift) #endif #define fREAD_PC() (PC) -#define fREAD_P0() (env->pred[0]) +#define fREAD_P0() (P0) #define fCHECK_PCALIGN(A) -- 2.25.1
[PULL 12/15] Hexagon (target/hexagon) Remove uses of op_regs_generated.h.inc
From: Taylor Simpson
Signed-off-by: Taylor Simpson
Reviewed-by: Brian Cain
Message-Id: <20240307032327.4799-7-ltaylorsimp...@gmail.com>
Signed-off-by: Brian Cain
---
target/hexagon/decode.c | 55 +++--
target/hexagon/mmvec/decode_ext_mmvec.c | 34 ---
target/hexagon/opcodes.c| 28 -
target/hexagon/opcodes.h| 4 --
4 files changed, 12 insertions(+), 109 deletions(-)
diff --git a/target/hexagon/decode.c b/target/hexagon/decode.c
index 84a3899556..23deba2426 100644
--- a/target/hexagon/decode.c
+++ b/target/hexagon/decode.c
@@ -115,24 +115,13 @@ static void
decode_fill_newvalue_regno(Packet *packet)
{
int i, use_regidx, offset, def_idx, dst_idx;
-uint16_t def_opcode, use_opcode;
-char *dststr;
for (i = 1; i < packet->num_insns; i++) {
if (GET_ATTRIB(packet->insn[i].opcode, A_DOTNEWVALUE) &&
!GET_ATTRIB(packet->insn[i].opcode, A_EXTENSION)) {
-use_opcode = packet->insn[i].opcode;
-/* It's a store, so we're adjusting the Nt field */
-if (GET_ATTRIB(use_opcode, A_STORE)) {
-use_regidx = strchr(opcode_reginfo[use_opcode], 't') -
-opcode_reginfo[use_opcode];
-} else {/* It's a Jump, so we're adjusting the Ns field */
-use_regidx = strchr(opcode_reginfo[use_opcode], 's') -
-opcode_reginfo[use_opcode];
-}
-g_assert(packet->insn[i].new_read_idx != -1 &&
- packet->insn[i].new_read_idx == use_regidx);
+g_assert(packet->insn[i].new_read_idx != -1);
+use_regidx = packet->insn[i].new_read_idx;
/*
* What's encoded at the N-field is the offset to who's producing
@@ -153,39 +142,9 @@ decode_fill_newvalue_regno(Packet *packet)
*/
g_assert(!((def_idx < 0) || (def_idx > (packet->num_insns - 1;
-/*
- * packet->insn[def_idx] is the producer
- * Figure out which type of destination it produces
- * and the corresponding index in the reginfo
- */
-def_opcode = packet->insn[def_idx].opcode;
-dststr = strstr(opcode_wregs[def_opcode], "Rd");
-if (dststr) {
-dststr = strchr(opcode_reginfo[def_opcode], 'd');
-} else {
-dststr = strstr(opcode_wregs[def_opcode], "Rx");
-if (dststr) {
-dststr = strchr(opcode_reginfo[def_opcode], 'x');
-} else {
-dststr = strstr(opcode_wregs[def_opcode], "Re");
-if (dststr) {
-dststr = strchr(opcode_reginfo[def_opcode], 'e');
-} else {
-dststr = strstr(opcode_wregs[def_opcode], "Ry");
-if (dststr) {
-dststr = strchr(opcode_reginfo[def_opcode], 'y');
-} else {
-g_assert_not_reached();
-}
-}
-}
-}
-g_assert(dststr != NULL);
-
/* Now patch up the consumer with the register number */
-dst_idx = dststr - opcode_reginfo[def_opcode];
-g_assert(packet->insn[def_idx].dest_idx != -1 &&
- packet->insn[def_idx].dest_idx == dst_idx);
+g_assert(packet->insn[def_idx].dest_idx != -1);
+dst_idx = packet->insn[def_idx].dest_idx;
packet->insn[i].regno[use_regidx] =
packet->insn[def_idx].regno[dst_idx];
/*
@@ -366,11 +325,7 @@ static void decode_shuffle_for_execution(Packet *packet)
for (flag = false, i = 0; i < last_insn + 1; i++) {
int opcode = packet->insn[i].opcode;
-g_assert(packet->insn[i].has_pred_dest ==
- (strstr(opcode_wregs[opcode], "Pd4") ||
- strstr(opcode_wregs[opcode], "Pe4")));
-if ((strstr(opcode_wregs[opcode], "Pd4") ||
- strstr(opcode_wregs[opcode], "Pe4")) &&
+if (packet->insn[i].has_pred_dest &&
GET_ATTRIB(opcode, A_STORE) == 0) {
/* This should be a compare (not a store conditional) */
if (flag) {
diff --git a/target/hexagon/mmvec/decode_ext_mmvec.c
b/target/hexagon/mmvec/decode_ext_mmvec.c
index c1320406df..f850d0154d 100644
--- a/target/hexagon/mmvec/decode_ext_mmvec.c
+++ b/target/hexagon/mmvec/decode_ext_mmvec.c
@@ -28,21 +28,15 @@ check_new_value(Packet *pkt)
{
/* .new value for a MMVector store */
int i, j;
-const char *regin
[PULL 08/15] Hexagon (target/hexagon) Mark new_read_idx in trans functions
From: Taylor Simpson
Check that the value matches opcode_reginfo
Signed-off-by: Taylor Simpson
Reviewed-by: Brian Cain
Message-Id: <20240307032327.4799-3-ltaylorsimp...@gmail.com>
Signed-off-by: Brian Cain
---
target/hexagon/decode.c | 2 ++
target/hexagon/gen_trans_funcs.py | 15 ++-
target/hexagon/insn.h | 3 ++-
target/hexagon/mmvec/decode_ext_mmvec.c | 2 ++
4 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/target/hexagon/decode.c b/target/hexagon/decode.c
index a40210ca1e..4595e30384 100644
--- a/target/hexagon/decode.c
+++ b/target/hexagon/decode.c
@@ -131,6 +131,8 @@ decode_fill_newvalue_regno(Packet *packet)
use_regidx = strchr(opcode_reginfo[use_opcode], 's') -
opcode_reginfo[use_opcode];
}
+g_assert(packet->insn[i].new_read_idx != -1 &&
+ packet->insn[i].new_read_idx == use_regidx);
/*
* What's encoded at the N-field is the offset to who's producing
diff --git a/target/hexagon/gen_trans_funcs.py
b/target/hexagon/gen_trans_funcs.py
index 53e844a44b..8acecdb993 100755
--- a/target/hexagon/gen_trans_funcs.py
+++ b/target/hexagon/gen_trans_funcs.py
@@ -68,6 +68,7 @@ def mark_which_imm_extended(f, tag):
## insn->regno[0] = args->Rd;
## insn->regno[1] = args->Rs;
## insn->regno[2] = args->Rt;
+## insn->new_read_idx = -1;
## return true;
## }
##
@@ -84,14 +85,14 @@ def gen_trans_funcs(f):
insn->opcode = {tag};
"""))
-regno = 0
-for reg in regs:
-reg_type = reg[0]
-reg_id = reg[1]
+new_read_idx = -1
+for regno, (reg_type, reg_id, *_) in enumerate(regs):
+reg = hex_common.get_register(tag, reg_type, reg_id)
f.write(code_fmt(f"""\
insn->regno[{regno}] = args->{reg_type}{reg_id};
"""))
-regno += 1
+if reg.is_read() and reg.is_new():
+new_read_idx = regno
if len(imms) != 0:
mark_which_imm_extended(f, tag)
@@ -112,6 +113,9 @@ def gen_trans_funcs(f):
insn->immed[{immno}] = args->{imm_type}{imm_letter};
"""))
+f.write(code_fmt(f"""\
+insn->new_read_idx = {new_read_idx};
+"""))
f.write(textwrap.dedent(f"""\
return true;
{close_curly}
@@ -120,5 +124,6 @@ def gen_trans_funcs(f):
if __name__ == "__main__":
hex_common.read_semantics_file(sys.argv[1])
+hex_common.init_registers()
with open(sys.argv[2], "w") as f:
gen_trans_funcs(f)
diff --git a/target/hexagon/insn.h b/target/hexagon/insn.h
index 3e7a22c91e..36502bf056 100644
--- a/target/hexagon/insn.h
+++ b/target/hexagon/insn.h
@@ -1,5 +1,5 @@
/*
- * Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights
Reserved.
+ * Copyright(c) 2019-2024 Qualcomm Innovation Center, Inc. All Rights
Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -39,6 +39,7 @@ struct Instruction {
uint32_t slot:3;
uint32_t which_extended:1;/* If has an extender, which immediate */
uint32_t new_value_producer_slot:4;
+int32_t new_read_idx;
bool part1; /*
* cmp-jumps are split into two insns.
diff --git a/target/hexagon/mmvec/decode_ext_mmvec.c
b/target/hexagon/mmvec/decode_ext_mmvec.c
index 202d84c7c0..e9007f5d71 100644
--- a/target/hexagon/mmvec/decode_ext_mmvec.c
+++ b/target/hexagon/mmvec/decode_ext_mmvec.c
@@ -41,6 +41,8 @@ check_new_value(Packet *pkt)
GET_ATTRIB(use_opcode, A_STORE)) {
int use_regidx = strchr(opcode_reginfo[use_opcode], 's') -
opcode_reginfo[use_opcode];
+g_assert(pkt->insn[i].new_read_idx != -1 &&
+ pkt->insn[i].new_read_idx == use_regidx);
/*
* What's encoded at the N-field is the offset to who's producing
* the value.
--
2.25.1
[PULL 00/15] Hexagon: simplify gen for packets w/o read-after-write
The following changes since commit 248f6f62df073a3b4158fd0093863ab885feabb5: Merge tag 'pull-axp-20240504' of https://gitlab.com/rth7680/qemu into staging (2024-05-04 08:39:46 -0700) are available in the Git repository at: https://github.com/quic/qemu tags/pull-hex-20240505 for you to fetch changes up to a4696661491cac8c1c08e7d482d751f808ce3143: Hexagon (target/hexagon) Remove hex_common.read_attribs_file (2024-05-05 16:22:07 -0700) Short-circuit for packets w/o read-after-write Cleanup unused code in gen_*.py scripts Taylor Simpson (15): Hexagon (target/hexagon) Analyze reads before writes Hexagon (target/hexagon) Enable more short-circuit packets (scalar core) Hexagon (target/hexagon) Enable more short-circuit packets (HVX) Hexagon (target/hexagon) Pass P0 explicitly to helpers that need it Hexagon (target/hexagon) Pass SP explicitly to helpers that need it Hexagon (target/hexagon) Only pass env to generated helper when needed Hexagon (target/hexagon) Add is_old/is_new to Register class Hexagon (target/hexagon) Mark new_read_idx in trans functions Hexagon (target/hexagon) Mark dest_idx in trans functions Hexagon (target/hexagon) Mark has_pred_dest in trans functions Hexagon (tests/tcg/hexagon) Test HVX .new read from high half of pair Hexagon (target/hexagon) Remove uses of op_regs_generated.h.inc Hexagon (target/hexagon) Remove gen_op_regs.py Hexagon (target/hexagon) Remove gen_shortcode.py Hexagon (target/hexagon) Remove hex_common.read_attribs_file target/hexagon/README | 11 +- target/hexagon/attribs_def.h.inc| 3 +- target/hexagon/decode.c | 48 +--- target/hexagon/gen_analyze_funcs.py | 70 ++-- target/hexagon/gen_helper_funcs.py | 21 +--- target/hexagon/gen_helper_protos.py | 31 ++ target/hexagon/gen_idef_parser_funcs.py | 5 +- target/hexagon/gen_op_attribs.py| 5 +- target/hexagon/gen_op_regs.py | 125 - target/hexagon/gen_opcodes_def.py | 4 +- target/hexagon/gen_printinsn.py | 5 +- target/hexagon/gen_shortcode.py | 63 --- target/hexagon/gen_tcg.h| 5 +- target/hexagon/gen_tcg_func_table.py| 5 +- target/hexagon/gen_tcg_funcs.py | 21 +--- target/hexagon/gen_trans_funcs.py | 26 - target/hexagon/hex_common.py| 189 ++-- target/hexagon/insn.h | 5 +- target/hexagon/macros.h | 6 +- target/hexagon/meson.build | 55 +++--- target/hexagon/mmvec/decode_ext_mmvec.c | 30 ++--- target/hexagon/opcodes.c| 35 -- target/hexagon/opcodes.h| 4 - target/hexagon/translate.c | 77 ++--- target/hexagon/translate.h | 119 tests/tcg/hexagon/hvx_misc.c| 16 ++- 26 files changed, 374 insertions(+), 610 deletions(-) delete mode 100755 target/hexagon/gen_op_regs.py delete mode 100755 target/hexagon/gen_shortcode.py
[PULL 09/15] Hexagon (target/hexagon) Mark dest_idx in trans functions
From: Taylor Simpson
Check that the value matches opcode_reginfo/opcode_wregs
Signed-off-by: Taylor Simpson
Reviewed-by: Brian Cain
Message-Id: <20240307032327.4799-4-ltaylorsimp...@gmail.com>
Signed-off-by: Brian Cain
---
target/hexagon/decode.c | 2 ++
target/hexagon/gen_trans_funcs.py | 6 ++
target/hexagon/insn.h | 1 +
target/hexagon/mmvec/decode_ext_mmvec.c | 2 ++
4 files changed, 11 insertions(+)
diff --git a/target/hexagon/decode.c b/target/hexagon/decode.c
index 4595e30384..a4d8500fea 100644
--- a/target/hexagon/decode.c
+++ b/target/hexagon/decode.c
@@ -184,6 +184,8 @@ decode_fill_newvalue_regno(Packet *packet)
/* Now patch up the consumer with the register number */
dst_idx = dststr - opcode_reginfo[def_opcode];
+g_assert(packet->insn[def_idx].dest_idx != -1 &&
+ packet->insn[def_idx].dest_idx == dst_idx);
packet->insn[i].regno[use_regidx] =
packet->insn[def_idx].regno[dst_idx];
/*
diff --git a/target/hexagon/gen_trans_funcs.py
b/target/hexagon/gen_trans_funcs.py
index 8acecdb993..1201172dda 100755
--- a/target/hexagon/gen_trans_funcs.py
+++ b/target/hexagon/gen_trans_funcs.py
@@ -69,6 +69,7 @@ def mark_which_imm_extended(f, tag):
## insn->regno[1] = args->Rs;
## insn->regno[2] = args->Rt;
## insn->new_read_idx = -1;
+## insn->dest_idx = 0;
## return true;
## }
##
@@ -86,6 +87,7 @@ def gen_trans_funcs(f):
"""))
new_read_idx = -1
+dest_idx = -1
for regno, (reg_type, reg_id, *_) in enumerate(regs):
reg = hex_common.get_register(tag, reg_type, reg_id)
f.write(code_fmt(f"""\
@@ -93,6 +95,9 @@ def gen_trans_funcs(f):
"""))
if reg.is_read() and reg.is_new():
new_read_idx = regno
+# dest_idx should be the first destination, so check for -1
+if reg.is_written() and dest_idx == -1:
+dest_idx = regno
if len(imms) != 0:
mark_which_imm_extended(f, tag)
@@ -115,6 +120,7 @@ def gen_trans_funcs(f):
f.write(code_fmt(f"""\
insn->new_read_idx = {new_read_idx};
+insn->dest_idx = {dest_idx};
"""))
f.write(textwrap.dedent(f"""\
return true;
diff --git a/target/hexagon/insn.h b/target/hexagon/insn.h
index 36502bf056..a770379958 100644
--- a/target/hexagon/insn.h
+++ b/target/hexagon/insn.h
@@ -40,6 +40,7 @@ struct Instruction {
uint32_t which_extended:1;/* If has an extender, which immediate */
uint32_t new_value_producer_slot:4;
int32_t new_read_idx;
+int32_t dest_idx;
bool part1; /*
* cmp-jumps are split into two insns.
diff --git a/target/hexagon/mmvec/decode_ext_mmvec.c
b/target/hexagon/mmvec/decode_ext_mmvec.c
index e9007f5d71..c1320406df 100644
--- a/target/hexagon/mmvec/decode_ext_mmvec.c
+++ b/target/hexagon/mmvec/decode_ext_mmvec.c
@@ -86,6 +86,8 @@ check_new_value(Packet *pkt)
/* still not there, we have a bad packet */
g_assert_not_reached();
}
+g_assert(pkt->insn[def_idx].dest_idx != -1 &&
+ pkt->insn[def_idx].dest_idx == dststr - reginfo);
int def_regnum = pkt->insn[def_idx].regno[dststr - reginfo];
/* Now patch up the consumer with the register number */
pkt->insn[i].regno[use_regidx] = def_regnum ^ def_oreg;
--
2.25.1
[PULL 03/15] Hexagon (target/hexagon) Enable more short-circuit packets (HVX)
From: Taylor Simpson
Look for read-after-write instead of overlap of reads and writes
HVX instructions with helpers have pass-by-reference semantics, so
we check for overlaps of reads and writes within the same instruction.
Signed-off-by: Taylor Simpson
Reviewed-by: Brian Cain
Message-Id: <20240201103340.119081-4-ltaylorsimp...@gmail.com>
Signed-off-by: Brian Cain
---
target/hexagon/gen_analyze_funcs.py | 19 ---
target/hexagon/hex_common.py| 45 ++-
target/hexagon/translate.c | 58 ++-
target/hexagon/translate.h | 88 +++--
4 files changed, 115 insertions(+), 95 deletions(-)
diff --git a/target/hexagon/gen_analyze_funcs.py
b/target/hexagon/gen_analyze_funcs.py
index 890e6a3a95..81e1d9cfa3 100755
--- a/target/hexagon/gen_analyze_funcs.py
+++ b/target/hexagon/gen_analyze_funcs.py
@@ -43,6 +43,16 @@ def gen_analyze_func(f, tag, regs, imms):
f.write("{\n")
f.write("Insn *insn G_GNUC_UNUSED = ctx->insn;\n")
+if (hex_common.is_hvx_insn(tag)):
+if hex_common.has_hvx_helper(tag):
+f.write(
+"const bool G_GNUC_UNUSED insn_has_hvx_helper = true;\n"
+)
+f.write("ctx_start_hvx_insn(ctx);\n")
+else:
+f.write(
+"const bool G_GNUC_UNUSED insn_has_hvx_helper = false;\n"
+)
## Declare all the registers
for regno, register in enumerate(regs):
@@ -64,15 +74,6 @@ def gen_analyze_func(f, tag, regs, imms):
if reg.is_written():
reg.analyze_write(f, tag, regno)
-has_generated_helper = not hex_common.skip_qemu_helper(
-tag
-) and not hex_common.is_idef_parser_enabled(tag)
-
-## Mark HVX instructions with generated helpers
-if (has_generated_helper and
-"A_CVI" in hex_common.attribdict[tag]):
-f.write("ctx->has_hvx_helper = true;\n")
-
f.write("}\n\n")
diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
index 33801e4bd7..9e7f613e3c 100755
--- a/target/hexagon/hex_common.py
+++ b/target/hexagon/hex_common.py
@@ -241,6 +241,16 @@ def is_idef_parser_enabled(tag):
return tag in idef_parser_enabled
+def is_hvx_insn(tag):
+return "A_CVI" in attribdict[tag]
+
+
+def has_hvx_helper(tag):
+return (is_hvx_insn(tag) and
+not skip_qemu_helper(tag) and
+not is_idef_parser_enabled(tag))
+
+
def imm_name(immlett):
return f"{immlett}iV"
@@ -704,7 +714,8 @@ def analyze_write(self, f, tag, regno):
newv = hvx_newv(tag)
predicated = "true" if is_predicated(tag) else "false"
f.write(code_fmt(f"""\
-ctx_log_vreg_write(ctx, {self.reg_num}, {newv}, {predicated});
+ctx_log_vreg_write(ctx, {self.reg_num}, {newv}, {predicated},
+ insn_has_hvx_helper);
"""))
class VRegSource(Register, Hvx, OldSource):
@@ -724,7 +735,7 @@ def helper_hvx_desc(self, f):
"""))
def analyze_read(self, f, regno):
f.write(code_fmt(f"""\
-ctx_log_vreg_read(ctx, {self.reg_num});
+ctx_log_vreg_read(ctx, {self.reg_num}, insn_has_hvx_helper);
"""))
class VRegNewSource(Register, Hvx, NewSource):
@@ -741,7 +752,7 @@ def helper_hvx_desc(self, f):
"""))
def analyze_read(self, f, regno):
f.write(code_fmt(f"""\
-ctx_log_vreg_read_new(ctx, {self.reg_num});
+ctx_log_vreg_read_new(ctx, {self.reg_num}, insn_has_hvx_helper);
"""))
class VRegReadWrite(Register, Hvx, ReadWrite):
@@ -767,13 +778,14 @@ def helper_hvx_desc(self, f):
"""))
def analyze_read(self, f, regno):
f.write(code_fmt(f"""\
-ctx_log_vreg_read(ctx, {self.reg_num});
+ctx_log_vreg_read(ctx, {self.reg_num}, insn_has_hvx_helper);
"""))
def analyze_write(self, f, tag, regno):
newv = hvx_newv(tag)
predicated = "true" if is_predicated(tag) else "false"
f.write(code_fmt(f"""\
-ctx_log_vreg_write(ctx, {self.reg_num}, {newv}, {predicated});
+ctx_log_vreg_write(ctx, {self.reg_num}, {newv}, {predicated},
+ insn_has_hvx_helper);
"""))
class VRegTmp(Register, Hvx, ReadWrite):
@@ -801,13 +813,14 @@ def helper_hvx_desc(self, f):
"""))
def analyze_read(self, f, regno):
f.write(code_fmt(f"""\
-ctx_log_vreg_read(ctx, {self.reg_num});
+ctx_log_vreg_read(
[PULL 01/15] Hexagon (target/hexagon) Analyze reads before writes
From: Taylor Simpson
We divide gen_analyze_funcs.py into 3 phases
Declare the operands
Analyze the register reads
Analyze the register writes
We also create special versions of ctx_log_*_read for new operands
Check that the operand is written before the read
This is a precursor to improving the analysis for short-circuiting
the packet semantics in a subsequent commit
Signed-off-by: Taylor Simpson
Reviewed-by: Brian Cain
Message-Id: <20240201103340.119081-2-ltaylorsimp...@gmail.com>
Signed-off-by: Brian Cain
---
target/hexagon/README | 9 +++--
target/hexagon/gen_analyze_funcs.py | 34 ++--
target/hexagon/hex_common.py| 63 +++--
target/hexagon/translate.h | 26 +++-
4 files changed, 83 insertions(+), 49 deletions(-)
diff --git a/target/hexagon/README b/target/hexagon/README
index 746ebec378..c1d8c8d0ab 100644
--- a/target/hexagon/README
+++ b/target/hexagon/README
@@ -183,10 +183,11 @@ when the override is present.
}
We also generate an analyze_ function for each instruction. Currently,
-these functions record the writes to registers by calling ctx_log_*. During
-gen_start_packet, we invoke the analyze_ function for each instruction in
-the packet, and we mark the implicit writes. After the analysis is performed,
-we initialize the result register for each of the predicated assignments.
+these functions record the reads and writes to registers by calling ctx_log_*.
+During gen_start_packet, we invoke the analyze_ function for each
instruction in
+the packet, and we mark the implicit writes. The analysis determines if the
packet
+semantics can be short-circuited. If not, we initialize the result register
for each
+of the predicated assignments.
In addition to instruction semantics, we use a generator to create the decode
tree. This generation is a four step process.
diff --git a/target/hexagon/gen_analyze_funcs.py
b/target/hexagon/gen_analyze_funcs.py
index a9af666cef..890e6a3a95 100755
--- a/target/hexagon/gen_analyze_funcs.py
+++ b/target/hexagon/gen_analyze_funcs.py
@@ -1,7 +1,7 @@
#!/usr/bin/env python3
##
-## Copyright(c) 2022-2023 Qualcomm Innovation Center, Inc. All Rights
Reserved.
+## Copyright(c) 2022-2024 Qualcomm Innovation Center, Inc. All Rights
Reserved.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
@@ -44,15 +44,25 @@ def gen_analyze_func(f, tag, regs, imms):
f.write("Insn *insn G_GNUC_UNUSED = ctx->insn;\n")
-i = 0
-## Analyze all the registers
-for regtype, regid in regs:
-reg = hex_common.get_register(tag, regtype, regid)
+## Declare all the registers
+for regno, register in enumerate(regs):
+reg_type, reg_id = register
+reg = hex_common.get_register(tag, reg_type, reg_id)
+reg.decl_reg_num(f, regno)
+
+## Analyze the register reads
+for regno, register in enumerate(regs):
+reg_type, reg_id = register
+reg = hex_common.get_register(tag, reg_type, reg_id)
+if reg.is_read():
+reg.analyze_read(f, regno)
+
+## Analyze the register writes
+for regno, register in enumerate(regs):
+reg_type, reg_id = register
+reg = hex_common.get_register(tag, reg_type, reg_id)
if reg.is_written():
-reg.analyze_write(f, tag, i)
-else:
-reg.analyze_read(f, i)
-i += 1
+reg.analyze_write(f, tag, regno)
has_generated_helper = not hex_common.skip_qemu_helper(
tag
@@ -89,13 +99,13 @@ def main():
tagimms = hex_common.get_tagimms()
with open(sys.argv[-1], "w") as f:
-f.write("#ifndef HEXAGON_TCG_FUNCS_H\n")
-f.write("#define HEXAGON_TCG_FUNCS_H\n\n")
+f.write("#ifndef HEXAGON_ANALYZE_FUNCS_C_INC\n")
+f.write("#define HEXAGON_ANALYZE_FUNCS_C_INC\n\n")
for tag in hex_common.tags:
gen_analyze_func(f, tag, tagregs[tag], tagimms[tag])
-f.write("#endif/* HEXAGON_TCG_FUNCS_H */\n")
+f.write("#endif/* HEXAGON_ANALYZE_FUNCS_C_INC */\n")
if __name__ == "__main__":
diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
index 195620c7ec..33801e4bd7 100755
--- a/target/hexagon/hex_common.py
+++ b/target/hexagon/hex_common.py
@@ -1,7 +1,7 @@
#!/usr/bin/env python3
##
-## Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights
Reserved.
+## Copyright(c) 2019-2024 Qualcomm Innovation Center, Inc. All Rights
Reserved.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
@@ -425,7 +425,6 @@ def log_write(self, f, tag):
gen_log_reg_writ
RE: [PATCH v3] Hexagon: add PC alignment check and exception
> -Original Message-
> From: Richard Henderson
> Sent: Tuesday, April 30, 2024 10:53 AM
> To: Matheus Bernardino (QUIC) ; qemu-
> de...@nongnu.org
> Cc: Brian Cain ; Sid Manning ;
> a...@rev.ng; a...@rev.ng; ltaylorsimp...@gmail.com; Laurent Vivier
>
> Subject: Re: [PATCH v3] Hexagon: add PC alignment check and exception
>
> WARNING: This email originated from outside of Qualcomm. Please be wary of
> any links or attachments, and do not enable macros.
>
> On 4/30/24 07:25, Matheus Tavares Bernardino wrote:
> > +void test_multi_cof(void)
> > +{
> > +asm volatile(
> > +"p0 = cmp.eq(r0, r0)\n"
> > +"{\n"
> > +"if (p0) jump test_multi_cof_unaligned\n"
> > +"jump 1f\n"
> > +"}\n"
> > +"1: nop\n"
> > +: : : "p0");
> > +}
>
> I will say you could just add the label to the end of the asm here, like
>
> .byte 0
> test_multi_cof_unaligned:
>
> rather than use a separate source file.
Agreed: that would simplify this test case definition and the patch a bit.
-Brian
RE: [PATCH] Hexagon: add PC alignment check and exception
> -Original Message-
> From: Matheus Bernardino (QUIC)
> Sent: Friday, April 26, 2024 1:16 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Sid Manning ;
> a...@rev.ng; a...@rev.ng; ltaylorsimp...@gmail.com
> Subject: [PATCH] Hexagon: add PC alignment check and exception
>
> The Hexagon Programmer's Reference Manual says that the exception 0x1e
> should be raised upon an unaligned program counter. Let's implement that
> and also add tests for both the most common case as well as packets with
> multiple change-of-flow instructions.
>
> Signed-off-by: Matheus Tavares Bernardino
Reviewed-by: Brian Cain
> ---
> target/hexagon/cpu_bits.h | 1 +
> target/hexagon/translate.h | 2 ++
> target/hexagon/genptr.c| 21 -
> target/hexagon/translate.c | 2 +-
> tests/tcg/hexagon/Makefile.target | 13 +
> tests/tcg/hexagon/unaligned_pc.S | 10 ++
> tests/tcg/hexagon/unaligned_pc_multi_cof.S | 13 +
> 7 files changed, 56 insertions(+), 6 deletions(-)
> create mode 100644 tests/tcg/hexagon/unaligned_pc.S
> create mode 100644 tests/tcg/hexagon/unaligned_pc_multi_cof.S
>
> diff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h
> index 96fef71729..d6900c8bda 100644
> --- a/target/hexagon/cpu_bits.h
> +++ b/target/hexagon/cpu_bits.h
> @@ -23,6 +23,7 @@
> #define HEX_EXCP_FETCH_NO_UPAGE 0x012
> #define HEX_EXCP_INVALID_PACKET 0x015
> #define HEX_EXCP_INVALID_OPCODE 0x015
> +#define HEX_EXCP_PC_NOT_ALIGNED 0x01e
> #define HEX_EXCP_PRIV_NO_UREAD 0x024
> #define HEX_EXCP_PRIV_NO_UWRITE 0x025
>
> diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h
> index 4dd59c6726..daf11eb584 100644
> --- a/target/hexagon/translate.h
> +++ b/target/hexagon/translate.h
> @@ -75,6 +75,8 @@ typedef struct DisasContext {
> TCGv dczero_addr;
> } DisasContext;
>
> +void gen_exception_end_tb(DisasContext *ctx, int excp);
> +
> static inline void ctx_log_pred_write(DisasContext *ctx, int pnum)
> {
> if (!test_bit(pnum, ctx->pregs_written)) {
> diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
> index dbae6c570a..c96edd9379 100644
> --- a/target/hexagon/genptr.c
> +++ b/target/hexagon/genptr.c
> @@ -473,6 +473,7 @@ static void gen_write_new_pc_addr(DisasContext
> *ctx, TCGv addr,
>TCGCond cond, TCGv pred)
> {
> TCGLabel *pred_false = NULL;
> +TCGLabel *branch_taken = NULL;
> if (cond != TCG_COND_ALWAYS) {
> pred_false = gen_new_label();
> tcg_gen_brcondi_tl(cond, pred, 0, pred_false);
> @@ -480,12 +481,22 @@ static void gen_write_new_pc_addr(DisasContext
> *ctx, TCGv addr,
>
> if (ctx->pkt->pkt_has_multi_cof) {
> /* If there are multiple branches in a packet, ignore the second one
> */
> -tcg_gen_movcond_tl(TCG_COND_NE, hex_gpr[HEX_REG_PC],
> - ctx->branch_taken, tcg_constant_tl(0),
> - hex_gpr[HEX_REG_PC], addr);
> +branch_taken = gen_new_label();
> +tcg_gen_brcondi_tl(TCG_COND_NE, ctx->branch_taken, 0,
> branch_taken);
> tcg_gen_movi_tl(ctx->branch_taken, 1);
> -} else {
> -tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], addr);
> +}
> +
> +TCGLabel *pc_aligned = gen_new_label();
> +TCGv pc_remainder = tcg_temp_new();
> +tcg_gen_andi_tl(pc_remainder, addr, PCALIGN_MASK);
> +tcg_gen_brcondi_tl(TCG_COND_EQ, pc_remainder, 0, pc_aligned);
> +gen_exception_end_tb(ctx, HEX_EXCP_PC_NOT_ALIGNED);
> +gen_set_label(pc_aligned);
> +
> +tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], addr);
> +
> +if (ctx->pkt->pkt_has_multi_cof) {
> +gen_set_label(branch_taken);
> }
>
> if (cond != TCG_COND_ALWAYS) {
> diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
> index f163eefe97..e6ee63a53e 100644
> --- a/target/hexagon/translate.c
> +++ b/target/hexagon/translate.c
> @@ -185,7 +185,7 @@ static void gen_end_tb(DisasContext *ctx)
> ctx->base.is_jmp = DISAS_NORETURN;
> }
>
> -static void gen_exception_end_tb(DisasContext *ctx, int excp)
> +void gen_exception_end_tb(DisasContext *ctx, int excp)
> {
> gen_exec_counters(ctx);
> tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->next_PC);
> diff --git a/tests/tcg/hexagon/Makefile.target
> b/tests/tcg/hexagon/Makefile.target
> index f839b2c0d5..02d7fff34c 100644
> --- a/tests/tcg/hexagon/Makefile.target
> +++ b/tests/tcg/hexagon/Makefile.target
> @@ -51,6 +51,19 @@ HEX_TESTS += scatter_gat
RE: [PATCH v2 1/3] Hexagon (target/hexagon) Analyze reads before writes
> -Original Message-
> From: Taylor Simpson
> Sent: Thursday, February 1, 2024 4:34 AM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ;
> Marco Liebel (QUIC) ;
> richard.hender...@linaro.org; phi...@linaro.org; a...@rev.ng; a...@rev.ng;
> ltaylorsimp...@gmail.com
> Subject: [PATCH v2 1/3] Hexagon (target/hexagon) Analyze reads before
> writes
>
> WARNING: This email originated from outside of Qualcomm. Please be wary
> of any links or attachments, and do not enable macros.
>
> We divide gen_analyze_funcs.py into 3 phases
> Declare the operands
> Analyze the register reads
> Analyze the register writes
>
> We also create special versions of ctx_log_*_read for new operands
> Check that the operand is written before the read
>
> This is a precursor to improving the analysis for short-circuiting
> the packet semantics in a subsequent commit
>
> Signed-off-by: Taylor Simpson
> ---
> target/hexagon/translate.h | 26 +++-
> target/hexagon/README | 9 +++--
> target/hexagon/gen_analyze_funcs.py | 34 ++--
> target/hexagon/hex_common.py| 63 +++--
> 4 files changed, 83 insertions(+), 49 deletions(-)
>
> diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h
> index 4dd59c6726..f06d71fc53 100644
> --- a/target/hexagon/translate.h
> +++ b/target/hexagon/translate.h
> @@ -1,5 +1,5 @@
> /*
> - * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights
> Reserved.
> + * Copyright(c) 2019-2024 Qualcomm Innovation Center, Inc. All Rights
> Reserved.
> *
> * This program is free software; you can redistribute it and/or modify
> * it under the terms of the GNU General Public License as published by
> @@ -75,6 +75,8 @@ typedef struct DisasContext {
> TCGv dczero_addr;
> } DisasContext;
>
> +bool is_gather_store_insn(DisasContext *ctx);
> +
> static inline void ctx_log_pred_write(DisasContext *ctx, int pnum)
> {
> if (!test_bit(pnum, ctx->pregs_written)) {
> @@ -89,6 +91,12 @@ static inline void ctx_log_pred_read(DisasContext *ctx,
> int pnum)
> set_bit(pnum, ctx->pregs_read);
> }
>
> +static inline void ctx_log_pred_read_new(DisasContext *ctx, int pnum)
> +{
> +g_assert(test_bit(pnum, ctx->pregs_written));
> +set_bit(pnum, ctx->pregs_read);
> +}
> +
> static inline void ctx_log_reg_write(DisasContext *ctx, int rnum,
> bool is_predicated)
> {
> @@ -120,6 +128,12 @@ static inline void ctx_log_reg_read(DisasContext
> *ctx, int rnum)
> set_bit(rnum, ctx->regs_read);
> }
>
> +static inline void ctx_log_reg_read_new(DisasContext *ctx, int rnum)
> +{
> +g_assert(test_bit(rnum, ctx->regs_written));
> +set_bit(rnum, ctx->regs_read);
> +}
> +
> static inline void ctx_log_reg_read_pair(DisasContext *ctx, int rnum)
> {
> ctx_log_reg_read(ctx, rnum);
> @@ -171,6 +185,15 @@ static inline void ctx_log_vreg_read(DisasContext
> *ctx, int rnum)
> set_bit(rnum, ctx->vregs_read);
> }
>
> +static inline void ctx_log_vreg_read_new(DisasContext *ctx, int rnum)
> +{
> +g_assert(is_gather_store_insn(ctx) ||
> + test_bit(rnum, ctx->vregs_updated) ||
> + test_bit(rnum, ctx->vregs_select) ||
> + test_bit(rnum, ctx->vregs_updated_tmp));
> +set_bit(rnum, ctx->vregs_read);
> +}
> +
> static inline void ctx_log_vreg_read_pair(DisasContext *ctx, int rnum)
> {
> ctx_log_vreg_read(ctx, rnum ^ 0);
> @@ -205,7 +228,6 @@ extern TCGv hex_vstore_addr[VSTORES_MAX];
> extern TCGv hex_vstore_size[VSTORES_MAX];
> extern TCGv hex_vstore_pending[VSTORES_MAX];
>
> -bool is_gather_store_insn(DisasContext *ctx);
> void process_store(DisasContext *ctx, int slot_num);
>
> FIELD(PROBE_PKT_SCALAR_STORE_S0, MMU_IDX, 0, 2)
> diff --git a/target/hexagon/README b/target/hexagon/README
> index 746ebec378..c1d8c8d0ab 100644
> --- a/target/hexagon/README
> +++ b/target/hexagon/README
> @@ -183,10 +183,11 @@ when the override is present.
> }
>
> We also generate an analyze_ function for each instruction. Currently,
> -these functions record the writes to registers by calling ctx_log_*. During
> -gen_start_packet, we invoke the analyze_ function for each instruction
> in
> -the packet, and we mark the implicit writes. After the analysis is
> performed,
> -we initialize the result register for each of the predicated assignments.
> +these functions record the reads and writes to registers by calling
> ctx_log_*.
> +During gen
RE: [PATCH v2 2/3] Hexagon (target/hexagon) Enable more short-circuit packets (scalar core)
> -Original Message-
> From: Taylor Simpson
> Sent: Thursday, February 1, 2024 4:34 AM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ;
> Marco Liebel (QUIC) ;
> richard.hender...@linaro.org; phi...@linaro.org; a...@rev.ng; a...@rev.ng;
> ltaylorsimp...@gmail.com
> Subject: [PATCH v2 2/3] Hexagon (target/hexagon) Enable more short-circuit
> packets (scalar core)
>
> WARNING: This email originated from outside of Qualcomm. Please be wary
> of any links or attachments, and do not enable macros.
>
> Look for read-after-write instead of overlap of reads and writes
>
> Here is an example with overalp but no read-after-write:
> 0x000200fc: 0x38103876 { R0 = add(R0,R1); R6 = add(R6,R7) }
>
> BEFORE:
> 000200fc
> mov_i32 loc2,$0x0
> mov_i32 loc2,r0
> add_i32 loc3,loc2,r1
> mov_i32 loc2,loc3
> mov_i32 loc4,$0x0
> mov_i32 loc4,r6
> add_i32 loc5,loc4,r7
> mov_i32 loc4,loc5
> mov_i32 r0,loc2
> mov_i32 r6,loc4
>
> AFTER:
> 000200fc
> add_i32 loc2,r0,r1
> mov_i32 r0,loc2
> add_i32 loc3,r6,r7
> mov_i32 r6,loc3
>
> We can also short-circuit packets with .new values by reading from the
> real destination instead of the temporary.
> 0x00020100: 0x78005ff3 { R19 = #0xff
> 0x00020104: 0x2002e204 if (cmp.eq(N19.new,R2)) jump:t PC+8 }
>
> BEFORE:
> 00020100
> mov_i32 pc,$0x20108
> mov_i32 loc8,$0x0
> mov_i32 loc8,$0xff
> setcond_i32 loc10,loc8,r2,eq
> mov_i32 loc6,loc10
> mov_i32 r19,loc8
> add_i32 pkt_cnt,pkt_cnt,$0x2
> add_i32 insn_cnt,insn_cnt,$0x4
> brcond_i32 loc6,$0x0,eq,$L1
> goto_tb $0x0
> mov_i32 pc,$0x20108
> exit_tb $0x7fbb5440
> set_label $L1
> goto_tb $0x1
> exit_tb $0x7fbb5441
> set_label $L0
> exit_tb $0x7fbb5443
>
> AFTER:
> 00020100
> mov_i32 pc,$0x20108
> mov_i32 r19,$0xff
> setcond_i32 loc7,r19,r2,eq
> mov_i32 loc4,loc7
> add_i32 pkt_cnt,pkt_cnt,$0x2
> add_i32 insn_cnt,insn_cnt,$0x4
> brcond_i32 loc4,$0x0,eq,$L1
> goto_tb $0x0
> mov_i32 pc,$0x20108
> exit_tb $0x7f976440
> set_label $L1
> goto_tb $0x1
> exit_tb $0x7f976441
> set_label $L0
> exit_tb $0x7f976443
>
> Signed-off-by: Taylor Simpson
> ---
> target/hexagon/translate.h | 13 +++--
> target/hexagon/translate.c | 21 -
> 2 files changed, 11 insertions(+), 23 deletions(-)
>
> diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h
> index f06d71fc53..d5e7f49ad8 100644
> --- a/target/hexagon/translate.h
> +++ b/target/hexagon/translate.h
> @@ -38,12 +38,10 @@ typedef struct DisasContext {
> int reg_log[REG_WRITES_MAX];
> int reg_log_idx;
> DECLARE_BITMAP(regs_written, TOTAL_PER_THREAD_REGS);
> -DECLARE_BITMAP(regs_read, TOTAL_PER_THREAD_REGS);
> DECLARE_BITMAP(predicated_regs, TOTAL_PER_THREAD_REGS);
> int preg_log[PRED_WRITES_MAX];
> int preg_log_idx;
> DECLARE_BITMAP(pregs_written, NUM_PREGS);
> -DECLARE_BITMAP(pregs_read, NUM_PREGS);
> uint8_t store_width[STORES_MAX];
> bool s1_store_processed;
> int future_vregs_idx;
> @@ -68,6 +66,7 @@ typedef struct DisasContext {
> bool is_tight_loop;
> bool short_circuit;
> bool has_hvx_helper;
> +bool read_after_write;
> TCGv new_value[TOTAL_PER_THREAD_REGS];
> TCGv new_pred_value[NUM_PREGS];
> TCGv pred_written;
> @@ -88,13 +87,14 @@ static inline void ctx_log_pred_write(DisasContext
> *ctx, int pnum)
>
> static inline void ctx_log_pred_read(DisasContext *ctx, int pnum)
> {
> -set_bit(pnum, ctx->pregs_read);
> +if (test_bit(pnum, ctx->pregs_written)) {
> +ctx->read_after_write = true;
> +}
> }
>
> static inline void ctx_log_pred_read_new(DisasContext *ctx, int pnum)
> {
> g_assert(test_bit(pnum, ctx->pregs_written));
> -set_bit(pnum, ctx->pregs_read);
> }
>
> static inline void ctx_log_reg_write(DisasContext *ctx, int rnum,
> @@ -125,13 +125,14 @@ static inline void
> ctx_log_reg_write_pair(DisasContext *ctx, int rnum,
>
> static inline void ctx_log_reg_read(DisasContext *ctx, int rnum)
> {
> -set_bit(rnum, ctx->regs_read);
> +if (test_bit(rnum, ctx->regs_written)) {
> +ctx->read_after_write = true;
> +}
> }
>
> static inline void ctx_log_reg_read_new(DisasContext *ctx, int rnum)
> {
> g_assert(test_bit(rnum, ctx->regs_written));
> -set_bit(rnum, ctx->regs_read);
> }
>
> static inline void ctx_log_reg_read_pair(Disas
RE: [PATCH v2 3/3] Hexagon (target/hexagon) Enable more short-circuit packets (HVX)
> -Original Message-
> From: Taylor Simpson
> Sent: Thursday, February 1, 2024 4:34 AM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ;
> Marco Liebel (QUIC) ;
> richard.hender...@linaro.org; phi...@linaro.org; a...@rev.ng; a...@rev.ng;
> ltaylorsimp...@gmail.com
> Subject: [PATCH v2 3/3] Hexagon (target/hexagon) Enable more short-circuit
> packets (HVX)
>
> WARNING: This email originated from outside of Qualcomm. Please be wary
> of any links or attachments, and do not enable macros.
>
> Look for read-after-write instead of overlap of reads and writes
>
> HVX instructions with helpers have pass-by-reference semantics, so
> we check for overlaps of reads and writes within the same instruction.
>
> Signed-off-by: Taylor Simpson
> ---
> target/hexagon/translate.h | 88 +++--
> target/hexagon/translate.c | 58 ++-
> target/hexagon/gen_analyze_funcs.py | 19 ---
> target/hexagon/hex_common.py| 45 ++-
> 4 files changed, 115 insertions(+), 95 deletions(-)
>
> diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h
> index d5e7f49ad8..00cc2bcd63 100644
> --- a/target/hexagon/translate.h
> +++ b/target/hexagon/translate.h
> @@ -50,23 +50,27 @@ typedef struct DisasContext {
> int tmp_vregs_num[VECTOR_TEMPS_MAX];
> int vreg_log[NUM_VREGS];
> int vreg_log_idx;
> +DECLARE_BITMAP(vregs_written, NUM_VREGS);
> +DECLARE_BITMAP(insn_vregs_written, NUM_VREGS);
> DECLARE_BITMAP(vregs_updated_tmp, NUM_VREGS);
> DECLARE_BITMAP(vregs_updated, NUM_VREGS);
> DECLARE_BITMAP(vregs_select, NUM_VREGS);
> DECLARE_BITMAP(predicated_future_vregs, NUM_VREGS);
> DECLARE_BITMAP(predicated_tmp_vregs, NUM_VREGS);
> -DECLARE_BITMAP(vregs_read, NUM_VREGS);
> +DECLARE_BITMAP(insn_vregs_read, NUM_VREGS);
> int qreg_log[NUM_QREGS];
> int qreg_log_idx;
> -DECLARE_BITMAP(qregs_read, NUM_QREGS);
> +DECLARE_BITMAP(qregs_written, NUM_QREGS);
> +DECLARE_BITMAP(insn_qregs_written, NUM_QREGS);
> +DECLARE_BITMAP(insn_qregs_read, NUM_QREGS);
> bool pre_commit;
> bool need_commit;
> TCGCond branch_cond;
> target_ulong branch_dest;
> bool is_tight_loop;
> bool short_circuit;
> -bool has_hvx_helper;
> bool read_after_write;
> +bool has_hvx_overlap;
> TCGv new_value[TOTAL_PER_THREAD_REGS];
> TCGv new_pred_value[NUM_PREGS];
> TCGv pred_written;
> @@ -146,10 +150,25 @@ intptr_t ctx_future_vreg_off(DisasContext *ctx, int
> regnum,
> intptr_t ctx_tmp_vreg_off(DisasContext *ctx, int regnum,
>int num, bool alloc_ok);
>
> +static inline void ctx_start_hvx_insn(DisasContext *ctx)
> +{
> +bitmap_zero(ctx->insn_vregs_written, NUM_VREGS);
> +bitmap_zero(ctx->insn_vregs_read, NUM_VREGS);
> +bitmap_zero(ctx->insn_qregs_written, NUM_QREGS);
> +bitmap_zero(ctx->insn_qregs_read, NUM_QREGS);
> +}
> +
> static inline void ctx_log_vreg_write(DisasContext *ctx,
>int rnum, VRegWriteType type,
> - bool is_predicated)
> + bool is_predicated, bool has_helper)
> {
> +if (has_helper) {
> +set_bit(rnum, ctx->insn_vregs_written);
> +if (test_bit(rnum, ctx->insn_vregs_read)) {
> +ctx->has_hvx_overlap = true;
> +}
> +}
> +set_bit(rnum, ctx->vregs_written);
> if (type != EXT_TMP) {
> if (!test_bit(rnum, ctx->vregs_updated)) {
> ctx->vreg_log[ctx->vreg_log_idx] = rnum;
> @@ -175,42 +194,77 @@ static inline void ctx_log_vreg_write(DisasContext
> *ctx,
>
> static inline void ctx_log_vreg_write_pair(DisasContext *ctx,
> int rnum, VRegWriteType type,
> - bool is_predicated)
> + bool is_predicated, bool
> has_helper)
> {
> -ctx_log_vreg_write(ctx, rnum ^ 0, type, is_predicated);
> -ctx_log_vreg_write(ctx, rnum ^ 1, type, is_predicated);
> +ctx_log_vreg_write(ctx, rnum ^ 0, type, is_predicated, has_helper);
> +ctx_log_vreg_write(ctx, rnum ^ 1, type, is_predicated, has_helper);
> }
>
> -static inline void ctx_log_vreg_read(DisasContext *ctx, int rnum)
> +static inline void ctx_log_vreg_read(DisasContext *ctx, int rnum,
> + bool has_helper)
> {
> -set_bit(rnum, ctx->vregs_read);
> +if (has_helper) {
&
RE: [PATCH v2 1/9] Hexagon (target/hexagon) Add is_old/is_new to Register class
> -Original Message-
> From: Taylor Simpson
> Sent: Wednesday, March 6, 2024 9:23 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ;
> Marco Liebel (QUIC) ;
> richard.hender...@linaro.org; phi...@linaro.org; a...@rev.ng; a...@rev.ng;
> ltaylorsimp...@gmail.com
> Subject: [PATCH v2 1/9] Hexagon (target/hexagon) Add is_old/is_new to
> Register class
>
> WARNING: This email originated from outside of Qualcomm. Please be wary
> of any links or attachments, and do not enable macros.
>
> Signed-off-by: Taylor Simpson
> Reviewed-by: Philippe Mathieu-Daudé
> ---
Reviewed-by: Brian Cain
> target/hexagon/hex_common.py | 14 +-
> 1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/target/hexagon/hex_common.py
> b/target/hexagon/hex_common.py
> index 195620c7ec..4bacef223f 100755
> --- a/target/hexagon/hex_common.py
> +++ b/target/hexagon/hex_common.py
> @@ -1,7 +1,7 @@
> #!/usr/bin/env python3
>
> ##
> -## Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights
> Reserved.
> +## Copyright(c) 2019-2024 Qualcomm Innovation Center, Inc. All Rights
> Reserved.
> ##
> ## This program is free software; you can redistribute it and/or modify
> ## it under the terms of the GNU General Public License as published by
> @@ -397,10 +397,18 @@ def is_readwrite(self):
> class OldSource(Source):
> def reg_tcg(self):
> return f"{self.regtype}{self.regid}V"
> +def is_old(self):
> +return True
> +def is_new(self):
> +return False
>
> class NewSource(Source):
> def reg_tcg(self):
> return f"{self.regtype}{self.regid}N"
> +def is_old(self):
> +return False
> +def is_new(self):
> +return True
>
> class ReadWrite:
> def reg_tcg(self):
> @@ -413,6 +421,10 @@ def is_read(self):
> return True
> def is_readwrite(self):
> return True
> +def is_old(self):
> +return True
> +def is_new(self):
> +return False
>
> class GprDest(Register, Single, Dest):
> def decl_tcg(self, f, tag, regno):
> --
> 2.34.1
RE: [PATCH v2 2/9] Hexagon (target/hexagon) Mark new_read_idx in trans functions
> -Original Message-
> From: Taylor Simpson
> Sent: Wednesday, March 6, 2024 9:23 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ;
> Marco Liebel (QUIC) ;
> richard.hender...@linaro.org; phi...@linaro.org; a...@rev.ng; a...@rev.ng;
> ltaylorsimp...@gmail.com
> Subject: [PATCH v2 2/9] Hexagon (target/hexagon) Mark new_read_idx in
> trans functions
>
> WARNING: This email originated from outside of Qualcomm. Please be wary
> of any links or attachments, and do not enable macros.
>
> Check that the value matches opcode_reginfo
>
> Signed-off-by: Taylor Simpson
> ---
Reviewed-by: Brian Cain
> target/hexagon/insn.h | 3 ++-
> target/hexagon/decode.c | 2 ++
> target/hexagon/mmvec/decode_ext_mmvec.c | 2 ++
> target/hexagon/gen_trans_funcs.py | 15 ++-
> 4 files changed, 16 insertions(+), 6 deletions(-)
>
> diff --git a/target/hexagon/insn.h b/target/hexagon/insn.h
> index 3e7a22c91e..36502bf056 100644
> --- a/target/hexagon/insn.h
> +++ b/target/hexagon/insn.h
> @@ -1,5 +1,5 @@
> /*
> - * Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights
> Reserved.
> + * Copyright(c) 2019-2024 Qualcomm Innovation Center, Inc. All Rights
> Reserved.
> *
> * This program is free software; you can redistribute it and/or modify
> * it under the terms of the GNU General Public License as published by
> @@ -39,6 +39,7 @@ struct Instruction {
> uint32_t slot:3;
> uint32_t which_extended:1;/* If has an extender, which immediate */
> uint32_t new_value_producer_slot:4;
> +int32_t new_read_idx;
>
> bool part1; /*
>* cmp-jumps are split into two insns.
> diff --git a/target/hexagon/decode.c b/target/hexagon/decode.c
> index a40210ca1e..4595e30384 100644
> --- a/target/hexagon/decode.c
> +++ b/target/hexagon/decode.c
> @@ -131,6 +131,8 @@ decode_fill_newvalue_regno(Packet *packet)
> use_regidx = strchr(opcode_reginfo[use_opcode], 's') -
> opcode_reginfo[use_opcode];
> }
> +g_assert(packet->insn[i].new_read_idx != -1 &&
> + packet->insn[i].new_read_idx == use_regidx);
>
> /*
> * What's encoded at the N-field is the offset to who's producing
> diff --git a/target/hexagon/mmvec/decode_ext_mmvec.c
> b/target/hexagon/mmvec/decode_ext_mmvec.c
> index 202d84c7c0..e9007f5d71 100644
> --- a/target/hexagon/mmvec/decode_ext_mmvec.c
> +++ b/target/hexagon/mmvec/decode_ext_mmvec.c
> @@ -41,6 +41,8 @@ check_new_value(Packet *pkt)
> GET_ATTRIB(use_opcode, A_STORE)) {
> int use_regidx = strchr(opcode_reginfo[use_opcode], 's') -
> opcode_reginfo[use_opcode];
> +g_assert(pkt->insn[i].new_read_idx != -1 &&
> + pkt->insn[i].new_read_idx == use_regidx);
> /*
> * What's encoded at the N-field is the offset to who's producing
> * the value.
> diff --git a/target/hexagon/gen_trans_funcs.py
> b/target/hexagon/gen_trans_funcs.py
> index 53e844a44b..8acecdb993 100755
> --- a/target/hexagon/gen_trans_funcs.py
> +++ b/target/hexagon/gen_trans_funcs.py
> @@ -68,6 +68,7 @@ def mark_which_imm_extended(f, tag):
> ## insn->regno[0] = args->Rd;
> ## insn->regno[1] = args->Rs;
> ## insn->regno[2] = args->Rt;
> +## insn->new_read_idx = -1;
> ## return true;
> ## }
> ##
> @@ -84,14 +85,14 @@ def gen_trans_funcs(f):
> insn->opcode = {tag};
> """))
>
> -regno = 0
> -for reg in regs:
> -reg_type = reg[0]
> -reg_id = reg[1]
> +new_read_idx = -1
> +for regno, (reg_type, reg_id, *_) in enumerate(regs):
> +reg = hex_common.get_register(tag, reg_type, reg_id)
> f.write(code_fmt(f"""\
> insn->regno[{regno}] = args->{reg_type}{reg_id};
> """))
> -regno += 1
> +if reg.is_read() and reg.is_new():
> +new_read_idx = regno
>
> if len(imms) != 0:
> mark_which_imm_extended(f, tag)
> @@ -112,6 +113,9 @@ def gen_trans_funcs(f):
> insn->immed[{immno}] = args->{imm_type}{imm_letter};
> """))
>
> +f.write(code_fmt(f"""\
> +insn->new_read_idx = {new_read_idx};
> +"""))
> f.write(textwrap.dedent(f"""\
> return true;
> {close_curly}
> @@ -120,5 +124,6 @@ def gen_trans_funcs(f):
>
> if __name__ == "__main__":
> hex_common.read_semantics_file(sys.argv[1])
> +hex_common.init_registers()
> with open(sys.argv[2], "w") as f:
> gen_trans_funcs(f)
> --
> 2.34.1
RE: [PATCH v2 3/9] Hexagon (target/hexagon) Mark dest_idx in trans functions
> -Original Message-
> From: Taylor Simpson
> Sent: Wednesday, March 6, 2024 9:23 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ;
> Marco Liebel (QUIC) ;
> richard.hender...@linaro.org; phi...@linaro.org; a...@rev.ng; a...@rev.ng;
> ltaylorsimp...@gmail.com
> Subject: [PATCH v2 3/9] Hexagon (target/hexagon) Mark dest_idx in trans
> functions
>
> WARNING: This email originated from outside of Qualcomm. Please be wary
> of any links or attachments, and do not enable macros.
>
> Check that the value matches opcode_reginfo/opcode_wregs
>
> Signed-off-by: Taylor Simpson
> ---
Reviewed-by: Brian Cain
> target/hexagon/insn.h | 1 +
> target/hexagon/decode.c | 2 ++
> target/hexagon/mmvec/decode_ext_mmvec.c | 2 ++
> target/hexagon/gen_trans_funcs.py | 6 ++
> 4 files changed, 11 insertions(+)
>
> diff --git a/target/hexagon/insn.h b/target/hexagon/insn.h
> index 36502bf056..a770379958 100644
> --- a/target/hexagon/insn.h
> +++ b/target/hexagon/insn.h
> @@ -40,6 +40,7 @@ struct Instruction {
> uint32_t which_extended:1;/* If has an extender, which immediate */
> uint32_t new_value_producer_slot:4;
> int32_t new_read_idx;
> +int32_t dest_idx;
>
> bool part1; /*
>* cmp-jumps are split into two insns.
> diff --git a/target/hexagon/decode.c b/target/hexagon/decode.c
> index 4595e30384..a4d8500fea 100644
> --- a/target/hexagon/decode.c
> +++ b/target/hexagon/decode.c
> @@ -184,6 +184,8 @@ decode_fill_newvalue_regno(Packet *packet)
>
> /* Now patch up the consumer with the register number */
> dst_idx = dststr - opcode_reginfo[def_opcode];
> +g_assert(packet->insn[def_idx].dest_idx != -1 &&
> + packet->insn[def_idx].dest_idx == dst_idx);
> packet->insn[i].regno[use_regidx] =
> packet->insn[def_idx].regno[dst_idx];
> /*
> diff --git a/target/hexagon/mmvec/decode_ext_mmvec.c
> b/target/hexagon/mmvec/decode_ext_mmvec.c
> index e9007f5d71..c1320406df 100644
> --- a/target/hexagon/mmvec/decode_ext_mmvec.c
> +++ b/target/hexagon/mmvec/decode_ext_mmvec.c
> @@ -86,6 +86,8 @@ check_new_value(Packet *pkt)
> /* still not there, we have a bad packet */
> g_assert_not_reached();
> }
> +g_assert(pkt->insn[def_idx].dest_idx != -1 &&
> + pkt->insn[def_idx].dest_idx == dststr - reginfo);
> int def_regnum = pkt->insn[def_idx].regno[dststr - reginfo];
> /* Now patch up the consumer with the register number */
> pkt->insn[i].regno[use_regidx] = def_regnum ^ def_oreg;
> diff --git a/target/hexagon/gen_trans_funcs.py
> b/target/hexagon/gen_trans_funcs.py
> index 8acecdb993..1201172dda 100755
> --- a/target/hexagon/gen_trans_funcs.py
> +++ b/target/hexagon/gen_trans_funcs.py
> @@ -69,6 +69,7 @@ def mark_which_imm_extended(f, tag):
> ## insn->regno[1] = args->Rs;
> ## insn->regno[2] = args->Rt;
> ## insn->new_read_idx = -1;
> +## insn->dest_idx = 0;
> ## return true;
> ## }
> ##
> @@ -86,6 +87,7 @@ def gen_trans_funcs(f):
> """))
>
> new_read_idx = -1
> +dest_idx = -1
> for regno, (reg_type, reg_id, *_) in enumerate(regs):
> reg = hex_common.get_register(tag, reg_type, reg_id)
> f.write(code_fmt(f"""\
> @@ -93,6 +95,9 @@ def gen_trans_funcs(f):
> """))
> if reg.is_read() and reg.is_new():
> new_read_idx = regno
> +# dest_idx should be the first destination, so check for -1
> +if reg.is_written() and dest_idx == -1:
> +dest_idx = regno
>
> if len(imms) != 0:
> mark_which_imm_extended(f, tag)
> @@ -115,6 +120,7 @@ def gen_trans_funcs(f):
>
> f.write(code_fmt(f"""\
> insn->new_read_idx = {new_read_idx};
> +insn->dest_idx = {dest_idx};
> """))
> f.write(textwrap.dedent(f"""\
> return true;
> --
> 2.34.1
RE: [PATCH v2 5/9] Hexagon (tests/tcg/hexagon) Test HVX .new read from high half of pair
> -Original Message-
> From: Taylor Simpson
> Sent: Wednesday, March 6, 2024 9:23 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ;
> Marco Liebel (QUIC) ;
> richard.hender...@linaro.org; phi...@linaro.org; a...@rev.ng; a...@rev.ng;
> ltaylorsimp...@gmail.com
> Subject: [PATCH v2 5/9] Hexagon (tests/tcg/hexagon) Test HVX .new read
> from high half of pair
>
> WARNING: This email originated from outside of Qualcomm. Please be wary
> of any links or attachments, and do not enable macros.
>
> Make sure the decoding of HVX .new is correctly handling this case
>
> Signed-off-by: Taylor Simpson
> ---
Reviewed-by: Brian Cain
> tests/tcg/hexagon/hvx_misc.c | 16 +++-
> 1 file changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/tests/tcg/hexagon/hvx_misc.c b/tests/tcg/hexagon/hvx_misc.c
> index b45170acd1..1fe14b5158 100644
> --- a/tests/tcg/hexagon/hvx_misc.c
> +++ b/tests/tcg/hexagon/hvx_misc.c
> @@ -1,5 +1,5 @@
> /*
> - * Copyright(c) 2021-2023 Qualcomm Innovation Center, Inc. All Rights
> Reserved.
> + * Copyright(c) 2021-2024 Qualcomm Innovation Center, Inc. All Rights
> Reserved.
> *
> * This program is free software; you can redistribute it and/or modify
> * it under the terms of the GNU General Public License as published by
> @@ -231,6 +231,7 @@ static void test_masked_store(bool invert)
> static void test_new_value_store(void)
> {
> void *p0 = buffer0;
> +void *p1 = buffer1;
> void *pout = output;
>
> asm("{\n\t"
> @@ -242,6 +243,19 @@ static void test_new_value_store(void)
> expect[0] = buffer0[0];
>
> check_output_w(__LINE__, 1);
> +
> +/* Test the .new read from the high half of a pair */
> +asm("v7 = vmem(%0 + #0)\n\t"
> +"v12 = vmem(%1 + #0)\n\t"
> +"{\n\t"
> +"v5:4 = vcombine(v12, v7)\n\t"
> +"vmem(%2 + #0) = v5.new\n\t"
> +"}\n\t"
> +: : "r"(p0), "r"(p1), "r"(pout) : "v4", "v5", "v7", "v12", "memory");
> +
> +expect[0] = buffer1[0];
> +
> +check_output_w(__LINE__, 1);
> }
>
> static void test_max_temps()
> --
> 2.34.1
RE: [PATCH v2 4/9] Hexagon (target/hexagon) Mark has_pred_dest in trans functions
> -Original Message-
> From: Taylor Simpson
> Sent: Wednesday, March 6, 2024 9:23 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ;
> Marco Liebel (QUIC) ;
> richard.hender...@linaro.org; phi...@linaro.org; a...@rev.ng; a...@rev.ng;
> ltaylorsimp...@gmail.com
> Subject: [PATCH v2 4/9] Hexagon (target/hexagon) Mark has_pred_dest in
> trans functions
>
> WARNING: This email originated from outside of Qualcomm. Please be wary
> of any links or attachments, and do not enable macros.
>
> Check that the value matches opcode_wregs
>
> Signed-off-by: Taylor Simpson
> ---
Reviewed-by: Brian Cain
> target/hexagon/insn.h | 1 +
> target/hexagon/decode.c | 3 +++
> target/hexagon/gen_trans_funcs.py | 5 +
> 3 files changed, 9 insertions(+)
>
> diff --git a/target/hexagon/insn.h b/target/hexagon/insn.h
> index a770379958..24dcf7fe9f 100644
> --- a/target/hexagon/insn.h
> +++ b/target/hexagon/insn.h
> @@ -41,6 +41,7 @@ struct Instruction {
> uint32_t new_value_producer_slot:4;
> int32_t new_read_idx;
> int32_t dest_idx;
> +bool has_pred_dest;
>
> bool part1; /*
>* cmp-jumps are split into two insns.
> diff --git a/target/hexagon/decode.c b/target/hexagon/decode.c
> index a4d8500fea..84a3899556 100644
> --- a/target/hexagon/decode.c
> +++ b/target/hexagon/decode.c
> @@ -366,6 +366,9 @@ static void decode_shuffle_for_execution(Packet
> *packet)
> for (flag = false, i = 0; i < last_insn + 1; i++) {
> int opcode = packet->insn[i].opcode;
>
> +g_assert(packet->insn[i].has_pred_dest ==
> + (strstr(opcode_wregs[opcode], "Pd4") ||
> + strstr(opcode_wregs[opcode], "Pe4")));
> if ((strstr(opcode_wregs[opcode], "Pd4") ||
> strstr(opcode_wregs[opcode], "Pe4")) &&
> GET_ATTRIB(opcode, A_STORE) == 0) {
> diff --git a/target/hexagon/gen_trans_funcs.py
> b/target/hexagon/gen_trans_funcs.py
> index 1201172dda..9f86b4edbd 100755
> --- a/target/hexagon/gen_trans_funcs.py
> +++ b/target/hexagon/gen_trans_funcs.py
> @@ -70,6 +70,7 @@ def mark_which_imm_extended(f, tag):
> ## insn->regno[2] = args->Rt;
> ## insn->new_read_idx = -1;
> ## insn->dest_idx = 0;
> +## insn->has_pred_dest = false;
> ## return true;
> ## }
> ##
> @@ -88,6 +89,7 @@ def gen_trans_funcs(f):
>
> new_read_idx = -1
> dest_idx = -1
> +has_pred_dest = "false"
> for regno, (reg_type, reg_id, *_) in enumerate(regs):
> reg = hex_common.get_register(tag, reg_type, reg_id)
> f.write(code_fmt(f"""\
> @@ -98,6 +100,8 @@ def gen_trans_funcs(f):
> # dest_idx should be the first destination, so check for -1
> if reg.is_written() and dest_idx == -1:
> dest_idx = regno
> +if reg_type == "P" and reg.is_written() and not reg.is_read():
> +has_pred_dest = "true"
>
> if len(imms) != 0:
> mark_which_imm_extended(f, tag)
> @@ -121,6 +125,7 @@ def gen_trans_funcs(f):
> f.write(code_fmt(f"""\
> insn->new_read_idx = {new_read_idx};
> insn->dest_idx = {dest_idx};
> +insn->has_pred_dest = {has_pred_dest};
> """))
> f.write(textwrap.dedent(f"""\
> return true;
> --
> 2.34.1
RE: [PATCH v2 6/9] Hexagon (target/hexagon) Remove uses of op_regs_generated.h.inc
> -Original Message-
> From: Taylor Simpson
> Sent: Wednesday, March 6, 2024 9:23 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ;
> Marco Liebel (QUIC) ;
> richard.hender...@linaro.org; phi...@linaro.org; a...@rev.ng; a...@rev.ng;
> ltaylorsimp...@gmail.com
> Subject: [PATCH v2 6/9] Hexagon (target/hexagon) Remove uses of
> op_regs_generated.h.inc
>
> WARNING: This email originated from outside of Qualcomm. Please be wary
> of any links or attachments, and do not enable macros.
>
> Signed-off-by: Taylor Simpson
> ---
Reviewed-by: Brian Cain
> target/hexagon/opcodes.h| 4 --
> target/hexagon/decode.c | 57 +++--
> target/hexagon/mmvec/decode_ext_mmvec.c | 34 +++
> target/hexagon/opcodes.c| 28
> 4 files changed, 13 insertions(+), 110 deletions(-)
>
> diff --git a/target/hexagon/opcodes.h b/target/hexagon/opcodes.h
> index fa7e321950..0ee11bd445 100644
> --- a/target/hexagon/opcodes.h
> +++ b/target/hexagon/opcodes.h
> @@ -40,10 +40,6 @@ typedef enum {
>
> extern const char * const opcode_names[];
>
> -extern const char * const opcode_reginfo[];
> -extern const char * const opcode_rregs[];
> -extern const char * const opcode_wregs[];
> -
> typedef struct {
> const char * const encoding;
> const EncClass enc_class;
> diff --git a/target/hexagon/decode.c b/target/hexagon/decode.c
> index 84a3899556..23deba2426 100644
> --- a/target/hexagon/decode.c
> +++ b/target/hexagon/decode.c
> @@ -115,24 +115,13 @@ static void
> decode_fill_newvalue_regno(Packet *packet)
> {
> int i, use_regidx, offset, def_idx, dst_idx;
> -uint16_t def_opcode, use_opcode;
> -char *dststr;
>
> for (i = 1; i < packet->num_insns; i++) {
> if (GET_ATTRIB(packet->insn[i].opcode, A_DOTNEWVALUE) &&
> !GET_ATTRIB(packet->insn[i].opcode, A_EXTENSION)) {
> -use_opcode = packet->insn[i].opcode;
> -
> -/* It's a store, so we're adjusting the Nt field */
> -if (GET_ATTRIB(use_opcode, A_STORE)) {
> -use_regidx = strchr(opcode_reginfo[use_opcode], 't') -
> -opcode_reginfo[use_opcode];
> -} else {/* It's a Jump, so we're adjusting the Ns field */
> -use_regidx = strchr(opcode_reginfo[use_opcode], 's') -
> -opcode_reginfo[use_opcode];
> -}
> -g_assert(packet->insn[i].new_read_idx != -1 &&
> - packet->insn[i].new_read_idx == use_regidx);
> +
> +g_assert(packet->insn[i].new_read_idx != -1);
> +use_regidx = packet->insn[i].new_read_idx;
>
> /*
> * What's encoded at the N-field is the offset to who's producing
> @@ -153,39 +142,9 @@ decode_fill_newvalue_regno(Packet *packet)
> */
> g_assert(!((def_idx < 0) || (def_idx > (packet->num_insns -
> 1;
>
> -/*
> - * packet->insn[def_idx] is the producer
> - * Figure out which type of destination it produces
> - * and the corresponding index in the reginfo
> - */
> -def_opcode = packet->insn[def_idx].opcode;
> -dststr = strstr(opcode_wregs[def_opcode], "Rd");
> -if (dststr) {
> -dststr = strchr(opcode_reginfo[def_opcode], 'd');
> -} else {
> -dststr = strstr(opcode_wregs[def_opcode], "Rx");
> -if (dststr) {
> -dststr = strchr(opcode_reginfo[def_opcode], 'x');
> -} else {
> -dststr = strstr(opcode_wregs[def_opcode], "Re");
> -if (dststr) {
> -dststr = strchr(opcode_reginfo[def_opcode], 'e');
> -} else {
> -dststr = strstr(opcode_wregs[def_opcode], "Ry");
> -if (dststr) {
> -dststr = strchr(opcode_reginfo[def_opcode], 'y');
> -} else {
> -g_assert_not_reached();
> -}
> -}
> -}
> -}
> -g_assert(dststr != NULL);
> -
> /* Now patch up the consumer with the register number */
> -dst_idx = dststr - opcode_reginfo[def_opcode];
> -g_assert(packet->insn[def_idx].dest_idx != -1 &&
> - packet->insn[def_
RE: [PATCH v2 7/9] Hexagon (target/hexagon) Remove gen_op_regs.py
> -Original Message-
> From: Taylor Simpson
> Sent: Wednesday, March 6, 2024 9:23 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ;
> Marco Liebel (QUIC) ;
> richard.hender...@linaro.org; phi...@linaro.org; a...@rev.ng; a...@rev.ng;
> ltaylorsimp...@gmail.com
> Subject: [PATCH v2 7/9] Hexagon (target/hexagon) Remove gen_op_regs.py
>
> WARNING: This email originated from outside of Qualcomm. Please be wary
> of any links or attachments, and do not enable macros.
>
> Signed-off-by: Taylor Simpson
> ---
Reviewed-by: Brian Cain
> target/hexagon/README | 1 -
> target/hexagon/gen_op_regs.py | 125 --
> target/hexagon/meson.build| 14 +---
> 3 files changed, 2 insertions(+), 138 deletions(-)
> delete mode 100755 target/hexagon/gen_op_regs.py
>
> diff --git a/target/hexagon/README b/target/hexagon/README
> index 746ebec378..065c05154d 100644
> --- a/target/hexagon/README
> +++ b/target/hexagon/README
> @@ -43,7 +43,6 @@ target/hexagon/gen_semantics.c. This step produces
> That file is consumed by the following python scripts to produce the
> indicated
> header files in /target/hexagon
> gen_opcodes_def.py -> opcodes_def_generated.h.inc
> -gen_op_regs.py -> op_regs_generated.h.inc
> gen_printinsn.py-> printinsn_generated.h.inc
> gen_op_attribs.py -> op_attribs_generated.h.inc
> gen_helper_protos.py-> helper_protos_generated.h.inc
> diff --git a/target/hexagon/gen_op_regs.py b/target/hexagon/gen_op_regs.py
> deleted file mode 100755
> index 7b7b33895a..00
> --- a/target/hexagon/gen_op_regs.py
> +++ /dev/null
> @@ -1,125 +0,0 @@
> -#!/usr/bin/env python3
> -
> -##
> -## Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights
> Reserved.
> -##
> -## This program is free software; you can redistribute it and/or modify
> -## it under the terms of the GNU General Public License as published by
> -## the Free Software Foundation; either version 2 of the License, or
> -## (at your option) any later version.
> -##
> -## This program is distributed in the hope that it will be useful,
> -## but WITHOUT ANY WARRANTY; without even the implied warranty of
> -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> -## GNU General Public License for more details.
> -##
> -## You should have received a copy of the GNU General Public License
> -## along with this program; if not, see <http://www.gnu.org/licenses/>.
> -##
> -
> -import sys
> -import re
> -import string
> -import hex_common
> -
> -
> -##
> -## Generate the register and immediate operands for each instruction
> -##
> -def calculate_regid_reg(tag):
> -def letter_inc(x):
> -return chr(ord(x) + 1)
> -
> -ordered_implregs = ["SP", "FP", "LR"]
> -srcdst_lett = "X"
> -src_lett = "S"
> -dst_lett = "D"
> -retstr = ""
> -mapdict = {}
> -for reg in ordered_implregs:
> -reg_rd = 0
> -reg_wr = 0
> -if ("A_IMPLICIT_WRITES_" + reg) in hex_common.attribdict[tag]:
> -reg_wr = 1
> -if reg_rd and reg_wr:
> -retstr += srcdst_lett
> -mapdict[srcdst_lett] = reg
> -srcdst_lett = letter_inc(srcdst_lett)
> -elif reg_rd:
> -retstr += src_lett
> -mapdict[src_lett] = reg
> -src_lett = letter_inc(src_lett)
> -elif reg_wr:
> -retstr += dst_lett
> -mapdict[dst_lett] = reg
> -dst_lett = letter_inc(dst_lett)
> -return retstr, mapdict
> -
> -
> -def calculate_regid_letters(tag):
> -retstr, mapdict = calculate_regid_reg(tag)
> -return retstr
> -
> -
> -def strip_reg_prefix(x):
> -y = x.replace("UREG.", "")
> -y = y.replace("MREG.", "")
> -return y.replace("GREG.", "")
> -
> -
> -def main():
> -hex_common.read_semantics_file(sys.argv[1])
> -hex_common.read_attribs_file(sys.argv[2])
> -hex_common.init_registers()
> -tagregs = hex_common.get_tagregs(full=True)
> -tagimms = hex_common.get_tagimms()
> -
> -with open(sys.argv[3], "w") as f:
> -for tag in hex_common.tags:
> -regs = tagregs[tag]
> -rregs = []
> -wregs = []
> -regids = ""
> -for
RE: [PATCH v2 9/9] Hexagon (target/hexagon) Remove hex_common.read_attribs_file
> -Original Message- > From: Taylor Simpson > Sent: Wednesday, March 6, 2024 9:23 PM > To: qemu-devel@nongnu.org > Cc: Brian Cain ; Matheus Bernardino (QUIC) > ; Sid Manning ; > Marco Liebel (QUIC) ; > richard.hender...@linaro.org; phi...@linaro.org; a...@rev.ng; a...@rev.ng; > ltaylorsimp...@gmail.com > Subject: [PATCH v2 9/9] Hexagon (target/hexagon) Remove > hex_common.read_attribs_file > > WARNING: This email originated from outside of Qualcomm. Please be wary > of any links or attachments, and do not enable macros. > > The attribinfo data structure is not used > Adjust the command-line arguments to the python scripts > Add hex_common.read_common_files for TCG/helper generation scripts > > Signed-off-by: Taylor Simpson > --- Reviewed-by: Brian Cain > target/hexagon/gen_analyze_funcs.py | 21 ++- > target/hexagon/gen_helper_funcs.py | 21 ++- > target/hexagon/gen_helper_protos.py | 21 ++- > target/hexagon/gen_idef_parser_funcs.py | 5 ++-- > target/hexagon/gen_op_attribs.py| 5 ++-- > target/hexagon/gen_opcodes_def.py | 4 +-- > target/hexagon/gen_printinsn.py | 5 ++-- > target/hexagon/gen_tcg_func_table.py| 5 ++-- > target/hexagon/gen_tcg_funcs.py | 21 ++- > target/hexagon/hex_common.py| 35 +++-- > target/hexagon/meson.build | 31 +++--- > 11 files changed, 54 insertions(+), 120 deletions(-) > > diff --git a/target/hexagon/gen_analyze_funcs.py > b/target/hexagon/gen_analyze_funcs.py > index a9af666cef..b73b4e2349 100755 > --- a/target/hexagon/gen_analyze_funcs.py > +++ b/target/hexagon/gen_analyze_funcs.py > @@ -1,7 +1,7 @@ > #!/usr/bin/env python3 > > ## > -## Copyright(c) 2022-2023 Qualcomm Innovation Center, Inc. All Rights > Reserved. > +## Copyright(c) 2022-2024 Qualcomm Innovation Center, Inc. All Rights > Reserved. > ## > ## This program is free software; you can redistribute it and/or modify > ## it under the terms of the GNU General Public License as published by > @@ -67,24 +67,7 @@ def gen_analyze_func(f, tag, regs, imms): > > > def main(): > -hex_common.read_semantics_file(sys.argv[1]) > -hex_common.read_attribs_file(sys.argv[2]) > -hex_common.read_overrides_file(sys.argv[3]) > -hex_common.read_overrides_file(sys.argv[4]) > -## Whether or not idef-parser is enabled is > -## determined by the number of arguments to > -## this script: > -## > -## 5 args. -> not enabled, > -## 6 args. -> idef-parser enabled. > -## > -## The 6:th arg. then holds a list of the successfully > -## parsed instructions. > -is_idef_parser_enabled = len(sys.argv) > 6 > -if is_idef_parser_enabled: > -hex_common.read_idef_parser_enabled_file(sys.argv[5]) > -hex_common.calculate_attribs() > -hex_common.init_registers() > +hex_common.read_common_files() > tagregs = hex_common.get_tagregs() > tagimms = hex_common.get_tagimms() > > diff --git a/target/hexagon/gen_helper_funcs.py > b/target/hexagon/gen_helper_funcs.py > index 9cc3d69c49..e9685bff2f 100755 > --- a/target/hexagon/gen_helper_funcs.py > +++ b/target/hexagon/gen_helper_funcs.py > @@ -1,7 +1,7 @@ > #!/usr/bin/env python3 > > ## > -## Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights > Reserved. > +## Copyright(c) 2019-2024 Qualcomm Innovation Center, Inc. All Rights > Reserved. > ## > ## This program is free software; you can redistribute it and/or modify > ## it under the terms of the GNU General Public License as published by > @@ -102,24 +102,7 @@ def gen_helper_function(f, tag, tagregs, tagimms): > > > def main(): > -hex_common.read_semantics_file(sys.argv[1]) > -hex_common.read_attribs_file(sys.argv[2]) > -hex_common.read_overrides_file(sys.argv[3]) > -hex_common.read_overrides_file(sys.argv[4]) > -## Whether or not idef-parser is enabled is > -## determined by the number of arguments to > -## this script: > -## > -## 5 args. -> not enabled, > -## 6 args. -> idef-parser enabled. > -## > -## The 6:th arg. then holds a list of the successfully > -## parsed instructions. > -is_idef_parser_enabled = len(sys.argv) > 6 > -if is_idef_parser_enabled: > -hex_common.read_idef_parser_enabled_file(sys.argv[5]) > -hex_common.calculate_attribs() > -hex_common.init_registers() > +hex_common.read_common_files() > tagregs = hex_common.get_tagregs() > tagimms = hex_common.get_tagimms() > > dif
RE: [PATCH v2 8/9] Hexagon (target/hexagon) Remove gen_shortcode.py
> -Original Message-
> From: Taylor Simpson
> Sent: Wednesday, March 6, 2024 9:23 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ;
> Marco Liebel (QUIC) ;
> richard.hender...@linaro.org; phi...@linaro.org; a...@rev.ng; a...@rev.ng;
> ltaylorsimp...@gmail.com
> Subject: [PATCH v2 8/9] Hexagon (target/hexagon) Remove gen_shortcode.py
>
> WARNING: This email originated from outside of Qualcomm. Please be wary
> of any links or attachments, and do not enable macros.
>
> This data structure is not used
>
> Signed-off-by: Taylor Simpson
> ---
Reviewed-by: Brian Cain
> target/hexagon/opcodes.c| 7
> target/hexagon/README | 1 -
> target/hexagon/gen_shortcode.py | 63 -
> target/hexagon/meson.build | 10 --
> 4 files changed, 81 deletions(-)
> delete mode 100755 target/hexagon/gen_shortcode.py
>
> diff --git a/target/hexagon/opcodes.c b/target/hexagon/opcodes.c
> index 02ae9cf787..c8bde2f9e9 100644
> --- a/target/hexagon/opcodes.c
> +++ b/target/hexagon/opcodes.c
> @@ -37,13 +37,6 @@ const char * const opcode_names[] = {
> };
>
>
> -const char * const opcode_short_semantics[] = {
> -#define DEF_SHORTCODE(TAG, SHORTCODE) [TAG] = #SHORTCODE,
> -#include "shortcode_generated.h.inc"
> -#undef DEF_SHORTCODE
> -NULL
> -};
> -
> DECLARE_BITMAP(opcode_attribs[XX_LAST_OPCODE], A_ZZ_LASTATTRIB);
>
> static void init_attribs(int tag, ...)
> diff --git a/target/hexagon/README b/target/hexagon/README
> index 065c05154d..65b4fcc0fa 100644
> --- a/target/hexagon/README
> +++ b/target/hexagon/README
> @@ -46,7 +46,6 @@ header files in /target/hexagon
> gen_printinsn.py-> printinsn_generated.h.inc
> gen_op_attribs.py -> op_attribs_generated.h.inc
> gen_helper_protos.py-> helper_protos_generated.h.inc
> -gen_shortcode.py-> shortcode_generated.h.inc
> gen_tcg_funcs.py-> tcg_funcs_generated.c.inc
> gen_tcg_func_table.py -> tcg_func_table_generated.c.inc
> gen_helper_funcs.py -> helper_funcs_generated.c.inc
> diff --git a/target/hexagon/gen_shortcode.py
> b/target/hexagon/gen_shortcode.py
> deleted file mode 100755
> index deb94446c4..00
> --- a/target/hexagon/gen_shortcode.py
> +++ /dev/null
> @@ -1,63 +0,0 @@
> -#!/usr/bin/env python3
> -
> -##
> -## Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights
> Reserved.
> -##
> -## This program is free software; you can redistribute it and/or modify
> -## it under the terms of the GNU General Public License as published by
> -## the Free Software Foundation; either version 2 of the License, or
> -## (at your option) any later version.
> -##
> -## This program is distributed in the hope that it will be useful,
> -## but WITHOUT ANY WARRANTY; without even the implied warranty of
> -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> -## GNU General Public License for more details.
> -##
> -## You should have received a copy of the GNU General Public License
> -## along with this program; if not, see <http://www.gnu.org/licenses/>.
> -##
> -
> -import sys
> -import re
> -import string
> -import hex_common
> -
> -
> -def gen_shortcode(f, tag):
> -f.write(f"DEF_SHORTCODE({tag}, {hex_common.semdict[tag]})\n")
> -
> -
> -def main():
> -hex_common.read_semantics_file(sys.argv[1])
> -hex_common.read_attribs_file(sys.argv[2])
> -hex_common.calculate_attribs()
> -tagregs = hex_common.get_tagregs()
> -tagimms = hex_common.get_tagimms()
> -
> -with open(sys.argv[3], "w") as f:
> -f.write("#ifndef DEF_SHORTCODE\n")
> -f.write("#define DEF_SHORTCODE(TAG,SHORTCODE)/* Nothing */\n")
> -f.write("#endif\n")
> -
> -for tag in hex_common.tags:
> -## Skip the priv instructions
> -if "A_PRIV" in hex_common.attribdict[tag]:
> -continue
> -## Skip the guest instructions
> -if "A_GUEST" in hex_common.attribdict[tag]:
> -continue
> -## Skip the diag instructions
> -if tag == "Y6_diag":
> -continue
> -if tag == "Y6_diag0":
> -continue
> -if tag == "Y6_diag1":
> -continue
> -
> -gen_shortcode(f, tag)
> -
> -f.wri
RE: [PATCH-for-9.1 08/27] target/hexagon: Convert to TCGCPUOps::get_cpu_state()
> -Original Message-
> From: Philippe Mathieu-Daudé
> Sent: Tuesday, March 19, 2024 10:43 AM
> To: qemu-devel@nongnu.org
> Cc: qemu-s3...@nongnu.org; Richard Henderson
> ; qemu-...@nongnu.org; qemu-
> a...@nongnu.org; qemu-ri...@nongnu.org; Anton Johansson ;
> Philippe Mathieu-Daudé ; Brian Cain
>
> Subject: [PATCH-for-9.1 08/27] target/hexagon: Convert to
> TCGCPUOps::get_cpu_state()
>
> WARNING: This email originated from outside of Qualcomm. Please be wary
> of any links or attachments, and do not enable macros.
>
> Convert cpu_get_tb_cpu_state() to TCGCPUOps::get_cpu_state().
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Brian Cain
> ---
> target/hexagon/cpu.h | 14 --
> target/hexagon/cpu.c | 13 +
> 2 files changed, 13 insertions(+), 14 deletions(-)
>
> diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
> index 935a9c3276..1d42c33827 100644
> --- a/target/hexagon/cpu.h
> +++ b/target/hexagon/cpu.h
> @@ -134,20 +134,6 @@ struct ArchCPU {
>
> FIELD(TB_FLAGS, IS_TIGHT_LOOP, 0, 1)
>
> -#define TARGET_HAS_CPU_GET_TB_CPU_STATE
> -
> -static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc,
> -uint64_t *cs_base, uint32_t *flags)
> -{
> -uint32_t hex_flags = 0;
> -*pc = env->gpr[HEX_REG_PC];
> -*cs_base = 0;
> -if (*pc == env->gpr[HEX_REG_SA0]) {
> -hex_flags = FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1);
> -}
> -*flags = hex_flags;
> -}
> -
> typedef HexagonCPU ArchCPU;
>
> void hexagon_translate_init(void);
> diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
> index 3a716b9be3..5e0a9441f2 100644
> --- a/target/hexagon/cpu.c
> +++ b/target/hexagon/cpu.c
> @@ -273,6 +273,18 @@ static void hexagon_restore_state_to_opc(CPUState
> *cs,
> cpu_env(cs)->gpr[HEX_REG_PC] = data[0];
> }
>
> +static void hexagon_get_cpu_state(CPUHexagonState *env, vaddr *pc,
> + uint64_t *cs_base, uint32_t *flags)
> +{
> +uint32_t hex_flags = 0;
> +*pc = env->gpr[HEX_REG_PC];
> +*cs_base = 0;
> +if (*pc == env->gpr[HEX_REG_SA0]) {
> +hex_flags = FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1);
> +}
> +*flags = hex_flags;
> +}
> +
> static void hexagon_cpu_reset_hold(Object *obj)
> {
> CPUState *cs = CPU(obj);
> @@ -327,6 +339,7 @@ static const TCGCPUOps hexagon_tcg_ops = {
> .initialize = hexagon_translate_init,
> .synchronize_from_tb = hexagon_cpu_synchronize_from_tb,
> .restore_state_to_opc = hexagon_restore_state_to_opc,
> +.get_cpu_state = hexagon_get_cpu_state,
> };
>
> static void hexagon_cpu_class_init(ObjectClass *c, void *data)
> --
> 2.41.0
RE: [PATCH v3 1/3] Hexagon (target/hexagon) Pass P0 explicitly to helpers that need it
> -Original Message- > From: Taylor Simpson > Sent: Tuesday, February 13, 2024 10:27 PM > To: qemu-devel@nongnu.org > Cc: Brian Cain ; Matheus Bernardino (QUIC) > ; Sid Manning ; Marco > Liebel (QUIC) ; richard.hender...@linaro.org; > phi...@linaro.org; a...@rev.ng; a...@rev.ng; ltaylorsimp...@gmail.com > Subject: [PATCH v3 1/3] Hexagon (target/hexagon) Pass P0 explicitly to helpers > that need it > > WARNING: This email originated from outside of Qualcomm. Please be wary of > any links or attachments, and do not enable macros. > > Rather than reading P0 from the env, pass it explicitly > > Signed-off-by: Taylor Simpson > Reviewed-by: Anton Johansson > Tested-by: Anton Johansson > --- Reviewed-by: Brian Cain > target/hexagon/macros.h | 4 ++-- > target/hexagon/hex_common.py | 12 +++- > 2 files changed, 13 insertions(+), 3 deletions(-) > > diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h > index 1376d6ccc1..aedc863fab 100644 > --- a/target/hexagon/macros.h > +++ b/target/hexagon/macros.h > @@ -1,5 +1,5 @@ > /* > - * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights > Reserved. > + * Copyright(c) 2019-2024 Qualcomm Innovation Center, Inc. All Rights > Reserved. > * > * This program is free software; you can redistribute it and/or modify > * it under the terms of the GNU General Public License as published by > @@ -358,7 +358,7 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val, > int shift) > #endif > #define fREAD_PC() (PC) > > -#define fREAD_P0() (env->pred[0]) > +#define fREAD_P0() (P0) > > #define fCHECK_PCALIGN(A) > > diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py > index 195620c7ec..14dcf261b4 100755 > --- a/target/hexagon/hex_common.py > +++ b/target/hexagon/hex_common.py > @@ -1,7 +1,7 @@ > #!/usr/bin/env python3 > > ## > -## Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights > Reserved. > +## Copyright(c) 2019-2024 Qualcomm Innovation Center, Inc. All Rights > Reserved. > ## > ## This program is free software; you can redistribute it and/or modify > ## it under the terms of the GNU General Public License as published by > @@ -197,6 +197,10 @@ def get_tagimms(): > return dict(zip(tags, list(map(compute_tag_immediates, tags > > > +def need_p0(tag): > +return "A_IMPLICIT_READS_P0" in attribdict[tag] > + > + > def need_slot(tag): > if ( > "A_CVI_SCATTER" not in attribdict[tag] > @@ -1118,6 +1122,12 @@ def helper_args(tag, regs, imms): > "tcg_constant_tl(ctx->next_PC)", > "target_ulong next_PC" > )) > +if need_p0(tag): > +args.append(HelperArg( > +"i32", > +"hex_pred[0]", > +"uint32_t P0" > +)) > if need_slot(tag): > args.append(HelperArg( > "i32", > -- > 2.34.1
RE: [PATCH v3 2/3] Hexagon (target/hexagon) Pass SP explicitly to helpers that need it
> -Original Message-
> From: Taylor Simpson
> Sent: Tuesday, February 13, 2024 10:27 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ; Marco
> Liebel (QUIC) ; richard.hender...@linaro.org;
> phi...@linaro.org; a...@rev.ng; a...@rev.ng; ltaylorsimp...@gmail.com
> Subject: [PATCH v3 2/3] Hexagon (target/hexagon) Pass SP explicitly to helpers
> that need it
>
> WARNING: This email originated from outside of Qualcomm. Please be wary of
> any links or attachments, and do not enable macros.
>
> Rather than reading SP from the env, pass it explicitly
>
> Signed-off-by: Taylor Simpson
> Reviewed-by: Anton Johansson
> Tested-by: Anton Johansson
> ---
Reviewed-by: Brian Cain
> target/hexagon/macros.h | 2 +-
> target/hexagon/attribs_def.h.inc | 3 ++-
> target/hexagon/hex_common.py | 11 +++
> 3 files changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
> index aedc863fab..feb798c6c0 100644
> --- a/target/hexagon/macros.h
> +++ b/target/hexagon/macros.h
> @@ -343,7 +343,7 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val,
> int shift)
>
> #define fREAD_LR() (env->gpr[HEX_REG_LR])
>
> -#define fREAD_SP() (env->gpr[HEX_REG_SP])
> +#define fREAD_SP() (SP)
> #define fREAD_LC0 (env->gpr[HEX_REG_LC0])
> #define fREAD_LC1 (env->gpr[HEX_REG_LC1])
> #define fREAD_SA0 (env->gpr[HEX_REG_SA0])
> diff --git a/target/hexagon/attribs_def.h.inc
> b/target/hexagon/attribs_def.h.inc
> index 87942d46f4..9e3a05f882 100644
> --- a/target/hexagon/attribs_def.h.inc
> +++ b/target/hexagon/attribs_def.h.inc
> @@ -1,5 +1,5 @@
> /*
> - * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights
> Reserved.
> + * Copyright(c) 2019-2024 Qualcomm Innovation Center, Inc. All Rights
> Reserved.
> *
> * This program is free software; you can redistribute it and/or modify
> * it under the terms of the GNU General Public License as published by
> @@ -117,6 +117,7 @@ DEF_ATTRIB(IMPLICIT_READS_P1, "Reads the P1
> register", "", "")
> DEF_ATTRIB(IMPLICIT_READS_P2, "Reads the P2 register", "", "")
> DEF_ATTRIB(IMPLICIT_READS_P3, "Reads the P3 register", "", "")
> DEF_ATTRIB(IMPLICIT_WRITES_USR, "May write USR", "", "")
> +DEF_ATTRIB(IMPLICIT_READS_SP, "Reads the SP register", "", "")
> DEF_ATTRIB(COMMUTES, "The operation is communitive", "", "")
> DEF_ATTRIB(DEALLOCRET, "dealloc_return", "", "")
> DEF_ATTRIB(DEALLOCFRAME, "deallocframe", "", "")
> diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
> index 14dcf261b4..b96f67972d 100755
> --- a/target/hexagon/hex_common.py
> +++ b/target/hexagon/hex_common.py
> @@ -101,6 +101,7 @@ def calculate_attribs():
> add_qemu_macro_attrib('fLSBNEW1', 'A_IMPLICIT_READS_P1')
> add_qemu_macro_attrib('fLSBNEW1NOT', 'A_IMPLICIT_READS_P1')
> add_qemu_macro_attrib('fREAD_P3', 'A_IMPLICIT_READS_P3')
> +add_qemu_macro_attrib('fREAD_SP', 'A_IMPLICIT_READS_SP')
>
> # Recurse down macros, find attributes from sub-macros
> macroValues = list(macros.values())
> @@ -201,6 +202,10 @@ def need_p0(tag):
> return "A_IMPLICIT_READS_P0" in attribdict[tag]
>
>
> +def need_sp(tag):
> +return "A_IMPLICIT_READS_SP" in attribdict[tag]
> +
> +
> def need_slot(tag):
> if (
> "A_CVI_SCATTER" not in attribdict[tag]
> @@ -1128,6 +1133,12 @@ def helper_args(tag, regs, imms):
> "hex_pred[0]",
> "uint32_t P0"
> ))
> +if need_sp(tag):
> +args.append(HelperArg(
> +"i32",
> +"hex_gpr[HEX_REG_SP]",
> +"uint32_t SP"
> +))
> if need_slot(tag):
> args.append(HelperArg(
> "i32",
> --
> 2.34.1
RE: [PATCH v3 2/3] Hexagon (target/hexagon) Pass SP explicitly to helpers that need it
> -Original Message-
> From: Taylor Simpson
> Sent: Tuesday, February 13, 2024 10:27 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ; Marco
> Liebel (QUIC) ; richard.hender...@linaro.org;
> phi...@linaro.org; a...@rev.ng; a...@rev.ng; ltaylorsimp...@gmail.com
> Subject: [PATCH v3 2/3] Hexagon (target/hexagon) Pass SP explicitly to helpers
> that need it
>
> WARNING: This email originated from outside of Qualcomm. Please be wary of
> any links or attachments, and do not enable macros.
>
> Rather than reading SP from the env, pass it explicitly
>
> Signed-off-by: Taylor Simpson
> Reviewed-by: Anton Johansson
> Tested-by: Anton Johansson
> ---
Reviewed-by: Brian Cain
> target/hexagon/macros.h | 2 +-
> target/hexagon/attribs_def.h.inc | 3 ++-
> target/hexagon/hex_common.py | 11 +++
> 3 files changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
> index aedc863fab..feb798c6c0 100644
> --- a/target/hexagon/macros.h
> +++ b/target/hexagon/macros.h
> @@ -343,7 +343,7 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val,
> int shift)
>
> #define fREAD_LR() (env->gpr[HEX_REG_LR])
>
> -#define fREAD_SP() (env->gpr[HEX_REG_SP])
> +#define fREAD_SP() (SP)
> #define fREAD_LC0 (env->gpr[HEX_REG_LC0])
> #define fREAD_LC1 (env->gpr[HEX_REG_LC1])
> #define fREAD_SA0 (env->gpr[HEX_REG_SA0])
> diff --git a/target/hexagon/attribs_def.h.inc
> b/target/hexagon/attribs_def.h.inc
> index 87942d46f4..9e3a05f882 100644
> --- a/target/hexagon/attribs_def.h.inc
> +++ b/target/hexagon/attribs_def.h.inc
> @@ -1,5 +1,5 @@
> /*
> - * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights
> Reserved.
> + * Copyright(c) 2019-2024 Qualcomm Innovation Center, Inc. All Rights
> Reserved.
> *
> * This program is free software; you can redistribute it and/or modify
> * it under the terms of the GNU General Public License as published by
> @@ -117,6 +117,7 @@ DEF_ATTRIB(IMPLICIT_READS_P1, "Reads the P1
> register", "", "")
> DEF_ATTRIB(IMPLICIT_READS_P2, "Reads the P2 register", "", "")
> DEF_ATTRIB(IMPLICIT_READS_P3, "Reads the P3 register", "", "")
> DEF_ATTRIB(IMPLICIT_WRITES_USR, "May write USR", "", "")
> +DEF_ATTRIB(IMPLICIT_READS_SP, "Reads the SP register", "", "")
> DEF_ATTRIB(COMMUTES, "The operation is communitive", "", "")
> DEF_ATTRIB(DEALLOCRET, "dealloc_return", "", "")
> DEF_ATTRIB(DEALLOCFRAME, "deallocframe", "", "")
> diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
> index 14dcf261b4..b96f67972d 100755
> --- a/target/hexagon/hex_common.py
> +++ b/target/hexagon/hex_common.py
> @@ -101,6 +101,7 @@ def calculate_attribs():
> add_qemu_macro_attrib('fLSBNEW1', 'A_IMPLICIT_READS_P1')
> add_qemu_macro_attrib('fLSBNEW1NOT', 'A_IMPLICIT_READS_P1')
> add_qemu_macro_attrib('fREAD_P3', 'A_IMPLICIT_READS_P3')
> +add_qemu_macro_attrib('fREAD_SP', 'A_IMPLICIT_READS_SP')
>
> # Recurse down macros, find attributes from sub-macros
> macroValues = list(macros.values())
> @@ -201,6 +202,10 @@ def need_p0(tag):
> return "A_IMPLICIT_READS_P0" in attribdict[tag]
>
>
> +def need_sp(tag):
> +return "A_IMPLICIT_READS_SP" in attribdict[tag]
> +
> +
> def need_slot(tag):
> if (
> "A_CVI_SCATTER" not in attribdict[tag]
> @@ -1128,6 +1133,12 @@ def helper_args(tag, regs, imms):
> "hex_pred[0]",
> "uint32_t P0"
> ))
> +if need_sp(tag):
> +args.append(HelperArg(
> +"i32",
> +"hex_gpr[HEX_REG_SP]",
> +"uint32_t SP"
> +))
> if need_slot(tag):
> args.append(HelperArg(
> "i32",
> --
> 2.34.1
RE: [PATCH v3 11/29] target/hexagon: Prefer fast cpu_env() over slower CPU QOM cast macro
> -Original Message-
> From: Philippe Mathieu-Daudé
> Sent: Monday, January 29, 2024 10:45 AM
> To: qemu-devel@nongnu.org
> Cc: qemu-ri...@nongnu.org; qemu-s3...@nongnu.org; Paolo Bonzini
> ; k...@vger.kernel.org; qemu-...@nongnu.org;
> qemu-...@nongnu.org; Richard Henderson ;
> Philippe Mathieu-Daudé ; Brian Cain
>
> Subject: [PATCH v3 11/29] target/hexagon: Prefer fast cpu_env() over slower
> CPU QOM cast macro
>
> WARNING: This email originated from outside of Qualcomm. Please be wary of
> any links or attachments, and do not enable macros.
>
> Mechanical patch produced running the command documented
> in scripts/coccinelle/cpu_env.cocci_template header.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/hexagon/cpu.c | 25 ++---
> target/hexagon/gdbstub.c | 6 ++
> 2 files changed, 8 insertions(+), 23 deletions(-)
>
> diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
> index 085d6c0115..17a22aa7a5 100644
> --- a/target/hexagon/cpu.c
> +++ b/target/hexagon/cpu.c
> @@ -236,10 +236,7 @@ static void hexagon_dump(CPUHexagonState *env,
> FILE *f, int flags)
>
> static void hexagon_dump_state(CPUState *cs, FILE *f, int flags)
> {
> -HexagonCPU *cpu = HEXAGON_CPU(cs);
> -CPUHexagonState *env = >env;
> -
> -hexagon_dump(env, f, flags);
> +hexagon_dump(cpu_env(cs), f, flags);
> }
>
> void hexagon_debug(CPUHexagonState *env)
> @@ -249,25 +246,19 @@ void hexagon_debug(CPUHexagonState *env)
>
> static void hexagon_cpu_set_pc(CPUState *cs, vaddr value)
> {
> -HexagonCPU *cpu = HEXAGON_CPU(cs);
> -CPUHexagonState *env = >env;
> -env->gpr[HEX_REG_PC] = value;
> +cpu_env(cs)->gpr[HEX_REG_PC] = value;
> }
>
> static vaddr hexagon_cpu_get_pc(CPUState *cs)
> {
> -HexagonCPU *cpu = HEXAGON_CPU(cs);
> -CPUHexagonState *env = >env;
> -return env->gpr[HEX_REG_PC];
> +return cpu_env(cs)->gpr[HEX_REG_PC];
> }
>
> static void hexagon_cpu_synchronize_from_tb(CPUState *cs,
> const TranslationBlock *tb)
> {
> -HexagonCPU *cpu = HEXAGON_CPU(cs);
> -CPUHexagonState *env = >env;
> tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
> -env->gpr[HEX_REG_PC] = tb->pc;
> +cpu_env(cs)->gpr[HEX_REG_PC] = tb->pc;
> }
>
> static bool hexagon_cpu_has_work(CPUState *cs)
> @@ -279,18 +270,14 @@ static void hexagon_restore_state_to_opc(CPUState
> *cs,
> const TranslationBlock *tb,
> const uint64_t *data)
> {
> -HexagonCPU *cpu = HEXAGON_CPU(cs);
> -CPUHexagonState *env = >env;
> -
> -env->gpr[HEX_REG_PC] = data[0];
> +cpu_env(cs)->gpr[HEX_REG_PC] = data[0];
> }
>
> static void hexagon_cpu_reset_hold(Object *obj)
> {
> CPUState *cs = CPU(obj);
> -HexagonCPU *cpu = HEXAGON_CPU(cs);
> HexagonCPUClass *mcc = HEXAGON_CPU_GET_CLASS(obj);
> -CPUHexagonState *env = >env;
> +CPUHexagonState *env = cpu_env(cs);
>
> if (mcc->parent_phases.hold) {
> mcc->parent_phases.hold(obj);
> diff --git a/target/hexagon/gdbstub.c b/target/hexagon/gdbstub.c
> index 54d37e006e..f773f8ea4f 100644
> --- a/target/hexagon/gdbstub.c
> +++ b/target/hexagon/gdbstub.c
> @@ -22,8 +22,7 @@
>
> int hexagon_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
> {
> -HexagonCPU *cpu = HEXAGON_CPU(cs);
> -CPUHexagonState *env = >env;
> +CPUHexagonState *env = cpu_env(cs);
>
> if (n == HEX_REG_P3_0_ALIASED) {
> uint32_t p3_0 = 0;
> @@ -42,8 +41,7 @@ int hexagon_gdb_read_register(CPUState *cs, GByteArray
> *mem_buf, int n)
>
> int hexagon_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
> {
> -HexagonCPU *cpu = HEXAGON_CPU(cs);
> -CPUHexagonState *env = >env;
> +CPUHexagonState *env = cpu_env(cs);
>
> if (n == HEX_REG_P3_0_ALIASED) {
> uint32_t p3_0 = ldtul_p(mem_buf);
> --
> 2.41.0
Reviewed-by: Brian Cain
KVM Forum 2024?
All, https://kvm-forum.qemu.org/ shows a plan for "Spring 2024" - so that's as soon as ~mid-March or as late as mid-June? I'd like to understand if we think that it's more likely to be later in that range? Last year was mid June I think? So should we expect something similar this year? -Brian
RE: hexagon: modeling a shared lock state
> -Original Message-
> From: Richard Henderson
> Sent: Wednesday, January 24, 2024 6:22 PM
> To: Brian Cain ; Philippe Mathieu-Daudé
>
> Cc: qemu-devel@nongnu.org; Sid Manning ; Marco
> Liebel ; Matheus Bernardino
>
> Subject: Re: hexagon: modeling a shared lock state
>
> WARNING: This email originated from outside of Qualcomm. Please be wary of
> any links or attachments, and do not enable macros.
>
> On 1/25/24 01:07, Brian Cain wrote:
> > Philippe,
> >
> > For hexagon sysemu, while internally reviewing patches to be upstreamed we
> noticed that
> > our design for a lock instruction is not quite suitable. The k0lock
> > instruction
> will halt
> > if some other hexagon hardware CPU has already claimed the kernel lock,
> only to continue
> > executing once some CPU executes the unlock instruction. We modeled this
> using a lock
> > state enumeration member { OWNER, WAITING, UNLOCKED } in **each**
> vCPU and atomically
> > transitioning the lock required us to have vCPU[n] write the updated lock
> state to vCPU[m]
> > when unlocking.
> >
> > In context:
> >
> https://github.com/quic/qemu/blob/hexagon_sysemu_20_dec_2023/target/he
> xagon/op_helper.c#L1790-L1821
> <https://github.com/quic/qemu/blob/hexagon_sysemu_20_dec_2023/target/h
> exagon/op_helper.c#L1790-L1821>
> >
> > So instead, maybe it makes more sense to have a system device hold a single
> representation
> > of the lock’s state and each vCPU can do some kind of access via load/store
> and/or
> > interrupts to/from the device? I was thinking of raising an interrupt on
> > the
> lock device
> > at the vCPU’s k0lock instruction to indicate demand for the lock, and then
> > the
> device
> > could raise an interrupt to one of the vCPUs when it’s granted the lock.
> > One
> drawback for
> > this is that this might add significant latency to the uncontested lock
> > case. So
> I also
> > considered doing a load of some part of the lock device’s memory that could
> indicate
> > whether the lock was available, and if available it would claim it with a
> > store
> (both
> > ld/st while holding BQL). Only if unavailable it would halt and raise the
> interrupt. Is
> > it possible to create an address space that’s independent of the true system
> memory map
> > for this use case or would we need to carve out some memory from the
> existing memory map
> > for this synthetic device? Or – do you have a suggestion for a better
> approach overall?
>
> I think you are over-thinking this. A system device would just get in the
> way. I
Ok, great - our existing design is ~roughly like this. But we can explore this
-- thanks for writing this example!
> think
> you want something like
>
>struct CPUHexagonState {
> ...
> bool hwlock_pending;
>}
>
>hexagon_cpu_has_work() {
> if (cpu->hwlock_pending) {
>return false;
> }
>}
>
>static void do_hwlock(CPUHexagonState *env, bool *lock)
>{
> bql_lock();
>
> if (*lock) {
>env->hwlock_pending = true;
>cs->halted = true;
>cs->exception_index = EXCP_HALTED;
>bql_unlock();
>cpu_loop_exit(cs);
In place of the above - we have cpu_interrupt(cs, CPU_INTERRUPT_HALT) -- but is
that equivalent? Is there one idiom that's preferred over another? Somehow it
seems simpler if we don't need to longjmp and IIRC some of these patterns do.
> } else {
>*lock = true;
>bql_unlock();
> }
>}
>
>static void do_hwunlock(CPUHexagonState *env, bool *lock)
>{
> CPUState *cs;
> BQL_LOCK_GUARD();
>
> *lock = false;
>
> CPU_FOREACH(cs) {
>if (cs->hwlock_pending) {
> cs->hwlock_pending = false;
> qemu_cpu_kick(cs);
>}
> }
>}
>
>static bool k0lock, tlblock;
>
>void HELPER(k0lock)(CPUHexagonState *env)
>void HELPER(tlblock)(CPUHexagonState *env)
>void HELPER(k0unlock)(CPUHexagonState *env)
>void HELPER(tlbunlock)(CPUHexagonState *env)
>
> Open questions are:
>
> (1) Do interrupts cancel lock wait? Either way, placement in
> hexagon_cpu_has_work is key.
Yeah - they do, we will double check the interaction w has_work.
> (2) I assume that the pc will not be advanced, so that after the kick we will
> re-
> execute
> the hwlock instruction. There will be a thundering herd racing to grab the
> lock
> again,
> but it saves queuing logic, which might be complicated if interrupts are
> involved.
Yes that's right, too. Thanks!
hexagon: modeling a shared lock state
Philippe,
For hexagon sysemu, while internally reviewing patches to be upstreamed we
noticed that our design for a lock instruction is not quite suitable. The
k0lock instruction will halt if some other hexagon hardware CPU has already
claimed the kernel lock, only to continue executing once some CPU executes the
unlock instruction. We modeled this using a lock state enumeration member {
OWNER, WAITING, UNLOCKED } in *each* vCPU and atomically transitioning the lock
required us to have vCPU[n] write the updated lock state to vCPU[m] when
unlocking.
In context:
https://github.com/quic/qemu/blob/hexagon_sysemu_20_dec_2023/target/hexagon/op_helper.c#L1790-L1821
So instead, maybe it makes more sense to have a system device hold a single
representation of the lock's state and each vCPU can do some kind of access via
load/store and/or interrupts to/from the device? I was thinking of raising an
interrupt on the lock device at the vCPU's k0lock instruction to indicate
demand for the lock, and then the device could raise an interrupt to one of the
vCPUs when it's granted the lock. One drawback for this is that this might add
significant latency to the uncontested lock case. So I also considered doing a
load of some part of the lock device's memory that could indicate whether the
lock was available, and if available it would claim it with a store (both ld/st
while holding BQL). Only if unavailable it would halt and raise the interrupt.
Is it possible to create an address space that's independent of the true
system memory map for this use case or would we need to carve out some memory
from the existing memory map for this synthetic device? Or - do you have a
suggestion for a better approach overall?
-Brian
[PULL 11/15] Hexagon (target/hexagon) Remove dead functions from hex_common.py
From: Taylor Simpson
These functions are no longer used after making the generators
object oriented.
Signed-off-by: Taylor Simpson
Reviewed-by: Brian Cain
Message-Id: <20231210220712.491494-10-ltaylorsimp...@gmail.com>
Signed-off-by: Brian Cain
---
target/hexagon/hex_common.py | 51
1 file changed, 51 deletions(-)
diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
index ca5e9630c1..195620c7ec 100755
--- a/target/hexagon/hex_common.py
+++ b/target/hexagon/hex_common.py
@@ -33,9 +33,6 @@
overrides = {} # tags with helper overrides
idef_parser_enabled = {} # tags enabled for idef-parser
-def bad_register(regtype, regid):
-raise Exception(f"Bad register parse: regtype '{regtype}' regid '{regid}'")
-
# We should do this as a hash for performance,
# but to keep order let's keep it as a list.
def uniquify(seq):
@@ -200,46 +197,6 @@ def get_tagimms():
return dict(zip(tags, list(map(compute_tag_immediates, tags
-def is_pair(regid):
-return len(regid) == 2
-
-
-def is_single(regid):
-return len(regid) == 1
-
-
-def is_written(regid):
-return regid[0] in "dexy"
-
-
-def is_writeonly(regid):
-return regid[0] in "de"
-
-
-def is_read(regid):
-return regid[0] in "stuvwxy"
-
-
-def is_readwrite(regid):
-return regid[0] in "xy"
-
-
-def is_scalar_reg(regtype):
-return regtype in "RPC"
-
-
-def is_hvx_reg(regtype):
-return regtype in "VQ"
-
-
-def is_old_val(regtype, regid, tag):
-return regtype + regid + "V" in semdict[tag]
-
-
-def is_new_val(regtype, regid, tag):
-return regtype + regid + "N" in semdict[tag]
-
-
def need_slot(tag):
if (
"A_CVI_SCATTER" not in attribdict[tag]
@@ -280,14 +237,6 @@ def skip_qemu_helper(tag):
return tag in overrides.keys()
-def is_tmp_result(tag):
-return "A_CVI_TMP" in attribdict[tag] or "A_CVI_TMP_DST" in attribdict[tag]
-
-
-def is_new_result(tag):
-return "A_CVI_NEW" in attribdict[tag]
-
-
def is_idef_parser_enabled(tag):
return tag in idef_parser_enabled
--
2.25.1
[PULL 10/15] Hexagon (target/hexagon) Remove unused WRITES_PRED_REG attribute
From: Taylor Simpson
This is the only remaining use of the is_written function. We will
remove it in the subsequent commit.
Signed-off-by: Taylor Simpson
Reviewed-by: Brian Cain
Message-Id: <20231210220712.491494-9-ltaylorsimp...@gmail.com>
Signed-off-by: Brian Cain
---
target/hexagon/attribs_def.h.inc | 1 -
target/hexagon/hex_common.py | 11 ---
2 files changed, 12 deletions(-)
diff --git a/target/hexagon/attribs_def.h.inc b/target/hexagon/attribs_def.h.inc
index 21d457fa4a..87942d46f4 100644
--- a/target/hexagon/attribs_def.h.inc
+++ b/target/hexagon/attribs_def.h.inc
@@ -117,7 +117,6 @@ DEF_ATTRIB(IMPLICIT_READS_P1, "Reads the P1 register", "",
"")
DEF_ATTRIB(IMPLICIT_READS_P2, "Reads the P2 register", "", "")
DEF_ATTRIB(IMPLICIT_READS_P3, "Reads the P3 register", "", "")
DEF_ATTRIB(IMPLICIT_WRITES_USR, "May write USR", "", "")
-DEF_ATTRIB(WRITES_PRED_REG, "Writes a predicate register", "", "")
DEF_ATTRIB(COMMUTES, "The operation is communitive", "", "")
DEF_ATTRIB(DEALLOCRET, "dealloc_return", "", "")
DEF_ATTRIB(DEALLOCFRAME, "deallocframe", "", "")
diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
index 4565dd1953..ca5e9630c1 100755
--- a/target/hexagon/hex_common.py
+++ b/target/hexagon/hex_common.py
@@ -94,10 +94,6 @@ def is_cond_call(tag):
def calculate_attribs():
add_qemu_macro_attrib("fREAD_PC", "A_IMPLICIT_READS_PC")
add_qemu_macro_attrib("fTRAP", "A_IMPLICIT_READS_PC")
-add_qemu_macro_attrib("fWRITE_P0", "A_WRITES_PRED_REG")
-add_qemu_macro_attrib("fWRITE_P1", "A_WRITES_PRED_REG")
-add_qemu_macro_attrib("fWRITE_P2", "A_WRITES_PRED_REG")
-add_qemu_macro_attrib("fWRITE_P3", "A_WRITES_PRED_REG")
add_qemu_macro_attrib("fSET_OVERFLOW", "A_IMPLICIT_WRITES_USR")
add_qemu_macro_attrib("fSET_LPCFG", "A_IMPLICIT_WRITES_USR")
add_qemu_macro_attrib("fLOAD", "A_SCALAR_LOAD")
@@ -122,13 +118,6 @@ def calculate_attribs():
continue
macro = macros[macname]
attribdict[tag] |= set(macro.attribs)
-# Figure out which instructions write predicate registers
-tagregs = get_tagregs()
-for tag in tags:
-regs = tagregs[tag]
-for regtype, regid in regs:
-if regtype == "P" and is_written(regid):
-attribdict[tag].add("A_WRITES_PRED_REG")
# Mark conditional jumps and calls
# Not all instructions are properly marked with A_CONDEXEC
for tag in tags:
--
2.25.1
[PULL 07/15] Hexagon (target/hexagon) Make generators object oriented - gen_idef_parser_funcs
From: Taylor Simpson
Signed-off-by: Taylor Simpson
Reviewed-by: Brian Cain
Message-Id: <20231210220712.491494-6-ltaylorsimp...@gmail.com>
Signed-off-by: Brian Cain
---
target/hexagon/gen_idef_parser_funcs.py | 20
1 file changed, 4 insertions(+), 16 deletions(-)
diff --git a/target/hexagon/gen_idef_parser_funcs.py
b/target/hexagon/gen_idef_parser_funcs.py
index f4518e653f..550a48cb7b 100644
--- a/target/hexagon/gen_idef_parser_funcs.py
+++ b/target/hexagon/gen_idef_parser_funcs.py
@@ -46,6 +46,7 @@ def main():
hex_common.read_semantics_file(sys.argv[1])
hex_common.read_attribs_file(sys.argv[2])
hex_common.calculate_attribs()
+hex_common.init_registers()
tagregs = hex_common.get_tagregs()
tagimms = hex_common.get_tagimms()
@@ -132,22 +133,9 @@ def main():
arguments = []
for regtype, regid in regs:
-prefix = "in " if hex_common.is_read(regid) else ""
-
-is_pair = hex_common.is_pair(regid)
-is_single_old = hex_common.is_single(regid) and
hex_common.is_old_val(
-regtype, regid, tag
-)
-is_single_new = hex_common.is_single(regid) and
hex_common.is_new_val(
-regtype, regid, tag
-)
-
-if is_pair or is_single_old:
-arguments.append(f"{prefix}{regtype}{regid}V")
-elif is_single_new:
-arguments.append(f"{prefix}{regtype}{regid}N")
-else:
-hex_common.bad_register(regtype, regid)
+reg = hex_common.get_register(tag, regtype, regid)
+prefix = "in " if reg.is_read() else ""
+arguments.append(f"{prefix}{reg.reg_tcg()}")
for immlett, bits, immshift in imms:
arguments.append(hex_common.imm_name(immlett))
--
2.25.1
[PULL 04/15] Hexagon (target/hexagon) Make generators object oriented - gen_tcg_funcs
From: Taylor Simpson
The generators are generally a bunch of Python if-then-else
statements based on the regtype and regid. Encapsulate regtype/regid
into a class hierarchy. Clients lookup the register and invoke
methods.
This has several advantages for making the code easier to read,
understand, and maintain
- The class name makes it more clear what the operand does
- All the methods for a given type of operand are together
- Don't need hex_common.bad_register
If a regtype/regid is missing, the lookup in hex_common.get_register
will fail
- We can remove the functions in hex_common that use regtype/regid
(e.g., is_read)
This patch creates the class hierarchy in hex_common and converts
gen_tcg_funcs.py. The other scripts will be converted in subsequent
patches in this series.
Signed-off-by: Taylor Simpson
Reviewed-by: Brian Cain
Message-Id: <20231210220712.491494-3-ltaylorsimp...@gmail.com>
Signed-off-by: Brian Cain
---
target/hexagon/gen_tcg_funcs.py | 571 ++-
target/hexagon/hex_common.py| 659
2 files changed, 683 insertions(+), 547 deletions(-)
diff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs.py
index 02d93bc5ce..3d8e3cb6a2 100755
--- a/target/hexagon/gen_tcg_funcs.py
+++ b/target/hexagon/gen_tcg_funcs.py
@@ -23,466 +23,13 @@
import hex_common
-##
-## Helpers for gen_tcg_func
-##
-def gen_decl_ea_tcg(f, tag):
-f.write("TCGv EA G_GNUC_UNUSED = tcg_temp_new();\n")
-
-
-def genptr_decl_pair_writable(f, tag, regtype, regid, regno):
-regN = f"{regtype}{regid}N"
-if regtype == "R":
-f.write(f"const int {regN} = insn->regno[{regno}];\n")
-elif regtype == "C":
-f.write(f"const int {regN} = insn->regno[{regno}] +
HEX_REG_SA0;\n")
-else:
-hex_common.bad_register(regtype, regid)
-f.write(f"TCGv_i64 {regtype}{regid}V = " f"get_result_gpr_pair(ctx,
{regN});\n")
-
-
-def genptr_decl_writable(f, tag, regtype, regid, regno):
-regN = f"{regtype}{regid}N"
-if regtype == "R":
-f.write(f"const int {regN} = insn->regno[{regno}];\n")
-f.write(f"TCGv {regtype}{regid}V = get_result_gpr(ctx, {regN});\n")
-elif regtype == "C":
-f.write(f"const int {regN} = insn->regno[{regno}] +
HEX_REG_SA0;\n")
-f.write(f"TCGv {regtype}{regid}V = get_result_gpr(ctx, {regN});\n")
-elif regtype == "P":
-f.write(f"const int {regN} = insn->regno[{regno}];\n")
-f.write(f"TCGv {regtype}{regid}V = tcg_temp_new();\n")
-else:
-hex_common.bad_register(regtype, regid)
-
-
-def genptr_decl(f, tag, regtype, regid, regno):
-regN = f"{regtype}{regid}N"
-if regtype == "R":
-if regid in {"ss", "tt"}:
-f.write(f"TCGv_i64 {regtype}{regid}V = tcg_temp_new_i64();\n")
-f.write(f"const int {regN} = insn->regno[{regno}];\n")
-elif regid in {"dd", "ee", "xx", "yy"}:
-genptr_decl_pair_writable(f, tag, regtype, regid, regno)
-elif regid in {"s", "t", "u", "v"}:
-f.write(
-f"TCGv {regtype}{regid}V = "
f"hex_gpr[insn->regno[{regno}]];\n"
-)
-elif regid in {"d", "e", "x", "y"}:
-genptr_decl_writable(f, tag, regtype, regid, regno)
-else:
-hex_common.bad_register(regtype, regid)
-elif regtype == "P":
-if regid in {"s", "t", "u", "v"}:
-f.write(
-f"TCGv {regtype}{regid}V = "
f"hex_pred[insn->regno[{regno}]];\n"
-)
-elif regid in {"d", "e", "x"}:
-genptr_decl_writable(f, tag, regtype, regid, regno)
-else:
-hex_common.bad_register(regtype, regid)
-elif regtype == "C":
-if regid == "ss":
-f.write(f"TCGv_i64 {regtype}{regid}V = "
f"tcg_temp_new_i64();\n")
-f.write(f"const int {regN} = insn->regno[{regno}] + "
"HEX_REG_SA0;\n")
-elif regid == "dd":
-genptr_decl_pair_writable(f, tag, regtype, regid, regno)
-elif regid == "s":
-f.write(f"TCGv {regtype}{regid}V = tcg_temp_new();\n")
-f.write(
-f"const int {regtype}{regid}N = insn->regno[{regno}] + "
-"HEX_REG_SA0;\n"
-)
-elif regid
[PULL 15/15] target/hexagon: reduce scope of def_regnum, remove dead assignment
This is intended to address a coverity finding: CID 1527408.
Signed-off-by: Brian Cain
Reviewed-by: Matheus Tavares Bernardino
Message-Id: <20240114234453.4114587-1-bc...@quicinc.com>
---
target/hexagon/mmvec/decode_ext_mmvec.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/target/hexagon/mmvec/decode_ext_mmvec.c
b/target/hexagon/mmvec/decode_ext_mmvec.c
index 174eb3b78b..202d84c7c0 100644
--- a/target/hexagon/mmvec/decode_ext_mmvec.c
+++ b/target/hexagon/mmvec/decode_ext_mmvec.c
@@ -33,7 +33,6 @@ check_new_value(Packet *pkt)
const char *dststr = NULL;
uint16_t def_opcode;
char letter;
-int def_regnum;
for (i = 1; i < pkt->num_insns; i++) {
uint16_t use_opcode = pkt->insn[i].opcode;
@@ -78,7 +77,6 @@ check_new_value(Packet *pkt)
}
}
if ((dststr == NULL) && GET_ATTRIB(def_opcode, A_CVI_GATHER)) {
-def_regnum = 0;
pkt->insn[i].regno[use_regidx] = def_oreg;
pkt->insn[i].new_value_producer_slot = pkt->insn[def_idx].slot;
} else {
@@ -86,7 +84,7 @@ check_new_value(Packet *pkt)
/* still not there, we have a bad packet */
g_assert_not_reached();
}
-def_regnum = pkt->insn[def_idx].regno[dststr - reginfo];
+int def_regnum = pkt->insn[def_idx].regno[dststr - reginfo];
/* Now patch up the consumer with the register number */
pkt->insn[i].regno[use_regidx] = def_regnum ^ def_oreg;
/* special case for (Vx,Vy) */
--
2.25.1
[PULL 13/15] Hexagon (target/hexagon) Use QEMU decodetree (16-bit instructions)
From: Taylor Simpson
Section 10.3 of the Hexagon V73 Programmer's Reference Manual
A duplex is encoded as a 32-bit instruction with bits [15:14] set to 00.
The sub-instructions that comprise a duplex are encoded as 13-bit fields
in the duplex.
Create a decoder for each subinstruction class (a, l1, l2, s1, s2).
Extend gen_trans_funcs.py to handle all instructions rather than
filter by instruction class.
There is a g_assert_not_reached() in decode_insns() in decode.c to
verify we never try to use the old decoder on 16-bit instructions.
Signed-off-by: Taylor Simpson
Reviewed-by: Brian Cain
Message-Id: <20240115221443.365287-3-ltaylorsimp...@gmail.com>
Signed-off-by: Brian Cain
---
target/hexagon/README | 1 +
target/hexagon/decode.c | 85 +
target/hexagon/gen_decodetree.py | 12 -
target/hexagon/gen_trans_funcs.py | 12 +
target/hexagon/meson.build| 90 +++
5 files changed, 188 insertions(+), 12 deletions(-)
diff --git a/target/hexagon/README b/target/hexagon/README
index 1b2a4d0eac..746ebec378 100644
--- a/target/hexagon/README
+++ b/target/hexagon/README
@@ -195,6 +195,7 @@ Step 1 is to run target/hexagon/gen_dectree_import.c to
produce
Step 2 is to import iset.py into target/hexagon/gen_decodetree.py to produce
/target/hexagon/normal_decode_generated
/target/hexagon/hvx_decode_generated
+/target/hexagon/subinsn_*_decode_generated
Step 3 is to process the above files with QEMU's decodetree.py to produce
/target/hexagon/decode_*_generated.c.inc
Step 4 is to import iset.py into target/hexagon/gen_trans_funcs.py to produce
diff --git a/target/hexagon/decode.c b/target/hexagon/decode.c
index bddad1f75e..160b23a895 100644
--- a/target/hexagon/decode.c
+++ b/target/hexagon/decode.c
@@ -60,6 +60,7 @@ static int decode_mapped_reg_##NAME(DisasContext *ctx, int x)
\
}
DECODE_MAPPED(R_16)
DECODE_MAPPED(R_8)
+DECODE_MAPPED(R__8)
/* Helper function for decodetree_trans_funcs_generated.c.inc */
static int shift_left(DisasContext *ctx, int x, int n, int immno)
@@ -77,6 +78,13 @@ static int shift_left(DisasContext *ctx, int x, int n, int
immno)
#include "decode_normal_generated.c.inc"
#include "decode_hvx_generated.c.inc"
+/* Include the generated decoder for 16 bit insn */
+#include "decode_subinsn_a_generated.c.inc"
+#include "decode_subinsn_l1_generated.c.inc"
+#include "decode_subinsn_l2_generated.c.inc"
+#include "decode_subinsn_s1_generated.c.inc"
+#include "decode_subinsn_s2_generated.c.inc"
+
/* Include the generated helpers for the decoder */
#include "decodetree_trans_funcs_generated.c.inc"
@@ -790,6 +798,63 @@ decode_insns_tablewalk(Insn *insn, const DectreeTable
*table,
}
}
+/*
+ * Section 10.3 of the Hexagon V73 Programmer's Reference Manual
+ *
+ * A duplex is encoded as a 32-bit instruction with bits [15:14] set to 00.
+ * The sub-instructions that comprise a duplex are encoded as 13-bit fields
+ * in the duplex.
+ *
+ * Per table 10-4, the 4-bit duplex iclass is encoded in bits 31:29, 13
+ */
+static uint32_t get_duplex_iclass(uint32_t encoding)
+{
+uint32_t iclass = extract32(encoding, 13, 1);
+iclass = deposit32(iclass, 1, 3, extract32(encoding, 29, 3));
+return iclass;
+}
+
+/*
+ * Per table 10-5, the duplex ICLASS field values that specify the group of
+ * each sub-instruction in a duplex
+ *
+ * This table points to the decode instruction for each entry in the table
+ */
+typedef bool (*subinsn_decode_func)(DisasContext *ctx, uint16_t insn);
+typedef struct {
+subinsn_decode_func decode_slot0_subinsn;
+subinsn_decode_func decode_slot1_subinsn;
+} subinsn_decode_groups;
+
+static const subinsn_decode_groups decode_groups[16] = {
+[0x0] = { decode_subinsn_l1, decode_subinsn_l1 },
+[0x1] = { decode_subinsn_l2, decode_subinsn_l1 },
+[0x2] = { decode_subinsn_l2, decode_subinsn_l2 },
+[0x3] = { decode_subinsn_a, decode_subinsn_a },
+[0x4] = { decode_subinsn_l1, decode_subinsn_a },
+[0x5] = { decode_subinsn_l2, decode_subinsn_a },
+[0x6] = { decode_subinsn_s1, decode_subinsn_a },
+[0x7] = { decode_subinsn_s2, decode_subinsn_a },
+[0x8] = { decode_subinsn_s1, decode_subinsn_l1 },
+[0x9] = { decode_subinsn_s1, decode_subinsn_l2 },
+[0xa] = { decode_subinsn_s1, decode_subinsn_s1 },
+[0xb] = { decode_subinsn_s2, decode_subinsn_s1 },
+[0xc] = { decode_subinsn_s2, decode_subinsn_l1 },
+[0xd] = { decode_subinsn_s2, decode_subinsn_l2 },
+[0xe] = { decode_subinsn_s2, decode_subinsn_s2 },
+[0xf] = { NULL, NULL }, /* Reserved */
+};
+
+static uint16_t get_slot0_subinsn(uint32_t encoding)
+{
+return extract32(encoding, 0, 13);
+}
+
+static uint16_t get_slot1_subinsn(uint32_t encoding)
+{
+return extract32(encoding, 16, 13);
+}
+
static unsigned int
decode_insns(
[PULL 01/15] tests/docker: Hexagon toolchain update
This update includes support for privileged instructions.
Signed-off-by: Brian Cain
Reviewed-by: Matheus Tavares Bernardino
Tested-by: Matheus Tavares Bernardino
Message-Id: <20240114232354.4109231-1-bc...@quicinc.com>
---
tests/docker/dockerfiles/debian-hexagon-cross.docker | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tests/docker/dockerfiles/debian-hexagon-cross.docker
b/tests/docker/dockerfiles/debian-hexagon-cross.docker
index 7c38d7c9e4..60bd8faa20 100644
--- a/tests/docker/dockerfiles/debian-hexagon-cross.docker
+++ b/tests/docker/dockerfiles/debian-hexagon-cross.docker
@@ -38,9 +38,9 @@ RUN apt-get update && \
RUN /usr/bin/pip3 install tomli
ENV TOOLCHAIN_INSTALL /opt
-ENV TOOLCHAIN_RELEASE 16.0.0
+ENV TOOLCHAIN_RELEASE 12.Dec.2023
ENV TOOLCHAIN_BASENAME
"clang+llvm-${TOOLCHAIN_RELEASE}-cross-hexagon-unknown-linux-musl"
-ENV TOOLCHAIN_URL
https://codelinaro.jfrog.io/artifactory/codelinaro-toolchain-for-hexagon/v${TOOLCHAIN_RELEASE}/${TOOLCHAIN_BASENAME}.tar.xz
+ENV TOOLCHAIN_URL
https://codelinaro.jfrog.io/artifactory/codelinaro-toolchain-for-hexagon/${TOOLCHAIN_RELEASE}/${TOOLCHAIN_BASENAME}.tar.xz
ENV CCACHE_WRAPPERSDIR "/usr/libexec/ccache-wrappers"
RUN curl -#SL "$TOOLCHAIN_URL" | tar -xJC "$TOOLCHAIN_INSTALL"
--
2.25.1
[PULL 02/15] Hexagon (target/hexagon) Fix shadow variable when idef-parser is off
From: Taylor Simpson
Adding -Werror=shadow=compatible-local causes Hexagon not to build
when idef-parser is off. The "label" variable in CHECK_NOSHUF_PRED
shadows a variable in the surrounding code.
Signed-off-by: Taylor Simpson
Reviewed-by: Brian Cain
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20231130183955.54314-1-ltaylorsimp...@gmail.com>
Signed-off-by: Brian Cain
---
target/hexagon/macros.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
index 9a51b5709b..f99390e2a8 100644
--- a/target/hexagon/macros.h
+++ b/target/hexagon/macros.h
@@ -93,13 +93,13 @@
#define CHECK_NOSHUF_PRED(GET_EA, SIZE, PRED) \
do { \
-TCGLabel *label = gen_new_label(); \
-tcg_gen_brcondi_tl(TCG_COND_EQ, PRED, 0, label); \
+TCGLabel *noshuf_label = gen_new_label(); \
+tcg_gen_brcondi_tl(TCG_COND_EQ, PRED, 0, noshuf_label); \
GET_EA; \
if (insn->slot == 0 && ctx->pkt->pkt_has_store_s1) { \
probe_noshuf_load(EA, SIZE, ctx->mem_idx); \
} \
-gen_set_label(label); \
+gen_set_label(noshuf_label); \
if (insn->slot == 0 && ctx->pkt->pkt_has_store_s1) { \
process_store(ctx, 1); \
} \
--
2.25.1
[PULL 12/15] Hexagon (target/hexagon) Use QEMU decodetree (32-bit instructions)
From: Taylor Simpson
The Decodetree Specification can be found here
https://www.qemu.org/docs/master/devel/decodetree.html
Covers all 32-bit instructions, including HVX
We generate separate decoders for each instruction class. The reason
will be more apparent in the next patch in this series.
We add 2 new scripts
gen_decodetree.pyGenerate the input to decodetree.py
gen_trans_funcs.py Generate the trans_* functions used by the
output of decodetree.py
Since the functions generated by decodetree.py take DisasContext * as an
argument, we add the argument to a couple of functions that didn't need
it previously. We also set the insn field in DisasContext during decode
because it is used by the trans_* functions.
There is a g_assert_not_reached() in decode_insns() in decode.c to
verify we never try to use the old decoder on 32-bit instructions
Signed-off-by: Taylor Simpson
Reviewed-by: Brian Cain
Message-Id: <20240115221443.365287-2-ltaylorsimp...@gmail.com>
Signed-off-by: Brian Cain
---
target/hexagon/README | 13 +-
target/hexagon/decode.c | 54 -
target/hexagon/decode.h | 5 +-
target/hexagon/gen_decodetree.py | 190 ++
target/hexagon/gen_trans_funcs.py | 132 +
target/hexagon/meson.build| 55 +
target/hexagon/translate.c| 4 +-
7 files changed, 439 insertions(+), 14 deletions(-)
create mode 100755 target/hexagon/gen_decodetree.py
create mode 100755 target/hexagon/gen_trans_funcs.py
diff --git a/target/hexagon/README b/target/hexagon/README
index 69b2ffe9bb..1b2a4d0eac 100644
--- a/target/hexagon/README
+++ b/target/hexagon/README
@@ -189,11 +189,16 @@ the packet, and we mark the implicit writes. After the
analysis is performed,
we initialize the result register for each of the predicated assignments.
In addition to instruction semantics, we use a generator to create the decode
-tree. This generation is also a two step process. The first step is to run
-target/hexagon/gen_dectree_import.c to produce
+tree. This generation is a four step process.
+Step 1 is to run target/hexagon/gen_dectree_import.c to produce
/target/hexagon/iset.py
-This file is imported by target/hexagon/dectree.py to produce
-/target/hexagon/dectree_generated.h.inc
+Step 2 is to import iset.py into target/hexagon/gen_decodetree.py to produce
+/target/hexagon/normal_decode_generated
+/target/hexagon/hvx_decode_generated
+Step 3 is to process the above files with QEMU's decodetree.py to produce
+/target/hexagon/decode_*_generated.c.inc
+Step 4 is to import iset.py into target/hexagon/gen_trans_funcs.py to produce
+/target/hexagon/decodetree_trans_funcs_generated.c.inc
*** Key Files ***
diff --git a/target/hexagon/decode.c b/target/hexagon/decode.c
index 946c55cc71..bddad1f75e 100644
--- a/target/hexagon/decode.c
+++ b/target/hexagon/decode.c
@@ -52,6 +52,34 @@ DEF_REGMAP(R_8, 8, 0, 1, 2, 3, 4, 5, 6, 7)
#define DECODE_MAPPED_REG(OPNUM, NAME) \
insn->regno[OPNUM] = DECODE_REGISTER_##NAME[insn->regno[OPNUM]];
+/* Helper functions for decode_*_generated.c.inc */
+#define DECODE_MAPPED(NAME) \
+static int decode_mapped_reg_##NAME(DisasContext *ctx, int x) \
+{ \
+return DECODE_REGISTER_##NAME[x]; \
+}
+DECODE_MAPPED(R_16)
+DECODE_MAPPED(R_8)
+
+/* Helper function for decodetree_trans_funcs_generated.c.inc */
+static int shift_left(DisasContext *ctx, int x, int n, int immno)
+{
+int ret = x;
+Insn *insn = ctx->insn;
+if (!insn->extension_valid ||
+insn->which_extended != immno) {
+ret <<= n;
+}
+return ret;
+}
+
+/* Include the generated decoder for 32 bit insn */
+#include "decode_normal_generated.c.inc"
+#include "decode_hvx_generated.c.inc"
+
+/* Include the generated helpers for the decoder */
+#include "decodetree_trans_funcs_generated.c.inc"
+
typedef struct {
const struct DectreeTable *table_link;
const struct DectreeTable *table_link_b;
@@ -550,7 +578,8 @@ apply_extender(Packet *pkt, int i, uint32_t extender)
int immed_num;
uint32_t base_immed;
-immed_num = opcode_which_immediate_is_extended(pkt->insn[i].opcode);
+immed_num = pkt->insn[i].which_extended;
+g_assert(immed_num ==
opcode_which_immediate_is_extended(pkt->insn[i].opcode));
base_immed = pkt->insn[i].immed[immed_num];
pkt->insn[i].immed[immed_num] = extender | fZXTN(6, 32, base_immed);
@@ -762,12 +791,19 @@ decode_insns_tablewalk(Insn *insn, const DectreeTable
*table,
}
static unsigned int
-decode_insns(Insn *insn, uint32_t encoding)
+decode_insns(DisasContext *ctx, Insn *insn, uint32_t encoding)
{
const DectreeTable *table;
if (parse_bits(encoding) != 0) {
+if (decode_normal(ctx, encoding) ||
+decode_hvx(ctx, encoding)) {
+insn->gene
[PULL 06/15] Hexagon (target/hexagon) Make generators object oriented - gen_helper_funcs
From: Taylor Simpson
Signed-off-by: Taylor Simpson
Reviewed-by: Brian Cain
Message-Id: <20231210220712.491494-5-ltaylorsimp...@gmail.com>
Signed-off-by: Brian Cain
---
target/hexagon/gen_helper_funcs.py | 370 +
target/hexagon/hex_common.py | 48 +++-
2 files changed, 104 insertions(+), 314 deletions(-)
diff --git a/target/hexagon/gen_helper_funcs.py
b/target/hexagon/gen_helper_funcs.py
index ce21d3b688..9cc3d69c49 100755
--- a/target/hexagon/gen_helper_funcs.py
+++ b/target/hexagon/gen_helper_funcs.py
@@ -23,181 +23,14 @@
import hex_common
-##
-## Helpers for gen_helper_function
-##
-def gen_decl_ea(f):
-f.write("uint32_t EA;\n")
-
-
-def gen_helper_return_type(f, regtype, regid, regno):
-if regno > 1:
-f.write(", ")
-f.write("int32_t")
-
-
-def gen_helper_return_type_pair(f, regtype, regid, regno):
-if regno > 1:
-f.write(", ")
-f.write("int64_t")
-
-
-def gen_helper_arg(f, regtype, regid, regno):
-if regno > 0:
-f.write(", ")
-f.write(f"int32_t {regtype}{regid}V")
-
-
-def gen_helper_arg_new(f, regtype, regid, regno):
-if regno >= 0:
-f.write(", ")
-f.write(f"int32_t {regtype}{regid}N")
-
-
-def gen_helper_arg_pair(f, regtype, regid, regno):
-if regno >= 0:
-f.write(", ")
-f.write(f"int64_t {regtype}{regid}V")
-
-
-def gen_helper_arg_ext(f, regtype, regid, regno):
-if regno > 0:
-f.write(", ")
-f.write(f"void *{regtype}{regid}V_void")
-
-
-def gen_helper_arg_ext_pair(f, regtype, regid, regno):
-if regno > 0:
-f.write(", ")
-f.write(f"void *{regtype}{regid}V_void")
-
-
-def gen_helper_arg_opn(f, regtype, regid, i, tag):
-if hex_common.is_pair(regid):
-if hex_common.is_hvx_reg(regtype):
-gen_helper_arg_ext_pair(f, regtype, regid, i)
-else:
-gen_helper_arg_pair(f, regtype, regid, i)
-elif hex_common.is_single(regid):
-if hex_common.is_old_val(regtype, regid, tag):
-if hex_common.is_hvx_reg(regtype):
-gen_helper_arg_ext(f, regtype, regid, i)
-else:
-gen_helper_arg(f, regtype, regid, i)
-elif hex_common.is_new_val(regtype, regid, tag):
-gen_helper_arg_new(f, regtype, regid, i)
-else:
-hex_common.bad_register(regtype, regid)
-else:
-hex_common.bad_register(regtype, regid)
-
-
-def gen_helper_arg_imm(f, immlett):
-f.write(f", int32_t {hex_common.imm_name(immlett)}")
-
-
-def gen_helper_dest_decl(f, regtype, regid, regno, subfield=""):
-f.write(f"int32_t {regtype}{regid}V{subfield} = 0;\n")
-
-
-def gen_helper_dest_decl_pair(f, regtype, regid, regno, subfield=""):
-f.write(f"int64_t {regtype}{regid}V{subfield} = 0;\n")
-
-
-def gen_helper_dest_decl_ext(f, regtype, regid):
-if regtype == "Q":
-f.write(
-f"/* {regtype}{regid}V is *(MMQReg *)"
f"({regtype}{regid}V_void) */\n"
-)
-else:
-f.write(
-f"/* {regtype}{regid}V is *(MMVector *)"
-f"({regtype}{regid}V_void) */\n"
-)
-
-
-def gen_helper_dest_decl_ext_pair(f, regtype, regid, regno):
-f.write(
-f"/* {regtype}{regid}V is *(MMVectorPair *))"
-f"{regtype}{regid}V_void) */\n"
-)
-
-
-def gen_helper_dest_decl_opn(f, regtype, regid, i):
-if hex_common.is_pair(regid):
-if hex_common.is_hvx_reg(regtype):
-gen_helper_dest_decl_ext_pair(f, regtype, regid, i)
-else:
-gen_helper_dest_decl_pair(f, regtype, regid, i)
-elif hex_common.is_single(regid):
-if hex_common.is_hvx_reg(regtype):
-gen_helper_dest_decl_ext(f, regtype, regid)
-else:
-gen_helper_dest_decl(f, regtype, regid, i)
-else:
-hex_common.bad_register(regtype, regid)
-
-
-def gen_helper_src_var_ext(f, regtype, regid):
-if regtype == "Q":
-f.write(
-f"/* {regtype}{regid}V is *(MMQReg *)"
f"({regtype}{regid}V_void) */\n"
-)
-else:
-f.write(
-f"/* {regtype}{regid}V is *(MMVector *)"
-f"({regtype}{regid}V_void) */\n"
-)
-
-
-def gen_helper_src_var_ext_pair(f, regtype, regid, regno):
-f.write(
-f"/* {regtype}{regid}V{regno} is *(MMVectorPair *)"
-f"({regtype}{regid}V{regno}_void) */\n"
-)
-
-
-def gen_helper_return(f, regtype, regid, regno):
-f.write(f"return {regtype}{regid}V;\n")
-
-
-def gen_helper_return_pair(f, regtype, regid, regno):
-f.write(f&qu
[PULL 14/15] Hexagon (target/hexagon) Remove old dectree.py
From: Taylor Simpson
Now that we are using QEMU decodetree.py, remove the old decoder
Signed-off-by: Taylor Simpson
Reviewed-by: Brian Cain
Message-Id: <20240115221443.365287-4-ltaylorsimp...@gmail.com>
Signed-off-by: Brian Cain
---
target/hexagon/decode.c | 344
target/hexagon/dectree.py | 403
target/hexagon/gen_dectree_import.c | 49
target/hexagon/meson.build | 12 -
target/hexagon/opcodes.c| 29 --
target/hexagon/opcodes.h| 2 -
6 files changed, 839 deletions(-)
delete mode 100755 target/hexagon/dectree.py
diff --git a/target/hexagon/decode.c b/target/hexagon/decode.c
index 160b23a895..a40210ca1e 100644
--- a/target/hexagon/decode.c
+++ b/target/hexagon/decode.c
@@ -88,175 +88,6 @@ static int shift_left(DisasContext *ctx, int x, int n, int
immno)
/* Include the generated helpers for the decoder */
#include "decodetree_trans_funcs_generated.c.inc"
-typedef struct {
-const struct DectreeTable *table_link;
-const struct DectreeTable *table_link_b;
-Opcode opcode;
-enum {
-DECTREE_ENTRY_INVALID,
-DECTREE_TABLE_LINK,
-DECTREE_SUBINSNS,
-DECTREE_EXTSPACE,
-DECTREE_TERMINAL
-} type;
-} DectreeEntry;
-
-typedef struct DectreeTable {
-unsigned int (*lookup_function)(int startbit, int width, uint32_t opcode);
-unsigned int size;
-unsigned int startbit;
-unsigned int width;
-const DectreeEntry table[];
-} DectreeTable;
-
-#define DECODE_NEW_TABLE(TAG, SIZE, WHATNOT) \
-static const DectreeTable dectree_table_##TAG;
-#define TABLE_LINK(TABLE) /* NOTHING */
-#define TERMINAL(TAG, ENC)/* NOTHING */
-#define SUBINSNS(TAG, CLASSA, CLASSB, ENC)/* NOTHING */
-#define EXTSPACE(TAG, ENC)/* NOTHING */
-#define INVALID() /* NOTHING */
-#define DECODE_END_TABLE(...) /* NOTHING */
-#define DECODE_MATCH_INFO(...)/* NOTHING */
-#define DECODE_LEGACY_MATCH_INFO(...) /* NOTHING */
-#define DECODE_OPINFO(...)/* NOTHING */
-
-#include "dectree_generated.h.inc"
-
-#undef DECODE_OPINFO
-#undef DECODE_MATCH_INFO
-#undef DECODE_LEGACY_MATCH_INFO
-#undef DECODE_END_TABLE
-#undef INVALID
-#undef TERMINAL
-#undef SUBINSNS
-#undef EXTSPACE
-#undef TABLE_LINK
-#undef DECODE_NEW_TABLE
-#undef DECODE_SEPARATOR_BITS
-
-#define DECODE_SEPARATOR_BITS(START, WIDTH) NULL, START, WIDTH
-#define DECODE_NEW_TABLE_HELPER(TAG, SIZE, FN, START, WIDTH) \
-static const DectreeTable dectree_table_##TAG = { \
-.size = SIZE, \
-.lookup_function = FN, \
-.startbit = START, \
-.width = WIDTH, \
-.table = {
-#define DECODE_NEW_TABLE(TAG, SIZE, WHATNOT) \
-DECODE_NEW_TABLE_HELPER(TAG, SIZE, WHATNOT)
-
-#define TABLE_LINK(TABLE) \
-{ .type = DECTREE_TABLE_LINK, .table_link = _table_##TABLE },
-#define TERMINAL(TAG, ENC) \
-{ .type = DECTREE_TERMINAL, .opcode = TAG },
-#define SUBINSNS(TAG, CLASSA, CLASSB, ENC) \
-{ \
-.type = DECTREE_SUBINSNS, \
-.table_link = _table_DECODE_SUBINSN_##CLASSA, \
-.table_link_b = _table_DECODE_SUBINSN_##CLASSB \
-},
-#define EXTSPACE(TAG, ENC) { .type = DECTREE_EXTSPACE },
-#define INVALID() { .type = DECTREE_ENTRY_INVALID, .opcode = XX_LAST_OPCODE },
-
-#define DECODE_END_TABLE(...) } };
-
-#define DECODE_MATCH_INFO(...)/* NOTHING */
-#define DECODE_LEGACY_MATCH_INFO(...) /* NOTHING */
-#define DECODE_OPINFO(...)/* NOTHING */
-
-#include "dectree_generated.h.inc"
-
-#undef DECODE_OPINFO
-#undef DECODE_MATCH_INFO
-#undef DECODE_LEGACY_MATCH_INFO
-#undef DECODE_END_TABLE
-#undef INVALID
-#undef TERMINAL
-#undef SUBINSNS
-#undef EXTSPACE
-#undef TABLE_LINK
-#undef DECODE_NEW_TABLE
-#undef DECODE_NEW_TABLE_HELPER
-#undef DECODE_SEPARATOR_BITS
-
-static const DectreeTable dectree_table_DECODE_EXT_EXT_noext = {
-.size = 1, .lookup_function = NULL, .startbit = 0, .width = 0,
-.table = {
-{ .type = DECTREE_ENTRY_INVALID, .opcode = XX_LAST_OPCODE },
-}
-};
-
-static const DectreeTable *ext_trees[XX_LAST_EXT_IDX];
-
-static void decode_ext_init(void)
-{
-int i;
-for (i = EXT_IDX_noext; i < EXT_IDX_noext_AFTER; i++) {
-ext_trees[i] = _table_DECODE_EXT_EXT_noext;
-}
-for (i = EXT_IDX_mmvec; i < EXT_IDX_mmvec_AFTER; i++) {
-ext_trees[i] = _table_DECODE_EXT_EXT_mmvec;
-}
-}
-
-typedef struct {
-uint32_t mask;
-uint32_t match;
-} DecodeITableEntry;
-
-#define DECODE_NEW_TABLE(TAG, SIZE, WHATNOT) /* NOTHING */
-#define TABLE_LINK(TABLE) /* NOTHING */
-#define TERMINAL(TAG, ENC)/* NOTHING */
-#define SUBINSNS(TAG, CLASSA, CLASSB, ENC)/* NOTHING */
-#define EXTSPACE(TAG, ENC)
[PULL 03/15] Hexagon (target/hexagon) Clean up handling of modifier registers
From: Taylor Simpson
Currently, the register number (MuN) for modifier registers is the
modifier register number rather than the index into hex_gpr. This
patch changes MuN to the hex_gpr index, which is consistent with
the handling of control registers.
Note that HELPER(fcircadd) needs the CS register corresponding to the
modifier register specified in the instruction. We create a TCGv
variable "CS" to hold the value to pass to the helper.
Reviewed-by: Brian Cain
Signed-off-by: Taylor Simpson
Message-Id: <20231210220712.491494-2-ltaylorsimp...@gmail.com>
Signed-off-by: Brian Cain
---
target/hexagon/gen_tcg.h| 9 -
target/hexagon/gen_tcg_funcs.py | 13 +
target/hexagon/idef-parser/parser-helpers.c | 8 +++-
target/hexagon/macros.h | 3 +--
4 files changed, 17 insertions(+), 16 deletions(-)
diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index d992059fce..1c4391b415 100644
--- a/target/hexagon/gen_tcg.h
+++ b/target/hexagon/gen_tcg.h
@@ -68,15 +68,14 @@
do { \
TCGv tcgv_siV = tcg_constant_tl(siV); \
tcg_gen_mov_tl(EA, RxV); \
-gen_helper_fcircadd(RxV, RxV, tcgv_siV, MuV, \
-hex_gpr[HEX_REG_CS0 + MuN]); \
+gen_helper_fcircadd(RxV, RxV, tcgv_siV, MuV, CS); \
} while (0)
#define GET_EA_pcr(SHIFT) \
do { \
TCGv ireg = tcg_temp_new(); \
tcg_gen_mov_tl(EA, RxV); \
gen_read_ireg(ireg, MuV, (SHIFT)); \
-gen_helper_fcircadd(RxV, RxV, ireg, MuV, hex_gpr[HEX_REG_CS0 + MuN]); \
+gen_helper_fcircadd(RxV, RxV, ireg, MuV, CS); \
} while (0)
/* Instructions with multiple definitions */
@@ -113,7 +112,7 @@
TCGv ireg = tcg_temp_new(); \
tcg_gen_mov_tl(EA, RxV); \
gen_read_ireg(ireg, MuV, SHIFT); \
-gen_helper_fcircadd(RxV, RxV, ireg, MuV, hex_gpr[HEX_REG_CS0 + MuN]); \
+gen_helper_fcircadd(RxV, RxV, ireg, MuV, CS); \
LOAD; \
} while (0)
@@ -427,7 +426,7 @@
TCGv BYTE G_GNUC_UNUSED = tcg_temp_new(); \
tcg_gen_mov_tl(EA, RxV); \
gen_read_ireg(ireg, MuV, SHIFT); \
-gen_helper_fcircadd(RxV, RxV, ireg, MuV, hex_gpr[HEX_REG_CS0 + MuN]); \
+gen_helper_fcircadd(RxV, RxV, ireg, MuV, CS); \
STORE; \
} while (0)
diff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs.py
index f5246cee6d..02d93bc5ce 100755
--- a/target/hexagon/gen_tcg_funcs.py
+++ b/target/hexagon/gen_tcg_funcs.py
@@ -99,10 +99,15 @@ def genptr_decl(f, tag, regtype, regid, regno):
hex_common.bad_register(regtype, regid)
elif regtype == "M":
if regid == "u":
-f.write(f"const int {regtype}{regid}N = "
f"insn->regno[{regno}];\n")
f.write(
-f"TCGv {regtype}{regid}V = hex_gpr[{regtype}{regid}N + "
-"HEX_REG_M0];\n"
+f"const int {regN} = insn->regno[{regno}] + HEX_REG_M0;\n"
+)
+f.write(
+f"TCGv {regtype}{regid}V = hex_gpr[{regN}];\n"
+)
+f.write(
+f"TCGv CS G_GNUC_UNUSED = "
+f"hex_gpr[{regN} - HEX_REG_M0 + HEX_REG_CS0];\n"
)
else:
hex_common.bad_register(regtype, regid)
@@ -528,7 +533,7 @@ def gen_tcg_func(f, tag, regs, imms):
):
declared.append(f"{regtype}{regid}V")
if regtype == "M":
-declared.append(f"{regtype}{regid}N")
+declared.append("CS")
elif hex_common.is_new_val(regtype, regid, tag):
declared.append(f"{regtype}{regid}N")
else:
diff --git a/target/hexagon/idef-parser/parser-helpers.c
b/target/hexagon/idef-parser/parser-helpers.c
index 4af020933a..95f2b43076 100644
--- a/target/hexagon/idef-parser/parser-helpers.c
+++ b/target/hexagon/idef-parser/parser-helpers.c
@@ -1541,10 +1541,8 @@ void gen_circ_op(Context *c,
HexValue *increment,
HexValue *modifier)
{
-HexValue cs = gen_tmp(c, locp, 32, UNSIGNED);
HexValue increment_m = *increment;
increment_m = rvalue_materialize(c, locp, _m);
-OUT(c, locp, "gen_read_reg(", , ", HEX_REG_CS0 + MuN);\n");
OUT(c,
locp,
"gen_helper_fcircadd(",
@@ -1555,7 +1553,7 @@ void gen_circ_op(Context *c,
_m,
", ",
modifier);
-OUT(c, locp, ", ", , ");\n");
+OUT(c, locp, ", CS);\n");
}
HexValue gen_locnt_op(Context *c, YYLTYPE *locp, HexValue *src)
@@ -2080,9 +2078,9 @@ void emit_arg(Context *c, YYLTYPE *locp, HexValue *arg)
char reg_i
[PULL 05/15] Hexagon (target/hexagon) Make generators object oriented - gen_helper_protos
From: Taylor Simpson
Signed-off-by: Taylor Simpson
Reviewed-by: Brian Cain
Message-Id: <20231210220712.491494-4-ltaylorsimp...@gmail.com>
Signed-off-by: Brian Cain
---
target/hexagon/gen_helper_protos.py | 149 ++--
target/hexagon/hex_common.py| 7 --
2 files changed, 8 insertions(+), 148 deletions(-)
diff --git a/target/hexagon/gen_helper_protos.py
b/target/hexagon/gen_helper_protos.py
index 131043795a..c82b0f54e4 100755
--- a/target/hexagon/gen_helper_protos.py
+++ b/target/hexagon/gen_helper_protos.py
@@ -22,39 +22,6 @@
import string
import hex_common
-##
-## Helpers for gen_helper_prototype
-##
-def_helper_types = {
-"N": "s32",
-"O": "s32",
-"P": "s32",
-"M": "s32",
-"C": "s32",
-"R": "s32",
-"V": "ptr",
-"Q": "ptr",
-}
-
-def_helper_types_pair = {
-"R": "s64",
-"C": "s64",
-"S": "s64",
-"G": "s64",
-"V": "ptr",
-"Q": "ptr",
-}
-
-
-def gen_def_helper_opn(f, tag, regtype, regid, i):
-if hex_common.is_pair(regid):
-f.write(f", {def_helper_types_pair[regtype]}")
-elif hex_common.is_single(regid):
-f.write(f", {def_helper_types[regtype]}")
-else:
-hex_common.bad_register(regtype, regid)
-
-
##
## Generate the DEF_HELPER prototype for an instruction
## For A2_add: Rd32=add(Rs32,Rt32)
@@ -65,116 +32,15 @@ def gen_helper_prototype(f, tag, tagregs, tagimms):
regs = tagregs[tag]
imms = tagimms[tag]
-numresults = 0
-numscalarresults = 0
-numscalarreadwrite = 0
-for regtype, regid in regs:
-if hex_common.is_written(regid):
-numresults += 1
-if hex_common.is_scalar_reg(regtype):
-numscalarresults += 1
-if hex_common.is_readwrite(regid):
-if hex_common.is_scalar_reg(regtype):
-numscalarreadwrite += 1
+declared = []
+ret_type = hex_common.helper_ret_type(tag, regs).proto_arg
+declared.append(ret_type)
-if numscalarresults > 1:
-## The helper is bogus when there is more than one result
-f.write(f"DEF_HELPER_1({tag}, void, env)\n")
-else:
-## Figure out how many arguments the helper will take
-if numscalarresults == 0:
-def_helper_size = len(regs) + len(imms) + numscalarreadwrite + 1
-if hex_common.need_pkt_has_multi_cof(tag):
-def_helper_size += 1
-if hex_common.need_pkt_need_commit(tag):
-def_helper_size += 1
-if hex_common.need_part1(tag):
-def_helper_size += 1
-if hex_common.need_slot(tag):
-def_helper_size += 1
-if hex_common.need_PC(tag):
-def_helper_size += 1
-if hex_common.helper_needs_next_PC(tag):
-def_helper_size += 1
-if hex_common.need_condexec_reg(tag, regs):
-def_helper_size += 1
-f.write(f"DEF_HELPER_{def_helper_size}({tag}")
-## The return type is void
-f.write(", void")
-else:
-def_helper_size = len(regs) + len(imms) + numscalarreadwrite
-if hex_common.need_pkt_has_multi_cof(tag):
-def_helper_size += 1
-if hex_common.need_pkt_need_commit(tag):
-def_helper_size += 1
-if hex_common.need_part1(tag):
-def_helper_size += 1
-if hex_common.need_slot(tag):
-def_helper_size += 1
-if hex_common.need_PC(tag):
-def_helper_size += 1
-if hex_common.need_condexec_reg(tag, regs):
-def_helper_size += 1
-if hex_common.helper_needs_next_PC(tag):
-def_helper_size += 1
-f.write(f"DEF_HELPER_{def_helper_size}({tag}")
+for arg in hex_common.helper_args(tag, regs, imms):
+declared.append(arg.proto_arg)
-## Generate the qemu DEF_HELPER type for each result
-## Iterate over this list twice
-## - Emit the scalar result
-## - Emit the vector result
-i = 0
-for regtype, regid in regs:
-if hex_common.is_written(regid):
-if not hex_common.is_hvx_reg(regtype):
-gen_def_helper_opn(f, tag, regtype, regid, i)
-i += 1
-
-## Put the env between the outputs and inputs
-f.write(", env")
-i += 1
-
-# Second pass
-for regtype, regid in regs:
-if hex_common.is_written(regid):
-if hex_common.is_hvx_reg(regt
[PULL 08/15] Hexagon (target/hexagon) Make generators object oriented - gen_op_regs
From: Taylor Simpson Reviewed-by: Brian Cain Signed-off-by: Taylor Simpson Message-Id: <20231210220712.491494-7-ltaylorsimp...@gmail.com> Signed-off-by: Brian Cain --- target/hexagon/gen_op_regs.py | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/hexagon/gen_op_regs.py b/target/hexagon/gen_op_regs.py index a8a7712129..7b7b33895a 100755 --- a/target/hexagon/gen_op_regs.py +++ b/target/hexagon/gen_op_regs.py @@ -70,6 +70,7 @@ def strip_reg_prefix(x): def main(): hex_common.read_semantics_file(sys.argv[1]) hex_common.read_attribs_file(sys.argv[2]) +hex_common.init_registers() tagregs = hex_common.get_tagregs(full=True) tagimms = hex_common.get_tagimms() @@ -80,11 +81,12 @@ def main(): wregs = [] regids = "" for regtype, regid, _, numregs in regs: -if hex_common.is_read(regid): +reg = hex_common.get_register(tag, regtype, regid) +if reg.is_read(): if regid[0] not in regids: regids += regid[0] rregs.append(regtype + regid + numregs) -if hex_common.is_written(regid): +if reg.is_written(): wregs.append(regtype + regid + numregs) if regid[0] not in regids: regids += regid[0] -- 2.25.1
[PULL 09/15] Hexagon (target/hexagon) Make generators object oriented - gen_analyze_funcs
From: Taylor Simpson
This patch conflicts with
https://lists.gnu.org/archive/html/qemu-devel/2023-11/msg00729.html
If that series goes in first, we'll rework this patch and vice versa.
Signed-off-by: Taylor Simpson
Reviewed-by: Brian Cain
Message-Id: <20231210220712.491494-8-ltaylorsimp...@gmail.com>
Signed-off-by: Brian Cain
---
target/hexagon/gen_analyze_funcs.py | 163 +---
target/hexagon/hex_common.py| 151 ++
2 files changed, 157 insertions(+), 157 deletions(-)
diff --git a/target/hexagon/gen_analyze_funcs.py
b/target/hexagon/gen_analyze_funcs.py
index c3b521abef..a9af666cef 100755
--- a/target/hexagon/gen_analyze_funcs.py
+++ b/target/hexagon/gen_analyze_funcs.py
@@ -23,162 +23,6 @@
import hex_common
-##
-## Helpers for gen_analyze_func
-##
-def is_predicated(tag):
-return "A_CONDEXEC" in hex_common.attribdict[tag]
-
-
-def analyze_opn_old(f, tag, regtype, regid, regno):
-regN = f"{regtype}{regid}N"
-predicated = "true" if is_predicated(tag) else "false"
-if regtype == "R":
-if regid in {"ss", "tt"}:
-f.write(f"const int {regN} = insn->regno[{regno}];\n")
-f.write(f"ctx_log_reg_read_pair(ctx, {regN});\n")
-elif regid in {"dd", "ee", "xx", "yy"}:
-f.write(f"const int {regN} = insn->regno[{regno}];\n")
-f.write(f"ctx_log_reg_write_pair(ctx, {regN},
{predicated});\n")
-elif regid in {"s", "t", "u", "v"}:
-f.write(f"const int {regN} = insn->regno[{regno}];\n")
-f.write(f"ctx_log_reg_read(ctx, {regN});\n")
-elif regid in {"d", "e", "x", "y"}:
-f.write(f"const int {regN} = insn->regno[{regno}];\n")
-f.write(f"ctx_log_reg_write(ctx, {regN}, {predicated});\n")
-else:
-hex_common.bad_register(regtype, regid)
-elif regtype == "P":
-if regid in {"s", "t", "u", "v"}:
-f.write(f"const int {regN} = insn->regno[{regno}];\n")
-f.write(f"ctx_log_pred_read(ctx, {regN});\n")
-elif regid in {"d", "e", "x"}:
-f.write(f"const int {regN} = insn->regno[{regno}];\n")
-f.write(f"ctx_log_pred_write(ctx, {regN});\n")
-else:
-hex_common.bad_register(regtype, regid)
-elif regtype == "C":
-if regid == "ss":
-f.write(
-f"const int {regN} = insn->regno[{regno}] "
-"+ HEX_REG_SA0;\n"
-)
-f.write(f"ctx_log_reg_read_pair(ctx, {regN});\n")
-elif regid == "dd":
-f.write(f"const int {regN} = insn->regno[{regno}] " "+
HEX_REG_SA0;\n")
-f.write(f"ctx_log_reg_write_pair(ctx, {regN},
{predicated});\n")
-elif regid == "s":
-f.write(
-f"const int {regN} = insn->regno[{regno}] "
-"+ HEX_REG_SA0;\n"
-)
-f.write(f"ctx_log_reg_read(ctx, {regN});\n")
-elif regid == "d":
-f.write(f"const int {regN} = insn->regno[{regno}] " "+
HEX_REG_SA0;\n")
-f.write(f"ctx_log_reg_write(ctx, {regN}, {predicated});\n")
-else:
-hex_common.bad_register(regtype, regid)
-elif regtype == "M":
-if regid == "u":
-f.write(f"const int {regN} = insn->regno[{regno}];\n")
-f.write(f"ctx_log_reg_read(ctx, {regN});\n")
-else:
-hex_common.bad_register(regtype, regid)
-elif regtype == "V":
-newv = "EXT_DFL"
-if hex_common.is_new_result(tag):
-newv = "EXT_NEW"
-elif hex_common.is_tmp_result(tag):
-newv = "EXT_TMP"
-if regid in {"dd", "xx"}:
-f.write(f"const int {regN} = insn->regno[{regno}];\n")
-f.write(
-f"ctx_log_vreg_write_pair(ctx, {regN}, {newv}, "
f"{predicated});\n"
-)
-elif regid in {"uu", "vv"}:
-f.write(f"const int {regN} = insn->regno[{regno}];\n")
-f.write(f"ctx_log_vreg_read_pair(ctx, {regN});\n")
-elif regid in {"s", "u",
[PULL 00/15] target-hexagon queue, hexagon docker
The following changes since commit 3f2a357b95845ea0bf7463eff6661e43b97d1afc: Merge tag 'hw-cpus-20240119' of https://github.com/philmd/qemu into staging (2024-01-19 11:39:38 +) are available in the Git repository at: https://github.com/quic/qemu tags/pull-hex-20240121 for you to fetch changes up to bbe4209c8b4300d722f47791f9151e1a69cb0135: target/hexagon: reduce scope of def_regnum, remove dead assignment (2024-01-21 22:02:48 -0800) Coverity fix, cross toolchain update, switch to decodetree Brian Cain (2): tests/docker: Hexagon toolchain update target/hexagon: reduce scope of def_regnum, remove dead assignment Taylor Simpson (13): Hexagon (target/hexagon) Fix shadow variable when idef-parser is off Hexagon (target/hexagon) Clean up handling of modifier registers Hexagon (target/hexagon) Make generators object oriented - gen_tcg_funcs Hexagon (target/hexagon) Make generators object oriented - gen_helper_protos Hexagon (target/hexagon) Make generators object oriented - gen_helper_funcs Hexagon (target/hexagon) Make generators object oriented - gen_idef_parser_funcs Hexagon (target/hexagon) Make generators object oriented - gen_op_regs Hexagon (target/hexagon) Make generators object oriented - gen_analyze_funcs Hexagon (target/hexagon) Remove unused WRITES_PRED_REG attribute Hexagon (target/hexagon) Remove dead functions from hex_common.py Hexagon (target/hexagon) Use QEMU decodetree (32-bit instructions) Hexagon (target/hexagon) Use QEMU decodetree (16-bit instructions) Hexagon (target/hexagon) Remove old dectree.py target/hexagon/README | 14 +- target/hexagon/attribs_def.h.inc | 1 - target/hexagon/decode.c| 439 +++--- target/hexagon/decode.h| 5 +- target/hexagon/dectree.py | 403 - target/hexagon/gen_analyze_funcs.py| 163 +--- target/hexagon/gen_decodetree.py | 198 + target/hexagon/gen_dectree_import.c| 49 -- target/hexagon/gen_helper_funcs.py | 370 ++--- target/hexagon/gen_helper_protos.py| 149 +--- target/hexagon/gen_idef_parser_funcs.py| 20 +- target/hexagon/gen_op_regs.py | 6 +- target/hexagon/gen_tcg.h | 9 +- target/hexagon/gen_tcg_funcs.py| 566 + target/hexagon/gen_trans_funcs.py | 124 +++ target/hexagon/hex_common.py | 921 +++-- target/hexagon/idef-parser/parser-helpers.c| 8 +- target/hexagon/macros.h| 9 +- target/hexagon/meson.build | 147 +++- target/hexagon/mmvec/decode_ext_mmvec.c| 4 +- target/hexagon/opcodes.c | 29 - target/hexagon/opcodes.h | 2 - target/hexagon/translate.c | 4 +- .../docker/dockerfiles/debian-hexagon-cross.docker | 4 +- 24 files changed, 1559 insertions(+), 2085 deletions(-) delete mode 100755 target/hexagon/dectree.py create mode 100755 target/hexagon/gen_decodetree.py create mode 100755 target/hexagon/gen_trans_funcs.py
RE: [PATCH v2 0/9] Hexagon (target/hexagon) Make generators object oriented
> -Original Message- > From: Taylor Simpson > Sent: Sunday, December 10, 2023 4:07 PM > To: qemu-devel@nongnu.org > Cc: Brian Cain ; Matheus Bernardino (QUIC) > ; Sid Manning ; Marco > Liebel (QUIC) ; richard.hender...@linaro.org; > phi...@linaro.org; a...@rev.ng; a...@rev.ng; ltaylorsimp...@gmail.com > Subject: [PATCH v2 0/9] Hexagon (target/hexagon) Make generators object > oriented > > WARNING: This email originated from outside of Qualcomm. Please be wary of > any links or attachments, and do not enable macros. > > See commit message in second patch > > **** Changes in v2 > Address feedback from Brian Cain > - Consolidate logic to create helper arg lists > > > Taylor Simpson (9): > Hexagon (target/hexagon) Clean up handling of modifier registers > Hexagon (target/hexagon) Make generators object oriented - > gen_tcg_funcs > Hexagon (target/hexagon) Make generators object oriented - > gen_helper_protos > Hexagon (target/hexagon) Make generators object oriented - > gen_helper_funcs > Hexagon (target/hexagon) Make generators object oriented - > gen_idef_parser_funcs > Hexagon (target/hexagon) Make generators object oriented - gen_op_regs > Hexagon (target/hexagon) Make generators object oriented - > gen_analyze_funcs > Hexagon (target/hexagon) Remove unused WRITES_PRED_REG attribute > Hexagon (target/hexagon) Remove dead functions from hex_common.py > > target/hexagon/gen_tcg.h| 9 +- > target/hexagon/macros.h | 3 +- > target/hexagon/attribs_def.h.inc| 1 - > target/hexagon/idef-parser/parser-helpers.c | 8 +- > target/hexagon/gen_analyze_funcs.py | 163 +--- > target/hexagon/gen_helper_funcs.py | 368 ++-- > target/hexagon/gen_helper_protos.py | 149 +--- > target/hexagon/gen_idef_parser_funcs.py | 20 +- > target/hexagon/gen_op_regs.py | 6 +- > target/hexagon/gen_tcg_funcs.py | 566 +--- > target/hexagon/hex_common.py| 921 ++-- > 11 files changed, 964 insertions(+), 1250 deletions(-) > > -- > 2.34.1 Queued - https://github.com/quic/qemu/tree/hex.next
RE: [PATCH v2 0/3] Hexagon (target/hexagon) Use QEMU decodetree
> -Original Message- > From: Taylor Simpson > Sent: Monday, January 15, 2024 4:15 PM > To: qemu-devel@nongnu.org > Cc: Brian Cain ; Matheus Bernardino (QUIC) > ; Sid Manning ; Marco > Liebel (QUIC) ; richard.hender...@linaro.org; > phi...@linaro.org; a...@rev.ng; a...@rev.ng; ltaylorsimp...@gmail.com > Subject: [PATCH v2 0/3] Hexagon (target/hexagon) Use QEMU decodetree > > WARNING: This email originated from outside of Qualcomm. Please be wary of > any links or attachments, and do not enable macros. > > Replace the old Hexagon dectree.py with QEMU decodetree > > Changes in v2 > Suggested Python improvements from Brian Cain > > > Taylor Simpson (3): > Hexagon (target/hexagon) Use QEMU decodetree (32-bit instructions) > Hexagon (target/hexagon) Use QEMU decodetree (16-bit instructions) > Hexagon (target/hexagon) Remove old dectree.py > > target/hexagon/decode.h | 5 +- > target/hexagon/opcodes.h| 2 - > target/hexagon/decode.c | 435 +++- > target/hexagon/gen_dectree_import.c | 49 > target/hexagon/opcodes.c| 29 -- > target/hexagon/translate.c | 4 +- > target/hexagon/README | 14 +- > target/hexagon/dectree.py | 403 -- > target/hexagon/gen_decodetree.py| 198 + > target/hexagon/gen_trans_funcs.py | 124 > target/hexagon/meson.build | 147 +- > 11 files changed, 586 insertions(+), 824 deletions(-) > delete mode 100755 target/hexagon/dectree.py > create mode 100755 target/hexagon/gen_decodetree.py > create mode 100755 target/hexagon/gen_trans_funcs.py > > -- > 2.34.1 Queued - https://github.com/quic/qemu/tree/hex.next
RE: [PATCH v2 3/3] Hexagon (target/hexagon) Remove old dectree.py
> -Original Message-
> From: Taylor Simpson
> Sent: Monday, January 8, 2024 4:49 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ; Marco
> Liebel (QUIC) ; richard.hender...@linaro.org;
> phi...@linaro.org; a...@rev.ng; a...@rev.ng; ltaylorsimp...@gmail.com
> Subject: [PATCH v2 3/3] Hexagon (target/hexagon) Remove old dectree.py
>
> WARNING: This email originated from outside of Qualcomm. Please be wary of
> any links or attachments, and do not enable macros.
>
> Now that we are using QEMU decodetree.py, remove the old decoder
>
> Signed-off-by: Taylor Simpson
> ---
> target/hexagon/opcodes.h| 2 -
> target/hexagon/decode.c | 344
> target/hexagon/gen_dectree_import.c | 49
> target/hexagon/opcodes.c| 29 --
> target/hexagon/dectree.py | 403
> target/hexagon/meson.build | 12 -
> 6 files changed, 839 deletions(-)
> delete mode 100755 target/hexagon/dectree.py
>
> diff --git a/target/hexagon/opcodes.h b/target/hexagon/opcodes.h
> index 6e90e00fe2..fa7e321950 100644
> --- a/target/hexagon/opcodes.h
> +++ b/target/hexagon/opcodes.h
> @@ -53,6 +53,4 @@ extern const OpcodeEncoding
> opcode_encodings[XX_LAST_OPCODE];
>
> void opcode_init(void);
>
> -int opcode_which_immediate_is_extended(Opcode opcode);
> -
> #endif
> diff --git a/target/hexagon/decode.c b/target/hexagon/decode.c
> index 160b23a895..a40210ca1e 100644
> --- a/target/hexagon/decode.c
> +++ b/target/hexagon/decode.c
> @@ -88,175 +88,6 @@ static int shift_left(DisasContext *ctx, int x, int n, int
> immno)
> /* Include the generated helpers for the decoder */
> #include "decodetree_trans_funcs_generated.c.inc"
>
> -typedef struct {
> -const struct DectreeTable *table_link;
> -const struct DectreeTable *table_link_b;
> -Opcode opcode;
> -enum {
> -DECTREE_ENTRY_INVALID,
> -DECTREE_TABLE_LINK,
> -DECTREE_SUBINSNS,
> -DECTREE_EXTSPACE,
> -DECTREE_TERMINAL
> -} type;
> -} DectreeEntry;
> -
> -typedef struct DectreeTable {
> -unsigned int (*lookup_function)(int startbit, int width, uint32_t
> opcode);
> -unsigned int size;
> -unsigned int startbit;
> -unsigned int width;
> -const DectreeEntry table[];
> -} DectreeTable;
> -
> -#define DECODE_NEW_TABLE(TAG, SIZE, WHATNOT) \
> -static const DectreeTable dectree_table_##TAG;
> -#define TABLE_LINK(TABLE) /* NOTHING */
> -#define TERMINAL(TAG, ENC)/* NOTHING */
> -#define SUBINSNS(TAG, CLASSA, CLASSB, ENC)/* NOTHING */
> -#define EXTSPACE(TAG, ENC)/* NOTHING */
> -#define INVALID() /* NOTHING */
> -#define DECODE_END_TABLE(...) /* NOTHING */
> -#define DECODE_MATCH_INFO(...)/* NOTHING */
> -#define DECODE_LEGACY_MATCH_INFO(...) /* NOTHING */
> -#define DECODE_OPINFO(...)/* NOTHING */
> -
> -#include "dectree_generated.h.inc"
> -
> -#undef DECODE_OPINFO
> -#undef DECODE_MATCH_INFO
> -#undef DECODE_LEGACY_MATCH_INFO
> -#undef DECODE_END_TABLE
> -#undef INVALID
> -#undef TERMINAL
> -#undef SUBINSNS
> -#undef EXTSPACE
> -#undef TABLE_LINK
> -#undef DECODE_NEW_TABLE
> -#undef DECODE_SEPARATOR_BITS
> -
> -#define DECODE_SEPARATOR_BITS(START, WIDTH) NULL, START, WIDTH
> -#define DECODE_NEW_TABLE_HELPER(TAG, SIZE, FN, START, WIDTH) \
> -static const DectreeTable dectree_table_##TAG = { \
> -.size = SIZE, \
> -.lookup_function = FN, \
> -.startbit = START, \
> -.width = WIDTH, \
> -.table = {
> -#define DECODE_NEW_TABLE(TAG, SIZE, WHATNOT) \
> -DECODE_NEW_TABLE_HELPER(TAG, SIZE, WHATNOT)
> -
> -#define TABLE_LINK(TABLE) \
> -{ .type = DECTREE_TABLE_LINK, .table_link = _table_##TABLE },
> -#define TERMINAL(TAG, ENC) \
> -{ .type = DECTREE_TERMINAL, .opcode = TAG },
> -#define SUBINSNS(TAG, CLASSA, CLASSB, ENC) \
> -{ \
> -.type = DECTREE_SUBINSNS, \
> -.table_link = _table_DECODE_SUBINSN_##CLASSA, \
> -.table_link_b = _table_DECODE_SUBINSN_##CLASSB \
> -},
> -#define EXTSPACE(TAG, ENC) { .type = DECTREE_EXTSPACE },
> -#define INVALID() { .type = DECTREE_ENTRY_INVALID, .opcode =
> XX_LAST_OPCODE },
> -
> -#define DECODE_END_TABLE(...) } };
> -
> -#define DECODE_MATCH_INFO(...)/* NOTHING */
> -#define DECODE_LEGACY_MATCH_INFO(...) /* NOTHING */
> -#define DECODE_OPINFO(...)
RE: [PATCH v2 2/3] Hexagon (target/hexagon) Use QEMU decodetree (16-bit instructions)
> -Original Message-
> From: Taylor Simpson
> Sent: Monday, January 8, 2024 4:49 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ; Marco
> Liebel (QUIC) ; richard.hender...@linaro.org;
> phi...@linaro.org; a...@rev.ng; a...@rev.ng; ltaylorsimp...@gmail.com
> Subject: [PATCH v2 2/3] Hexagon (target/hexagon) Use QEMU decodetree (16-
> bit instructions)
>
> WARNING: This email originated from outside of Qualcomm. Please be wary of
> any links or attachments, and do not enable macros.
>
> Section 10.3 of the Hexagon V73 Programmer's Reference Manual
>
> A duplex is encoded as a 32-bit instruction with bits [15:14] set to 00.
> The sub-instructions that comprise a duplex are encoded as 13-bit fields
> in the duplex.
>
> Create a decoder for each subinstruction class (a, l1, l2, s1, s2).
>
> Extend gen_trans_funcs.py to handle all instructions rather than
> filter by instruction class.
>
> There is a g_assert_not_reached() in decode_insns() in decode.c to
> verify we never try to use the old decoder on 16-bit instructions.
>
> Signed-off-by: Taylor Simpson
> ---
> target/hexagon/decode.c | 85 +
> target/hexagon/README | 1 +
> target/hexagon/gen_decodetree.py | 14 -
> target/hexagon/gen_trans_funcs.py | 12 +
> target/hexagon/meson.build| 90 +++
> 5 files changed, 190 insertions(+), 12 deletions(-)
>
> diff --git a/target/hexagon/decode.c b/target/hexagon/decode.c
> index bddad1f75e..160b23a895 100644
> --- a/target/hexagon/decode.c
> +++ b/target/hexagon/decode.c
> @@ -60,6 +60,7 @@ static int decode_mapped_reg_##NAME(DisasContext
> *ctx, int x) \
> }
> DECODE_MAPPED(R_16)
> DECODE_MAPPED(R_8)
> +DECODE_MAPPED(R__8)
>
> /* Helper function for decodetree_trans_funcs_generated.c.inc */
> static int shift_left(DisasContext *ctx, int x, int n, int immno)
> @@ -77,6 +78,13 @@ static int shift_left(DisasContext *ctx, int x, int n, int
> immno)
> #include "decode_normal_generated.c.inc"
> #include "decode_hvx_generated.c.inc"
>
> +/* Include the generated decoder for 16 bit insn */
> +#include "decode_subinsn_a_generated.c.inc"
> +#include "decode_subinsn_l1_generated.c.inc"
> +#include "decode_subinsn_l2_generated.c.inc"
> +#include "decode_subinsn_s1_generated.c.inc"
> +#include "decode_subinsn_s2_generated.c.inc"
> +
> /* Include the generated helpers for the decoder */
> #include "decodetree_trans_funcs_generated.c.inc"
>
> @@ -790,6 +798,63 @@ decode_insns_tablewalk(Insn *insn, const
> DectreeTable *table,
> }
> }
>
> +/*
> + * Section 10.3 of the Hexagon V73 Programmer's Reference Manual
> + *
> + * A duplex is encoded as a 32-bit instruction with bits [15:14] set to 00.
> + * The sub-instructions that comprise a duplex are encoded as 13-bit fields
> + * in the duplex.
> + *
> + * Per table 10-4, the 4-bit duplex iclass is encoded in bits 31:29, 13
> + */
> +static uint32_t get_duplex_iclass(uint32_t encoding)
> +{
> +uint32_t iclass = extract32(encoding, 13, 1);
> +iclass = deposit32(iclass, 1, 3, extract32(encoding, 29, 3));
> +return iclass;
> +}
> +
> +/*
> + * Per table 10-5, the duplex ICLASS field values that specify the group of
> + * each sub-instruction in a duplex
> + *
> + * This table points to the decode instruction for each entry in the table
> + */
> +typedef bool (*subinsn_decode_func)(DisasContext *ctx, uint16_t insn);
> +typedef struct {
> +subinsn_decode_func decode_slot0_subinsn;
> +subinsn_decode_func decode_slot1_subinsn;
> +} subinsn_decode_groups;
> +
> +static const subinsn_decode_groups decode_groups[16] = {
> +[0x0] = { decode_subinsn_l1, decode_subinsn_l1 },
> +[0x1] = { decode_subinsn_l2, decode_subinsn_l1 },
> +[0x2] = { decode_subinsn_l2, decode_subinsn_l2 },
> +[0x3] = { decode_subinsn_a, decode_subinsn_a },
> +[0x4] = { decode_subinsn_l1, decode_subinsn_a },
> +[0x5] = { decode_subinsn_l2, decode_subinsn_a },
> +[0x6] = { decode_subinsn_s1, decode_subinsn_a },
> +[0x7] = { decode_subinsn_s2, decode_subinsn_a },
> +[0x8] = { decode_subinsn_s1, decode_subinsn_l1 },
> +[0x9] = { decode_subinsn_s1, decode_subinsn_l2 },
> +[0xa] = { decode_subinsn_s1, decode_subinsn_s1 },
> +[0xb] = { decode_subinsn_s2, decode_subinsn_s1 },
> +[0xc] = { decode_subinsn_s2, decode_subinsn_l1 },
> +[0xd] = { decode_subinsn_s2, decode_subinsn_l2 },
> +[0xe] = { decode_subinsn_s2, decode_subinsn_s2 },
> +[0xf] = { NULL,
RE: [PATCH v2 1/3] Hexagon (target/hexagon) Use QEMU decodetree (32-bit instructions)
> -Original Message-
> From: Taylor Simpson
> Sent: Monday, January 8, 2024 4:49 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ; Marco
> Liebel (QUIC) ; richard.hender...@linaro.org;
> phi...@linaro.org; a...@rev.ng; a...@rev.ng; ltaylorsimp...@gmail.com
> Subject: [PATCH v2 1/3] Hexagon (target/hexagon) Use QEMU decodetree (32-
> bit instructions)
>
> WARNING: This email originated from outside of Qualcomm. Please be wary of
> any links or attachments, and do not enable macros.
>
> The Decodetree Specification can be found here
> https://www.qemu.org/docs/master/devel/decodetree.html
>
> Covers all 32-bit instructions, including HVX
>
> We generate separate decoders for each instruction class. The reason
> will be more apparent in the next patch in this series.
>
> We add 2 new scripts
> gen_decodetree.pyGenerate the input to decodetree.py
> gen_trans_funcs.py Generate the trans_* functions used by the
> output of decodetree.py
>
> Since the functions generated by decodetree.py take DisasContext * as an
> argument, we add the argument to a couple of functions that didn't need
> it previously. We also set the insn field in DisasContext during decode
> because it is used by the trans_* functions.
>
> There is a g_assert_not_reached() in decode_insns() in decode.c to
> verify we never try to use the old decoder on 32-bit instructions
>
> Signed-off-by: Taylor Simpson
> ---
> target/hexagon/decode.h | 5 +-
> target/hexagon/decode.c | 54 -
> target/hexagon/translate.c| 4 +-
> target/hexagon/README | 13 +-
> target/hexagon/gen_decodetree.py | 193 ++
> target/hexagon/gen_trans_funcs.py | 132
> target/hexagon/meson.build| 55 +
> 7 files changed, 442 insertions(+), 14 deletions(-)
> create mode 100755 target/hexagon/gen_decodetree.py
> create mode 100755 target/hexagon/gen_trans_funcs.py
>
> diff --git a/target/hexagon/decode.h b/target/hexagon/decode.h
> index c66f5ea64d..3f3012b978 100644
> --- a/target/hexagon/decode.h
> +++ b/target/hexagon/decode.h
> @@ -21,12 +21,13 @@
> #include "cpu.h"
> #include "opcodes.h"
> #include "insn.h"
> +#include "translate.h"
>
> void decode_init(void);
>
> void decode_send_insn_to(Packet *packet, int start, int newloc);
>
> -int decode_packet(int max_words, const uint32_t *words, Packet *pkt,
> - bool disas_only);
> +int decode_packet(DisasContext *ctx, int max_words, const uint32_t *words,
> + Packet *pkt, bool disas_only);
>
> #endif
> diff --git a/target/hexagon/decode.c b/target/hexagon/decode.c
> index 946c55cc71..bddad1f75e 100644
> --- a/target/hexagon/decode.c
> +++ b/target/hexagon/decode.c
> @@ -52,6 +52,34 @@ DEF_REGMAP(R_8, 8, 0, 1, 2, 3, 4, 5, 6, 7)
> #define DECODE_MAPPED_REG(OPNUM, NAME) \
> insn->regno[OPNUM] = DECODE_REGISTER_##NAME[insn->regno[OPNUM]];
>
> +/* Helper functions for decode_*_generated.c.inc */
> +#define DECODE_MAPPED(NAME) \
> +static int decode_mapped_reg_##NAME(DisasContext *ctx, int x) \
> +{ \
> +return DECODE_REGISTER_##NAME[x]; \
> +}
> +DECODE_MAPPED(R_16)
> +DECODE_MAPPED(R_8)
> +
> +/* Helper function for decodetree_trans_funcs_generated.c.inc */
> +static int shift_left(DisasContext *ctx, int x, int n, int immno)
> +{
> +int ret = x;
> +Insn *insn = ctx->insn;
> +if (!insn->extension_valid ||
> +insn->which_extended != immno) {
> +ret <<= n;
> +}
> +return ret;
> +}
> +
> +/* Include the generated decoder for 32 bit insn */
> +#include "decode_normal_generated.c.inc"
> +#include "decode_hvx_generated.c.inc"
> +
> +/* Include the generated helpers for the decoder */
> +#include "decodetree_trans_funcs_generated.c.inc"
> +
> typedef struct {
> const struct DectreeTable *table_link;
> const struct DectreeTable *table_link_b;
> @@ -550,7 +578,8 @@ apply_extender(Packet *pkt, int i, uint32_t extender)
> int immed_num;
> uint32_t base_immed;
>
> -immed_num = opcode_which_immediate_is_extended(pkt->insn[i].opcode);
> +immed_num = pkt->insn[i].which_extended;
> +g_assert(immed_num == opcode_which_immediate_is_extended(pkt-
> >insn[i].opcode));
> base_immed = pkt->insn[i].immed[immed_num];
>
> pkt->insn[i].immed[immed_num] = extender | fZXTN(6, 32, base_immed);
> @@ -762,12 +791,19 @@ decode_insns_tabl
[PATCH] Reduce scope of def_regnum, remove dead assignment
This is intended to address a coverity finding: CID 1527408.
Signed-off-by: Brian Cain
---
target/hexagon/mmvec/decode_ext_mmvec.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/target/hexagon/mmvec/decode_ext_mmvec.c
b/target/hexagon/mmvec/decode_ext_mmvec.c
index 174eb3b78b..202d84c7c0 100644
--- a/target/hexagon/mmvec/decode_ext_mmvec.c
+++ b/target/hexagon/mmvec/decode_ext_mmvec.c
@@ -33,7 +33,6 @@ check_new_value(Packet *pkt)
const char *dststr = NULL;
uint16_t def_opcode;
char letter;
-int def_regnum;
for (i = 1; i < pkt->num_insns; i++) {
uint16_t use_opcode = pkt->insn[i].opcode;
@@ -78,7 +77,6 @@ check_new_value(Packet *pkt)
}
}
if ((dststr == NULL) && GET_ATTRIB(def_opcode, A_CVI_GATHER)) {
-def_regnum = 0;
pkt->insn[i].regno[use_regidx] = def_oreg;
pkt->insn[i].new_value_producer_slot = pkt->insn[def_idx].slot;
} else {
@@ -86,7 +84,7 @@ check_new_value(Packet *pkt)
/* still not there, we have a bad packet */
g_assert_not_reached();
}
-def_regnum = pkt->insn[def_idx].regno[dststr - reginfo];
+int def_regnum = pkt->insn[def_idx].regno[dststr - reginfo];
/* Now patch up the consumer with the register number */
pkt->insn[i].regno[use_regidx] = def_regnum ^ def_oreg;
/* special case for (Vx,Vy) */
--
2.25.1
[PATCH] tests/docker: Hexagon toolchain update
This update includes support for privileged instructions.
Signed-off-by: Brian Cain
---
tests/docker/dockerfiles/debian-hexagon-cross.docker | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tests/docker/dockerfiles/debian-hexagon-cross.docker
b/tests/docker/dockerfiles/debian-hexagon-cross.docker
index 7c38d7c9e4..60bd8faa20 100644
--- a/tests/docker/dockerfiles/debian-hexagon-cross.docker
+++ b/tests/docker/dockerfiles/debian-hexagon-cross.docker
@@ -38,9 +38,9 @@ RUN apt-get update && \
RUN /usr/bin/pip3 install tomli
ENV TOOLCHAIN_INSTALL /opt
-ENV TOOLCHAIN_RELEASE 16.0.0
+ENV TOOLCHAIN_RELEASE 12.Dec.2023
ENV TOOLCHAIN_BASENAME
"clang+llvm-${TOOLCHAIN_RELEASE}-cross-hexagon-unknown-linux-musl"
-ENV TOOLCHAIN_URL
https://codelinaro.jfrog.io/artifactory/codelinaro-toolchain-for-hexagon/v${TOOLCHAIN_RELEASE}/${TOOLCHAIN_BASENAME}.tar.xz
+ENV TOOLCHAIN_URL
https://codelinaro.jfrog.io/artifactory/codelinaro-toolchain-for-hexagon/${TOOLCHAIN_RELEASE}/${TOOLCHAIN_BASENAME}.tar.xz
ENV CCACHE_WRAPPERSDIR "/usr/libexec/ccache-wrappers"
RUN curl -#SL "$TOOLCHAIN_URL" | tar -xJC "$TOOLCHAIN_INSTALL"
--
2.25.1
RE: [PATCH v2 8/9] Hexagon (target/hexagon) Remove unused WRITES_PRED_REG attribute
> -Original Message-
> From: Taylor Simpson
> Sent: Sunday, December 10, 2023 4:07 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ; Marco
> Liebel (QUIC) ; richard.hender...@linaro.org;
> phi...@linaro.org; a...@rev.ng; a...@rev.ng; ltaylorsimp...@gmail.com
> Subject: [PATCH v2 8/9] Hexagon (target/hexagon) Remove unused
> WRITES_PRED_REG attribute
>
> WARNING: This email originated from outside of Qualcomm. Please be wary of
> any links or attachments, and do not enable macros.
>
> This is the only remaining use of the is_written function. We will
> remove it in the subsequent commit.
>
> Signed-off-by: Taylor Simpson
> ---
> target/hexagon/attribs_def.h.inc | 1 -
> target/hexagon/hex_common.py | 11 ---
> 2 files changed, 12 deletions(-)
>
> diff --git a/target/hexagon/attribs_def.h.inc
> b/target/hexagon/attribs_def.h.inc
> index 21d457fa4a..87942d46f4 100644
> --- a/target/hexagon/attribs_def.h.inc
> +++ b/target/hexagon/attribs_def.h.inc
> @@ -117,7 +117,6 @@ DEF_ATTRIB(IMPLICIT_READS_P1, "Reads the P1
> register", "", "")
> DEF_ATTRIB(IMPLICIT_READS_P2, "Reads the P2 register", "", "")
> DEF_ATTRIB(IMPLICIT_READS_P3, "Reads the P3 register", "", "")
> DEF_ATTRIB(IMPLICIT_WRITES_USR, "May write USR", "", "")
> -DEF_ATTRIB(WRITES_PRED_REG, "Writes a predicate register", "", "")
> DEF_ATTRIB(COMMUTES, "The operation is communitive", "", "")
> DEF_ATTRIB(DEALLOCRET, "dealloc_return", "", "")
> DEF_ATTRIB(DEALLOCFRAME, "deallocframe", "", "")
> diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
> index 4565dd1953..ca5e9630c1 100755
> --- a/target/hexagon/hex_common.py
> +++ b/target/hexagon/hex_common.py
> @@ -94,10 +94,6 @@ def is_cond_call(tag):
> def calculate_attribs():
> add_qemu_macro_attrib("fREAD_PC", "A_IMPLICIT_READS_PC")
> add_qemu_macro_attrib("fTRAP", "A_IMPLICIT_READS_PC")
> -add_qemu_macro_attrib("fWRITE_P0", "A_WRITES_PRED_REG")
> -add_qemu_macro_attrib("fWRITE_P1", "A_WRITES_PRED_REG")
> -add_qemu_macro_attrib("fWRITE_P2", "A_WRITES_PRED_REG")
> -add_qemu_macro_attrib("fWRITE_P3", "A_WRITES_PRED_REG")
> add_qemu_macro_attrib("fSET_OVERFLOW", "A_IMPLICIT_WRITES_USR")
> add_qemu_macro_attrib("fSET_LPCFG", "A_IMPLICIT_WRITES_USR")
> add_qemu_macro_attrib("fLOAD", "A_SCALAR_LOAD")
> @@ -122,13 +118,6 @@ def calculate_attribs():
> continue
> macro = macros[macname]
> attribdict[tag] |= set(macro.attribs)
> -# Figure out which instructions write predicate registers
> -tagregs = get_tagregs()
> -for tag in tags:
> -regs = tagregs[tag]
> -for regtype, regid in regs:
> -if regtype == "P" and is_written(regid):
> -attribdict[tag].add("A_WRITES_PRED_REG")
> # Mark conditional jumps and calls
> # Not all instructions are properly marked with A_CONDEXEC
> for tag in tags:
> --
> 2.34.1
Reviewed-by: Brian Cain
RE: [PATCH v2 9/9] Hexagon (target/hexagon) Remove dead functions from hex_common.py
> -Original Message-
> From: Taylor Simpson
> Sent: Sunday, December 10, 2023 4:07 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ; Marco
> Liebel (QUIC) ; richard.hender...@linaro.org;
> phi...@linaro.org; a...@rev.ng; a...@rev.ng; ltaylorsimp...@gmail.com
> Subject: [PATCH v2 9/9] Hexagon (target/hexagon) Remove dead functions
> from hex_common.py
>
> WARNING: This email originated from outside of Qualcomm. Please be wary of
> any links or attachments, and do not enable macros.
>
> These functions are no longer used after making the generators
> object oriented.
>
> Signed-off-by: Taylor Simpson
> ---
> target/hexagon/hex_common.py | 51
> 1 file changed, 51 deletions(-)
>
> diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
> index ca5e9630c1..195620c7ec 100755
> --- a/target/hexagon/hex_common.py
> +++ b/target/hexagon/hex_common.py
> @@ -33,9 +33,6 @@
> overrides = {} # tags with helper overrides
> idef_parser_enabled = {} # tags enabled for idef-parser
>
> -def bad_register(regtype, regid):
> -raise Exception(f"Bad register parse: regtype '{regtype}' regid
> '{regid}'")
> -
> # We should do this as a hash for performance,
> # but to keep order let's keep it as a list.
> def uniquify(seq):
> @@ -200,46 +197,6 @@ def get_tagimms():
> return dict(zip(tags, list(map(compute_tag_immediates, tags
>
>
> -def is_pair(regid):
> -return len(regid) == 2
> -
> -
> -def is_single(regid):
> -return len(regid) == 1
> -
> -
> -def is_written(regid):
> -return regid[0] in "dexy"
> -
> -
> -def is_writeonly(regid):
> -return regid[0] in "de"
> -
> -
> -def is_read(regid):
> -return regid[0] in "stuvwxy"
> -
> -
> -def is_readwrite(regid):
> -return regid[0] in "xy"
> -
> -
> -def is_scalar_reg(regtype):
> -return regtype in "RPC"
> -
> -
> -def is_hvx_reg(regtype):
> -return regtype in "VQ"
> -
> -
> -def is_old_val(regtype, regid, tag):
> -return regtype + regid + "V" in semdict[tag]
> -
> -
> -def is_new_val(regtype, regid, tag):
> -return regtype + regid + "N" in semdict[tag]
> -
> -
> def need_slot(tag):
> if (
> "A_CVI_SCATTER" not in attribdict[tag]
> @@ -280,14 +237,6 @@ def skip_qemu_helper(tag):
> return tag in overrides.keys()
>
>
> -def is_tmp_result(tag):
> -return "A_CVI_TMP" in attribdict[tag] or "A_CVI_TMP_DST" in
> attribdict[tag]
> -
> -
> -def is_new_result(tag):
> -return "A_CVI_NEW" in attribdict[tag]
> -
> -
> def is_idef_parser_enabled(tag):
> return tag in idef_parser_enabled
>
> --
> 2.34.1
Reviewed-by: Brian Cain
RE: [PATCH v2 6/9] Hexagon (target/hexagon) Make generators object oriented - gen_op_regs
> -Original Message- > From: Taylor Simpson > Sent: Sunday, December 10, 2023 4:07 PM > To: qemu-devel@nongnu.org > Cc: Brian Cain ; Matheus Bernardino (QUIC) > ; Sid Manning ; Marco > Liebel (QUIC) ; richard.hender...@linaro.org; > phi...@linaro.org; a...@rev.ng; a...@rev.ng; ltaylorsimp...@gmail.com > Subject: [PATCH v2 6/9] Hexagon (target/hexagon) Make generators object > oriented - gen_op_regs > > WARNING: This email originated from outside of Qualcomm. Please be wary of > any links or attachments, and do not enable macros. > > Reviewed-by: Brian Cain > Signed-off-by: Taylor Simpson > --- > target/hexagon/gen_op_regs.py | 6 -- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/target/hexagon/gen_op_regs.py b/target/hexagon/gen_op_regs.py > index a8a7712129..7b7b33895a 100755 > --- a/target/hexagon/gen_op_regs.py > +++ b/target/hexagon/gen_op_regs.py > @@ -70,6 +70,7 @@ def strip_reg_prefix(x): > def main(): > hex_common.read_semantics_file(sys.argv[1]) > hex_common.read_attribs_file(sys.argv[2]) > +hex_common.init_registers() > tagregs = hex_common.get_tagregs(full=True) > tagimms = hex_common.get_tagimms() > > @@ -80,11 +81,12 @@ def main(): > wregs = [] > regids = "" > for regtype, regid, _, numregs in regs: > -if hex_common.is_read(regid): > +reg = hex_common.get_register(tag, regtype, regid) > +if reg.is_read(): > if regid[0] not in regids: > regids += regid[0] > rregs.append(regtype + regid + numregs) > -if hex_common.is_written(regid): > +if reg.is_written(): > wregs.append(regtype + regid + numregs) > if regid[0] not in regids: > regids += regid[0] > -- > 2.34.1 Reviewed-by: Brian Cain
RE: [PATCH v2 4/9] Hexagon (target/hexagon) Make generators object oriented - gen_helper_funcs
> -Original Message-
> From: Taylor Simpson
> Sent: Sunday, December 10, 2023 4:07 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ; Marco
> Liebel (QUIC) ; richard.hender...@linaro.org;
> phi...@linaro.org; a...@rev.ng; a...@rev.ng; ltaylorsimp...@gmail.com
> Subject: [PATCH v2 4/9] Hexagon (target/hexagon) Make generators object
> oriented - gen_helper_funcs
>
> WARNING: This email originated from outside of Qualcomm. Please be wary of
> any links or attachments, and do not enable macros.
>
> Signed-off-by: Taylor Simpson
> ---
> target/hexagon/gen_helper_funcs.py | 368 +
> target/hexagon/hex_common.py | 48 +++-
> 2 files changed, 103 insertions(+), 313 deletions(-)
>
> diff --git a/target/hexagon/gen_helper_funcs.py
> b/target/hexagon/gen_helper_funcs.py
> index ce21d3b688..9cc3d69c49 100755
> --- a/target/hexagon/gen_helper_funcs.py
> +++ b/target/hexagon/gen_helper_funcs.py
> @@ -23,181 +23,14 @@
> import hex_common
>
>
> -##
> -## Helpers for gen_helper_function
> -##
> -def gen_decl_ea(f):
> -f.write("uint32_t EA;\n")
> -
> -
> -def gen_helper_return_type(f, regtype, regid, regno):
> -if regno > 1:
> -f.write(", ")
> -f.write("int32_t")
> -
> -
> -def gen_helper_return_type_pair(f, regtype, regid, regno):
> -if regno > 1:
> -f.write(", ")
> -f.write("int64_t")
> -
> -
> -def gen_helper_arg(f, regtype, regid, regno):
> -if regno > 0:
> -f.write(", ")
> -f.write(f"int32_t {regtype}{regid}V")
> -
> -
> -def gen_helper_arg_new(f, regtype, regid, regno):
> -if regno >= 0:
> -f.write(", ")
> -f.write(f"int32_t {regtype}{regid}N")
> -
> -
> -def gen_helper_arg_pair(f, regtype, regid, regno):
> -if regno >= 0:
> -f.write(", ")
> -f.write(f"int64_t {regtype}{regid}V")
> -
> -
> -def gen_helper_arg_ext(f, regtype, regid, regno):
> -if regno > 0:
> -f.write(", ")
> -f.write(f"void *{regtype}{regid}V_void")
> -
> -
> -def gen_helper_arg_ext_pair(f, regtype, regid, regno):
> -if regno > 0:
> -f.write(", ")
> -f.write(f"void *{regtype}{regid}V_void")
> -
> -
> -def gen_helper_arg_opn(f, regtype, regid, i, tag):
> -if hex_common.is_pair(regid):
> -if hex_common.is_hvx_reg(regtype):
> -gen_helper_arg_ext_pair(f, regtype, regid, i)
> -else:
> -gen_helper_arg_pair(f, regtype, regid, i)
> -elif hex_common.is_single(regid):
> -if hex_common.is_old_val(regtype, regid, tag):
> -if hex_common.is_hvx_reg(regtype):
> -gen_helper_arg_ext(f, regtype, regid, i)
> -else:
> -gen_helper_arg(f, regtype, regid, i)
> -elif hex_common.is_new_val(regtype, regid, tag):
> -gen_helper_arg_new(f, regtype, regid, i)
> -else:
> -hex_common.bad_register(regtype, regid)
> -else:
> -hex_common.bad_register(regtype, regid)
> -
> -
> -def gen_helper_arg_imm(f, immlett):
> -f.write(f", int32_t {hex_common.imm_name(immlett)}")
> -
> -
> -def gen_helper_dest_decl(f, regtype, regid, regno, subfield=""):
> -f.write(f"int32_t {regtype}{regid}V{subfield} = 0;\n")
> -
> -
> -def gen_helper_dest_decl_pair(f, regtype, regid, regno, subfield=""):
> -f.write(f"int64_t {regtype}{regid}V{subfield} = 0;\n")
> -
> -
> -def gen_helper_dest_decl_ext(f, regtype, regid):
> -if regtype == "Q":
> -f.write(
> -f"/* {regtype}{regid}V is *(MMQReg *)"
> f"({regtype}{regid}V_void)
> */\n"
> -)
> -else:
> -f.write(
> -f"/* {regtype}{regid}V is *(MMVector *)"
> -f"({regtype}{regid}V_void) */\n"
> -)
> -
> -
> -def gen_helper_dest_decl_ext_pair(f, regtype, regid, regno):
> -f.write(
> -f"/* {regtype}{regid}V is *(MMVectorPair *))"
> -f"{regtype}{regid}V_void) */\n"
> -)
> -
> -
> -def gen_helper_dest_decl_opn(f, regtype, regid, i):
> -if hex_common.is_pair(regid):
> -if hex_common.is_hvx_reg(regtype):
> -gen_helper_dest_decl_ext_pair(f, regtype, regid, i)
> -else:
> -gen_helper_dest_decl_pair(f, regtype, regid, i)
> -elif he
RE: [PATCH v2 7/9] Hexagon (target/hexagon) Make generators object oriented - gen_analyze_funcs
> -Original Message-
> From: Taylor Simpson
> Sent: Sunday, December 10, 2023 4:07 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ; Marco
> Liebel (QUIC) ; richard.hender...@linaro.org;
> phi...@linaro.org; a...@rev.ng; a...@rev.ng; ltaylorsimp...@gmail.com
> Subject: [PATCH v2 7/9] Hexagon (target/hexagon) Make generators object
> oriented - gen_analyze_funcs
>
> WARNING: This email originated from outside of Qualcomm. Please be wary of
> any links or attachments, and do not enable macros.
>
> This patch conflicts with
> https://lists.gnu.org/archive/html/qemu-devel/2023-11/msg00729.html
> If that series goes in first, we'll rework this patch and vice versa.
>
> Signed-off-by: Taylor Simpson
> ---
> target/hexagon/gen_analyze_funcs.py | 163 +---
> target/hexagon/hex_common.py| 151 ++
> 2 files changed, 157 insertions(+), 157 deletions(-)
>
> diff --git a/target/hexagon/gen_analyze_funcs.py
> b/target/hexagon/gen_analyze_funcs.py
> index c3b521abef..a9af666cef 100755
> --- a/target/hexagon/gen_analyze_funcs.py
> +++ b/target/hexagon/gen_analyze_funcs.py
> @@ -23,162 +23,6 @@
> import hex_common
>
>
> -##
> -## Helpers for gen_analyze_func
> -##
> -def is_predicated(tag):
> -return "A_CONDEXEC" in hex_common.attribdict[tag]
> -
> -
> -def analyze_opn_old(f, tag, regtype, regid, regno):
> -regN = f"{regtype}{regid}N"
> -predicated = "true" if is_predicated(tag) else "false"
> -if regtype == "R":
> -if regid in {"ss", "tt"}:
> -f.write(f"const int {regN} = insn->regno[{regno}];\n")
> -f.write(f"ctx_log_reg_read_pair(ctx, {regN});\n")
> -elif regid in {"dd", "ee", "xx", "yy"}:
> -f.write(f"const int {regN} = insn->regno[{regno}];\n")
> -f.write(f"ctx_log_reg_write_pair(ctx, {regN},
> {predicated});\n")
> -elif regid in {"s", "t", "u", "v"}:
> -f.write(f"const int {regN} = insn->regno[{regno}];\n")
> -f.write(f"ctx_log_reg_read(ctx, {regN});\n")
> -elif regid in {"d", "e", "x", "y"}:
> -f.write(f"const int {regN} = insn->regno[{regno}];\n")
> -f.write(f"ctx_log_reg_write(ctx, {regN}, {predicated});\n")
> -else:
> -hex_common.bad_register(regtype, regid)
> -elif regtype == "P":
> -if regid in {"s", "t", "u", "v"}:
> -f.write(f"const int {regN} = insn->regno[{regno}];\n")
> -f.write(f"ctx_log_pred_read(ctx, {regN});\n")
> -elif regid in {"d", "e", "x"}:
> -f.write(f"const int {regN} = insn->regno[{regno}];\n")
> -f.write(f"ctx_log_pred_write(ctx, {regN});\n")
> -else:
> -hex_common.bad_register(regtype, regid)
> -elif regtype == "C":
> -if regid == "ss":
> -f.write(
> -f"const int {regN} = insn->regno[{regno}] "
> -"+ HEX_REG_SA0;\n"
> -)
> -f.write(f"ctx_log_reg_read_pair(ctx, {regN});\n")
> -elif regid == "dd":
> -f.write(f"const int {regN} = insn->regno[{regno}] " "+
> HEX_REG_SA0;\n")
> -f.write(f"ctx_log_reg_write_pair(ctx, {regN},
> {predicated});\n")
> -elif regid == "s":
> -f.write(
> -f"const int {regN} = insn->regno[{regno}] "
> -"+ HEX_REG_SA0;\n"
> -)
> -f.write(f"ctx_log_reg_read(ctx, {regN});\n")
> -elif regid == "d":
> -f.write(f"const int {regN} = insn->regno[{regno}] " "+
> HEX_REG_SA0;\n")
> -f.write(f"ctx_log_reg_write(ctx, {regN}, {predicated});\n")
> -else:
> -hex_common.bad_register(regtype, regid)
> -elif regtype == "M":
> -if regid == "u":
> -f.write(f"const int {regN} = insn->regno[{regno}];\n")
> -f.write(f"ctx_log_reg_read(ctx, {regN});\n")
> -
RE: [PATCH v2 2/9] Hexagon (target/hexagon) Make generators object oriented - gen_tcg_funcs
> -Original Message-
> From: Taylor Simpson
> Sent: Sunday, December 10, 2023 4:07 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ; Marco
> Liebel (QUIC) ; richard.hender...@linaro.org;
> phi...@linaro.org; a...@rev.ng; a...@rev.ng; ltaylorsimp...@gmail.com
> Subject: [PATCH v2 2/9] Hexagon (target/hexagon) Make generators object
> oriented - gen_tcg_funcs
>
> WARNING: This email originated from outside of Qualcomm. Please be wary of
> any links or attachments, and do not enable macros.
>
> The generators are generally a bunch of Python if-then-else
> statements based on the regtype and regid. Encapsulate regtype/regid
> into a class hierarchy. Clients lookup the register and invoke
> methods.
>
> This has several advantages for making the code easier to read,
> understand, and maintain
> - The class name makes it more clear what the operand does
> - All the methods for a given type of operand are together
> - Don't need hex_common.bad_register
> If a regtype/regid is missing, the lookup in hex_common.get_register
> will fail
> - We can remove the functions in hex_common that use regtype/regid
> (e.g., is_read)
>
> This patch creates the class hierarchy in hex_common and converts
> gen_tcg_funcs.py. The other scripts will be converted in subsequent
> patches in this series.
>
> Signed-off-by: Taylor Simpson
> ---
> target/hexagon/gen_tcg_funcs.py | 571 ++-
> target/hexagon/hex_common.py| 659
>
> 2 files changed, 683 insertions(+), 547 deletions(-)
>
> diff --git a/target/hexagon/gen_tcg_funcs.py
> b/target/hexagon/gen_tcg_funcs.py
> index 02d93bc5ce..3d8e3cb6a2 100755
> --- a/target/hexagon/gen_tcg_funcs.py
> +++ b/target/hexagon/gen_tcg_funcs.py
> @@ -23,466 +23,13 @@
> import hex_common
>
>
> -##
> -## Helpers for gen_tcg_func
> -##
> -def gen_decl_ea_tcg(f, tag):
> -f.write("TCGv EA G_GNUC_UNUSED = tcg_temp_new();\n")
> -
> -
> -def genptr_decl_pair_writable(f, tag, regtype, regid, regno):
> -regN = f"{regtype}{regid}N"
> -if regtype == "R":
> -f.write(f"const int {regN} = insn->regno[{regno}];\n")
> -elif regtype == "C":
> -f.write(f"const int {regN} = insn->regno[{regno}] +
> HEX_REG_SA0;\n")
> -else:
> -hex_common.bad_register(regtype, regid)
> -f.write(f"TCGv_i64 {regtype}{regid}V = " f"get_result_gpr_pair(ctx,
> {regN});\n")
> -
> -
> -def genptr_decl_writable(f, tag, regtype, regid, regno):
> -regN = f"{regtype}{regid}N"
> -if regtype == "R":
> -f.write(f"const int {regN} = insn->regno[{regno}];\n")
> -f.write(f"TCGv {regtype}{regid}V = get_result_gpr(ctx,
> {regN});\n")
> -elif regtype == "C":
> -f.write(f"const int {regN} = insn->regno[{regno}] +
> HEX_REG_SA0;\n")
> -f.write(f"TCGv {regtype}{regid}V = get_result_gpr(ctx,
> {regN});\n")
> -elif regtype == "P":
> -f.write(f"const int {regN} = insn->regno[{regno}];\n")
> -f.write(f"TCGv {regtype}{regid}V = tcg_temp_new();\n")
> -else:
> -hex_common.bad_register(regtype, regid)
> -
> -
> -def genptr_decl(f, tag, regtype, regid, regno):
> -regN = f"{regtype}{regid}N"
> -if regtype == "R":
> -if regid in {"ss", "tt"}:
> -f.write(f"TCGv_i64 {regtype}{regid}V =
> tcg_temp_new_i64();\n")
> -f.write(f"const int {regN} = insn->regno[{regno}];\n")
> -elif regid in {"dd", "ee", "xx", "yy"}:
> -genptr_decl_pair_writable(f, tag, regtype, regid, regno)
> -elif regid in {"s", "t", "u", "v"}:
> -f.write(
> -f"TCGv {regtype}{regid}V = "
> f"hex_gpr[insn->regno[{regno}]];\n"
> -)
> -elif regid in {"d", "e", "x", "y"}:
> -genptr_decl_writable(f, tag, regtype, regid, regno)
> -else:
> -hex_common.bad_register(regtype, regid)
> -elif regtype == "P":
> -if regid in {"s", "t", "u", "v"}:
> -f.write(
> -f"TCGv {regtype}{regid}V = "
> f"hex_pred[insn->reg
RE: [PATCH v2 3/9] Hexagon (target/hexagon) Make generators object oriented - gen_helper_protos
> -Original Message-
> From: Taylor Simpson
> Sent: Sunday, December 10, 2023 4:07 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ; Marco
> Liebel (QUIC) ; richard.hender...@linaro.org;
> phi...@linaro.org; a...@rev.ng; a...@rev.ng; ltaylorsimp...@gmail.com
> Subject: [PATCH v2 3/9] Hexagon (target/hexagon) Make generators object
> oriented - gen_helper_protos
>
> WARNING: This email originated from outside of Qualcomm. Please be wary of
> any links or attachments, and do not enable macros.
>
> Signed-off-by: Taylor Simpson
> ---
> target/hexagon/gen_helper_protos.py | 149 ++--
> target/hexagon/hex_common.py| 7 --
> 2 files changed, 8 insertions(+), 148 deletions(-)
>
> diff --git a/target/hexagon/gen_helper_protos.py
> b/target/hexagon/gen_helper_protos.py
> index 131043795a..c82b0f54e4 100755
> --- a/target/hexagon/gen_helper_protos.py
> +++ b/target/hexagon/gen_helper_protos.py
> @@ -22,39 +22,6 @@
> import string
> import hex_common
>
> -##
> -## Helpers for gen_helper_prototype
> -##
> -def_helper_types = {
> -"N": "s32",
> -"O": "s32",
> -"P": "s32",
> -"M": "s32",
> -"C": "s32",
> -"R": "s32",
> -"V": "ptr",
> -"Q": "ptr",
> -}
> -
> -def_helper_types_pair = {
> -"R": "s64",
> -"C": "s64",
> -"S": "s64",
> -"G": "s64",
> -"V": "ptr",
> -"Q": "ptr",
> -}
> -
> -
> -def gen_def_helper_opn(f, tag, regtype, regid, i):
> -if hex_common.is_pair(regid):
> -f.write(f", {def_helper_types_pair[regtype]}")
> -elif hex_common.is_single(regid):
> -f.write(f", {def_helper_types[regtype]}")
> -else:
> -hex_common.bad_register(regtype, regid)
> -
> -
> ##
> ## Generate the DEF_HELPER prototype for an instruction
> ## For A2_add: Rd32=add(Rs32,Rt32)
> @@ -65,116 +32,15 @@ def gen_helper_prototype(f, tag, tagregs, tagimms):
> regs = tagregs[tag]
> imms = tagimms[tag]
>
> -numresults = 0
> -numscalarresults = 0
> -numscalarreadwrite = 0
> -for regtype, regid in regs:
> -if hex_common.is_written(regid):
> -numresults += 1
> -if hex_common.is_scalar_reg(regtype):
> -numscalarresults += 1
> -if hex_common.is_readwrite(regid):
> -if hex_common.is_scalar_reg(regtype):
> -numscalarreadwrite += 1
> -
> -if numscalarresults > 1:
> -## The helper is bogus when there is more than one result
> -f.write(f"DEF_HELPER_1({tag}, void, env)\n")
> -else:
> -## Figure out how many arguments the helper will take
> -if numscalarresults == 0:
> -def_helper_size = len(regs) + len(imms) + numscalarreadwrite + 1
> -if hex_common.need_pkt_has_multi_cof(tag):
> -def_helper_size += 1
> -if hex_common.need_pkt_need_commit(tag):
> -def_helper_size += 1
> -if hex_common.need_part1(tag):
> -def_helper_size += 1
> -if hex_common.need_slot(tag):
> -def_helper_size += 1
> -if hex_common.need_PC(tag):
> -def_helper_size += 1
> -if hex_common.helper_needs_next_PC(tag):
> -def_helper_size += 1
> -if hex_common.need_condexec_reg(tag, regs):
> -def_helper_size += 1
> -f.write(f"DEF_HELPER_{def_helper_size}({tag}")
> -## The return type is void
> -f.write(", void")
> -else:
> -def_helper_size = len(regs) + len(imms) + numscalarreadwrite
> -if hex_common.need_pkt_has_multi_cof(tag):
> -def_helper_size += 1
> -if hex_common.need_pkt_need_commit(tag):
> -def_helper_size += 1
> -if hex_common.need_part1(tag):
> -def_helper_size += 1
> -if hex_common.need_slot(tag):
> -def_helper_size += 1
> -if hex_common.need_PC(tag):
> -def_helper_size += 1
> -if hex_common.need_condexec_reg(tag, regs):
> -def_helper_size += 1
> -if hex_common.helper_needs_next_PC(tag):
> -def_he
RE: [PATCH v2 5/9] Hexagon (target/hexagon) Make generators object oriented - gen_idef_parser_funcs
> -Original Message-
> From: Taylor Simpson
> Sent: Sunday, December 10, 2023 4:07 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ; Marco
> Liebel (QUIC) ; richard.hender...@linaro.org;
> phi...@linaro.org; a...@rev.ng; a...@rev.ng; ltaylorsimp...@gmail.com
> Subject: [PATCH v2 5/9] Hexagon (target/hexagon) Make generators object
> oriented - gen_idef_parser_funcs
>
> WARNING: This email originated from outside of Qualcomm. Please be wary of
> any links or attachments, and do not enable macros.
>
> Signed-off-by: Taylor Simpson
> ---
> target/hexagon/gen_idef_parser_funcs.py | 20
> 1 file changed, 4 insertions(+), 16 deletions(-)
>
> diff --git a/target/hexagon/gen_idef_parser_funcs.py
> b/target/hexagon/gen_idef_parser_funcs.py
> index f4518e653f..550a48cb7b 100644
> --- a/target/hexagon/gen_idef_parser_funcs.py
> +++ b/target/hexagon/gen_idef_parser_funcs.py
> @@ -46,6 +46,7 @@ def main():
> hex_common.read_semantics_file(sys.argv[1])
> hex_common.read_attribs_file(sys.argv[2])
> hex_common.calculate_attribs()
> +hex_common.init_registers()
> tagregs = hex_common.get_tagregs()
> tagimms = hex_common.get_tagimms()
>
> @@ -132,22 +133,9 @@ def main():
>
> arguments = []
> for regtype, regid in regs:
> -prefix = "in " if hex_common.is_read(regid) else ""
> -
> -is_pair = hex_common.is_pair(regid)
> -is_single_old = hex_common.is_single(regid) and
> hex_common.is_old_val(
> -regtype, regid, tag
> -)
> -is_single_new = hex_common.is_single(regid) and
> hex_common.is_new_val(
> -regtype, regid, tag
> -)
> -
> -if is_pair or is_single_old:
> -arguments.append(f"{prefix}{regtype}{regid}V")
> -elif is_single_new:
> -arguments.append(f"{prefix}{regtype}{regid}N")
> -else:
> -hex_common.bad_register(regtype, regid)
> +reg = hex_common.get_register(tag, regtype, regid)
> +prefix = "in " if reg.is_read() else ""
> +arguments.append(f"{prefix}{reg.reg_tcg()}")
>
> for immlett, bits, immshift in imms:
> arguments.append(hex_common.imm_name(immlett))
> --
> 2.34.1
Reviewed-by: Brian Cain
testing without the translation cache
Alex, A very long time ago QEMU supported disabling the translation cache via "-translation no-cache". That option was deliberately removed. We are looking into a hexagon-specific failure when there's a TB lookup miss from a cpu_loop_exit_restore().I'd like to test our fix for this failure and was wondering if there's any mechanism to disable the cache. There's a "-accel tcg,tb-size=0" - but this won't accomplish what I'm looking to do - will it? If not, is there another way to disable the cache? -Brian
RE: [PATCH 3/9] Hexagon (target/hexagon) Make generators object oriented - gen_helper_protos
> -Original Message-
> From: Taylor Simpson
> Sent: Monday, December 4, 2023 7:53 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ; Marco
> Liebel (QUIC) ; richard.hender...@linaro.org;
> phi...@linaro.org; a...@rev.ng; a...@rev.ng; ltaylorsimp...@gmail.com
> Subject: [PATCH 3/9] Hexagon (target/hexagon) Make generators object
> oriented - gen_helper_protos
>
> WARNING: This email originated from outside of Qualcomm. Please be wary of
> any links or attachments, and do not enable macros.
>
> Signed-off-by: Taylor Simpson
> ---
> target/hexagon/gen_helper_protos.py | 184
> target/hexagon/hex_common.py| 15 +--
> 2 files changed, 55 insertions(+), 144 deletions(-)
>
> diff --git a/target/hexagon/gen_helper_protos.py
> b/target/hexagon/gen_helper_protos.py
> index 131043795a..9277199e1d 100755
> --- a/target/hexagon/gen_helper_protos.py
> +++ b/target/hexagon/gen_helper_protos.py
> @@ -22,39 +22,6 @@
> import string
> import hex_common
>
> -##
> -## Helpers for gen_helper_prototype
> -##
> -def_helper_types = {
> -"N": "s32",
> -"O": "s32",
> -"P": "s32",
> -"M": "s32",
> -"C": "s32",
> -"R": "s32",
> -"V": "ptr",
> -"Q": "ptr",
> -}
> -
> -def_helper_types_pair = {
> -"R": "s64",
> -"C": "s64",
> -"S": "s64",
> -"G": "s64",
> -"V": "ptr",
> -"Q": "ptr",
> -}
> -
> -
> -def gen_def_helper_opn(f, tag, regtype, regid, i):
> -if hex_common.is_pair(regid):
> -f.write(f", {def_helper_types_pair[regtype]}")
> -elif hex_common.is_single(regid):
> -f.write(f", {def_helper_types[regtype]}")
> -else:
> -hex_common.bad_register(regtype, regid)
> -
> -
> ##
> ## Generate the DEF_HELPER prototype for an instruction
> ## For A2_add: Rd32=add(Rs32,Rt32)
> @@ -65,116 +32,62 @@ def gen_helper_prototype(f, tag, tagregs, tagimms):
> regs = tagregs[tag]
> imms = tagimms[tag]
>
> -numresults = 0
> +## If there is a scalar result, it is the return type
> +return_type = ""
Should we use `return_type = None` here?
> numscalarresults = 0
> -numscalarreadwrite = 0
> for regtype, regid in regs:
> -if hex_common.is_written(regid):
> -numresults += 1
> -if hex_common.is_scalar_reg(regtype):
> +reg = hex_common.get_register(tag, regtype, regid)
> +if reg.is_written() and reg.is_scalar_reg():
> +return_type = reg.helper_proto_type()
> numscalarresults += 1
> -if hex_common.is_readwrite(regid):
> -if hex_common.is_scalar_reg(regtype):
> -numscalarreadwrite += 1
> +if numscalarresults == 0:
> +return_type = "void"
Should we use `return_type = None` here?
>
> if numscalarresults > 1:
> -## The helper is bogus when there is more than one result
> -f.write(f"DEF_HELPER_1({tag}, void, env)\n")
> -else:
> -## Figure out how many arguments the helper will take
> -if numscalarresults == 0:
> -def_helper_size = len(regs) + len(imms) + numscalarreadwrite + 1
> -if hex_common.need_pkt_has_multi_cof(tag):
> -def_helper_size += 1
> -if hex_common.need_pkt_need_commit(tag):
> -def_helper_size += 1
> -if hex_common.need_part1(tag):
> -def_helper_size += 1
> -if hex_common.need_slot(tag):
> -def_helper_size += 1
> -if hex_common.need_PC(tag):
> -def_helper_size += 1
> -if hex_common.helper_needs_next_PC(tag):
> -def_helper_size += 1
> -if hex_common.need_condexec_reg(tag, regs):
> -def_helper_size += 1
> -f.write(f"DEF_HELPER_{def_helper_size}({tag}")
> -## The return type is void
> -f.write(", void")
> -else:
> -def_helper_size = len(regs) + len(imms) + numscalarreadwrite
> -if hex_common.need_pkt_has_multi_cof(tag):
> -def_helper_size += 1
> -if hex_common.need_pkt_need_commit(tag):
> -def_helper_size += 1
> -if hex_common.
RE: [PATCH 1/9] Hexagon (target/hexagon) Clean up handling of modifier registers
> -Original Message-
> From: Taylor Simpson
> Sent: Monday, December 4, 2023 7:53 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ; Marco
> Liebel (QUIC) ; richard.hender...@linaro.org;
> phi...@linaro.org; a...@rev.ng; a...@rev.ng; ltaylorsimp...@gmail.com
> Subject: [PATCH 1/9] Hexagon (target/hexagon) Clean up handling of modifier
> registers
>
> WARNING: This email originated from outside of Qualcomm. Please be wary of
> any links or attachments, and do not enable macros.
>
> Currently, the register number (MuN) for modifier registers is the
> modifier register number rather than the index into hex_gpr. This
> patch changes MuN to the hex_gpr index, which is consistent with
> the handling of control registers.
>
> Note that HELPER(fcircadd) needs the CS register corresponding to the
> modifier register specified in the instruction. We create a TCGv
> variable "CS" to hold the value to pass to the helper.
>
> Signed-off-by: Taylor Simpson
> ---
> target/hexagon/gen_tcg.h| 9 -
> target/hexagon/macros.h | 3 +--
> target/hexagon/idef-parser/parser-helpers.c | 8 +++-
> target/hexagon/gen_tcg_funcs.py | 13 +
> 4 files changed, 17 insertions(+), 16 deletions(-)
>
> diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
> index d992059fce..1c4391b415 100644
> --- a/target/hexagon/gen_tcg.h
> +++ b/target/hexagon/gen_tcg.h
> @@ -68,15 +68,14 @@
> do { \
> TCGv tcgv_siV = tcg_constant_tl(siV); \
> tcg_gen_mov_tl(EA, RxV); \
> -gen_helper_fcircadd(RxV, RxV, tcgv_siV, MuV, \
> -hex_gpr[HEX_REG_CS0 + MuN]); \
> +gen_helper_fcircadd(RxV, RxV, tcgv_siV, MuV, CS); \
> } while (0)
> #define GET_EA_pcr(SHIFT) \
> do { \
> TCGv ireg = tcg_temp_new(); \
> tcg_gen_mov_tl(EA, RxV); \
> gen_read_ireg(ireg, MuV, (SHIFT)); \
> -gen_helper_fcircadd(RxV, RxV, ireg, MuV, hex_gpr[HEX_REG_CS0 +
> MuN]); \
> +gen_helper_fcircadd(RxV, RxV, ireg, MuV, CS); \
> } while (0)
>
> /* Instructions with multiple definitions */
> @@ -113,7 +112,7 @@
> TCGv ireg = tcg_temp_new(); \
> tcg_gen_mov_tl(EA, RxV); \
> gen_read_ireg(ireg, MuV, SHIFT); \
> -gen_helper_fcircadd(RxV, RxV, ireg, MuV, hex_gpr[HEX_REG_CS0 +
> MuN]); \
> +gen_helper_fcircadd(RxV, RxV, ireg, MuV, CS); \
> LOAD; \
> } while (0)
>
> @@ -427,7 +426,7 @@
> TCGv BYTE G_GNUC_UNUSED = tcg_temp_new(); \
> tcg_gen_mov_tl(EA, RxV); \
> gen_read_ireg(ireg, MuV, SHIFT); \
> -gen_helper_fcircadd(RxV, RxV, ireg, MuV, hex_gpr[HEX_REG_CS0 +
> MuN]); \
> +gen_helper_fcircadd(RxV, RxV, ireg, MuV, CS); \
> STORE; \
> } while (0)
>
> diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
> index 9a51b5709b..939f22e76b 100644
> --- a/target/hexagon/macros.h
> +++ b/target/hexagon/macros.h
> @@ -462,8 +462,7 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val,
> int shift)
> #define fPM_CIRI(REG, IMM, MVAL) \
> do { \
> TCGv tcgv_siV = tcg_constant_tl(siV); \
> -gen_helper_fcircadd(REG, REG, tcgv_siV, MuV, \
> -hex_gpr[HEX_REG_CS0 + MuN]); \
> +gen_helper_fcircadd(REG, REG, tcgv_siV, MuV, CS); \
> } while (0)
> #else
> #define fEA_IMM(IMM)do { EA = (IMM); } while (0)
> diff --git a/target/hexagon/idef-parser/parser-helpers.c
> b/target/hexagon/idef-
> parser/parser-helpers.c
> index 4af020933a..95f2b43076 100644
> --- a/target/hexagon/idef-parser/parser-helpers.c
> +++ b/target/hexagon/idef-parser/parser-helpers.c
> @@ -1541,10 +1541,8 @@ void gen_circ_op(Context *c,
> HexValue *increment,
> HexValue *modifier)
> {
> -HexValue cs = gen_tmp(c, locp, 32, UNSIGNED);
> HexValue increment_m = *increment;
> increment_m = rvalue_materialize(c, locp, _m);
> -OUT(c, locp, "gen_read_reg(", , ", HEX_REG_CS0 + MuN);\n");
> OUT(c,
> locp,
> "gen_helper_fcircadd(",
> @@ -1555,7 +1553,7 @@ void gen_circ_op(Context *c,
> _m,
> ", ",
> modifier);
> -OUT(c, locp, ", ", , ");\n");
> +OUT(c, locp, ", CS);\n");
> }
>
> HexValue gen_locnt_op(Context *c, YYLTYPE *locp, HexValue *src)
> @@ -2080,9 +2078,9 @@ void emit_arg(Context *c, YYLTYPE *locp, HexValue
>
RE: [PATCH 6/9] Hexagon (target/hexagon) Make generators object oriented - gen_op_regs
> -Original Message- > From: Taylor Simpson > Sent: Monday, December 4, 2023 7:53 PM > To: qemu-devel@nongnu.org > Cc: Brian Cain ; Matheus Bernardino (QUIC) > ; Sid Manning ; Marco > Liebel (QUIC) ; richard.hender...@linaro.org; > phi...@linaro.org; a...@rev.ng; a...@rev.ng; ltaylorsimp...@gmail.com > Subject: [PATCH 6/9] Hexagon (target/hexagon) Make generators object > oriented - gen_op_regs > > WARNING: This email originated from outside of Qualcomm. Please be wary of > any links or attachments, and do not enable macros. > > Signed-off-by: Taylor Simpson > --- > target/hexagon/gen_op_regs.py | 6 -- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/target/hexagon/gen_op_regs.py b/target/hexagon/gen_op_regs.py > index a8a7712129..7b7b33895a 100755 > --- a/target/hexagon/gen_op_regs.py > +++ b/target/hexagon/gen_op_regs.py > @@ -70,6 +70,7 @@ def strip_reg_prefix(x): > def main(): > hex_common.read_semantics_file(sys.argv[1]) > hex_common.read_attribs_file(sys.argv[2]) > +hex_common.init_registers() > tagregs = hex_common.get_tagregs(full=True) > tagimms = hex_common.get_tagimms() > > @@ -80,11 +81,12 @@ def main(): > wregs = [] > regids = "" > for regtype, regid, _, numregs in regs: > -if hex_common.is_read(regid): > +reg = hex_common.get_register(tag, regtype, regid) > +if reg.is_read(): > if regid[0] not in regids: > regids += regid[0] > rregs.append(regtype + regid + numregs) > -if hex_common.is_written(regid): > +if reg.is_written(): > wregs.append(regtype + regid + numregs) > if regid[0] not in regids: > regids += regid[0] > -- > 2.34.1 Reviewed-by: Brian Cain
RE: [PATCH 2/9] Hexagon (target/hexagon) Make generators object oriented - gen_tcg_funcs
> -Original Message-
> From: Taylor Simpson
> Sent: Monday, December 4, 2023 7:53 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ; Marco
> Liebel (QUIC) ; richard.hender...@linaro.org;
> phi...@linaro.org; a...@rev.ng; a...@rev.ng; ltaylorsimp...@gmail.com
> Subject: [PATCH 2/9] Hexagon (target/hexagon) Make generators object
> oriented - gen_tcg_funcs
>
> WARNING: This email originated from outside of Qualcomm. Please be wary of
> any links or attachments, and do not enable macros.
>
> The generators are generally a bunch of Python if-then-else
> statements based on the regtype and regid. Encapsulate regtype/regid
> into a class hierarchy. Clients lookup the register and invoke
> methods.
>
> This has several advantages for making the code easier to read,
> understand, and maintain
> - The class name makes it more clear what the operand does
> - All the methods for a given type of operand are together
> - Don't need hex_common.bad_register
> If a regtype/regid is missing, the lookup in hex_common.get_register
> will fail
> - We can remove the functions in hex_common that use regtype/regid
> (e.g., is_read)
>
> This patch creates the class hierarchy in hex_common and converts
> gen_tcg_funcs.py. The other scripts will be converted in subsequent
> patches in this series.
>
> Signed-off-by: Taylor Simpson
> ---
> target/hexagon/gen_tcg_funcs.py | 583 +++-
> target/hexagon/hex_common.py| 542 +
> 2 files changed, 589 insertions(+), 536 deletions(-)
>
> diff --git a/target/hexagon/gen_tcg_funcs.py
> b/target/hexagon/gen_tcg_funcs.py
> index 02d93bc5ce..8c2bc03c10 100755
> --- a/target/hexagon/gen_tcg_funcs.py
> +++ b/target/hexagon/gen_tcg_funcs.py
> @@ -23,466 +23,13 @@
> import hex_common
>
>
> -##
> -## Helpers for gen_tcg_func
> -##
> -def gen_decl_ea_tcg(f, tag):
> -f.write("TCGv EA G_GNUC_UNUSED = tcg_temp_new();\n")
> -
> -
> -def genptr_decl_pair_writable(f, tag, regtype, regid, regno):
> -regN = f"{regtype}{regid}N"
> -if regtype == "R":
> -f.write(f"const int {regN} = insn->regno[{regno}];\n")
> -elif regtype == "C":
> -f.write(f"const int {regN} = insn->regno[{regno}] +
> HEX_REG_SA0;\n")
> -else:
> -hex_common.bad_register(regtype, regid)
> -f.write(f"TCGv_i64 {regtype}{regid}V = " f"get_result_gpr_pair(ctx,
> {regN});\n")
> -
> -
> -def genptr_decl_writable(f, tag, regtype, regid, regno):
> -regN = f"{regtype}{regid}N"
> -if regtype == "R":
> -f.write(f"const int {regN} = insn->regno[{regno}];\n")
> -f.write(f"TCGv {regtype}{regid}V = get_result_gpr(ctx,
> {regN});\n")
> -elif regtype == "C":
> -f.write(f"const int {regN} = insn->regno[{regno}] +
> HEX_REG_SA0;\n")
> -f.write(f"TCGv {regtype}{regid}V = get_result_gpr(ctx,
> {regN});\n")
> -elif regtype == "P":
> -f.write(f"const int {regN} = insn->regno[{regno}];\n")
> -f.write(f"TCGv {regtype}{regid}V = tcg_temp_new();\n")
> -else:
> -hex_common.bad_register(regtype, regid)
> -
> -
> -def genptr_decl(f, tag, regtype, regid, regno):
> -regN = f"{regtype}{regid}N"
> -if regtype == "R":
> -if regid in {"ss", "tt"}:
> -f.write(f"TCGv_i64 {regtype}{regid}V =
> tcg_temp_new_i64();\n")
> -f.write(f"const int {regN} = insn->regno[{regno}];\n")
> -elif regid in {"dd", "ee", "xx", "yy"}:
> -genptr_decl_pair_writable(f, tag, regtype, regid, regno)
> -elif regid in {"s", "t", "u", "v"}:
> -f.write(
> -f"TCGv {regtype}{regid}V = "
> f"hex_gpr[insn->regno[{regno}]];\n"
> -)
> -elif regid in {"d", "e", "x", "y"}:
> -genptr_decl_writable(f, tag, regtype, regid, regno)
> -else:
> -hex_common.bad_register(regtype, regid)
> -elif regtype == "P":
> -if regid in {"s", "t", "u", "v"}:
> -f.write(
> -f"TCGv {regtype}{regid}V = "
> f"hex_pred[insn->regno[
RE: [PATCH] Hexagon (target/hexagon) Fix shadow variable when idef-parser is off
> -Original Message-
> From: Philippe Mathieu-Daudé
> Sent: Thursday, November 30, 2023 2:17 PM
> To: Taylor Simpson ; qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ; Marco
> Liebel (QUIC) ; richard.hender...@linaro.org;
> a...@rev.ng; a...@rev.ng
> Subject: Re: [PATCH] Hexagon (target/hexagon) Fix shadow variable when idef-
> parser is off
>
> WARNING: This email originated from outside of Qualcomm. Please be wary of
> any links or attachments, and do not enable macros.
>
> On 30/11/23 19:39, Taylor Simpson wrote:
> > Adding -Werror=shadow=compatible-local causes Hexagon not to build
> > when idef-parser is off. The "label" variable in CHECK_NOSHUF_PRED
> > shadows a variable in the surrounding code.
> >
> > Signed-off-by: Taylor Simpson
> > ---
> > target/hexagon/macros.h | 6 +++---
> > 1 file changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
> > index 9a51b5709b..f99390e2a8 100644
> > --- a/target/hexagon/macros.h
> > +++ b/target/hexagon/macros.h
> > @@ -93,13 +93,13 @@
> >
> > #define CHECK_NOSHUF_PRED(GET_EA, SIZE, PRED) \
> > do { \
> > -TCGLabel *label = gen_new_label(); \
> > -tcg_gen_brcondi_tl(TCG_COND_EQ, PRED, 0, label); \
> > +TCGLabel *noshuf_label = gen_new_label(); \
> > +tcg_gen_brcondi_tl(TCG_COND_EQ, PRED, 0, noshuf_label); \
>
> Fragile, but sufficient.
The fragility here refers to the fact that CHECK_NOSHUF_PRED() macro could show
up in other contexts and then could shadow those?
We could change the macro to a function or expand the macro to take a label
declared outside. Would that be preferred? Or are there other suggestions?
-Brian
RE: [PATCH] Hexagon (target/hexagon) Fix shadow variable when idef-parser is off
> -Original Message-
> From: Taylor Simpson
> Sent: Thursday, November 30, 2023 12:40 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ; Marco
> Liebel (QUIC) ; richard.hender...@linaro.org;
> phi...@linaro.org; a...@rev.ng; a...@rev.ng; ltaylorsimp...@gmail.com
> Subject: [PATCH] Hexagon (target/hexagon) Fix shadow variable when idef-
> parser is off
>
> WARNING: This email originated from outside of Qualcomm. Please be wary of
> any links or attachments, and do not enable macros.
>
> Adding -Werror=shadow=compatible-local causes Hexagon not to build
> when idef-parser is off. The "label" variable in CHECK_NOSHUF_PRED
> shadows a variable in the surrounding code.
>
> Signed-off-by: Taylor Simpson
> ---
> target/hexagon/macros.h | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
> index 9a51b5709b..f99390e2a8 100644
> --- a/target/hexagon/macros.h
> +++ b/target/hexagon/macros.h
> @@ -93,13 +93,13 @@
>
> #define CHECK_NOSHUF_PRED(GET_EA, SIZE, PRED) \
> do { \
> -TCGLabel *label = gen_new_label(); \
> -tcg_gen_brcondi_tl(TCG_COND_EQ, PRED, 0, label); \
> +TCGLabel *noshuf_label = gen_new_label(); \
> +tcg_gen_brcondi_tl(TCG_COND_EQ, PRED, 0, noshuf_label); \
> GET_EA; \
> if (insn->slot == 0 && ctx->pkt->pkt_has_store_s1) { \
> probe_noshuf_load(EA, SIZE, ctx->mem_idx); \
> } \
> -gen_set_label(label); \
> +gen_set_label(noshuf_label); \
> if (insn->slot == 0 && ctx->pkt->pkt_has_store_s1) { \
> process_store(ctx, 1); \
> } \
> --
> 2.34.1
Reviewed-by: Brian Cain
RE: [PULL v2 25/30] Hexagon HVX (target/hexagon) instruction decoding
> -Original Message-
> From: Brian Cain
> Sent: Tuesday, November 21, 2023 9:52 AM
> To: Peter Maydell
> Cc: qemu-devel@nongnu.org; richard.hender...@linaro.org; f4...@amsat.org
> Subject: RE: [PULL v2 25/30] Hexagon HVX (target/hexagon) instruction
> decoding
>
>
>
> > -Original Message-
> > From: qemu-devel-bounces+bcain=quicinc@nongnu.org > bounces+bcain=quicinc@nongnu.org> On Behalf Of Peter Maydell
> > Sent: Tuesday, November 21, 2023 8:33 AM
> > To: Taylor Simpson
> > Cc: qemu-devel@nongnu.org; richard.hender...@linaro.org;
> f4...@amsat.org
> > Subject: Re: [PULL v2 25/30] Hexagon HVX (target/hexagon) instruction
> > decoding
> >
> > WARNING: This email originated from outside of Qualcomm. Please be wary
> of
> > any links or attachments, and do not enable macros.
> >
> > On Wed, 3 Nov 2021 at 21:17, Taylor Simpson
> wrote:
> > >
> > > Add new file to target/hexagon/meson.build
> > >
> > > Acked-by: Richard Henderson
> > > Signed-off-by: Taylor Simpson
> >
> > Hi; Coverity points out a variable written to and then
> > overwritten before it's ever used in this function (CID 1527408):
> >
> >
> >
> >
> > > +static void
> > > +check_new_value(Packet *pkt)
> > > +{
> > > +/* .new value for a MMVector store */
> > > +int i, j;
> > > +const char *reginfo;
> > > +const char *destletters;
> > > +const char *dststr = NULL;
> > > +uint16_t def_opcode;
> > > +char letter;
> > > +int def_regnum;
> >
> > def_regnum has function level scope...
> >
> > > +
> > > +for (i = 1; i < pkt->num_insns; i++) {
> > > +uint16_t use_opcode = pkt->insn[i].opcode;
> > > +if (GET_ATTRIB(use_opcode, A_DOTNEWVALUE) &&
> > > +GET_ATTRIB(use_opcode, A_CVI) &&
> > > +GET_ATTRIB(use_opcode, A_STORE)) {
> > > +int use_regidx = strchr(opcode_reginfo[use_opcode], 's') -
> > > +opcode_reginfo[use_opcode];
> > > +/*
> > > + * What's encoded at the N-field is the offset to who's
> > > producing
> > > + * the value.
> > > + * Shift off the LSB which indicates odd/even register.
> > > + */
> > > +int def_off = ((pkt->insn[i].regno[use_regidx]) >> 1);
> > > +int def_oreg = pkt->insn[i].regno[use_regidx] & 1;
> > > +int def_idx = -1;
> > > +for (j = i - 1; (j >= 0) && (def_off >= 0); j--) {
> > > +if (!GET_ATTRIB(pkt->insn[j].opcode, A_CVI)) {
> > > +continue;
> > > +}
> > > +def_off--;
> > > +if (def_off == 0) {
> > > +def_idx = j;
> > > +break;
> > > +}
> > > +}
> > > +/*
> > > + * Check for a badly encoded N-field which points to an
> > > instruction
> > > + * out-of-range
> > > + */
> > > +g_assert(!((def_off != 0) || (def_idx < 0) ||
> > > + (def_idx > (pkt->num_insns - 1;
> > > +
> > > +/* def_idx is the index of the producer */
> > > +def_opcode = pkt->insn[def_idx].opcode;
> > > +reginfo = opcode_reginfo[def_opcode];
> > > +destletters = "dexy";
> > > +for (j = 0; (letter = destletters[j]) != 0; j++) {
> > > +dststr = strchr(reginfo, letter);
> > > +if (dststr != NULL) {
> > > +break;
> > > +}
> > > +}
> > > +if ((dststr == NULL) && GET_ATTRIB(def_opcode,
> > > A_CVI_GATHER))
> {
> > > +def_regnum = 0;
> >
> > In this half of the if() we set it to 0...
> >
> > > +pkt->insn[i].regno[use_regidx] = def_oreg;
> > > +pkt->insn[i].new_value_producer_slot =
> > > pkt->insn[def_idx].slot;
> > > +} else {
> > > +if (dststr == NULL) {
> > > +/* still not there, we have a bad packet */
> > > +
RE: [PULL v2 25/30] Hexagon HVX (target/hexagon) instruction decoding
> -Original Message-
> From: qemu-devel-bounces+bcain=quicinc@nongnu.org bounces+bcain=quicinc@nongnu.org> On Behalf Of Peter Maydell
> Sent: Tuesday, November 21, 2023 8:33 AM
> To: Taylor Simpson
> Cc: qemu-devel@nongnu.org; richard.hender...@linaro.org; f4...@amsat.org
> Subject: Re: [PULL v2 25/30] Hexagon HVX (target/hexagon) instruction
> decoding
>
> WARNING: This email originated from outside of Qualcomm. Please be wary of
> any links or attachments, and do not enable macros.
>
> On Wed, 3 Nov 2021 at 21:17, Taylor Simpson wrote:
> >
> > Add new file to target/hexagon/meson.build
> >
> > Acked-by: Richard Henderson
> > Signed-off-by: Taylor Simpson
>
> Hi; Coverity points out a variable written to and then
> overwritten before it's ever used in this function (CID 1527408):
>
>
>
>
> > +static void
> > +check_new_value(Packet *pkt)
> > +{
> > +/* .new value for a MMVector store */
> > +int i, j;
> > +const char *reginfo;
> > +const char *destletters;
> > +const char *dststr = NULL;
> > +uint16_t def_opcode;
> > +char letter;
> > +int def_regnum;
>
> def_regnum has function level scope...
>
> > +
> > +for (i = 1; i < pkt->num_insns; i++) {
> > +uint16_t use_opcode = pkt->insn[i].opcode;
> > +if (GET_ATTRIB(use_opcode, A_DOTNEWVALUE) &&
> > +GET_ATTRIB(use_opcode, A_CVI) &&
> > +GET_ATTRIB(use_opcode, A_STORE)) {
> > +int use_regidx = strchr(opcode_reginfo[use_opcode], 's') -
> > +opcode_reginfo[use_opcode];
> > +/*
> > + * What's encoded at the N-field is the offset to who's
> > producing
> > + * the value.
> > + * Shift off the LSB which indicates odd/even register.
> > + */
> > +int def_off = ((pkt->insn[i].regno[use_regidx]) >> 1);
> > +int def_oreg = pkt->insn[i].regno[use_regidx] & 1;
> > +int def_idx = -1;
> > +for (j = i - 1; (j >= 0) && (def_off >= 0); j--) {
> > +if (!GET_ATTRIB(pkt->insn[j].opcode, A_CVI)) {
> > +continue;
> > +}
> > +def_off--;
> > +if (def_off == 0) {
> > +def_idx = j;
> > +break;
> > +}
> > +}
> > +/*
> > + * Check for a badly encoded N-field which points to an
> > instruction
> > + * out-of-range
> > + */
> > +g_assert(!((def_off != 0) || (def_idx < 0) ||
> > + (def_idx > (pkt->num_insns - 1;
> > +
> > +/* def_idx is the index of the producer */
> > +def_opcode = pkt->insn[def_idx].opcode;
> > +reginfo = opcode_reginfo[def_opcode];
> > +destletters = "dexy";
> > +for (j = 0; (letter = destletters[j]) != 0; j++) {
> > +dststr = strchr(reginfo, letter);
> > +if (dststr != NULL) {
> > +break;
> > +}
> > +}
> > +if ((dststr == NULL) && GET_ATTRIB(def_opcode, A_CVI_GATHER))
> > {
> > +def_regnum = 0;
>
> In this half of the if() we set it to 0...
>
> > +pkt->insn[i].regno[use_regidx] = def_oreg;
> > +pkt->insn[i].new_value_producer_slot =
> > pkt->insn[def_idx].slot;
> > +} else {
> > +if (dststr == NULL) {
> > +/* still not there, we have a bad packet */
> > +g_assert_not_reached();
> > +}
> > +def_regnum = pkt->insn[def_idx].regno[dststr - reginfo];
> > +/* Now patch up the consumer with the register number */
> > +pkt->insn[i].regno[use_regidx] = def_regnum ^ def_oreg;
> > +/* special case for (Vx,Vy) */
> > +dststr = strchr(reginfo, 'y');
> > +if (def_oreg && strchr(reginfo, 'x') && dststr) {
> > +def_regnum = pkt->insn[def_idx].regno[dststr -
> > reginfo];
> > +pkt->insn[i].regno[use_regidx] = def_regnum;
> > +}
>
> ...but the only place we read def_regnum is in this other half of the
> if(), and if we get here then we've set it to something out of pxt->insn.
>
> Were we supposed to do something with def_regnum outside this if(),
> or could we instead drop the initialization in the first half of the if()
> and move its declaration inside this else {} block ?
Hmm -- we'll take a look at this and get back to you.
> > +/*
> > + * We need to remember who produces this value to later
> > + * check if it was dynamically cancelled
> > + */
> > +pkt->insn[i].new_value_producer_slot =
> > pkt->insn[def_idx].slot;
> > +}
> > +}
> > +}
> > +}
>
> thanks
> -- PMM
RE: [RFC PATCH] Hexagon (target/hexagon) Make generators object oriented
> -Original Message-
> From: ltaylorsimp...@gmail.com
> Sent: Thursday, November 16, 2023 1:19 PM
> To: Brian Cain ; qemu-devel@nongnu.org
> Cc: Matheus Bernardino (QUIC) ; Sid Manning
> ; richard.hender...@linaro.org; phi...@linaro.org;
> a...@rev.ng; a...@rev.ng
> Subject: RE: [RFC PATCH] Hexagon (target/hexagon) Make generators object
> oriented
>
> WARNING: This email originated from outside of Qualcomm. Please be wary of
> any links or attachments, and do not enable macros.
>
> > -----Original Message-
> > From: Brian Cain
> > Sent: Thursday, November 16, 2023 10:25 AM
> > To: ltaylorsimp...@gmail.com; qemu-devel@nongnu.org
> > Cc: Matheus Bernardino (QUIC) ; Sid
> > Manning ; richard.hender...@linaro.org;
> > phi...@linaro.org; a...@rev.ng; a...@rev.ng
> > Subject: RE: [RFC PATCH] Hexagon (target/hexagon) Make generators object
> > oriented
> >
> >
> >
> > > -Original Message-
> > > From: ltaylorsimp...@gmail.com
> > > Sent: Wednesday, November 15, 2023 4:03 PM
> > > To: Brian Cain ; qemu-devel@nongnu.org
> > > Cc: Matheus Bernardino (QUIC) ; Sid
> > Manning
> > > ; richard.hender...@linaro.org;
> > > phi...@linaro.org; a...@rev.ng; a...@rev.ng
> > > Subject: RE: [RFC PATCH] Hexagon (target/hexagon) Make generators
> > > object oriented
> > >
> > > > -Original Message-
> > > > From: Brian Cain
> > > > Sent: Wednesday, November 15, 2023 1:51 PM
> > > > To: Taylor Simpson ; qemu-
> > de...@nongnu.org
> > > > Cc: Matheus Bernardino (QUIC) ; Sid
> > > > Manning ; richard.hender...@linaro.org;
> > > > phi...@linaro.org; a...@rev.ng; a...@rev.ng
> > > > Subject: RE: [RFC PATCH] Hexagon (target/hexagon) Make generators
> > > > object oriented
> > > >
> > > >
> > > >
> > > > > -Original Message-
> > > > > From: Taylor Simpson
> > > > > Sent: Thursday, November 9, 2023 3:26 PM
> > > > > To: qemu-devel@nongnu.org
> > > > > Cc: Brian Cain ; Matheus Bernardino (QUIC)
> > > > > ; Sid Manning ;
> > > > > richard.hender...@linaro.org; phi...@linaro.org; a...@rev.ng;
> > > > a...@rev.ng;
> > > > > ltaylorsimp...@gmail.com
> > > > > Subject: [RFC PATCH] Hexagon (target/hexagon) Make generators
> > > > > object oriented
> > > > >
> > > > > RFC - This patch handles gen_tcg_funcs.py. I'd like to get
> > > > > comments on the general approach before working on the other
> > Python scripts.
> > > > >
> > > > > The generators are generally a bunch of Python if-then-else
> > > > > statements based on the regtype and regid. Encapsulate
> > > > > regtype/regid into a class hierarchy. Clients lookup the register
> > > > > and invoke methods.
> > > > >
> > > > > This has several advantages for making the code easier to read,
> > > > > understand, and maintain
> > > > > - The class name makes it more clear what the operand does
> > > > > - All the methods for a given type of operand are together
> > > > > - Don't need as many calls to hex_common.bad_register
> > > > > - We can remove the functions in hex_common that use regtype/regid
> > > > > (e.g., is_read)
> > > > >
> > > > > Signed-off-by: Taylor Simpson
> > > > > ---
> > > > > diff --git a/target/hexagon/hex_common.py
> > > > b/target/hexagon/hex_common.py
> > > > > index 0da65d6dd6..13ee55b6b2 100755
> > > > > --- a/target/hexagon/hex_common.py
> > > > > +++ b/target/hexagon/hex_common.py
> > > > > +class PredReadWrite(ReadWrite):
> > > > > +def genptr_decl(self, f, tag, regno):
> > > > > +f.write(f"const int {self.regN} =
> > > > > insn->regno[{regno}];\n")
> > > > > +f.write(f"TCGv {self.regV} = tcg_temp_new();\n")
> > > > > +f.write(f"tcg_gen_mov_tl({self.regV},
> > hex_pred[{self.regN}]);\n")
> > > >
> > > > Instead of successive calls to f.write(), each passing their own
> > > > string with a newline, use triple quotes:
> > > >
> > > > f.write(f"""const int {self.regN} = insn->regno[{regno}];
> &
RE: [RFC PATCH] Hexagon (target/hexagon) Make generators object oriented
> -Original Message-
> From: ltaylorsimp...@gmail.com
> Sent: Wednesday, November 15, 2023 4:03 PM
> To: Brian Cain ; qemu-devel@nongnu.org
> Cc: Matheus Bernardino (QUIC) ; Sid Manning
> ; richard.hender...@linaro.org; phi...@linaro.org;
> a...@rev.ng; a...@rev.ng
> Subject: RE: [RFC PATCH] Hexagon (target/hexagon) Make generators object
> oriented
>
> WARNING: This email originated from outside of Qualcomm. Please be wary of
> any links or attachments, and do not enable macros.
>
> > -----Original Message-
> > From: Brian Cain
> > Sent: Wednesday, November 15, 2023 1:51 PM
> > To: Taylor Simpson ; qemu-devel@nongnu.org
> > Cc: Matheus Bernardino (QUIC) ; Sid
> > Manning ; richard.hender...@linaro.org;
> > phi...@linaro.org; a...@rev.ng; a...@rev.ng
> > Subject: RE: [RFC PATCH] Hexagon (target/hexagon) Make generators object
> > oriented
> >
> >
> >
> > > -Original Message-----
> > > From: Taylor Simpson
> > > Sent: Thursday, November 9, 2023 3:26 PM
> > > To: qemu-devel@nongnu.org
> > > Cc: Brian Cain ; Matheus Bernardino (QUIC)
> > > ; Sid Manning ;
> > > richard.hender...@linaro.org; phi...@linaro.org; a...@rev.ng;
> > a...@rev.ng;
> > > ltaylorsimp...@gmail.com
> > > Subject: [RFC PATCH] Hexagon (target/hexagon) Make generators object
> > > oriented
> > >
> > > RFC - This patch handles gen_tcg_funcs.py. I'd like to get comments
> > > on the general approach before working on the other Python scripts.
> > >
> > > The generators are generally a bunch of Python if-then-else
> > > statements based on the regtype and regid. Encapsulate regtype/regid
> > > into a class hierarchy. Clients lookup the register and invoke
> > > methods.
> > >
> > > This has several advantages for making the code easier to read,
> > > understand, and maintain
> > > - The class name makes it more clear what the operand does
> > > - All the methods for a given type of operand are together
> > > - Don't need as many calls to hex_common.bad_register
> > > - We can remove the functions in hex_common that use regtype/regid
> > > (e.g., is_read)
> > >
> > > Signed-off-by: Taylor Simpson
> > > ---
> > > diff --git a/target/hexagon/hex_common.py
> > b/target/hexagon/hex_common.py
> > > index 0da65d6dd6..13ee55b6b2 100755
> > > --- a/target/hexagon/hex_common.py
> > > +++ b/target/hexagon/hex_common.py
> > > +class ModifierSource(Source):
> > > +def genptr_decl(self, f, tag, regno):
> > > +f.write(f"const int {self.regN} = insn->regno[{regno}];\n")
> > > +f.write(f"TCGv {self.regV} = hex_gpr[{self.regN} +
> > HEX_REG_M0];\n")
> > > +def idef_arg(self, declared):
> > > +declared.append(self.regV)
> > > +declared.append(self.regN)
> > > +
> >
> > IMO it's easier to reason about a function if it doesn't modify its inputs
> > and
> > instead it returns the transformed input. If idef_arg instead returned a
> > new
> > list or returned an iterable for the caller to catenate, it would be
> > clearer.
>
> We should figure out a better way to handle the special case of modifier
> registers. For every other register type,
> Idef_arg simply returns self.regV. For circular addressing, we also need the
> value of the corresponding CS register. Currently,
> we solve this by passing the register number so that idef-parser can get the
> value (i.e., hex_gpr[HEX_REG_CS0 + self.regN]).
>
> We could have idef-parser skip the circular addressing instructions (it
> already
> skips the bit-reverse instructions). That seems
> like a big hammer though. Any other thoughts?
>
>
> > > +class PredReadWrite(ReadWrite):
> > > +def genptr_decl(self, f, tag, regno):
> > > +f.write(f"const int {self.regN} = insn->regno[{regno}];\n")
> > > +f.write(f"TCGv {self.regV} = tcg_temp_new();\n")
> > > +f.write(f"tcg_gen_mov_tl({self.regV},
> > > hex_pred[{self.regN}]);\n")
> >
> > Instead of successive calls to f.write(), each passing their own string
> > with a
> > newline, use triple quotes:
> >
> > f.write(f"""const int {self.regN} = insn->regno[{regno}];
> > TCGv {self.regV} = tcg_temp_new();
> > tcg_gen_mov_tl({self.regV}, hex_pred[{self.regN}]);\n""")
> >
&g
RE: [RFC PATCH] Hexagon (target/hexagon) Make generators object oriented
> -Original Message-
> From: qemu-devel-bounces+bcain=quicinc@nongnu.org AFAICT the keys for registers and new_registers can be derived from the values
> themselves. Rather than worry about copy/paste errors causing these not to
> correspond, you can create a dictionary from an iterable like so:
>
> registers = (
> GprDest("R", "d"),
> GprDest("R", "e"),
> GprSource("R", "s"),
> GprSource("R", "t"),
> ...
> )
> registers = { reg.regtype + reg.regid for reg in registers }
Sorry, forgot the value - that would yield a set and not a dict.
registers = { reg.regtype + reg.regid: reg for reg in registers }
RE: [RFC PATCH] Hexagon (target/hexagon) Make generators object oriented
> -Original Message-
> From: Taylor Simpson
> Sent: Thursday, November 9, 2023 3:26 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ;
> richard.hender...@linaro.org; phi...@linaro.org; a...@rev.ng; a...@rev.ng;
> ltaylorsimp...@gmail.com
> Subject: [RFC PATCH] Hexagon (target/hexagon) Make generators object
> oriented
>
> WARNING: This email originated from outside of Qualcomm. Please be wary of
> any links or attachments, and do not enable macros.
>
> RFC - This patch handles gen_tcg_funcs.py. I'd like to get comments
> on the general approach before working on the other Python scripts.
>
> The generators are generally a bunch of Python if-then-else
> statements based on the regtype and regid. Encapsulate regtype/regid
> into a class hierarchy. Clients lookup the register and invoke
> methods.
>
> This has several advantages for making the code easier to read,
> understand, and maintain
> - The class name makes it more clear what the operand does
> - All the methods for a given type of operand are together
> - Don't need as many calls to hex_common.bad_register
> - We can remove the functions in hex_common that use regtype/regid
> (e.g., is_read)
>
> Signed-off-by: Taylor Simpson
> ---
> target/hexagon/gen_tcg_funcs.py | 568 +++-
> target/hexagon/hex_common.py| 467 ++
> 2 files changed, 509 insertions(+), 526 deletions(-)
>
> diff --git a/target/hexagon/gen_tcg_funcs.py
> b/target/hexagon/gen_tcg_funcs.py
> index f5246cee6d..f7a0c59397 100755
> --- a/target/hexagon/gen_tcg_funcs.py
> +++ b/target/hexagon/gen_tcg_funcs.py
> @@ -23,454 +23,6 @@
> import hex_common
>
>
> -##
> -## Helpers for gen_tcg_func
> -##
> -def gen_decl_ea_tcg(f, tag):
> -f.write("TCGv EA G_GNUC_UNUSED = tcg_temp_new();\n")
> -
> -
> -def genptr_decl_pair_writable(f, tag, regtype, regid, regno):
> -regN = f"{regtype}{regid}N"
> -if regtype == "R":
> -f.write(f"const int {regN} = insn->regno[{regno}];\n")
> -elif regtype == "C":
> -f.write(f"const int {regN} = insn->regno[{regno}] +
> HEX_REG_SA0;\n")
> -else:
> -hex_common.bad_register(regtype, regid)
> -f.write(f"TCGv_i64 {regtype}{regid}V = " f"get_result_gpr_pair(ctx,
> {regN});\n")
> -
> -
> -def genptr_decl_writable(f, tag, regtype, regid, regno):
> -regN = f"{regtype}{regid}N"
> -if regtype == "R":
> -f.write(f"const int {regN} = insn->regno[{regno}];\n")
> -f.write(f"TCGv {regtype}{regid}V = get_result_gpr(ctx,
> {regN});\n")
> -elif regtype == "C":
> -f.write(f"const int {regN} = insn->regno[{regno}] +
> HEX_REG_SA0;\n")
> -f.write(f"TCGv {regtype}{regid}V = get_result_gpr(ctx,
> {regN});\n")
> -elif regtype == "P":
> -f.write(f"const int {regN} = insn->regno[{regno}];\n")
> -f.write(f"TCGv {regtype}{regid}V = tcg_temp_new();\n")
> -else:
> -hex_common.bad_register(regtype, regid)
> -
> -
> -def genptr_decl(f, tag, regtype, regid, regno):
> -regN = f"{regtype}{regid}N"
> -if regtype == "R":
> -if regid in {"ss", "tt"}:
> -f.write(f"TCGv_i64 {regtype}{regid}V =
> tcg_temp_new_i64();\n")
> -f.write(f"const int {regN} = insn->regno[{regno}];\n")
> -elif regid in {"dd", "ee", "xx", "yy"}:
> -genptr_decl_pair_writable(f, tag, regtype, regid, regno)
> -elif regid in {"s", "t", "u", "v"}:
> -f.write(
> -f"TCGv {regtype}{regid}V = "
> f"hex_gpr[insn->regno[{regno}]];\n"
> -)
> -elif regid in {"d", "e", "x", "y"}:
> -genptr_decl_writable(f, tag, regtype, regid, regno)
> -else:
> -hex_common.bad_register(regtype, regid)
> -elif regtype == "P":
> -if regid in {"s", "t", "u", "v"}:
> -f.write(
> -f"TCGv {regtype}{regid}V = "
> f"hex_pred[insn->regno[{regno}]];\n"
> -)
> -elif regid in {"d", "e", "x"}:
> -genptr_d
QEMU snapshotting
Alexander, Bandan, Paolo, Stefan, Manuel, Hi, I'm Brian and I maintain the Hexagon arch for QEMU. Elia, a security researcher at Qualcomm is exploring ways to fuzz some hexagon OS kernel with QEMU and in particular leveraging snapshotting, inspired by your research and more. I'm not an expert on the details, but I'd like to make an introduction and see if there's an opportunity for us to learn from one another. Maybe we can have a call to kick things off? -Brian
RE: [PATCH 0/1] Enable -Wshadow=local
> -Original Message- > From: Stefan Hajnoczi > Sent: Thursday, October 26, 2023 7:52 PM > To: Markus Armbruster > Cc: qemu-devel@nongnu.org; pbonz...@redhat.com; > marcandre.lur...@redhat.com; berra...@redhat.com; th...@redhat.com; > phi...@linaro.org; Brian Cain ; i...@bsdimp.com; > stefa...@redhat.com > Subject: Re: [PATCH 0/1] Enable -Wshadow=local > > WARNING: This email originated from outside of Qualcomm. Please be wary of > any links or attachments, and do not enable macros. > > On Thu, 26 Oct 2023 at 14:32, Markus Armbruster > wrote: > > > > Requires Brian's pull request and two patches from Thomas to compile: > > > > [PULL 0/2] hex queue - GETPC() fixes, shadowing fixes > > [PATCH v2] block/snapshot: Fix compiler warning with -Wshadow=local > > [PATCH v2] migration/ram: Fix compilation with -Wshadow=local > > > > Stefan, the PR was posted a week ago; anything blocking it? > > It's not in a pull request, so I won't see it. I don't have tooling > that can spot individual patch series that need to go into > qemu.git/master, so I rely on being emailed about them. My mistake -- I thought I had emailed you. But I see now that I likely used the wrong email address. > > Would you like me to merge this patch series into qemu.git/master? > > Stefan > > > Warner, I believe not waiting for your cleanup of bsd-user is fine. > > Please holler if it isn't. > > > > Based-on: <20231019021733.2258592-1-bc...@quicinc.com> > > Based-on: <20231023175038.111607-1-th...@redhat.com> > > Based-on: <20231024092220.55305-1-th...@redhat.com> > > > > Markus Armbruster (1): > > meson: Enable -Wshadow=local > > > > meson.build | 1 + > > 1 file changed, 1 insertion(+) > > > > -- > > 2.41.0 > > > >
RE: [PATCH v2 07/16] target/hexagon: Declare QOM definitions in 'cpu-qom.h'
> -Original Message-
> From: Philippe Mathieu-Daudé
> Sent: Friday, October 13, 2023 9:01 AM
> To: qemu-devel@nongnu.org
> Cc: Eduardo Habkost ; Xiaojuan Yang
> ; Michael S. Tsirkin ; qemu-
> p...@nongnu.org; Aleksandar Rikalo ; David
> Hildenbrand ; qemu-s3...@nongnu.org; Edgar E. Iglesias
> ; Jiaxun Yang ; Song
> Gao ; Philippe Mathieu-Daudé ;
> Paolo Bonzini ; Stafford Horne ;
> Alistair Francis ; Yanan Wang
> ; Max Filippov ; Artyom
> Tarasenko ; Marcel Apfelbaum
> ; Cédric Le Goater ; Laurent
> Vivier ; Aurelien Jarno ; qemu-
> ri...@nongnu.org; Palmer Dabbelt ; Yoshinori Sato
> ; Bastian Koppelmann paderborn.de>; Bin Meng ; Daniel Henrique
> Barboza ; Mark Cave-Ayland ayl...@ilande.co.uk>; Weiwei Li ; Daniel Henrique
> Barboza ; Nicholas Piggin
> ; qemu-...@nongnu.org; Liu Zhiwei
> ; Marek Vasut ; Laurent
> Vivier ; Peter Maydell ; Brian
> Cain ; Thomas Huth ; Chris Wulff
> ; Sergio Lopez ; Richard Henderson
> ; Ilya Leoshkevich ;
> Michael Rolnik
> Subject: [PATCH v2 07/16] target/hexagon: Declare QOM definitions in 'cpu-
> qom.h'
>
> WARNING: This email originated from outside of Qualcomm. Please be wary of
> any links or attachments, and do not enable macros.
>
> "target/foo/cpu.h" contains the target specific declarations.
>
> A heterogeneous setup need to access target agnostic declarations
> (at least the QOM ones, to instantiate the objects).
>
> Our convention is to add such target agnostic QOM declarations in
> the "target/foo/cpu-qom.h" header.
>
> Extract QOM definitions from "cpu.h" to "cpu-qom.h".
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/hexagon/cpu-qom.h | 28
> target/hexagon/cpu.h | 15 +--
> 2 files changed, 29 insertions(+), 14 deletions(-)
> create mode 100644 target/hexagon/cpu-qom.h
>
> diff --git a/target/hexagon/cpu-qom.h b/target/hexagon/cpu-qom.h
> new file mode 100644
> index 00..f02df7ee6f
> --- /dev/null
> +++ b/target/hexagon/cpu-qom.h
> @@ -0,0 +1,28 @@
> +/*
> + * QEMU Hexagon CPU QOM header (target agnostic)
> + *
> + * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights
> Reserved.
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +
> +#ifndef QEMU_HEXAGON_CPU_QOM_H
> +#define QEMU_HEXAGON_CPU_QOM_H
> +
> +#include "hw/core/cpu.h"
> +#include "qom/object.h"
> +
> +#define TYPE_HEXAGON_CPU "hexagon-cpu"
> +
> +#define HEXAGON_CPU_TYPE_SUFFIX "-" TYPE_HEXAGON_CPU
> +#define HEXAGON_CPU_TYPE_NAME(name) (name
> HEXAGON_CPU_TYPE_SUFFIX)
> +
> +#define TYPE_HEXAGON_CPU_V67 HEXAGON_CPU_TYPE_NAME("v67")
> +#define TYPE_HEXAGON_CPU_V68 HEXAGON_CPU_TYPE_NAME("v68")
> +#define TYPE_HEXAGON_CPU_V69 HEXAGON_CPU_TYPE_NAME("v69")
> +#define TYPE_HEXAGON_CPU_V71 HEXAGON_CPU_TYPE_NAME("v71")
> +#define TYPE_HEXAGON_CPU_V73 HEXAGON_CPU_TYPE_NAME("v73")
> +
> +OBJECT_DECLARE_CPU_TYPE(HexagonCPU, HexagonCPUClass,
> HEXAGON_CPU)
> +
> +#endif
> diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
> index 035ac4fb6d..7d16083c6a 100644
> --- a/target/hexagon/cpu.h
> +++ b/target/hexagon/cpu.h
> @@ -20,11 +20,10 @@
>
> #include "fpu/softfloat-types.h"
>
> +#include "cpu-qom.h"
> #include "exec/cpu-defs.h"
> #include "hex_regs.h"
> #include "mmvec/mmvec.h"
> -#include "qom/object.h"
> -#include "hw/core/cpu.h"
> #include "hw/registerfields.h"
>
> #define NUM_PREGS 4
> @@ -36,18 +35,8 @@
> #define PRED_WRITES_MAX 5 /* 4 insns + endloop */
> #define VSTORES_MAX 2
>
> -#define TYPE_HEXAGON_CPU "hexagon-cpu"
> -
> -#define HEXAGON_CPU_TYPE_SUFFIX "-" TYPE_HEXAGON_CPU
> -#define HEXAGON_CPU_TYPE_NAME(name) (name
> HEXAGON_CPU_TYPE_SUFFIX)
> #define CPU_RESOLVING_TYPE TYPE_HEXAGON_CPU
>
> -#define TYPE_HEXAGON_CPU_V67 HEXAGON_CPU_TYPE_NAME("v67")
> -#define TYPE_HEXAGON_CPU_V68 HEXAGON_CPU_TYPE_NAME("v68")
> -#define TYPE_HEXAGON_CPU_V69 HEXAGON_CPU_TYPE_NAME("v69")
> -#define TYPE_HEXAGON_CPU_V71 HEXAGON_CPU_TYPE_NAME("v71")
> -#define TYPE_HEXAGON_CPU_V73 HEXAGON_CPU_TYPE_NAME("v73")
> -
> void hexagon_cpu_list(void);
> #define cpu_list hexagon_cpu_list
>
> @@ -127,8 +116,6 @@ typedef struct CPUArchState {
> VTCMStoreLog vtcm_log;
> } CPUHexagonState;
>
> -OBJECT_DECLARE_CPU_TYPE(HexagonCPU, HexagonCPUClass,
> HEXAGON_CPU)
> -
> typedef struct HexagonCPUClass {
> CPUClass parent_class;
>
> --
> 2.41.0
Reviewed-by: Brian Cain
[PULL 1/2] target/hexagon: move GETPC() calls to top level helpers
From: Matheus Tavares Bernardino
As docs/devel/loads-stores.rst states:
``GETPC()`` should be used with great care: calling
it in other functions that are *not* the top level
``HELPER(foo)`` will cause unexpected behavior. Instead, the
value of ``GETPC()`` should be read from the helper and passed
if needed to the functions that the helper calls.
Let's fix the GETPC() usage in Hexagon, making sure it's always called
from top level helpers and passed down to the places where it's
needed. There are a few snippets where that is not currently the case:
- probe_store(), which is only called from two helpers, so it's easy to
move GETPC() up.
- mem_load*() functions, which are also called directly from helpers,
but through the MEM_LOAD*() set of macros. Note that this are only
used when compiling with --disable-hexagon-idef-parser.
In this case, we also take this opportunity to simplify the code,
unifying the mem_load*() functions.
- HELPER(probe_hvx_stores), when called from another helper, ends up
using its own GETPC() expansion instead of the top level caller.
Signed-off-by: Matheus Tavares Bernardino
Reviewed-by: Taylor Simpson
Message-Id:
<2c74c3696946edba7cc5b2942cf296a5af532052.1689070412.git.quic_mathb...@quicinc.com>-ne
Reviewed-by: Brian Cain
Signed-off-by: Brian Cain
Message-Id: <20231008220945.983643-2-bc...@quicinc.com>
---
target/hexagon/macros.h| 19 +-
target/hexagon/op_helper.c | 75 +++---
target/hexagon/op_helper.h | 9 -
3 files changed, 38 insertions(+), 65 deletions(-)
diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
index b356d85792..9a51b5709b 100644
--- a/target/hexagon/macros.h
+++ b/target/hexagon/macros.h
@@ -173,15 +173,6 @@
#define MEM_STORE8(VA, DATA, SLOT) \
MEM_STORE8_FUNC(DATA)(tcg_env, VA, DATA, SLOT)
#else
-#define MEM_LOAD1s(VA) ((int8_t)mem_load1(env, pkt_has_store_s1, slot, VA))
-#define MEM_LOAD1u(VA) ((uint8_t)mem_load1(env, pkt_has_store_s1, slot, VA))
-#define MEM_LOAD2s(VA) ((int16_t)mem_load2(env, pkt_has_store_s1, slot, VA))
-#define MEM_LOAD2u(VA) ((uint16_t)mem_load2(env, pkt_has_store_s1, slot, VA))
-#define MEM_LOAD4s(VA) ((int32_t)mem_load4(env, pkt_has_store_s1, slot, VA))
-#define MEM_LOAD4u(VA) ((uint32_t)mem_load4(env, pkt_has_store_s1, slot, VA))
-#define MEM_LOAD8s(VA) ((int64_t)mem_load8(env, pkt_has_store_s1, slot, VA))
-#define MEM_LOAD8u(VA) ((uint64_t)mem_load8(env, pkt_has_store_s1, slot, VA))
-
#define MEM_STORE1(VA, DATA, SLOT) log_store32(env, VA, DATA, 1, SLOT)
#define MEM_STORE2(VA, DATA, SLOT) log_store32(env, VA, DATA, 2, SLOT)
#define MEM_STORE4(VA, DATA, SLOT) log_store32(env, VA, DATA, 4, SLOT)
@@ -530,8 +521,16 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val,
int shift)
#ifdef QEMU_GENERATE
#define fLOAD(NUM, SIZE, SIGN, EA, DST) MEM_LOAD##SIZE##SIGN(DST, EA)
#else
+#define MEM_LOAD1 cpu_ldub_data_ra
+#define MEM_LOAD2 cpu_lduw_data_ra
+#define MEM_LOAD4 cpu_ldl_data_ra
+#define MEM_LOAD8 cpu_ldq_data_ra
+
#define fLOAD(NUM, SIZE, SIGN, EA, DST) \
-DST = (size##SIZE##SIGN##_t)MEM_LOAD##SIZE##SIGN(EA)
+do { \
+check_noshuf(env, pkt_has_store_s1, slot, EA, SIZE, GETPC()); \
+DST = (size##SIZE##SIGN##_t)MEM_LOAD##SIZE(env, EA, GETPC()); \
+} while (0)
#endif
#define fMEMOP(NUM, SIZE, SIGN, EA, FNTYPE, VALUE)
diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
index 12967ac21e..8ca3976a65 100644
--- a/target/hexagon/op_helper.c
+++ b/target/hexagon/op_helper.c
@@ -95,9 +95,8 @@ void HELPER(debug_check_store_width)(CPUHexagonState *env,
int slot, int check)
}
}
-void HELPER(commit_store)(CPUHexagonState *env, int slot_num)
+static void commit_store(CPUHexagonState *env, int slot_num, uintptr_t ra)
{
-uintptr_t ra = GETPC();
uint8_t width = env->mem_log_stores[slot_num].width;
target_ulong va = env->mem_log_stores[slot_num].va;
@@ -119,6 +118,12 @@ void HELPER(commit_store)(CPUHexagonState *env, int
slot_num)
}
}
+void HELPER(commit_store)(CPUHexagonState *env, int slot_num)
+{
+uintptr_t ra = GETPC();
+commit_store(env, slot_num, ra);
+}
+
void HELPER(gather_store)(CPUHexagonState *env, uint32_t addr, int slot)
{
mem_gather_store(env, addr, slot);
@@ -467,13 +472,12 @@ int32_t HELPER(cabacdecbin_pred)(int64_t RssV, int64_t
RttV)
}
static void probe_store(CPUHexagonState *env, int slot, int mmu_idx,
-bool is_predicated)
+bool is_predicated, uintptr_t retaddr)
{
if (!is_predicated || !(env->slot_cancelled & (1 << slot))) {
size1u_t width = env->mem_log_stores[slot].width;
target_ulong va = env->mem_log_stores[slot].va;
-uintptr_t ra = GETPC();
-probe_write(env, va, width, mmu_idx, ra);
+probe_write(env, va, width, mmu_idx, retaddr);
}
}
@@ -494,12 +498,13 @@ void HELPER(probe_pkt_s
[PULL 0/2] hex queue - GETPC() fixes, shadowing fixes
The following changes since commit deaca3fd30d3a8829160f8d3705d65ad83176800: Merge tag 'pull-vfio-20231018' of https://github.com/legoater/qemu into staging (2023-10-18 06:21:15 -0400) are available in the Git repository at: https://github.com/quic/qemu tags/pull-hex-20231018 for you to fetch changes up to 20c34a9216f41977803659f5bd458618c291d56c: target/hexagon: fix some occurrences of -Wshadow=local (2023-10-18 16:56:17 -0700) hexagon: GETPC() fixes, shadowing fixes Brian Cain (1): target/hexagon: fix some occurrences of -Wshadow=local Matheus Tavares Bernardino (1): target/hexagon: move GETPC() calls to top level helpers target/hexagon/imported/alu.idef | 6 +-- target/hexagon/macros.h | 19 + target/hexagon/mmvec/macros.h| 2 +- target/hexagon/op_helper.c | 84 +++- target/hexagon/op_helper.h | 9 - target/hexagon/translate.c | 10 ++--- 6 files changed, 50 insertions(+), 80 deletions(-)
[PULL 2/2] target/hexagon: fix some occurrences of -Wshadow=local
Of the changes in this commit, the changes in `HELPER(commit_hvx_stores)()`
are less obvious. They are required because of some macro invocations like
SCATTER_OP_WRITE_TO_MEM().
e.g.:
In file included from ../target/hexagon/op_helper.c:31:
../target/hexagon/mmvec/macros.h:205:18: error: declaration of ‘i’ shadows
a previous local [-Werror=shadow=compatible-local]
205 | for (int i = 0; i < sizeof(MMVector); i += sizeof(TYPE)) { \
| ^
../target/hexagon/op_helper.c:157:17: note: in expansion of macro
‘SCATTER_OP_WRITE_TO_MEM’
157 | SCATTER_OP_WRITE_TO_MEM(uint16_t);
| ^~~
../target/hexagon/op_helper.c:135:9: note: shadowed declaration is here
135 | int i;
| ^
In file included from ../target/hexagon/op_helper.c:31:
../target/hexagon/mmvec/macros.h:204:19: error: declaration of ‘ra’ shadows
a previous local [-Werror=shadow=compatible-local]
204 | uintptr_t ra = GETPC(); \
| ^~
../target/hexagon/op_helper.c:160:17: note: in expansion of macro
‘SCATTER_OP_WRITE_TO_MEM’
160 | SCATTER_OP_WRITE_TO_MEM(uint32_t);
| ^~~
../target/hexagon/op_helper.c:134:15: note: shadowed declaration is here
134 | uintptr_t ra = GETPC();
| ^~
Reviewed-by: Matheus Tavares Bernardino
Signed-off-by: Brian Cain
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20231008220945.983643-3-bc...@quicinc.com>
---
target/hexagon/imported/alu.idef | 6 +++---
target/hexagon/mmvec/macros.h| 2 +-
target/hexagon/op_helper.c | 9 +++--
target/hexagon/translate.c | 10 +-
4 files changed, 12 insertions(+), 15 deletions(-)
diff --git a/target/hexagon/imported/alu.idef b/target/hexagon/imported/alu.idef
index 12d2aac5d4..b855676989 100644
--- a/target/hexagon/imported/alu.idef
+++ b/target/hexagon/imported/alu.idef
@@ -1142,9 +1142,9 @@
Q6INSN(A4_cround_rr,"Rd32=cround(Rs32,Rt32)",ATTRIBS(),"Convergent Round", {RdV
tmp128 = fSHIFTR128(tmp128, SHIFT);\
DST = fCAST16S_8S(tmp128);\
} else {\
-size16s_t rndbit_128 = fCAST8S_16S((1LL << (SHIFT - 1))); \
-size16s_t src_128 = fCAST8S_16S(SRC); \
-size16s_t tmp128 = fADD128(src_128, rndbit_128);\
+rndbit_128 = fCAST8S_16S((1LL << (SHIFT - 1))); \
+src_128 = fCAST8S_16S(SRC); \
+tmp128 = fADD128(src_128, rndbit_128);\
tmp128 = fSHIFTR128(tmp128, SHIFT);\
DST = fCAST16S_8S(tmp128);\
}
diff --git a/target/hexagon/mmvec/macros.h b/target/hexagon/mmvec/macros.h
index a655634fd1..1ceb9453ee 100644
--- a/target/hexagon/mmvec/macros.h
+++ b/target/hexagon/mmvec/macros.h
@@ -201,7 +201,7 @@
} while (0)
#define SCATTER_OP_WRITE_TO_MEM(TYPE) \
do { \
-uintptr_t ra = GETPC(); \
+ra = GETPC(); \
for (int i = 0; i < sizeof(MMVector); i += sizeof(TYPE)) { \
if (test_bit(i, env->vtcm_log.mask)) { \
TYPE dst = 0; \
diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
index 8ca3976a65..da10ac5847 100644
--- a/target/hexagon/op_helper.c
+++ b/target/hexagon/op_helper.c
@@ -132,10 +132,9 @@ void HELPER(gather_store)(CPUHexagonState *env, uint32_t
addr, int slot)
void HELPER(commit_hvx_stores)(CPUHexagonState *env)
{
uintptr_t ra = GETPC();
-int i;
/* Normal (possibly masked) vector store */
-for (i = 0; i < VSTORES_MAX; i++) {
+for (int i = 0; i < VSTORES_MAX; i++) {
if (env->vstore_pending[i]) {
env->vstore_pending[i] = 0;
target_ulong va = env->vstore[i].va;
@@ -162,7 +161,7 @@ void HELPER(commit_hvx_stores)(CPUHexagonState *env)
g_assert_not_reached();
}
} else {
-for (i = 0; i < sizeof(MMVector); i++) {
+for (int i = 0; i < sizeof(MMVector); i++) {
if (test_bit(i, env->vtcm_log.mask)) {
cpu_stb_data_ra(env, env->vtcm_log.va[i],
env->vtcm_log.data.ub[i], ra);
@@ -505,10 +504,8 @@ void HELPER(probe_pkt_scalar_store_s0)(CPUHexagonState
*env, int args)
static void probe_hvx_stores(CPUHexagonState *env, int mmu_idx,
uintptr_t retaddr)
{
-int i;
-
/* Normal (possibly masked) vector store */
-for (i = 0; i < VSTORES_MAX; i++) {
+for (int i = 0; i < VSTORES_MAX; i++) {
if (env->vstore_pending[i]) {
target_ulong va = env->vstore[i].va;
int size = env->vstore[i].size;
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index 663b7bbc3a..666c061180 100644
--- a
RE: [PATCH v2 3/3] target/hexagon: avoid shadowing globals
> -Original Message- > From: Philippe Mathieu-Daudé > Sent: Tuesday, October 10, 2023 12:23 AM > To: Brian Cain ; richard.hender...@linaro.org; > a...@rev.ng > Cc: arm...@redhat.com; peter.mayd...@linaro.org; Matheus Bernardino > (QUIC) ; stefa...@redhat.com; a...@rev.ng; > Marco Liebel (QUIC) ; ltaylorsimp...@gmail.com; > Thomas Huth ; Daniel P. Berrangé > ; qemu-devel@nongnu.org > Subject: Re: [PATCH v2 3/3] target/hexagon: avoid shadowing globals > > WARNING: This email originated from outside of Qualcomm. Please be wary of > any links or attachments, and do not enable macros. > > On 9/10/23 22:53, Brian Cain wrote: > >> On 9/10/23 08:09, Philippe Mathieu-Daudé wrote: > >>> On 6/10/23 00:22, Brian Cain wrote: > >>>> The typedef `vaddr` is shadowed by `vaddr` identifiers, so we rename the > >>>> identifiers to avoid shadowing the type name. > >>> > >>> This one surprises me, since we have other occurences: > >>> > >>> include/exec/memory.h:751:bool memory_get_xlat_addr(IOMMUTLBEntry > >>> *iotlb, void **vaddr, > >>> include/qemu/plugin.h:199:void qemu_plugin_vcpu_mem_cb(CPUState > >>> *cpu, uint64_t vaddr, > >>> target/arm/internals.h:643:G_NORETURN void > >>> arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, > >>> target/i386/tcg/helper-tcg.h:70:G_NORETURN void > >>> handle_unaligned_access(CPUX86State *env, vaddr vaddr, > >>> ... > >>> > >>> $ git grep -w vaddr, | wc -l > >>>207 > >>> > >>> What is the error/warning like? > >> > >> OK I could reproduce, I suppose you are building with Clang which > >> doesn't support shadow-local so you get global warnings too (as > >> mentioned in this patch subject...): > > > > No -- I generally build with gcc and only double-check the clang results to > make sure I don't see any new failures there. > > > > But I've not tested "-Wshadow" with clang yet. I found these by adding "- > Wshadow=global" to "-Wshadow=local". I thought it might be useful to > address these too while we're here. > > > >> In file included from ../../gdbstub/trace.h:1, > >>from ../../gdbstub/softmmu.c:30: > >> trace/trace-gdbstub.h: In function > '_nocheck__trace_gdbstub_hit_watchpoint': > >> trace/trace-gdbstub.h:903:106: error: declaration of 'vaddr' shadows a > >> global declaration [-Werror=shadow] > >> 903 | static inline void _nocheck__trace_gdbstub_hit_watchpoint(const > >> char * type, int cpu_gdb_index, uint64_t vaddr) > >> | > >> ~^ > >> In file included from include/sysemu/accel-ops.h:13, > >>from include/sysemu/cpus.h:4, > >>from ../../gdbstub/softmmu.c:21: > >> include/exec/cpu-common.h:21:18: note: shadowed declaration is here > >> 21 | typedef uint64_t vaddr; > >> | ^ > >> trace/trace-gdbstub.h: In function 'trace_gdbstub_hit_watchpoint': > >> trace/trace-gdbstub.h:923:96: error: declaration of 'vaddr' shadows a > >> global declaration [-Werror=shadow] > >> 923 | static inline void trace_gdbstub_hit_watchpoint(const char * > >> type, int cpu_gdb_index, uint64_t vaddr) > >> | > >> ~^ > >> include/exec/cpu-common.h:21:18: note: shadowed declaration is here > >> 21 | typedef uint64_t vaddr; > >> | ^ > > If we have to clean that for -Wshadow=global, I'm tempted to rename > the typedef as 'vaddr_t' and keep the 'vaddr' variable names. > > Richard, Anton, what do you think? Feels like I may have strolled into uncharted territory. I'll just drop the patch that is intended to address -Wshadow=global and resurrect it if/when we decide to take that on in general. > >> Clang users got confused by this, IIUC Markus and Thomas idea is > >> to only enable these warnings for GCC, enforcing them for Clang > >> users via CI (until Clang get this option supported). Personally > >> I'd rather enable the warning once for all, waiting for Clang > >> support (or clean/enable global shadowing for GCC too). > > > > Hopefully it's helpful or at least benign if we address the shadowed globals > under target/hexagon/ for now, even if "-Wshadow=global" is not enabled. > > > >> See this thread: > >> https://lore.kernel.org/qemu-devel/11abc551-188e-85c0-fe55- > >> b2b58d351...@redhat.com/ > >> > >> Regards, > >> > >> Phil.
RE: [PATCH v2 3/3] target/hexagon: avoid shadowing globals
> -Original Message- > From: Philippe Mathieu-Daudé > Sent: Monday, October 9, 2023 1:43 AM > To: Brian Cain ; qemu-devel@nongnu.org > Cc: arm...@redhat.com; richard.hender...@linaro.org; > peter.mayd...@linaro.org; Matheus Bernardino (QUIC) > ; stefa...@redhat.com; a...@rev.ng; > a...@rev.ng; Marco Liebel (QUIC) ; > ltaylorsimp...@gmail.com; Thomas Huth ; Daniel P. > Berrangé > Subject: Re: [PATCH v2 3/3] target/hexagon: avoid shadowing globals > > WARNING: This email originated from outside of Qualcomm. Please be wary of > any links or attachments, and do not enable macros. > > On 9/10/23 08:09, Philippe Mathieu-Daudé wrote: > > Hi Brian, > > > > On 6/10/23 00:22, Brian Cain wrote: > >> The typedef `vaddr` is shadowed by `vaddr` identifiers, so we rename the > >> identifiers to avoid shadowing the type name. > > > > This one surprises me, since we have other occurences: > > > > include/exec/memory.h:751:bool memory_get_xlat_addr(IOMMUTLBEntry > > *iotlb, void **vaddr, > > include/qemu/plugin.h:199:void qemu_plugin_vcpu_mem_cb(CPUState > > *cpu, uint64_t vaddr, > > target/arm/internals.h:643:G_NORETURN void > > arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, > > target/i386/tcg/helper-tcg.h:70:G_NORETURN void > > handle_unaligned_access(CPUX86State *env, vaddr vaddr, > > ... > > > > $ git grep -w vaddr, | wc -l > > 207 > > > > What is the error/warning like? > > OK I could reproduce, I suppose you are building with Clang which > doesn't support shadow-local so you get global warnings too (as > mentioned in this patch subject...): No -- I generally build with gcc and only double-check the clang results to make sure I don't see any new failures there. But I've not tested "-Wshadow" with clang yet. I found these by adding "-Wshadow=global" to "-Wshadow=local". I thought it might be useful to address these too while we're here. > In file included from ../../gdbstub/trace.h:1, > from ../../gdbstub/softmmu.c:30: > trace/trace-gdbstub.h: In function '_nocheck__trace_gdbstub_hit_watchpoint': > trace/trace-gdbstub.h:903:106: error: declaration of 'vaddr' shadows a > global declaration [-Werror=shadow] >903 | static inline void _nocheck__trace_gdbstub_hit_watchpoint(const > char * type, int cpu_gdb_index, uint64_t vaddr) >| > ~^ > In file included from include/sysemu/accel-ops.h:13, > from include/sysemu/cpus.h:4, > from ../../gdbstub/softmmu.c:21: > include/exec/cpu-common.h:21:18: note: shadowed declaration is here > 21 | typedef uint64_t vaddr; >| ^ > trace/trace-gdbstub.h: In function 'trace_gdbstub_hit_watchpoint': > trace/trace-gdbstub.h:923:96: error: declaration of 'vaddr' shadows a > global declaration [-Werror=shadow] >923 | static inline void trace_gdbstub_hit_watchpoint(const char * > type, int cpu_gdb_index, uint64_t vaddr) >| >~^ > include/exec/cpu-common.h:21:18: note: shadowed declaration is here > 21 | typedef uint64_t vaddr; >| ^ > > Clang users got confused by this, IIUC Markus and Thomas idea is > to only enable these warnings for GCC, enforcing them for Clang > users via CI (until Clang get this option supported). Personally > I'd rather enable the warning once for all, waiting for Clang > support (or clean/enable global shadowing for GCC too). Hopefully it's helpful or at least benign if we address the shadowed globals under target/hexagon/ for now, even if "-Wshadow=global" is not enabled. > See this thread: > https://lore.kernel.org/qemu-devel/11abc551-188e-85c0-fe55- > b2b58d351...@redhat.com/ > > Regards, > > Phil.
[PATCH v3 3/3] target/hexagon: avoid shadowing globals
The typedef `vaddr` is shadowed by `vaddr` identifiers, so we rename the
identifiers to avoid shadowing the type name.
The global `tcg_env` is shadowed by local `tcg_env` arguments, so we
rename the function arguments to avoid shadowing the global.
Signed-off-by: Brian Cain
---
target/hexagon/genptr.c | 56 -
target/hexagon/genptr.h | 18
target/hexagon/mmvec/system_ext_mmvec.c | 4 +-
target/hexagon/mmvec/system_ext_mmvec.h | 2 +-
target/hexagon/op_helper.c | 4 +-
5 files changed, 42 insertions(+), 42 deletions(-)
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index dbae6c570a..fa577e05dc 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -334,28 +334,28 @@ void gen_set_byte_i64(int N, TCGv_i64 result, TCGv src)
tcg_gen_deposit_i64(result, result, src64, N * 8, 8);
}
-static inline void gen_load_locked4u(TCGv dest, TCGv vaddr, int mem_index)
+static inline void gen_load_locked4u(TCGv dest, TCGv v_addr, int mem_index)
{
-tcg_gen_qemu_ld_tl(dest, vaddr, mem_index, MO_TEUL);
-tcg_gen_mov_tl(hex_llsc_addr, vaddr);
+tcg_gen_qemu_ld_tl(dest, v_addr, mem_index, MO_TEUL);
+tcg_gen_mov_tl(hex_llsc_addr, v_addr);
tcg_gen_mov_tl(hex_llsc_val, dest);
}
-static inline void gen_load_locked8u(TCGv_i64 dest, TCGv vaddr, int mem_index)
+static inline void gen_load_locked8u(TCGv_i64 dest, TCGv v_addr, int mem_index)
{
-tcg_gen_qemu_ld_i64(dest, vaddr, mem_index, MO_TEUQ);
-tcg_gen_mov_tl(hex_llsc_addr, vaddr);
+tcg_gen_qemu_ld_i64(dest, v_addr, mem_index, MO_TEUQ);
+tcg_gen_mov_tl(hex_llsc_addr, v_addr);
tcg_gen_mov_i64(hex_llsc_val_i64, dest);
}
static inline void gen_store_conditional4(DisasContext *ctx,
- TCGv pred, TCGv vaddr, TCGv src)
+ TCGv pred, TCGv v_addr, TCGv src)
{
TCGLabel *fail = gen_new_label();
TCGLabel *done = gen_new_label();
TCGv one, zero, tmp;
-tcg_gen_brcond_tl(TCG_COND_NE, vaddr, hex_llsc_addr, fail);
+tcg_gen_brcond_tl(TCG_COND_NE, v_addr, hex_llsc_addr, fail);
one = tcg_constant_tl(0xff);
zero = tcg_constant_tl(0);
@@ -374,13 +374,13 @@ static inline void gen_store_conditional4(DisasContext
*ctx,
}
static inline void gen_store_conditional8(DisasContext *ctx,
- TCGv pred, TCGv vaddr, TCGv_i64 src)
+ TCGv pred, TCGv v_addr, TCGv_i64 src)
{
TCGLabel *fail = gen_new_label();
TCGLabel *done = gen_new_label();
TCGv_i64 one, zero, tmp;
-tcg_gen_brcond_tl(TCG_COND_NE, vaddr, hex_llsc_addr, fail);
+tcg_gen_brcond_tl(TCG_COND_NE, v_addr, hex_llsc_addr, fail);
one = tcg_constant_i64(0xff);
zero = tcg_constant_i64(0);
@@ -407,57 +407,57 @@ static TCGv gen_slotval(DisasContext *ctx)
}
#endif
-void gen_store32(TCGv vaddr, TCGv src, int width, uint32_t slot)
+void gen_store32(TCGv v_addr, TCGv src, int width, uint32_t slot)
{
-tcg_gen_mov_tl(hex_store_addr[slot], vaddr);
+tcg_gen_mov_tl(hex_store_addr[slot], v_addr);
tcg_gen_movi_tl(hex_store_width[slot], width);
tcg_gen_mov_tl(hex_store_val32[slot], src);
}
-void gen_store1(TCGv_env tcg_env, TCGv vaddr, TCGv src, uint32_t slot)
+void gen_store1(TCGv_env tcg_env_, TCGv v_addr, TCGv src, uint32_t slot)
{
-gen_store32(vaddr, src, 1, slot);
+gen_store32(v_addr, src, 1, slot);
}
-void gen_store1i(TCGv_env tcg_env, TCGv vaddr, int32_t src, uint32_t slot)
+void gen_store1i(TCGv_env tcg_env_, TCGv v_addr, int32_t src, uint32_t slot)
{
TCGv tmp = tcg_constant_tl(src);
-gen_store1(tcg_env, vaddr, tmp, slot);
+gen_store1(tcg_env_, v_addr, tmp, slot);
}
-void gen_store2(TCGv_env tcg_env, TCGv vaddr, TCGv src, uint32_t slot)
+void gen_store2(TCGv_env tcg_env_, TCGv v_addr, TCGv src, uint32_t slot)
{
-gen_store32(vaddr, src, 2, slot);
+gen_store32(v_addr, src, 2, slot);
}
-void gen_store2i(TCGv_env tcg_env, TCGv vaddr, int32_t src, uint32_t slot)
+void gen_store2i(TCGv_env tcg_env_, TCGv v_addr, int32_t src, uint32_t slot)
{
TCGv tmp = tcg_constant_tl(src);
-gen_store2(tcg_env, vaddr, tmp, slot);
+gen_store2(tcg_env_, v_addr, tmp, slot);
}
-void gen_store4(TCGv_env tcg_env, TCGv vaddr, TCGv src, uint32_t slot)
+void gen_store4(TCGv_env tcg_env_, TCGv v_addr, TCGv src, uint32_t slot)
{
-gen_store32(vaddr, src, 4, slot);
+gen_store32(v_addr, src, 4, slot);
}
-void gen_store4i(TCGv_env tcg_env, TCGv vaddr, int32_t src, uint32_t slot)
+void gen_store4i(TCGv_env tcg_env_, TCGv v_addr, int32_t src, uint32_t slot)
{
TCGv tmp = tcg_constant_tl(src);
-gen_store4(tcg_env, vaddr, tmp, slot);
+gen_store4(tcg_env_, v_addr, tmp, slot);
}
-void gen_store8(TCGv_env tcg_env, TCGv vaddr, TCGv_i64 src, uint32_t slot)
+void gen_store8(TCGv_env tcg_env_, TCGv
[PATCH v3 2/3] target/hexagon: fix some occurrences of -Wshadow=local
Of the changes in this commit, the changes in `HELPER(commit_hvx_stores)()`
are less obvious. They are required because of some macro invocations like
SCATTER_OP_WRITE_TO_MEM().
e.g.:
In file included from ../target/hexagon/op_helper.c:31:
../target/hexagon/mmvec/macros.h:205:18: error: declaration of ‘i’ shadows
a previous local [-Werror=shadow=compatible-local]
205 | for (int i = 0; i < sizeof(MMVector); i += sizeof(TYPE)) { \
| ^
../target/hexagon/op_helper.c:157:17: note: in expansion of macro
‘SCATTER_OP_WRITE_TO_MEM’
157 | SCATTER_OP_WRITE_TO_MEM(uint16_t);
| ^~~
../target/hexagon/op_helper.c:135:9: note: shadowed declaration is here
135 | int i;
| ^
In file included from ../target/hexagon/op_helper.c:31:
../target/hexagon/mmvec/macros.h:204:19: error: declaration of ‘ra’ shadows
a previous local [-Werror=shadow=compatible-local]
204 | uintptr_t ra = GETPC(); \
| ^~
../target/hexagon/op_helper.c:160:17: note: in expansion of macro
‘SCATTER_OP_WRITE_TO_MEM’
160 | SCATTER_OP_WRITE_TO_MEM(uint32_t);
| ^~~
../target/hexagon/op_helper.c:134:15: note: shadowed declaration is here
134 | uintptr_t ra = GETPC();
| ^~
Reviewed-by: Matheus Tavares Bernardino
Signed-off-by: Brian Cain
---
target/hexagon/imported/alu.idef | 6 +++---
target/hexagon/mmvec/macros.h| 2 +-
target/hexagon/op_helper.c | 9 +++--
target/hexagon/translate.c | 10 +-
4 files changed, 12 insertions(+), 15 deletions(-)
diff --git a/target/hexagon/imported/alu.idef b/target/hexagon/imported/alu.idef
index 12d2aac5d4..b855676989 100644
--- a/target/hexagon/imported/alu.idef
+++ b/target/hexagon/imported/alu.idef
@@ -1142,9 +1142,9 @@
Q6INSN(A4_cround_rr,"Rd32=cround(Rs32,Rt32)",ATTRIBS(),"Convergent Round", {RdV
tmp128 = fSHIFTR128(tmp128, SHIFT);\
DST = fCAST16S_8S(tmp128);\
} else {\
-size16s_t rndbit_128 = fCAST8S_16S((1LL << (SHIFT - 1))); \
-size16s_t src_128 = fCAST8S_16S(SRC); \
-size16s_t tmp128 = fADD128(src_128, rndbit_128);\
+rndbit_128 = fCAST8S_16S((1LL << (SHIFT - 1))); \
+src_128 = fCAST8S_16S(SRC); \
+tmp128 = fADD128(src_128, rndbit_128);\
tmp128 = fSHIFTR128(tmp128, SHIFT);\
DST = fCAST16S_8S(tmp128);\
}
diff --git a/target/hexagon/mmvec/macros.h b/target/hexagon/mmvec/macros.h
index a655634fd1..1ceb9453ee 100644
--- a/target/hexagon/mmvec/macros.h
+++ b/target/hexagon/mmvec/macros.h
@@ -201,7 +201,7 @@
} while (0)
#define SCATTER_OP_WRITE_TO_MEM(TYPE) \
do { \
-uintptr_t ra = GETPC(); \
+ra = GETPC(); \
for (int i = 0; i < sizeof(MMVector); i += sizeof(TYPE)) { \
if (test_bit(i, env->vtcm_log.mask)) { \
TYPE dst = 0; \
diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
index 8ca3976a65..da10ac5847 100644
--- a/target/hexagon/op_helper.c
+++ b/target/hexagon/op_helper.c
@@ -132,10 +132,9 @@ void HELPER(gather_store)(CPUHexagonState *env, uint32_t
addr, int slot)
void HELPER(commit_hvx_stores)(CPUHexagonState *env)
{
uintptr_t ra = GETPC();
-int i;
/* Normal (possibly masked) vector store */
-for (i = 0; i < VSTORES_MAX; i++) {
+for (int i = 0; i < VSTORES_MAX; i++) {
if (env->vstore_pending[i]) {
env->vstore_pending[i] = 0;
target_ulong va = env->vstore[i].va;
@@ -162,7 +161,7 @@ void HELPER(commit_hvx_stores)(CPUHexagonState *env)
g_assert_not_reached();
}
} else {
-for (i = 0; i < sizeof(MMVector); i++) {
+for (int i = 0; i < sizeof(MMVector); i++) {
if (test_bit(i, env->vtcm_log.mask)) {
cpu_stb_data_ra(env, env->vtcm_log.va[i],
env->vtcm_log.data.ub[i], ra);
@@ -505,10 +504,8 @@ void HELPER(probe_pkt_scalar_store_s0)(CPUHexagonState
*env, int args)
static void probe_hvx_stores(CPUHexagonState *env, int mmu_idx,
uintptr_t retaddr)
{
-int i;
-
/* Normal (possibly masked) vector store */
-for (i = 0; i < VSTORES_MAX; i++) {
+for (int i = 0; i < VSTORES_MAX; i++) {
if (env->vstore_pending[i]) {
target_ulong va = env->vstore[i].va;
int size = env->vstore[i].size;
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index 663b7bbc3a..666c061180 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -553,7 +553,7 @@ static void gen_start_
[PATCH v3 0/3] hexagon: GETPC() fixes, shadowing fixes
Changes since v2: - rebased, suggested by Markus - s/cpu_env/tcg_env/ - For local shadows: s/tcg_env/tcg_env_/ Brian Cain (2): target/hexagon: fix some occurrences of -Wshadow=local target/hexagon: avoid shadowing globals Matheus Tavares Bernardino (1): target/hexagon: move GETPC() calls to top level helpers target/hexagon/genptr.c | 56 - target/hexagon/genptr.h | 18 +++--- target/hexagon/imported/alu.idef| 6 +- target/hexagon/macros.h | 19 +++--- target/hexagon/mmvec/macros.h | 2 +- target/hexagon/mmvec/system_ext_mmvec.c | 4 +- target/hexagon/mmvec/system_ext_mmvec.h | 2 +- target/hexagon/op_helper.c | 84 ++--- target/hexagon/op_helper.h | 9 --- target/hexagon/translate.c | 10 +-- 10 files changed, 90 insertions(+), 120 deletions(-) -- 2.25.1
[PATCH v3 1/3] target/hexagon: move GETPC() calls to top level helpers
From: Matheus Tavares Bernardino
As docs/devel/loads-stores.rst states:
``GETPC()`` should be used with great care: calling
it in other functions that are *not* the top level
``HELPER(foo)`` will cause unexpected behavior. Instead, the
value of ``GETPC()`` should be read from the helper and passed
if needed to the functions that the helper calls.
Let's fix the GETPC() usage in Hexagon, making sure it's always called
from top level helpers and passed down to the places where it's
needed. There are a few snippets where that is not currently the case:
- probe_store(), which is only called from two helpers, so it's easy to
move GETPC() up.
- mem_load*() functions, which are also called directly from helpers,
but through the MEM_LOAD*() set of macros. Note that this are only
used when compiling with --disable-hexagon-idef-parser.
In this case, we also take this opportunity to simplify the code,
unifying the mem_load*() functions.
- HELPER(probe_hvx_stores), when called from another helper, ends up
using its own GETPC() expansion instead of the top level caller.
Signed-off-by: Matheus Tavares Bernardino
Reviewed-by: Taylor Simpson
Message-Id:
<2c74c3696946edba7cc5b2942cf296a5af532052.1689070412.git.quic_mathb...@quicinc.com>-ne
Reviewed-by: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/macros.h| 19 +-
target/hexagon/op_helper.c | 75 +++---
target/hexagon/op_helper.h | 9 -
3 files changed, 38 insertions(+), 65 deletions(-)
diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
index b356d85792..9a51b5709b 100644
--- a/target/hexagon/macros.h
+++ b/target/hexagon/macros.h
@@ -173,15 +173,6 @@
#define MEM_STORE8(VA, DATA, SLOT) \
MEM_STORE8_FUNC(DATA)(tcg_env, VA, DATA, SLOT)
#else
-#define MEM_LOAD1s(VA) ((int8_t)mem_load1(env, pkt_has_store_s1, slot, VA))
-#define MEM_LOAD1u(VA) ((uint8_t)mem_load1(env, pkt_has_store_s1, slot, VA))
-#define MEM_LOAD2s(VA) ((int16_t)mem_load2(env, pkt_has_store_s1, slot, VA))
-#define MEM_LOAD2u(VA) ((uint16_t)mem_load2(env, pkt_has_store_s1, slot, VA))
-#define MEM_LOAD4s(VA) ((int32_t)mem_load4(env, pkt_has_store_s1, slot, VA))
-#define MEM_LOAD4u(VA) ((uint32_t)mem_load4(env, pkt_has_store_s1, slot, VA))
-#define MEM_LOAD8s(VA) ((int64_t)mem_load8(env, pkt_has_store_s1, slot, VA))
-#define MEM_LOAD8u(VA) ((uint64_t)mem_load8(env, pkt_has_store_s1, slot, VA))
-
#define MEM_STORE1(VA, DATA, SLOT) log_store32(env, VA, DATA, 1, SLOT)
#define MEM_STORE2(VA, DATA, SLOT) log_store32(env, VA, DATA, 2, SLOT)
#define MEM_STORE4(VA, DATA, SLOT) log_store32(env, VA, DATA, 4, SLOT)
@@ -530,8 +521,16 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val,
int shift)
#ifdef QEMU_GENERATE
#define fLOAD(NUM, SIZE, SIGN, EA, DST) MEM_LOAD##SIZE##SIGN(DST, EA)
#else
+#define MEM_LOAD1 cpu_ldub_data_ra
+#define MEM_LOAD2 cpu_lduw_data_ra
+#define MEM_LOAD4 cpu_ldl_data_ra
+#define MEM_LOAD8 cpu_ldq_data_ra
+
#define fLOAD(NUM, SIZE, SIGN, EA, DST) \
-DST = (size##SIZE##SIGN##_t)MEM_LOAD##SIZE##SIGN(EA)
+do { \
+check_noshuf(env, pkt_has_store_s1, slot, EA, SIZE, GETPC()); \
+DST = (size##SIZE##SIGN##_t)MEM_LOAD##SIZE(env, EA, GETPC()); \
+} while (0)
#endif
#define fMEMOP(NUM, SIZE, SIGN, EA, FNTYPE, VALUE)
diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
index 12967ac21e..8ca3976a65 100644
--- a/target/hexagon/op_helper.c
+++ b/target/hexagon/op_helper.c
@@ -95,9 +95,8 @@ void HELPER(debug_check_store_width)(CPUHexagonState *env,
int slot, int check)
}
}
-void HELPER(commit_store)(CPUHexagonState *env, int slot_num)
+static void commit_store(CPUHexagonState *env, int slot_num, uintptr_t ra)
{
-uintptr_t ra = GETPC();
uint8_t width = env->mem_log_stores[slot_num].width;
target_ulong va = env->mem_log_stores[slot_num].va;
@@ -119,6 +118,12 @@ void HELPER(commit_store)(CPUHexagonState *env, int
slot_num)
}
}
+void HELPER(commit_store)(CPUHexagonState *env, int slot_num)
+{
+uintptr_t ra = GETPC();
+commit_store(env, slot_num, ra);
+}
+
void HELPER(gather_store)(CPUHexagonState *env, uint32_t addr, int slot)
{
mem_gather_store(env, addr, slot);
@@ -467,13 +472,12 @@ int32_t HELPER(cabacdecbin_pred)(int64_t RssV, int64_t
RttV)
}
static void probe_store(CPUHexagonState *env, int slot, int mmu_idx,
-bool is_predicated)
+bool is_predicated, uintptr_t retaddr)
{
if (!is_predicated || !(env->slot_cancelled & (1 << slot))) {
size1u_t width = env->mem_log_stores[slot].width;
target_ulong va = env->mem_log_stores[slot].va;
-uintptr_t ra = GETPC();
-probe_write(env, va, width, mmu_idx, ra);
+probe_write(env, va, width, mmu_idx, retaddr);
}
}
@@ -494,12 +498,13 @@ void HELPER(probe_pkt_scalar_store_s0)(CPUHexagonState
*env, int args)
RE: [PATCH v2 3/3] target/hexagon: avoid shadowing globals
> -Original Message- > From: ltaylorsimp...@gmail.com > Sent: Friday, October 6, 2023 11:01 AM > To: Brian Cain ; qemu-devel@nongnu.org > Cc: arm...@redhat.com; richard.hender...@linaro.org; phi...@linaro.org; > peter.mayd...@linaro.org; Matheus Bernardino (QUIC) > ; stefa...@redhat.com; a...@rev.ng; > a...@rev.ng; Marco Liebel (QUIC) > Subject: RE: [PATCH v2 3/3] target/hexagon: avoid shadowing globals > > WARNING: This email originated from outside of Qualcomm. Please be wary of > any links or attachments, and do not enable macros. > > > -----Original Message- > > From: Brian Cain > > Sent: Thursday, October 5, 2023 4:22 PM > > To: qemu-devel@nongnu.org > > Cc: bc...@quicinc.com; arm...@redhat.com; richard.hender...@linaro.org; > > phi...@linaro.org; peter.mayd...@linaro.org; quic_mathb...@quicinc.com; > > stefa...@redhat.com; a...@rev.ng; a...@rev.ng; > > quic_mlie...@quicinc.com; ltaylorsimp...@gmail.com > > Subject: [PATCH v2 3/3] target/hexagon: avoid shadowing globals > > > > The typedef `vaddr` is shadowed by `vaddr` identifiers, so we rename the > > identifiers to avoid shadowing the type name. > > > > The global `cpu_env` is shadowed by local `cpu_env` arguments, so we > > rename the function arguments to avoid shadowing the global. > > > > Signed-off-by: Brian Cain > > --- > > target/hexagon/genptr.c | 56 - > > target/hexagon/genptr.h | 18 > > target/hexagon/mmvec/system_ext_mmvec.c | 4 +- > > target/hexagon/mmvec/system_ext_mmvec.h | 2 +- > > target/hexagon/op_helper.c | 4 +- > > 5 files changed, 42 insertions(+), 42 deletions(-) > > > > diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index > > 217bc7bb5a..11377ac92b 100644 > > --- a/target/hexagon/genptr.c > > +++ b/target/hexagon/genptr.c > > @@ -334,28 +334,28 @@ void gen_set_byte_i64(int N, TCGv_i64 result, > TCGv > > src) > > tcg_gen_deposit_i64(result, result, src64, N * 8, 8); } > > > > -static inline void gen_load_locked4u(TCGv dest, TCGv vaddr, int > > mem_index) > > +static inline void gen_load_locked4u(TCGv dest, TCGv v_addr, int > > +mem_index) > > I'd recommend moving both the type and the arg name to the new line, also > indent the new line. > static inline void gen_load_locked4u(TCGv dest, TCGv v_addr, > int > mem_index) > > > > > > -static inline void gen_load_locked8u(TCGv_i64 dest, TCGv vaddr, int > > mem_index) > > +static inline void gen_load_locked8u(TCGv_i64 dest, TCGv v_addr, int > > +mem_index) > > Ditto > > > static inline void gen_store_conditional4(DisasContext *ctx, > > - TCGv pred, TCGv vaddr, TCGv src) > > + TCGv pred, TCGv v_addr, TCGv > > + src) > > Ditto > > > zero = tcg_constant_tl(0); > > @@ -374,13 +374,13 @@ static inline void > > gen_store_conditional4(DisasContext *ctx, } > > > > static inline void gen_store_conditional8(DisasContext *ctx, > > - TCGv pred, TCGv vaddr, TCGv_i64 > > src) > > + TCGv pred, TCGv v_addr, > > + TCGv_i64 src) > > Indent > > > -void mem_gather_store(CPUHexagonState *env, target_ulong vaddr, int > > slot) > > +void mem_gather_store(CPUHexagonState *env, target_ulong v_addr, int > > +slot) > > Ditto > > > -void mem_gather_store(CPUHexagonState *env, target_ulong vaddr, int > > slot); > > +void mem_gather_store(CPUHexagonState *env, target_ulong v_addr, int > > +slot); > > Ditto I could be mistaken but AFAICT none of these lines are wrapped in the way they're quoted above in my patch (nor the baseline). I don't think any of these lines exceed 80 columns, so they shouldn't need wrapping, either. I double checked how it's displayed at the archive https://lists.gnu.org/archive/html/qemu-devel/2023-10/msg01667.html to make sure that it wasn't a misconfiguration of my mailer. For another perspective - refer to the commit used to create this patch: https://github.com/quic/qemu/commit/7f20565d403d16337ab6d69ee663121a3eef71e6 Is your review comment that "these lines should be wrapped and when you do, make sure you do it like this"? Or "if you are going to wrap them, wrap them like this"? Or something else? > Otherwise, > Reviewed-by: Taylor Simpson >
[PATCH v2 2/3] target/hexagon: fix some occurrences of -Wshadow=local
Of the changes in this commit, the changes in `HELPER(commit_hvx_stores)()`
are less obvious. They are required because of some macro invocations like
SCATTER_OP_WRITE_TO_MEM().
e.g.:
In file included from ../target/hexagon/op_helper.c:31:
../target/hexagon/mmvec/macros.h:205:18: error: declaration of ‘i’ shadows
a previous local [-Werror=shadow=compatible-local]
205 | for (int i = 0; i < sizeof(MMVector); i += sizeof(TYPE)) { \
| ^
../target/hexagon/op_helper.c:157:17: note: in expansion of macro
‘SCATTER_OP_WRITE_TO_MEM’
157 | SCATTER_OP_WRITE_TO_MEM(uint16_t);
| ^~~
../target/hexagon/op_helper.c:135:9: note: shadowed declaration is here
135 | int i;
| ^
In file included from ../target/hexagon/op_helper.c:31:
../target/hexagon/mmvec/macros.h:204:19: error: declaration of ‘ra’ shadows
a previous local [-Werror=shadow=compatible-local]
204 | uintptr_t ra = GETPC(); \
| ^~
../target/hexagon/op_helper.c:160:17: note: in expansion of macro
‘SCATTER_OP_WRITE_TO_MEM’
160 | SCATTER_OP_WRITE_TO_MEM(uint32_t);
| ^~~
../target/hexagon/op_helper.c:134:15: note: shadowed declaration is here
134 | uintptr_t ra = GETPC();
| ^~
Reviewed-by: Matheus Tavares Bernardino
Signed-off-by: Brian Cain
---
target/hexagon/imported/alu.idef | 6 +++---
target/hexagon/mmvec/macros.h| 6 +++---
target/hexagon/op_helper.c | 9 +++--
target/hexagon/translate.c | 9 -
4 files changed, 13 insertions(+), 17 deletions(-)
diff --git a/target/hexagon/imported/alu.idef b/target/hexagon/imported/alu.idef
index 12d2aac5d4..b855676989 100644
--- a/target/hexagon/imported/alu.idef
+++ b/target/hexagon/imported/alu.idef
@@ -1142,9 +1142,9 @@
Q6INSN(A4_cround_rr,"Rd32=cround(Rs32,Rt32)",ATTRIBS(),"Convergent Round", {RdV
tmp128 = fSHIFTR128(tmp128, SHIFT);\
DST = fCAST16S_8S(tmp128);\
} else {\
-size16s_t rndbit_128 = fCAST8S_16S((1LL << (SHIFT - 1))); \
-size16s_t src_128 = fCAST8S_16S(SRC); \
-size16s_t tmp128 = fADD128(src_128, rndbit_128);\
+rndbit_128 = fCAST8S_16S((1LL << (SHIFT - 1))); \
+src_128 = fCAST8S_16S(SRC); \
+tmp128 = fADD128(src_128, rndbit_128);\
tmp128 = fSHIFTR128(tmp128, SHIFT);\
DST = fCAST16S_8S(tmp128);\
}
diff --git a/target/hexagon/mmvec/macros.h b/target/hexagon/mmvec/macros.h
index a655634fd1..728a63d35f 100644
--- a/target/hexagon/mmvec/macros.h
+++ b/target/hexagon/mmvec/macros.h
@@ -201,14 +201,14 @@
} while (0)
#define SCATTER_OP_WRITE_TO_MEM(TYPE) \
do { \
-uintptr_t ra = GETPC(); \
+uintptr_t ra_ = GETPC(); \
for (int i = 0; i < sizeof(MMVector); i += sizeof(TYPE)) { \
if (test_bit(i, env->vtcm_log.mask)) { \
TYPE dst = 0; \
TYPE inc = 0; \
for (int j = 0; j < sizeof(TYPE); j++) { \
uint8_t val; \
-val = cpu_ldub_data_ra(env, env->vtcm_log.va[i + j], ra); \
+val = cpu_ldub_data_ra(env, env->vtcm_log.va[i + j], ra_);
\
dst |= val << (8 * j); \
inc |= env->vtcm_log.data.ub[j + i] << (8 * j); \
clear_bit(j + i, env->vtcm_log.mask); \
@@ -217,7 +217,7 @@
dst += inc; \
for (int j = 0; j < sizeof(TYPE); j++) { \
cpu_stb_data_ra(env, env->vtcm_log.va[i + j], \
-(dst >> (8 * j)) & 0xFF, ra); \
+(dst >> (8 * j)) & 0xFF, ra_); \
} \
} \
} \
diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
index 8ca3976a65..da10ac5847 100644
--- a/target/hexagon/op_helper.c
+++ b/target/hexagon/op_helper.c
@@ -132,10 +132,9 @@ void HELPER(gather_store)(CPUHexagonState *env, uint32_t
addr, int slot)
void HELPER(commit_hvx_stores)(CPUHexagonState *env)
{
uintptr_t ra = GETPC();
-int i;
/* Normal (possibly masked) vector store */
-for (i = 0; i < VSTORES_MAX; i++) {
+for (int i = 0; i < VSTORES_MAX; i++) {
if (env->vstore_pending[i]) {
env->vstore_pending[i] = 0;
target_ulong va = env->vstore[i].va;
@@ -162,7 +161,7 @@ void HELPER(commit_hvx_stores)(CPUHexagonState *env)
g_assert_not_reached();
}
} else {
-for (i = 0; i < sizeof(MMVector); i++) {
+for (int i = 0; i < sizeof(MMVector); i++) {
[PATCH v2 1/3] target/hexagon: move GETPC() calls to top level helpers
From: Matheus Tavares Bernardino
As docs/devel/loads-stores.rst states:
``GETPC()`` should be used with great care: calling
it in other functions that are *not* the top level
``HELPER(foo)`` will cause unexpected behavior. Instead, the
value of ``GETPC()`` should be read from the helper and passed
if needed to the functions that the helper calls.
Let's fix the GETPC() usage in Hexagon, making sure it's always called
from top level helpers and passed down to the places where it's
needed. There are a few snippets where that is not currently the case:
- probe_store(), which is only called from two helpers, so it's easy to
move GETPC() up.
- mem_load*() functions, which are also called directly from helpers,
but through the MEM_LOAD*() set of macros. Note that this are only
used when compiling with --disable-hexagon-idef-parser.
In this case, we also take this opportunity to simplify the code,
unifying the mem_load*() functions.
- HELPER(probe_hvx_stores), when called from another helper, ends up
using its own GETPC() expansion instead of the top level caller.
Signed-off-by: Matheus Tavares Bernardino
Reviewed-by: Taylor Simpson
Message-Id:
<2c74c3696946edba7cc5b2942cf296a5af532052.1689070412.git.quic_mathb...@quicinc.com>-ne
Reviewed-by: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/macros.h| 19 +-
target/hexagon/op_helper.c | 75 +++---
target/hexagon/op_helper.h | 9 -
3 files changed, 38 insertions(+), 65 deletions(-)
diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
index 5451b061ee..dafa0df6ed 100644
--- a/target/hexagon/macros.h
+++ b/target/hexagon/macros.h
@@ -173,15 +173,6 @@
#define MEM_STORE8(VA, DATA, SLOT) \
MEM_STORE8_FUNC(DATA)(cpu_env, VA, DATA, SLOT)
#else
-#define MEM_LOAD1s(VA) ((int8_t)mem_load1(env, pkt_has_store_s1, slot, VA))
-#define MEM_LOAD1u(VA) ((uint8_t)mem_load1(env, pkt_has_store_s1, slot, VA))
-#define MEM_LOAD2s(VA) ((int16_t)mem_load2(env, pkt_has_store_s1, slot, VA))
-#define MEM_LOAD2u(VA) ((uint16_t)mem_load2(env, pkt_has_store_s1, slot, VA))
-#define MEM_LOAD4s(VA) ((int32_t)mem_load4(env, pkt_has_store_s1, slot, VA))
-#define MEM_LOAD4u(VA) ((uint32_t)mem_load4(env, pkt_has_store_s1, slot, VA))
-#define MEM_LOAD8s(VA) ((int64_t)mem_load8(env, pkt_has_store_s1, slot, VA))
-#define MEM_LOAD8u(VA) ((uint64_t)mem_load8(env, pkt_has_store_s1, slot, VA))
-
#define MEM_STORE1(VA, DATA, SLOT) log_store32(env, VA, DATA, 1, SLOT)
#define MEM_STORE2(VA, DATA, SLOT) log_store32(env, VA, DATA, 2, SLOT)
#define MEM_STORE4(VA, DATA, SLOT) log_store32(env, VA, DATA, 4, SLOT)
@@ -530,8 +521,16 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val,
int shift)
#ifdef QEMU_GENERATE
#define fLOAD(NUM, SIZE, SIGN, EA, DST) MEM_LOAD##SIZE##SIGN(DST, EA)
#else
+#define MEM_LOAD1 cpu_ldub_data_ra
+#define MEM_LOAD2 cpu_lduw_data_ra
+#define MEM_LOAD4 cpu_ldl_data_ra
+#define MEM_LOAD8 cpu_ldq_data_ra
+
#define fLOAD(NUM, SIZE, SIGN, EA, DST) \
-DST = (size##SIZE##SIGN##_t)MEM_LOAD##SIZE##SIGN(EA)
+do { \
+check_noshuf(env, pkt_has_store_s1, slot, EA, SIZE, GETPC()); \
+DST = (size##SIZE##SIGN##_t)MEM_LOAD##SIZE(env, EA, GETPC()); \
+} while (0)
#endif
#define fMEMOP(NUM, SIZE, SIGN, EA, FNTYPE, VALUE)
diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
index 12967ac21e..8ca3976a65 100644
--- a/target/hexagon/op_helper.c
+++ b/target/hexagon/op_helper.c
@@ -95,9 +95,8 @@ void HELPER(debug_check_store_width)(CPUHexagonState *env,
int slot, int check)
}
}
-void HELPER(commit_store)(CPUHexagonState *env, int slot_num)
+static void commit_store(CPUHexagonState *env, int slot_num, uintptr_t ra)
{
-uintptr_t ra = GETPC();
uint8_t width = env->mem_log_stores[slot_num].width;
target_ulong va = env->mem_log_stores[slot_num].va;
@@ -119,6 +118,12 @@ void HELPER(commit_store)(CPUHexagonState *env, int
slot_num)
}
}
+void HELPER(commit_store)(CPUHexagonState *env, int slot_num)
+{
+uintptr_t ra = GETPC();
+commit_store(env, slot_num, ra);
+}
+
void HELPER(gather_store)(CPUHexagonState *env, uint32_t addr, int slot)
{
mem_gather_store(env, addr, slot);
@@ -467,13 +472,12 @@ int32_t HELPER(cabacdecbin_pred)(int64_t RssV, int64_t
RttV)
}
static void probe_store(CPUHexagonState *env, int slot, int mmu_idx,
-bool is_predicated)
+bool is_predicated, uintptr_t retaddr)
{
if (!is_predicated || !(env->slot_cancelled & (1 << slot))) {
size1u_t width = env->mem_log_stores[slot].width;
target_ulong va = env->mem_log_stores[slot].va;
-uintptr_t ra = GETPC();
-probe_write(env, va, width, mmu_idx, ra);
+probe_write(env, va, width, mmu_idx, retaddr);
}
}
@@ -494,12 +498,13 @@ void HELPER(probe_pkt_scalar_store_s0)(CPUHexagonState
*env, int args)
[PATCH v2 3/3] target/hexagon: avoid shadowing globals
The typedef `vaddr` is shadowed by `vaddr` identifiers, so we rename the
identifiers to avoid shadowing the type name.
The global `cpu_env` is shadowed by local `cpu_env` arguments, so we
rename the function arguments to avoid shadowing the global.
Signed-off-by: Brian Cain
---
target/hexagon/genptr.c | 56 -
target/hexagon/genptr.h | 18
target/hexagon/mmvec/system_ext_mmvec.c | 4 +-
target/hexagon/mmvec/system_ext_mmvec.h | 2 +-
target/hexagon/op_helper.c | 4 +-
5 files changed, 42 insertions(+), 42 deletions(-)
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index 217bc7bb5a..11377ac92b 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -334,28 +334,28 @@ void gen_set_byte_i64(int N, TCGv_i64 result, TCGv src)
tcg_gen_deposit_i64(result, result, src64, N * 8, 8);
}
-static inline void gen_load_locked4u(TCGv dest, TCGv vaddr, int mem_index)
+static inline void gen_load_locked4u(TCGv dest, TCGv v_addr, int mem_index)
{
-tcg_gen_qemu_ld_tl(dest, vaddr, mem_index, MO_TEUL);
-tcg_gen_mov_tl(hex_llsc_addr, vaddr);
+tcg_gen_qemu_ld_tl(dest, v_addr, mem_index, MO_TEUL);
+tcg_gen_mov_tl(hex_llsc_addr, v_addr);
tcg_gen_mov_tl(hex_llsc_val, dest);
}
-static inline void gen_load_locked8u(TCGv_i64 dest, TCGv vaddr, int mem_index)
+static inline void gen_load_locked8u(TCGv_i64 dest, TCGv v_addr, int mem_index)
{
-tcg_gen_qemu_ld_i64(dest, vaddr, mem_index, MO_TEUQ);
-tcg_gen_mov_tl(hex_llsc_addr, vaddr);
+tcg_gen_qemu_ld_i64(dest, v_addr, mem_index, MO_TEUQ);
+tcg_gen_mov_tl(hex_llsc_addr, v_addr);
tcg_gen_mov_i64(hex_llsc_val_i64, dest);
}
static inline void gen_store_conditional4(DisasContext *ctx,
- TCGv pred, TCGv vaddr, TCGv src)
+ TCGv pred, TCGv v_addr, TCGv src)
{
TCGLabel *fail = gen_new_label();
TCGLabel *done = gen_new_label();
TCGv one, zero, tmp;
-tcg_gen_brcond_tl(TCG_COND_NE, vaddr, hex_llsc_addr, fail);
+tcg_gen_brcond_tl(TCG_COND_NE, v_addr, hex_llsc_addr, fail);
one = tcg_constant_tl(0xff);
zero = tcg_constant_tl(0);
@@ -374,13 +374,13 @@ static inline void gen_store_conditional4(DisasContext
*ctx,
}
static inline void gen_store_conditional8(DisasContext *ctx,
- TCGv pred, TCGv vaddr, TCGv_i64 src)
+ TCGv pred, TCGv v_addr, TCGv_i64 src)
{
TCGLabel *fail = gen_new_label();
TCGLabel *done = gen_new_label();
TCGv_i64 one, zero, tmp;
-tcg_gen_brcond_tl(TCG_COND_NE, vaddr, hex_llsc_addr, fail);
+tcg_gen_brcond_tl(TCG_COND_NE, v_addr, hex_llsc_addr, fail);
one = tcg_constant_i64(0xff);
zero = tcg_constant_i64(0);
@@ -407,57 +407,57 @@ static TCGv gen_slotval(DisasContext *ctx)
}
#endif
-void gen_store32(TCGv vaddr, TCGv src, int width, uint32_t slot)
+void gen_store32(TCGv v_addr, TCGv src, int width, uint32_t slot)
{
-tcg_gen_mov_tl(hex_store_addr[slot], vaddr);
+tcg_gen_mov_tl(hex_store_addr[slot], v_addr);
tcg_gen_movi_tl(hex_store_width[slot], width);
tcg_gen_mov_tl(hex_store_val32[slot], src);
}
-void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot)
+void gen_store1(TCGv_env cpu_env_, TCGv v_addr, TCGv src, uint32_t slot)
{
-gen_store32(vaddr, src, 1, slot);
+gen_store32(v_addr, src, 1, slot);
}
-void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot)
+void gen_store1i(TCGv_env cpu_env_, TCGv v_addr, int32_t src, uint32_t slot)
{
TCGv tmp = tcg_constant_tl(src);
-gen_store1(cpu_env, vaddr, tmp, slot);
+gen_store1(cpu_env_, v_addr, tmp, slot);
}
-void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot)
+void gen_store2(TCGv_env cpu_env_, TCGv v_addr, TCGv src, uint32_t slot)
{
-gen_store32(vaddr, src, 2, slot);
+gen_store32(v_addr, src, 2, slot);
}
-void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot)
+void gen_store2i(TCGv_env cpu_env_, TCGv v_addr, int32_t src, uint32_t slot)
{
TCGv tmp = tcg_constant_tl(src);
-gen_store2(cpu_env, vaddr, tmp, slot);
+gen_store2(cpu_env_, v_addr, tmp, slot);
}
-void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot)
+void gen_store4(TCGv_env cpu_env_, TCGv v_addr, TCGv src, uint32_t slot)
{
-gen_store32(vaddr, src, 4, slot);
+gen_store32(v_addr, src, 4, slot);
}
-void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot)
+void gen_store4i(TCGv_env cpu_env_, TCGv v_addr, int32_t src, uint32_t slot)
{
TCGv tmp = tcg_constant_tl(src);
-gen_store4(cpu_env, vaddr, tmp, slot);
+gen_store4(cpu_env_, v_addr, tmp, slot);
}
-void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src, uint32_t slot)
+void gen_store8(TCGv_env cpu_env_, TCGv
[PATCH v2 0/3] hexagon: GETPC() and shadowing fixes
In v2: reworked with suggestions from Philippe and added a new patch to cover -Wshadow=global. Brian Cain (2): target/hexagon: fix some occurrences of -Wshadow=local target/hexagon: avoid shadowing globals Matheus Tavares Bernardino (1): target/hexagon: move GETPC() calls to top level helpers target/hexagon/genptr.c | 56 - target/hexagon/genptr.h | 18 +++--- target/hexagon/imported/alu.idef| 6 +- target/hexagon/macros.h | 19 +++--- target/hexagon/mmvec/macros.h | 6 +- target/hexagon/mmvec/system_ext_mmvec.c | 4 +- target/hexagon/mmvec/system_ext_mmvec.h | 2 +- target/hexagon/op_helper.c | 84 ++--- target/hexagon/op_helper.h | 9 --- target/hexagon/translate.c | 9 ++- 10 files changed, 91 insertions(+), 122 deletions(-) -- 2.25.1
