-extensions-programming-reference.html
Signed-off-by: Cathy Zhang
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index ca997a68cd..c4d623b8b9 100644
--- a/target/i386/cpu.c
+++ b/target/i386
-instruction-set-extensions-programming-reference.pdf
The associated kvm patch link is as follows:
https://lore.kernel.org/patchwork/patch/1268026/
Signed-off-by: Cathy Zhang
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/i386
-instruction-set-extensions-programming-reference.pdf
The associated kvm patch link is as follows:
https://lore.kernel.org/patchwork/patch/1268025/
Signed-off-by: Cathy Zhang
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target
to choose which
memory accesses do not need to be tracked in the TSX read set.
Cathy Zhang (2):
target/i386: Add SERIALIZE cpu feature
target/i386: Enable TSX Suspend Load Address Tracking feature
target/i386/cpu.c | 4 ++--
target/i386/cpu.h | 4
2 files changed, 6 insertions(+), 2 deletions
-set-extensions-programming-reference.pdf
Signed-off-by: Cathy Zhang
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 92fafa2..c8c95c3 100644
--- a/target/i386/cpu.c
+++ b/target/i386
Cooper Lake is intel's successor to Cascade Lake, the new
CPU model inherits features from Cascadelake-Server, while
add one platform associated new feature: AVX512_BF16. Meanwhile,
add STIBP for speculative execution.
Signed-off-by: Cathy Zhang
Reviewed-by: Xiaoyao Li
Reviewed-by: Tao Xu
and macro defined here as needed.
Cathy Zhang (3):
i386: Add MSR feature bit for MDS-NO
i386: Add macro for stibp
i386: Add new CPU model Cooperlake
target/i386/cpu.c | 60 +++
target/i386/cpu.h | 3 +++
2 files changed, 63 insertions
Define MSR_ARCH_CAP_MDS_NO in the IA32_ARCH_CAPABILITIES MSR to allow
CPU models to report the feature when host supports it.
Signed-off-by: Cathy Zhang
Reviewed-by: Xiaoyao Li
Reviewed-by: Tao Xu
---
target/i386/cpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/i386/cpu.h b
stibp feature is already added through the following commit.
https://github.com/qemu/qemu/commit/0e8916582991b9fd0b94850a8444b8b80d0a0955
Add a macro for it to allow CPU models to report it when host supports.
Signed-off-by: Cathy Zhang
Reviewed-by: Xiaoyao Li
Reviewed-by: Tao Xu
---
target
Define MSR_ARCH_CAP_MDS_NO in the IA32_ARCH_CAPABILITIES MSR to allow
CPU models to report the feature when host supports it.
Signed-off-by: Cathy Zhang
---
target/i386/cpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index eaa5395..e757149 100644
stibp feature is already added through the following commit.
https://github.com/qemu/qemu/commit/0e8916582991b9fd0b94850a8444b8b80d0a0955
Add a macro for it to allow CPU models report it when host supports.
Signed-off-by: Cathy Zhang
---
target/i386/cpu.h | 1 +
1 file changed, 1 insertion
Cooper Lake is intel's successor to Cascade Lake, the new
CPU model inherits features from Cascadelake-Server, while
add one platform associated new feature: AVX512_BF16, and
STIBP for speculative execution.
Signed-off-by: Cathy Zhang
---
target/i386/cpu.c | 59
and macro defined here as needed.
Cathy Zhang (3):
i386: Add MSR feature bit for MDS-NO
i386: Add macro for stibp
i386: Add new CPU model Cooperlake
target/i386/cpu.c | 59 +++
target/i386/cpu.h | 2 ++
2 files changed, 61 insertions
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