Re: [Qemu-devel] [PATCH v2 1/4] target-mips: add CPU definition for MIPS32R5
Reviewed-by: Eric Johnson eric.john...@imgtec.com
From: qemu-devel-bounces+eric.johnson=imgtec@nongnu.org
[qemu-devel-bounces+eric.johnson=imgtec@nongnu.org] on behalf of Petar
Jovanovic [petar.jovano...@rt-rk.com]
Sent: Friday, January 24, 2014 8:18 AM
To: qemu-devel@nongnu.org
Cc: Petar Jovanovic; aurel...@aurel32.net
Subject: [Qemu-devel] [PATCH v2 1/4] target-mips: add CPU definition for
MIPS32R5
From: Petar Jovanovic petar.jovano...@imgtec.com
Add mips32r5-generic among CPU definitions for MIPS.
Define ISA_MIPS32R3 and ISA_MIPS32R5.
Signed-off-by: Petar Jovanovic petar.jovano...@imgtec.com
---
target-mips/mips-defs.h |8
target-mips/translate_init.c | 25 +
2 files changed, 33 insertions(+)
diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h
index bf094a3..9dfa516 100644
--- a/target-mips/mips-defs.h
+++ b/target-mips/mips-defs.h
@@ -29,6 +29,8 @@
#defineISA_MIPS32R20x0040
#defineISA_MIPS64 0x0080
#defineISA_MIPS64R20x0100
+#define ISA_MIPS32R3 0x0200
+#define ISA_MIPS32R5 0x0400
/* MIPS ASEs. */
#defineASE_MIPS16 0x1000
@@ -64,6 +66,12 @@
#defineCPU_MIPS32R2(CPU_MIPS32 | ISA_MIPS32R2)
#defineCPU_MIPS64R2(CPU_MIPS64 | CPU_MIPS32R2 |
ISA_MIPS64R2)
+/* MIPS Technologies Release 3 */
+#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
+
+/* MIPS Technologies Release 5 */
+#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5)
+
/* Strictly follow the architecture standard:
- Disallow special instruction handling for PMON/SPIM.
Note that we still maintain Count/Compare to match the host clock. */
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index c45b1b2..d74a0af 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -333,6 +333,31 @@ static const mips_def_t mips_defs[] =
.insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
.mmu_type = MMU_TYPE_R4000,
},
+{
+/* A generic CPU providing MIPS32 Release 5 features.
+ FIXME: Eventually this should be replaced by a real CPU model. */
+.name = mips32r5-generic,
+.CP0_PRid = 0x00019700,
+.CP0_Config0 = MIPS_CONFIG0 | (0x1 CP0C0_AR) |
+(MMU_TYPE_R4000 CP0C0_MT),
+.CP0_Config1 = MIPS_CONFIG1 | (1 CP0C1_FP) | (15 CP0C1_MMU) |
+ (0 CP0C1_IS) | (3 CP0C1_IL) | (1 CP0C1_IA) |
+ (0 CP0C1_DS) | (3 CP0C1_DL) | (1 CP0C1_DA) |
+ (1 CP0C1_CA),
+.CP0_Config2 = MIPS_CONFIG2,
+.CP0_Config3 = MIPS_CONFIG3,
+.CP0_LLAddr_rw_bitmask = 0,
+.CP0_LLAddr_shift = 4,
+.SYNCI_Step = 32,
+.CCRes = 2,
+.CP0_Status_rw_bitmask = 0x3778FF1F,
+.CP1_fcr0 = (1 FCR0_F64) | (1 FCR0_L) | (1 FCR0_W) |
+(1 FCR0_D) | (1 FCR0_S) | (0x93 FCR0_PRID),
+.SEGBITS = 32,
+.PABITS = 32,
+.insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
+.mmu_type = MMU_TYPE_R4000,
+},
#if defined(TARGET_MIPS64)
{
.name = R4000,
--
1.7.9.5
Re: [Qemu-devel] [PATCH v2 2/4] target-mips: add support for CP0_Config4
Reviewed-by: Eric Johnson eric.john...@imgtec.com
From: qemu-devel-bounces+eric.johnson=imgtec@nongnu.org
[qemu-devel-bounces+eric.johnson=imgtec@nongnu.org] on behalf of Petar
Jovanovic [petar.jovano...@rt-rk.com]
Sent: Friday, January 24, 2014 8:18 AM
To: qemu-devel@nongnu.org
Cc: Petar Jovanovic; aurel...@aurel32.net
Subject: [Qemu-devel] [PATCH v2 2/4] target-mips: add support for CP0_Config4
From: Petar Jovanovic petar.jovano...@imgtec.com
Add CP0_Config4, define rw_bitmask.
Signed-off-by: Petar Jovanovic petar.jovano...@imgtec.com
---
target-mips/cpu.h|3 +++
target-mips/helper.h |1 +
target-mips/op_helper.c |6 ++
target-mips/translate.c | 15 +--
target-mips/translate_init.c |9 -
5 files changed, 31 insertions(+), 3 deletions(-)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 9caf447..e8216ab 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -368,6 +368,9 @@ struct CPUMIPSState {
#define CP0C3_MT 2
#define CP0C3_SM 1
#define CP0C3_TL 0
+uint32_t CP0_Config4;
+uint32_t CP0_Config4_rw_bitmask;
+#define CP0C4_M31
int32_t CP0_Config6;
int32_t CP0_Config7;
/* XXX: Maybe make LLAddr per-TC? */
diff --git a/target-mips/helper.h b/target-mips/helper.h
index 1a8b86d..9e4508b 100644
--- a/target-mips/helper.h
+++ b/target-mips/helper.h
@@ -134,6 +134,7 @@ DEF_HELPER_2(mtc0_ebase, void, env, tl)
DEF_HELPER_2(mttc0_ebase, void, env, tl)
DEF_HELPER_2(mtc0_config0, void, env, tl)
DEF_HELPER_2(mtc0_config2, void, env, tl)
+DEF_HELPER_2(mtc0_config4, void, env, tl)
DEF_HELPER_2(mtc0_lladdr, void, env, tl)
DEF_HELPER_3(mtc0_watchlo, void, env, tl, i32)
DEF_HELPER_3(mtc0_watchhi, void, env, tl, i32)
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 8e3a6d7..ed8dde8 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -1489,6 +1489,12 @@ void helper_mtc0_config2(CPUMIPSState *env, target_ulong
arg1)
env-CP0_Config2 = (env-CP0_Config2 0x8FFF0FFF);
}
+void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1)
+{
+env-CP0_Config4 = (env-CP0_Config4 (~env-CP0_Config4_rw_bitmask)) |
+ (arg1 env-CP0_Config4_rw_bitmask);
+}
+
void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
{
target_long mask = env-CP0_LLAddr_rw_bitmask;
diff --git a/target-mips/translate.c b/target-mips/translate.c
index ef0a2c3..db2f430 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -4405,7 +4405,11 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config3));
rn = Config3;
break;
-/* 4,5 are reserved */
+case 4:
+gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config4));
+rn = Config4;
+break;
+/* 5 is reserved */
/* 6,7 are implementation dependent */
case 6:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6));
@@ -4982,7 +4986,12 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
/* ignored, read only */
rn = Config3;
break;
-/* 4,5 are reserved */
+case 4:
+gen_helper_mtc0_config4(cpu_env, arg);
+rn = Config4;
+ctx-bstate = BS_STOP;
+break;
+/* 5 is reserved */
/* 6,7 are implementation dependent */
case 6:
/* ignored */
@@ -15916,6 +15925,8 @@ void cpu_state_reset(CPUMIPSState *env)
env-CP0_Config1 = env-cpu_model-CP0_Config1;
env-CP0_Config2 = env-cpu_model-CP0_Config2;
env-CP0_Config3 = env-cpu_model-CP0_Config3;
+env-CP0_Config4 = env-cpu_model-CP0_Config4;
+env-CP0_Config4_rw_bitmask = env-cpu_model-CP0_Config4_rw_bitmask;
env-CP0_Config6 = env-cpu_model-CP0_Config6;
env-CP0_Config7 = env-cpu_model-CP0_Config7;
env-CP0_LLAddr_rw_bitmask = env-cpu_model-CP0_LLAddr_rw_bitmask
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index d74a0af..a0398cd 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -45,6 +45,9 @@
(0 CP0C3_VEIC) | (0 CP0C3_VInt) | (0 CP0C3_SP) |\
(0 CP0C3_SM) | (0 CP0C3_TL))
+#define MIPS_CONFIG4 \
+((0 CP0C4_M))
+
/* MMU types, the first four entries have the same layout as the
CP0C0_MT field. */
enum mips_mmu_types {
@@ -64,6 +67,8 @@ struct mips_def_t {
int32_t CP0_Config1;
int32_t CP0_Config2;
int32_t CP0_Config3;
+int32_t CP0_Config4;
+int32_t CP0_Config4_rw_bitmask;
int32_t CP0_Config6;
int32_t CP0_Config7;
target_ulong CP0_LLAddr_rw_bitmask;
@@ -345,7 +350,9 @@ static const mips_def_t mips_defs[] =
(0 CP0C1_DS) | (3 CP0C1_DL) | (1 CP0C1_DA
Re: [Qemu-devel] [PATCH v2 4/4] target-mips: add user-mode FR switch support for MIPS32r5
Reviewed-by: Eric Johnson eric.john...@imgtec.com
From: qemu-devel-bounces+eric.johnson=imgtec@nongnu.org
[qemu-devel-bounces+eric.johnson=imgtec@nongnu.org] on behalf of Petar
Jovanovic [petar.jovano...@rt-rk.com]
Sent: Friday, January 24, 2014 8:18 AM
To: qemu-devel@nongnu.org
Cc: Petar Jovanovic; aurel...@aurel32.net
Subject: [Qemu-devel] [PATCH v2 4/4] target-mips: add user-mode FR switch
support for MIPS32r5
From: Petar Jovanovic petar.jovano...@imgtec.com
Description of UFR feature:
Required in MIPS32r5 if floating point is implemented and user-mode FR
switching is supported. The UFR register allows user-mode to clear StatusFR
by executing a CTC1 to UFR with GPR[0] as input, and read StatusFR by
executing a CFC1 to UFR.
helper_ctc1 has been extended with an additional parameter rt to check
requirements for UFR feature.
Definition of mips32r5-generic has been modified to include support for UFR.
Signed-off-by: Petar Jovanovic petar.jovano...@imgtec.com
---
target-mips/helper.h |2 +-
target-mips/op_helper.c | 41 ++---
target-mips/translate.c | 14 --
target-mips/translate_init.c |9 +
4 files changed, 56 insertions(+), 10 deletions(-)
diff --git a/target-mips/helper.h b/target-mips/helper.h
index b82f8e8..8c7921a 100644
--- a/target-mips/helper.h
+++ b/target-mips/helper.h
@@ -179,7 +179,7 @@ DEF_HELPER_2(yield, tl, env, tl)
/* CP1 functions */
DEF_HELPER_2(cfc1, tl, env, i32)
-DEF_HELPER_3(ctc1, void, env, tl, i32)
+DEF_HELPER_4(ctc1, void, env, tl, i32, i32)
DEF_HELPER_2(float_cvtd_s, i64, env, i32)
DEF_HELPER_2(float_cvtd_w, i64, env, i32)
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index eaf4d26..2ef6633 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -2199,12 +2199,23 @@ static inline void restore_flush_mode(CPUMIPSState *env)
target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
{
-target_ulong arg1;
+target_ulong arg1 = 0;
switch (reg) {
case 0:
arg1 = (int32_t)env-active_fpu.fcr0;
break;
+case 1:
+/* UFR Support - Read Status FR */
+if (env-active_fpu.fcr0 (1 FCR0_UFRP)) {
+if (env-CP0_Config5 (1 CP0C5_UFR)) {
+arg1 = (int32_t)
+ ((env-CP0_Status (1 CP0St_FR)) CP0St_FR);
+} else {
+helper_raise_exception(env, EXCP_RI);
+}
+}
+break;
case 25:
arg1 = ((env-active_fpu.fcr31 24) 0xfe) |
((env-active_fpu.fcr31 23) 0x1);
break;
@@ -,9 +2233,33 @@ target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
return arg1;
}
-void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t reg)
+void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t
rt)
{
-switch(reg) {
+switch (fs) {
+case 1:
+/* UFR Alias - Reset Status FR */
+if (!((env-active_fpu.fcr0 (1 FCR0_UFRP)) (rt == 0))) {
+return;
+}
+if (env-CP0_Config5 (1 CP0C5_UFR)) {
+env-CP0_Status = ~(1 CP0St_FR);
+compute_hflags(env);
+} else {
+helper_raise_exception(env, EXCP_RI);
+}
+break;
+case 4:
+/* UNFR Alias - Set Status FR */
+if (!((env-active_fpu.fcr0 (1 FCR0_UFRP)) (rt == 0))) {
+return;
+}
+if (env-CP0_Config5 (1 CP0C5_UFR)) {
+env-CP0_Status |= (1 CP0St_FR);
+compute_hflags(env);
+} else {
+helper_raise_exception(env, EXCP_RI);
+}
+break;
case 25:
if (arg1 0xff00)
return;
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 02a90cb..083f6ab 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -6818,7 +6818,12 @@ static void gen_mttr(CPUMIPSState *env, DisasContext
*ctx, int rd, int rt,
break;
case 3:
/* XXX: For now we support only a single FPU context. */
-gen_helper_0e1i(ctc1, t0, rd);
+{
+TCGv_i32 fs_tmp = tcg_const_i32(rd);
+
+gen_helper_0e2i(ctc1, t0, fs_tmp, rt);
+tcg_temp_free_i32(fs_tmp);
+}
break;
/* COP2: Not implemented. */
case 4:
@@ -7254,7 +7259,12 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc,
int rt, int fs)
break;
case OPC_CTC1:
gen_load_gpr(t0, rt);
-gen_helper_0e1i(ctc1, t0, fs);
+{
+TCGv_i32 fs_tmp = tcg_const_i32(fs);
+
+gen_helper_0e2i(ctc1, t0, fs_tmp, rt);
+tcg_temp_free_i32(fs_tmp);
+}
opn = ctc1;
break;
#if defined(TARGET_MIPS64)
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index 3d4dc88..29d39e2 100644
--- a/target-mips/translate_init.c
+++ b
Re: [Qemu-devel] [PATCH v2 3/4] target-mips: add support for CP0_Config5
Reviewed-by: Eric Johnson eric.john...@imgtec.com
From: qemu-devel-bounces+eric.johnson=imgtec@nongnu.org
[qemu-devel-bounces+eric.johnson=imgtec@nongnu.org] on behalf of Petar
Jovanovic [petar.jovano...@rt-rk.com]
Sent: Friday, January 24, 2014 8:18 AM
To: qemu-devel@nongnu.org
Cc: Petar Jovanovic; aurel...@aurel32.net
Subject: [Qemu-devel] [PATCH v2 3/4] target-mips: add support for CP0_Config5
From: Petar Jovanovic petar.jovano...@imgtec.com
Add CP0_Config5, define rw_bitmask and enable modifications.
Signed-off-by: Petar Jovanovic petar.jovano...@imgtec.com
---
target-mips/cpu.h| 10 ++
target-mips/helper.h |1 +
target-mips/op_helper.c |6 ++
target-mips/translate.c | 14 --
target-mips/translate_init.c | 12 +++-
5 files changed, 40 insertions(+), 3 deletions(-)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index e8216ab..60c8061 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -73,6 +73,7 @@ struct CPUMIPSFPUContext {
float_status fp_status;
/* fpu implementation/revision register (fir) */
uint32_t fcr0;
+#define FCR0_UFRP 28
#define FCR0_F64 22
#define FCR0_L 21
#define FCR0_W 20
@@ -371,6 +372,15 @@ struct CPUMIPSState {
uint32_t CP0_Config4;
uint32_t CP0_Config4_rw_bitmask;
#define CP0C4_M31
+uint32_t CP0_Config5;
+uint32_t CP0_Config5_rw_bitmask;
+#define CP0C5_M 31
+#define CP0C5_K 30
+#define CP0C5_CV 29
+#define CP0C5_EVA28
+#define CP0C5_MSAEn 27
+#define CP0C5_UFR2
+#define CP0C5_NFExists 0
int32_t CP0_Config6;
int32_t CP0_Config7;
/* XXX: Maybe make LLAddr per-TC? */
diff --git a/target-mips/helper.h b/target-mips/helper.h
index 9e4508b..b82f8e8 100644
--- a/target-mips/helper.h
+++ b/target-mips/helper.h
@@ -135,6 +135,7 @@ DEF_HELPER_2(mttc0_ebase, void, env, tl)
DEF_HELPER_2(mtc0_config0, void, env, tl)
DEF_HELPER_2(mtc0_config2, void, env, tl)
DEF_HELPER_2(mtc0_config4, void, env, tl)
+DEF_HELPER_2(mtc0_config5, void, env, tl)
DEF_HELPER_2(mtc0_lladdr, void, env, tl)
DEF_HELPER_3(mtc0_watchlo, void, env, tl, i32)
DEF_HELPER_3(mtc0_watchhi, void, env, tl, i32)
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index ed8dde8..eaf4d26 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -1495,6 +1495,12 @@ void helper_mtc0_config4(CPUMIPSState *env, target_ulong
arg1)
(arg1 env-CP0_Config4_rw_bitmask);
}
+void helper_mtc0_config5(CPUMIPSState *env, target_ulong arg1)
+{
+env-CP0_Config5 = (env-CP0_Config5 (~env-CP0_Config5_rw_bitmask)) |
+ (arg1 env-CP0_Config5_rw_bitmask);
+}
+
void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
{
target_long mask = env-CP0_LLAddr_rw_bitmask;
diff --git a/target-mips/translate.c b/target-mips/translate.c
index db2f430..02a90cb 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -4409,7 +4409,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config4));
rn = Config4;
break;
-/* 5 is reserved */
+case 5:
+gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5));
+rn = Config5;
+break;
/* 6,7 are implementation dependent */
case 6:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6));
@@ -4991,7 +4994,12 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
rn = Config4;
ctx-bstate = BS_STOP;
break;
-/* 5 is reserved */
+case 5:
+gen_helper_mtc0_config5(cpu_env, arg);
+rn = Config5;
+/* Stop translation as we may have switched the execution mode */
+ctx-bstate = BS_STOP;
+break;
/* 6,7 are implementation dependent */
case 6:
/* ignored */
@@ -15927,6 +15935,8 @@ void cpu_state_reset(CPUMIPSState *env)
env-CP0_Config3 = env-cpu_model-CP0_Config3;
env-CP0_Config4 = env-cpu_model-CP0_Config4;
env-CP0_Config4_rw_bitmask = env-cpu_model-CP0_Config4_rw_bitmask;
+env-CP0_Config5 = env-cpu_model-CP0_Config5;
+env-CP0_Config5_rw_bitmask = env-cpu_model-CP0_Config5_rw_bitmask;
env-CP0_Config6 = env-cpu_model-CP0_Config6;
env-CP0_Config7 = env-cpu_model-CP0_Config7;
env-CP0_LLAddr_rw_bitmask = env-cpu_model-CP0_LLAddr_rw_bitmask
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index a0398cd..3d4dc88 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -48,6 +48,9 @@
#define MIPS_CONFIG4 \
((0 CP0C4_M))
+#define MIPS_CONFIG5 \
+((0 CP0C5_M))
+
/* MMU types
Re: [Qemu-devel] [PATCH 2/3] target-mips: add support for CP0_Config5
Hi Petar,
When Config5 exists, Config4 must exist. So it wouldn't be reserved anymore.
You change does not seem to set Config3.M or Config4.M either. They must be
set when Config5 is present.
Eric
-Original Message-
From: qemu-devel-bounces+eric.johnson=imgtec@nongnu.org
[mailto:qemu-devel-bounces+eric.johnson=imgtec@nongnu.org] On Behalf Of
Petar Jovanovic
Sent: Wednesday, January 22, 2014 10:32 AM
To: qemu-devel@nongnu.org
Cc: Petar Jovanovic; aurel...@aurel32.net
Subject: [Qemu-devel] [PATCH 2/3] target-mips: add support for CP0_Config5
From: Petar Jovanovic petar.jovano...@imgtec.com
Add CP0_Config5, define rw_bitmask and enable modifications.
Signed-off-by: Petar Jovanovic petar.jovano...@imgtec.com
---
target-mips/cpu.h| 10 ++
target-mips/helper.h |1 +
target-mips/op_helper.c |5 +
target-mips/translate.c | 16 ++--
target-mips/translate_init.c | 10 ++
5 files changed, 40 insertions(+), 2 deletions(-)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 9caf447..25bbe3c 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -73,6 +73,7 @@ struct CPUMIPSFPUContext {
float_status fp_status;
/* fpu implementation/revision register (fir) */
uint32_t fcr0;
+#define FCR0_UFRP 28
#define FCR0_F64 22
#define FCR0_L 21
#define FCR0_W 20
@@ -368,6 +369,15 @@ struct CPUMIPSState {
#define CP0C3_MT 2
#define CP0C3_SM 1
#define CP0C3_TL 0
+int32_t CP0_Config5;
+uint32_t CP0_Config5_rw_bitmask;
+#define CP0C5_M 31
+#define CP0C5_K 30
+#define CP0C5_CV 29
+#define CP0C5_EVA28
+#define CP0C5_MSAEn 27
+#define CP0C5_UFR2
+#define CP0C5_NFExists 0
int32_t CP0_Config6;
int32_t CP0_Config7;
/* XXX: Maybe make LLAddr per-TC? */ diff --git a/target-mips/helper.h
b/target-mips/helper.h index 1a8b86d..1f52728 100644
--- a/target-mips/helper.h
+++ b/target-mips/helper.h
@@ -134,6 +134,7 @@ DEF_HELPER_2(mtc0_ebase, void, env, tl)
DEF_HELPER_2(mttc0_ebase, void, env, tl) DEF_HELPER_2(mtc0_config0, void, env,
tl) DEF_HELPER_2(mtc0_config2, void, env, tl)
+DEF_HELPER_2(mtc0_config5, void, env, tl)
DEF_HELPER_2(mtc0_lladdr, void, env, tl) DEF_HELPER_3(mtc0_watchlo, void,
env, tl, i32) DEF_HELPER_3(mtc0_watchhi, void, env, tl, i32) diff --git
a/target-mips/op_helper.c b/target-mips/op_helper.c index 8e3a6d7..9c9c022
100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -1489,6 +1489,11 @@ void helper_mtc0_config2(CPUMIPSState *env, target_ulong
arg1)
env-CP0_Config2 = (env-CP0_Config2 0x8FFF0FFF); }
+void helper_mtc0_config5(CPUMIPSState *env, target_ulong arg1) {
+env-CP0_Config5 = arg1 env-CP0_Config5_rw_bitmask; }
+
void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1) {
target_long mask = env-CP0_LLAddr_rw_bitmask; diff --git
a/target-mips/translate.c b/target-mips/translate.c index ef0a2c3..437b58a
100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -4405,7 +4405,11 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config3));
rn = Config3;
break;
-/* 4,5 are reserved */
+/* 4 is reserved */
+case 5:
+gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5));
+rn = Config5;
+break;
/* 6,7 are implementation dependent */
case 6:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6)); @@
-4982,7 +4986,13 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg,
int sel)
/* ignored, read only */
rn = Config3;
break;
-/* 4,5 are reserved */
+/* 4 is reserved */
+case 5:
+gen_helper_mtc0_config5(cpu_env, arg);
+rn = Config5;
+/* Stop translation as we may have switched the execution mode */
+ctx-bstate = BS_STOP;
+break;
/* 6,7 are implementation dependent */
case 6:
/* ignored */
@@ -15916,6 +15926,8 @@ void cpu_state_reset(CPUMIPSState *env)
env-CP0_Config1 = env-cpu_model-CP0_Config1;
env-CP0_Config2 = env-cpu_model-CP0_Config2;
env-CP0_Config3 = env-cpu_model-CP0_Config3;
+env-CP0_Config5 = env-cpu_model-CP0_Config5;
+env-CP0_Config5_rw_bitmask =
+ env-cpu_model-CP0_Config5_rw_bitmask;
env-CP0_Config6 = env-cpu_model-CP0_Config6;
env-CP0_Config7 = env-cpu_model-CP0_Config7;
env-CP0_LLAddr_rw_bitmask = env-cpu_model-CP0_LLAddr_rw_bitmask
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index
6ab6b73..09938f9 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -45,6 +45,9 @@
(0 CP0C3_VEIC) | (0 CP0C3_VInt) | (0 CP0C3_SP) |\
(0 CP0C3_SM) | (0 CP0C3_TL))
+#define MIPS_CONFIG5
Re: [Qemu-devel] [PATCH] target-mips: fix 34Kf configuration for DSP ASE
Hi Yongbok, You need to make Status.MX writeable as well. - .CP0_Status_rw_bitmask = 0x3678FF1F, + .CP0_Status_rw_bitmask = 0x3778FF1F, -Eric -Original Message- From: qemu-devel-bounces+eric.johnson=imgtec@nongnu.org [mailto:qemu-devel- bounces+eric.johnson=imgtec@nongnu.org] On Behalf Of Yongbok Kim Sent: Thursday, August 01, 2013 3:35 AM To: qemu-devel@nongnu.org Cc: Yongbok Kim; Cristian Cuna; Leon Alrae; aurel...@aurel32.net Subject: [Qemu-devel] [PATCH] target-mips: fix 34Kf configuration for DSP ASE 34Kf core does support DSP ASE. CP0_Config3 configuration for 34Kf and description are wrong. Please refer to MIPS32(R) 34Kf(TM) Processor Core Datasheet Signed-off-by: Yongbok Kim yongbok@imgtec.com --- target-mips/translate_init.c |5 ++--- 1 files changed, 2 insertions(+), 3 deletions(-) diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index 7cf238f..4cd9ed5 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -274,14 +274,13 @@ static const mips_def_t mips_defs[] = (0 CP0C1_DS) | (3 CP0C1_DL) | (1 CP0C1_DA) | (1 CP0C1_CA), .CP0_Config2 = MIPS_CONFIG2, -.CP0_Config3 = MIPS_CONFIG3 | (1 CP0C3_VInt) | (1 CP0C3_MT), +.CP0_Config3 = MIPS_CONFIG3 | (1 CP0C3_VInt) | (1 CP0C3_MT) | + (1 CP0C3_DSPP), .CP0_LLAddr_rw_bitmask = 0, .CP0_LLAddr_shift = 0, .SYNCI_Step = 32, .CCRes = 2, -/* No DSP implemented. */ .CP0_Status_rw_bitmask = 0x3678FF1F, -/* No DSP implemented. */ .CP0_TCStatus_rw_bitmask = (0 CP0TCSt_TCU3) | (0 CP0TCSt_TCU2) | (1 CP0TCSt_TCU1) | (1 CP0TCSt_TCU0) | (0 CP0TCSt_TMX) | (1 CP0TCSt_DT) | -- 1.7.4
Re: [Qemu-devel] [ANNOUNCE] 1.5 development tree is now open
On 02/15/2013 03:41 PM, Anthony Liguori wrote: Happy hacking! Regards, Anthony Liguori We might want to update the planning section of http://wiki.qemu.org/Contribute/StartHere to link to 1.4 and 1.5. I don't think I have a Wiki account otherwise I would just fix it myself. -Eric
Re: [Qemu-devel] [PATCH] target-mips: Replace macros by inline functions
;
@@ -2621,7 +2627,7 @@ uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t
fst0)
set_float_rounding_mode(float_round_up,env-active_fpu.fp_status);
wt2 = float32_to_int32(fst0,env-active_fpu.fp_status);
-RESTORE_ROUNDING_MODE;
+restore_rounding_mode(env);
if (get_float_exception_flags(env-active_fpu.fp_status)
(float_flag_invalid | float_flag_overflow)) {
wt2 = FP_TO_INT32_OVERFLOW;
@@ -2636,7 +2642,7 @@ uint64_t helper_float_floorl_d(CPUMIPSState *env,
uint64_t fdt0)
set_float_rounding_mode(float_round_down,env-active_fpu.fp_status);
dt2 = float64_to_int64(fdt0,env-active_fpu.fp_status);
-RESTORE_ROUNDING_MODE;
+restore_rounding_mode(env);
if (get_float_exception_flags(env-active_fpu.fp_status)
(float_flag_invalid | float_flag_overflow)) {
dt2 = FP_TO_INT64_OVERFLOW;
@@ -2651,7 +2657,7 @@ uint64_t helper_float_floorl_s(CPUMIPSState *env,
uint32_t fst0)
set_float_rounding_mode(float_round_down,env-active_fpu.fp_status);
dt2 = float32_to_int64(fst0,env-active_fpu.fp_status);
-RESTORE_ROUNDING_MODE;
+restore_rounding_mode(env);
if (get_float_exception_flags(env-active_fpu.fp_status)
(float_flag_invalid | float_flag_overflow)) {
dt2 = FP_TO_INT64_OVERFLOW;
@@ -2666,7 +2672,7 @@ uint32_t helper_float_floorw_d(CPUMIPSState *env,
uint64_t fdt0)
set_float_rounding_mode(float_round_down,env-active_fpu.fp_status);
wt2 = float64_to_int32(fdt0,env-active_fpu.fp_status);
-RESTORE_ROUNDING_MODE;
+restore_rounding_mode(env);
if (get_float_exception_flags(env-active_fpu.fp_status)
(float_flag_invalid | float_flag_overflow)) {
wt2 = FP_TO_INT32_OVERFLOW;
@@ -2681,7 +2687,7 @@ uint32_t helper_float_floorw_s(CPUMIPSState *env,
uint32_t fst0)
set_float_rounding_mode(float_round_down,env-active_fpu.fp_status);
wt2 = float32_to_int32(fst0,env-active_fpu.fp_status);
-RESTORE_ROUNDING_MODE;
+restore_rounding_mode(env);
if (get_float_exception_flags(env-active_fpu.fp_status)
(float_flag_invalid | float_flag_overflow)) {
wt2 = FP_TO_INT32_OVERFLOW;
Reviewed-by: Eric Johnson er...@mips.com
Re: [Qemu-devel] [PATCH qom-cpu 2/7] target-mips: Clean up mips_cpu_map_tc() documentation
On 12/19/2012 07:31 AM, Andreas Färber wrote: This function will be touched again soon, so a good understanding of env vs. other helps. Adopt gtk-doc style. Signed-off-by: Andreas Färberafaer...@suse.de --- target-mips/op_helper.c | 14 +- 1 Datei geändert, 9 Zeilen hinzugefügt(+), 5 Zeilen entfernt(-) diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index f9f2b23..83998ab 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -573,11 +573,15 @@ static inline void mips_tc_sleep(MIPSCPU *cpu, int tc) } } -/* tc should point to an int with the value of the global TC index. - This function will transform it into a local index within the - returned CPUMIPSState. - - FIXME: This code assumes that all VPEs have the same number of TCs, +/** + * mips_cpu_map_tc: + * @env: CPU from which mapping is performed. + * @tc: Should point to an int with the value of the global TC index. + * + * This function will transform @tc into a local index within the + * returned #CPUMIPSState. + */ +/* FIXME: This code assumes that all VPEs have the same number of TCs, which depends on runtime setup. Can probably be fixed by walking the list of CPUMIPSStates. */ static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc) Reviewed-by: Eric Johnson er...@mips.com
Re: [Qemu-devel] [PATCH] target-mips: Fix helper and tests for dot/cross-dot product instructions
On 01/01/2013 08:08 PM, Petar Jovanovic wrote:
From: Petar Jovanovicpet...@mips.com
Helper function for dpa_w_ph, dpax_w_ph, dps_w_ph and dpsx_w_ph incorrectly
defines halfword vector elements as unsigned values. This results in wrong
output which is not triggered in the tests as they also follow this logic.
Signed-off-by: Petar Jovanovicpet...@mips.com
---
target-mips/dsp_helper.c|2 +-
tests/tcg/mips/mips32-dspr2/dpa_w_ph.c |4 ++--
tests/tcg/mips/mips32-dspr2/dpax_w_ph.c | 17 +
tests/tcg/mips/mips32-dspr2/dps_w_ph.c | 17 +
tests/tcg/mips/mips32-dspr2/dpsx_w_ph.c |4 ++--
5 files changed, 39 insertions(+), 5 deletions(-)
diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c
index a33e2bf..4870e3d 100644
--- a/target-mips/dsp_helper.c
+++ b/target-mips/dsp_helper.c
@@ -2473,7 +2473,7 @@ DP_OB(dpsu_h_obr, 0, 24, 16, 8, 0, 24, 16, 8, 0);
void helper_##name(uint32_t ac, target_ulong rs, target_ulong rt,
\
CPUMIPSState *env)
\
{
\
-uint16_t rsB, rsA, rtB, rtA;
\
+int16_t rsB, rsA, rtB, rtA;
\
int32_t tempA, tempB;
\
int64_t acc;
\
\
diff --git a/tests/tcg/mips/mips32-dspr2/dpa_w_ph.c
b/tests/tcg/mips/mips32-dspr2/dpa_w_ph.c
index 1cfbdb0..fae49f1 100644
--- a/tests/tcg/mips/mips32-dspr2/dpa_w_ph.c
+++ b/tests/tcg/mips/mips32-dspr2/dpa_w_ph.c
@@ -26,8 +26,8 @@ int main()
ach = 6, acl = 7;
rs = 0x00FF;
rt = 0x0002;
-resulth = 0x05;
-resultl = 0xfffe0206;
+resulth = 0x06;
+resultl = 0x206;
__asm
(mthi %0, $ac1\n\t
mtlo %1, $ac1\n\t
diff --git a/tests/tcg/mips/mips32-dspr2/dpax_w_ph.c
b/tests/tcg/mips/mips32-dspr2/dpax_w_ph.c
index f756997..514797c 100644
--- a/tests/tcg/mips/mips32-dspr2/dpax_w_ph.c
+++ b/tests/tcg/mips/mips32-dspr2/dpax_w_ph.c
@@ -23,5 +23,22 @@ int main()
assert(ach == resulth);
assert(acl == resultl);
+ach = 6, acl = 7;
+rs = 0x00FF;
+rt = 0x0002;
+resulth = 0x05;
+resultl = 0xFF06;
+__asm
+(mthi %0, $ac1\n\t
+ mtlo %1, $ac1\n\t
+ dpax.w.ph $ac1, %2, %3\n\t
+ mfhi %0, $ac1\n\t
+ mflo %1, $ac1\n\t
+ : +r(ach), +r(acl)
+ : r(rs), r(rt)
+);
+assert(ach == resulth);
+assert(acl == resultl);
+
return 0;
}
diff --git a/tests/tcg/mips/mips32-dspr2/dps_w_ph.c
b/tests/tcg/mips/mips32-dspr2/dps_w_ph.c
index 8303643..f51f9b9 100644
--- a/tests/tcg/mips/mips32-dspr2/dps_w_ph.c
+++ b/tests/tcg/mips/mips32-dspr2/dps_w_ph.c
@@ -23,5 +23,22 @@ int main()
assert(ach == resulth);
assert(acl == resultl);
+ach = 6, acl = 7;
+rs = 0x00FF;
+rt = 0x0002;
+resulth = 0x05;
+resultl = 0xFE08;
+__asm
+(mthi %0, $ac1\n\t
+ mtlo %1, $ac1\n\t
+ dps.w.ph $ac1, %2, %3\n\t
+ mfhi %0, $ac1\n\t
+ mflo %1, $ac1\n\t
+ : +r(ach), +r(acl)
+ : r(rs), r(rt)
+);
+assert(ach == resulth);
+assert(acl == resultl);
+
return 0;
}
diff --git a/tests/tcg/mips/mips32-dspr2/dpsx_w_ph.c
b/tests/tcg/mips/mips32-dspr2/dpsx_w_ph.c
index 6db59a4..bb49a40 100644
--- a/tests/tcg/mips/mips32-dspr2/dpsx_w_ph.c
+++ b/tests/tcg/mips/mips32-dspr2/dpsx_w_ph.c
@@ -9,8 +9,8 @@ int main()
rs = 0xBC0123AD;
rt = 0x01643721;
-resulth = 0x04;
-resultl = 0xD751F050;
+resulth = 0x05;
+resultl = 0xE72F050;
__asm
(mthi %0, $ac1\n\t
mtlo %1, $ac1\n\t
Reviewed-by: Eric Johnson er...@mips.com
[Qemu-devel] [PATCH] target-mips: Allow DSP access to be disabled once enabled.
Clear the DSP hflags at the start of compute_hflags. Otherwise access
is not properly disabled once enabled.
Signed-off-by: Eric Johnson er...@mips.com
---
target-mips/cpu.h |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 31602ac..5963d62 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -751,7 +751,7 @@ static inline void compute_hflags(CPUMIPSState *env)
{
env-hflags = ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
- MIPS_HFLAG_UX);
+ MIPS_HFLAG_UX | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2);
if (!(env-CP0_Status (1 CP0St_EXL))
!(env-CP0_Status (1 CP0St_ERL))
!(env-hflags MIPS_HFLAG_DM)) {
--
1.7.4.4
Re: [Qemu-devel] [PATCH] linux-user: fix mips 32-on-64 prealloc case
On 01/03/2013 09:24 AM, Alexander Graf wrote: On 03.01.2013, at 18:19, Peter Maydell wrote: On 3 January 2013 13:17, Alexander Grafag...@suse.de wrote: MIPS only supports 31 bits of virtual address space for user space, so let's make sure we stay within that limit with our preallocated memory block. This fixes the MIPS user space targets when executed without command line option. This looks weird -- why should the guest care that we've reserved a 4GB block which it only uses half of? Or is the problem that host mmap() ends up handing out addresses from anywhere in the 4GB reserved area? Even worse, it starts from the top IIRC. MIPS uses the upper virtual address bit for kernel/user space indication. I'm not sure where exactly this logic falls apart in our case, but user space virtual addresses above 2GB are simple illegal in that world, so I wouldn't expect QEMU or a guest process to cope with them. Alex While making this change please keep in mind that newer MIPS32 processors allow more than 31 bits of user address space (up to 3.5 GiB) if they have Enhanced Virtual Address support. For example see the Software User's Manual for the interAptiv processors: At the bottom of the page http://www.mips.com/products/processor-cores/aptiv/interaptiv/ is the link interAptiv^(TM) Multiprocessing System Software User's Manual http://www.mips.com/secure-download/index.dot?product_name=/auth/MD00904-2B-interAptiv-SUM-01.04.pdf Go to section 1.2.7.5 Enhanced Virtual Address Eric
Re: [Qemu-devel] [PATCH] linux-user: fix mips 32-on-64 prealloc case
On 01/03/2013 10:50 AM, Richard Henderson wrote: On 01/03/2013 10:39 AM, Eric Johnson wrote: While making this change please keep in mind that newer MIPS32 processors allow more than 31 bits of user address space (up to 3.5 GiB) if they have Enhanced Virtual Address support. Interesting. Well, would you be able to help figure out exactly what's going on in: http://lists.gnu.org/archive/html/qemu-devel/2012-12/msg03233.html and the thread leading up to it? Now, I don't *know* that this is an emulation failure -- the linux-user-test binary certainly isn't aware of enhanced virtual addresses. So it's possible that (older?) binaries can't cope with more than 2GB. Alternately, it really is a translation problem somewhere... r~ That is correct. The current test and MIPS32 processors supported by QEMU do not support more than 2 GiB of user space. I didn't mean to imply otherwise. Looking at the MIPS32 processor linux-user on a 64-bit host issue is already on my long list of tasks. Sorry I have not been able to look at it yet. On second thought ignore my EVA comment for now. We'll worry about that when implementing EVA. Eric
[Qemu-devel] [PATCH] target-mips: Fix seg fault for LUI when MIPS_DEBUG_DISAS==1.
The call to gen_logic_imm for OPC_LUI passes -1 for rs. This
causes the MIPS_DEBUG statement to seg fault due to the deference
of regnames[rs]. This patch fixes that.
Signed-off-by: Eric Johnson er...@mips.com
---
target-mips/translate.c | 18 +++---
1 files changed, 11 insertions(+), 7 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 8175da0..aba6327 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -2013,7 +2013,6 @@ static void gen_logic_imm(CPUMIPSState *env, DisasContext
*ctx, uint32_t opc,
int rt, int rs, int16_t imm)
{
target_ulong uimm;
-const char *opn = imm logic;
if (rt == 0) {
/* If no destination, treat it as a NOP. */
@@ -2027,29 +2026,34 @@ static void gen_logic_imm(CPUMIPSState *env,
DisasContext *ctx, uint32_t opc,
tcg_gen_andi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
else
tcg_gen_movi_tl(cpu_gpr[rt], 0);
-opn = andi;
+MIPS_DEBUG(%s %s, %s, TARGET_FMT_lx, andi, regnames[rt],
+regnames[rs], uimm);
break;
case OPC_ORI:
if (rs != 0)
tcg_gen_ori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
else
tcg_gen_movi_tl(cpu_gpr[rt], uimm);
-opn = ori;
+MIPS_DEBUG(%s %s, %s, TARGET_FMT_lx, ori, regnames[rt],
+regnames[rs], uimm);
break;
case OPC_XORI:
if (likely(rs != 0))
tcg_gen_xori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
else
tcg_gen_movi_tl(cpu_gpr[rt], uimm);
-opn = xori;
+MIPS_DEBUG(%s %s, %s, TARGET_FMT_lx, xori, regnames[rt],
+regnames[rs], uimm);
break;
case OPC_LUI:
tcg_gen_movi_tl(cpu_gpr[rt], imm 16);
-opn = lui;
+MIPS_DEBUG(lui %s, TARGET_FMT_lx, regnames[rt], uimm);
+break;
+
+default:
+MIPS_DEBUG(Unknown logical immediate opcode %08x, opc);
break;
}
-(void)opn; /* avoid a compiler warning */
-MIPS_DEBUG(%s %s, %s, TARGET_FMT_lx, opn, regnames[rt], regnames[rs],
uimm);
}
/* Set on less than with immediate operand */
--
1.7.4.4
[Qemu-devel] [PATCH] Allow microMIPS SWP and SDP to have RD equal to BASE.
The microMIPS SWP and SDP instructions do not modify GPRs. So their
behavior is well defined when RD equals BASE. The MIPS Architecture
Verification Programs (AVPs) check that they work as expected. This
is required for AVPs to pass.
Signed-off-by: Eric Johnson er...@mips.com
---
target-mips/translate.c | 10 +-
1 files changed, 9 insertions(+), 1 deletions(-)
The patch applies to a8467c7a0e8b024a18608ff7db31ca2f2297e641.
diff --git a/target-mips/translate.c b/target-mips/translate.c
index d5b1c76..82cf75b 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -10034,7 +10034,7 @@ static void gen_ldst_pair (DisasContext *ctx, uint32_t
opc, int rd,
const char *opn = ldst_pair;
TCGv t0, t1;
-if (ctx-hflags MIPS_HFLAG_BMASK || rd == 31 || rd == base) {
+if (ctx-hflags MIPS_HFLAG_BMASK || rd == 31) {
generate_exception(ctx, EXCP_RI);
return;
}
@@ -10046,6 +10046,10 @@ static void gen_ldst_pair (DisasContext *ctx, uint32_t
opc, int rd,
switch (opc) {
case LWP:
+if (rd == base) {
+generate_exception(ctx, EXCP_RI);
+return;
+}
save_cpu_state(ctx, 0);
op_ld_lw(t1, t0, ctx);
gen_store_gpr(t1, rd);
@@ -10067,6 +10071,10 @@ static void gen_ldst_pair (DisasContext *ctx, uint32_t
opc, int rd,
break;
#ifdef TARGET_MIPS64
case LDP:
+if (rd == base) {
+generate_exception(ctx, EXCP_RI);
+return;
+}
save_cpu_state(ctx, 0);
op_ld_ld(t1, t0, ctx);
gen_store_gpr(t1, rd);
[Qemu-devel] [PATCH] Fix compile when MIPS_DEBUG_DISAS is defined.
When MIPS_DEBUG_DISAS is defined the gen_logic_imm, gen_slt_imm,
gen_cond_move, gen_logic and gen_slt functions cause errors because ctx
is not defined. Fixed the functions by passing in the DisasContext.
Signed-off-by: Eric Johnson er...@mips.com
---
target-mips/translate.c | 72 +-
1 files changed, 39 insertions(+), 33 deletions(-)
This patch applies to a8467c7a0e8b024a18608ff7db31ca2f2297e641.
diff --git a/target-mips/translate.c b/target-mips/translate.c
index d5b1c76..00afc48 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -1420,7 +1420,8 @@ static void gen_arith_imm (CPUState *env, DisasContext
*ctx, uint32_t opc,
}
/* Logic with immediate operand */
-static void gen_logic_imm (CPUState *env, uint32_t opc, int rt, int rs,
int16_t imm)
+static void gen_logic_imm(CPUState *env, DisasContext *ctx, uint32_t opc,
+int rt, int rs, int16_t imm)
{
target_ulong uimm;
const char *opn = imm logic;
@@ -1463,7 +1464,8 @@ static void gen_logic_imm (CPUState *env, uint32_t opc,
int rt, int rs, int16_t
}
/* Set on less than with immediate operand */
-static void gen_slt_imm (CPUState *env, uint32_t opc, int rt, int rs, int16_t
imm)
+static void gen_slt_imm(CPUState *env, DisasContext *ctx, uint32_t opc,
+int rt, int rs, int16_t imm)
{
target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */
const char *opn = imm arith;
@@ -1764,7 +1766,8 @@ static void gen_arith (CPUState *env, DisasContext *ctx,
uint32_t opc,
}
/* Conditional move */
-static void gen_cond_move (CPUState *env, uint32_t opc, int rd, int rs, int rt)
+static void gen_cond_move(CPUState *env, DisasContext *ctx, uint32_t opc,
+int rd, int rs, int rt)
{
const char *opn = cond move;
int l1;
@@ -1802,7 +1805,8 @@ static void gen_cond_move (CPUState *env, uint32_t opc,
int rd, int rs, int rt)
}
/* Logic */
-static void gen_logic (CPUState *env, uint32_t opc, int rd, int rs, int rt)
+static void gen_logic(CPUState *env, DisasContext *ctx, uint32_t opc, int rd,
+int rs, int rt)
{
const char *opn = logic;
@@ -1863,7 +1867,8 @@ static void gen_logic (CPUState *env, uint32_t opc, int
rd, int rs, int rt)
}
/* Set on lower than */
-static void gen_slt (CPUState *env, uint32_t opc, int rd, int rs, int rt)
+static void gen_slt(CPUState *env, DisasContext *ctx, uint32_t opc, int rd,
+int rs, int rt)
{
const char *opn = slt;
TCGv t0, t1;
@@ -8763,10 +8768,10 @@ static int decode_extended_mips16_opc (CPUState *env,
DisasContext *ctx,
gen_arith_imm(env, ctx, OPC_ADDIU, rx, rx, imm);
break;
case M16_OPC_SLTI:
-gen_slt_imm(env, OPC_SLTI, 24, rx, imm);
+gen_slt_imm(env, ctx, OPC_SLTI, 24, rx, imm);
break;
case M16_OPC_SLTIU:
-gen_slt_imm(env, OPC_SLTIU, 24, rx, imm);
+gen_slt_imm(env, ctx, OPC_SLTIU, 24, rx, imm);
break;
case M16_OPC_I8:
switch (funct) {
@@ -8978,14 +8983,14 @@ static int decode_mips16_opc (CPUState *env,
DisasContext *ctx,
{
int16_t imm = (uint8_t) ctx-opcode;
-gen_slt_imm(env, OPC_SLTI, 24, rx, imm);
+gen_slt_imm(env, ctx, OPC_SLTI, 24, rx, imm);
}
break;
case M16_OPC_SLTIU:
{
int16_t imm = (uint8_t) ctx-opcode;
-gen_slt_imm(env, OPC_SLTIU, 24, rx, imm);
+gen_slt_imm(env, ctx, OPC_SLTIU, 24, rx, imm);
}
break;
case M16_OPC_I8:
@@ -9061,7 +9066,7 @@ static int decode_mips16_opc (CPUState *env, DisasContext
*ctx,
{
int16_t imm = (uint8_t) ctx-opcode;
-gen_logic_imm(env, OPC_XORI, 24, rx, imm);
+gen_logic_imm(env, ctx, OPC_XORI, 24, rx, imm);
}
break;
#if defined(TARGET_MIPS64)
@@ -9173,10 +9178,10 @@ static int decode_mips16_opc (CPUState *env,
DisasContext *ctx,
}
break;
case RR_SLT:
-gen_slt(env, OPC_SLT, 24, rx, ry);
+gen_slt(env, ctx, OPC_SLT, 24, rx, ry);
break;
case RR_SLTU:
-gen_slt(env, OPC_SLTU, 24, rx, ry);
+gen_slt(env, ctx, OPC_SLTU, 24, rx, ry);
break;
case RR_BREAK:
generate_exception(ctx, EXCP_BREAK);
@@ -9197,22 +9202,22 @@ static int decode_mips16_opc (CPUState *env,
DisasContext *ctx,
break;
#endif
case RR_CMP:
-gen_logic(env, OPC_XOR, 24, rx, ry);
+gen_logic(env, ctx, OPC_XOR, 24, rx, ry);
break;
case RR_NEG:
gen_arith(env, ctx, OPC_SUBU, rx, 0, ry);
break;
case RR_AND:
-gen_logic(env, OPC_AND, rx, rx, ry);
+gen_logic(env, ctx, OPC_AND, rx, rx, ry);
break;
case RR_OR:
-gen_logic(env, OPC_OR, rx, rx, ry);
+gen_logic(env, ctx, OPC_OR, rx, rx, ry
