Reviewed-by: Frank Chang
Daniel Henrique Barboza 於 2024年3月8日 週五 上午12:04寫道：
>
> From: Tomasz Jeznach
>
> Extend memory transaction attributes with process identifier to allow
> per-request address translation logic to use requester_id / process_id
> to identify memory mapp
From: Frank Chang
Currently, QEMU only sets the iforce register to 0 and returns early
when claiming the iforce register. However, this may leave mip.meip
remains at 1 if a spurious external interrupt triggered by iforce
register is the only pending interrupt to be claimed, and the interrupt
From: Frank Chang
Add missing include guard in pmu.h to avoid the problem of double
inclusion.
Signed-off-by: Frank Chang
---
target/riscv/pmu.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h
index 505fc850d3..7c0ad661e0 100644
--- a/target
Reviewed-by: Frank Chang
On Tue, Feb 6, 2024 at 9:19 PM Jason Chien wrote:
> The original implementation sets $pc to the address read from the jump
> vector table first and links $ra with the address of the next instruction
> after the updated $pc. After jumping to the up
Reviewed-by: Frank Chang
On Wed, Aug 9, 2023 at 6:23 PM Jason Chien wrote:
> In pcie_bus_realize(), a root bus is realized as a PCIe bus and a non-root
> bus is realized as a PCIe bus if its parent bus is a PCIe bus. However,
> the child bus "dw-pcie" is realized before t
Reviewed-by: Frank Chang
On Tue, Jul 4, 2023 at 4:41 PM Jason Chien wrote:
> RVA23 Profiles states:
> The RVA23 profiles are intended to be used for 64-bit application
> processors that will run rich OS stacks from standard binary OS
> distributions and with a substantial number of
Reviewed-by: Frank Chang
On Fri, May 19, 2023 at 2:23 PM Tommy Wu wrote:
> When we receive a packet from the xilinx_axienet and then try to s2mem
> through the xilinx_axidma, if the descriptor ring buffer is full in the
> xilinx axidma driver, we’ll assert the DMASR.HALTED in the
&
Reviewed-by: Frank Chang
On Tue, Feb 21, 2023 at 5:10 PM Weiwei Li wrote:
> The spec can be found in https://github.com/riscv/riscv-zicond.
> Two instructions are added:
> - czero.eqz: Moves zero to a register rd, if the condition rs2 is
>equal to zero, otherwise mov
Reviewed-by: Frank Chang
On Wed, Feb 22, 2023 at 2:46 AM Daniel Henrique Barboza <
dbarb...@ventanamicro.com> wrote:
> Commit 752614cab8e6 ("target/riscv: rvv: Add tail agnostic for vector
> load / store instructions") added code to set the tail elements to 1 in
> th
Reviewed-by: Frank Chang
On Mon, Feb 13, 2023 at 5:45 PM LIU Zhiwei
wrote:
> vslide1up_##BITWIDTH is used by the vslide1up.vx and vslide1up.vf. So its
> scalar input should be uint64_t to hold the 64 bits float register.And the
> same for vslide1down_##BITWIDTH.
>
> This bug is
Reviewed-by: Frank Chang
On Thu, Feb 9, 2023 at 8:34 AM Alistair Francis <
alistair.fran...@opensource.wdc.com> wrote:
> From: Alistair Francis
>
> This patch adds some active RISC-V members as reviewers to the
> MAINTAINERS file.
>
> Signed-off-by: Alistair Francis
From: Frank Chang
The RVV specification does not require that the core needs to support
the privileged specification v1.12.0 to support RVV, and there is no
dependency from ISA level.
This commit removes the restriction from both RVV CSRs and extension CPU
ISA string.
Signed-off-by: Frank
I realized that I should also remove the privileged version check
in isa_edata_arr[], too.
I will send out v2 patch to fix it.
Regards,
Frank Chang
On Tue, Feb 7, 2023 at 4:43 PM wrote:
> From: Frank Chang
>
> The RVV specification does not require that the core needs t
From: Frank Chang
The RVV specification does not require that the core needs to support
the privileged specification v1.12.0 to support RVV, and there is no
dependency from ISA level. This commit removes the restriction.
Signed-off-by: Frank Chang
---
target/riscv/csr.c | 21
ot;sv39";
> +case VM_1_10_MBARE:
> +return "none";
> +}
> +}
> +
> +g_assert_not_reached();
> +}
> +
> +/* Sets the satp mode to the max supported */
> +static void set_satp_mode_default_map(RISCVCPU *cpu)
> +{
&g
Reviewed-by: Frank Chang
On Fri, Feb 3, 2023 at 2:02 PM Alexandre Ghiti
wrote:
> Currently, the max satp mode is set with the only constraint that it must
> be
> implemented in QEMU, i.e. set in valid_vm_1_10_[32|64].
>
> But we actually need to add another level of constrai
On Thu, Feb 2, 2023 at 9:01 PM Alexandre Ghiti
wrote:
> Hi Frank,
>
> On Wed, Feb 1, 2023 at 4:49 PM Frank Chang wrote:
> >
> > On Tue, Jan 31, 2023 at 10:36 PM Alexandre Ghiti
> wrote:
> >>
> >> Currently, the max satp mode is set with the only con
lid_vm_1_10_32 and valid_vm_1_10_64 are defined in !CONFIG_USER_ONLY
section.
This issue also exists in patch 3.
You have to move valid_vm_1_10_32 and valid_vm_1_10_64 out from
!CONFIG_USER_ONLY.
Regards,
Frank Chang
> -if (riscv_feature(>env, RISCV_FEATURE_MMU)) {
> -
Reviewed-by: Frank Chang
On Tue, Jan 31, 2023 at 10:36 PM Alexandre Ghiti
wrote:
> The 'mmu-type' should reflect what the hardware is capable of so use the
> new satp_mode field in RISCVCPUConfig to do that.
>
> Signed-off-by: Alexandre Ghiti
> Reviewed-by: Andrew Jo
Reviewed-by: Frank Chang
On Tue, Jan 31, 2023 at 10:29 PM Alexandre Ghiti
wrote:
> This array is actually used as a boolean so swap its current char type
> to a boolean and at the same time, change the type of validate_vm to
> bool since it returns valid_vm_1_10_[32|64].
>
Reviewed-by: Frank Chang
On Fri, Jan 13, 2023 at 6:35 PM Alexandre Ghiti
wrote:
> One can extract the DeviceState pointer from the Object pointer, so pass
> the Object for future commits to access other fields of Object.
>
> No functional changes intended.
>
> Signed-off-b
e add another helper function to wrap this for the "named" CPUs?
Regards,
Frank Chang
On Mon, Dec 12, 2022 at 6:23 PM Alexandre Ghiti
wrote:
> RISC-V specifies multiple sizes for addressable memory and Linux probes for
> the machine's support at startup via the satp CSR regis
Reviewed-by: Frank Chang
On Thu, Dec 15, 2022 at 11:09 PM Elta <503386...@qq.com> wrote:
> Should be cpu->cfg.elen in range [8, 64].
>
> Signed-off-by: Dongxue Zhang
> ---
> target/riscv/cpu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --
Reviewed-by: Frank Chang
On Wed, Sep 14, 2022 at 6:12 PM Alistair Francis via
wrote:
> Instead of using our properties to set a config value which then might
> be used to set the resetvec (depending on your timing), let's instead
> just set the resetvec directly in the e
Reviewed-by: Frank Chang
On Thu, Sep 22, 2022 at 4:41 PM Tommy Wu wrote:
> Create the AON device when we realize the sifive_e machine.
> This patch only implemented the functionality of the watchdog timer,
> not all the functionality of the AON device.
>
> Signed-off-by: Tommy
Reviewed-by: Frank Chang
On Thu, Sep 22, 2022 at 4:41 PM Tommy Wu wrote:
> The watchdog timer is in the always-on domain device of HiFive 1 rev b,
> so this patch added the AON device to the sifive_e machine. This patch
> only implemented the functionality of the watchdog timer.
>
Reviewed-by: Frank Chang
On Thu, Sep 22, 2022 at 4:42 PM Tommy Wu wrote:
> Add some simple tests of the watchdog timer in the always-on domain device
> of HiFive 1 rev b.
>
> Signed-off-by: Tommy Wu
> ---
> tests/qtest/meson.build | 3 +
> tests/qtest/
Reviewed-by: Frank Chang
On Wed, Aug 17, 2022 at 11:45 PM Yang Liu wrote:
> Starting with RVV1.0, the original vf[w]redsum_vs instruction was renamed
> to vf[w]redusum_vs. The distinction between ordered and unordered is also
> more consistent with other instructions,
Reviewed-by: Frank Chang
On Wed, Aug 17, 2022 at 11:32 PM Yang Liu wrote:
> Remove duplicate code by wrapping vfwredsum_vs's OP function.
>
> Signed-off-by: Yang Liu
> ---
> target/riscv/vector_helper.c | 56 +++-
> 1 file changed, 10
Hi Bernhard,
I think there's already a similar patch for this bug fix:
https://www.mail-archive.com/qemu-devel@nongnu.org/msg905424.html
Regards,
Frank Chang
On Thu, Sep 22, 2022 at 3:53 PM Bernhard Beschow wrote:
> SiFiveEState inherits from SysBusDevice while it's TypeInfo cla
From: Frank Chang
After RISCVException enum is introduced, riscv_csrrw_debug() returns
RISCV_EXCP_NONE to indicate there's no error. RISC-V vector GDB stub
should check the result against RISCV_EXCP_NONE instead of value 0.
Otherwise, 'E14' packet would be incorrectly reported for vector CSRs
ot;, "output from TCG plugins\n"},
> #endif
> +{ CPU_LOG_TB_VU, "vu",
> + "include vector unit registers in the 'cpu' logging" },
> { LOG_STRACE, "strace",
>"log every user-mode syscall, its input, and its result" },
> { LOG_PER_THREAD, "tid",
> --
> 2.34.0
>
>
Reviewed-by: Frank Chang
gt; + cpu->cfg.elen < 8)) {
> error_setg(errp,
> "Vector extension implementation only supports
> ELEN "
> "in the range [8, 64]");
>
From: Frank Chang
If the value written to tselect is greater than or equal to the number
of supported triggers, then the following reads of tselect would return
value 0.
Signed-off-by: Frank Chang
---
target/riscv/cpu.h | 1 +
target/riscv/debug.c | 6 ++
2 files changed, 7 insertions
From: Frank Chang
Type 6 trigger is similar to a type 2 trigger, but provides additional
functionality and should be used instead of type 2 in newer
implementations.
Signed-off-by: Frank Chang
---
target/riscv/debug.c | 174 ++-
target/riscv/debug.h
From: Frank Chang
Type 2 trigger cannot be fired in VU/VS modes.
Signed-off-by: Frank Chang
---
target/riscv/debug.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index ab23566113..ce9ff15d75 100644
--- a/target/riscv/debug.c
+++ b
From: Frank Chang
Trigger actions are shared among all triggers. Extract to a common
function.
Signed-off-by: Frank Chang
---
target/riscv/debug.c | 55 ++--
target/riscv/debug.h | 13 +++
2 files changed, 66 insertions(+), 2 deletions(-)
diff
From: Frank Chang
Current RISC-V debug assumes that only type 2 trigger is supported.
To allow more types of triggers to be supported in the future
(e.g. type 6 trigger, which is similar to type 2 trigger with additional
functionality), we should determine the trigger type from tdata1.type
From: Frank Chang
tinfo.info:
One bit for each possible type enumerated in tdata1.
If the bit is set, then that type is supported by the currently
selected trigger.
Signed-off-by: Frank Chang
---
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c | 8
target/riscv/debug.c
From: Frank Chang
Introduce build_tdata1() to build tdata1 register content, which can be
shared among all types of triggers.
Signed-off-by: Frank Chang
---
target/riscv/debug.c | 15 ++-
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/target/riscv/debug.c b/target
From: Frank Chang
The value of tselect CSR can be written should be limited within the
range of supported triggers number.
Signed-off-by: Frank Chang
---
target/riscv/debug.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/target/riscv/debug.c b/target/riscv
From: Frank Chang
This patchset refactors RISC-V Debug support to allow more types of
triggers to be extended.
The initial support of type 6 trigger, which is similar to type 2
trigger with additional functionality, is also introduced in this
patchset.
Frank Chang (9):
target/riscv: debug
From: Frank Chang
Replace type2_trigger_t with the real tdata1, tdata2, and tdata3 CSRs,
which allows us to support more types of triggers in the future.
Signed-off-by: Frank Chang
---
target/riscv/cpu.h | 6 ++-
target/riscv/debug.c | 101
ak;
> -case CSR_INSTRETH:
> -if (!get_field(env->mcounteren, COUNTEREN_IR)) {
> -return RISCV_EXCP_ILLEGAL_INST;
> -}
> -break;
> -case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
> -
VMSTATE_UINTTL(mhpmcounterh_prev, PMUCTRState),
> +VMSTATE_UINT8(write_done, PMUCTRState),
> VMSTATE_BOOL(started, PMUCTRState),
> VMSTATE_END_OF_LIST()
> }
> @@ -355,6 +356,9 @@ const VMStateDescription vmstate_riscv_cpu = {
>
From: Frank Chang
"mimpid" cpu option was mistyped to "mipid".
Fixes: 9951ba94 ("target/riscv: Support configuarable marchid, mvendorid, mipid
CSR values")
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 4 ++--
target/riscv/cp
From: Frank Chang
"mimpid" cpu option was mistyped to "mipid".
Fixes: 9951ba94 ("target/riscv: Support configuarable marchid, mvendorid, mipid
CSR values")
Signed-off-by: Frank Chang
---
target/riscv/cpu.c | 4 ++--
target/riscv/cpu.h | 2 +-
target/riscv/csr.c
From: Frank Chang
"mimpid" cpu option was mistyped to "mipid".
Fixes commit: 9951ba94
Signed-off-by: Frank Chang
---
target/riscv/cpu.c | 4 ++--
target/riscv/cpu.h | 2 +-
target/riscv/csr.c | 8
3 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/
On Fri, May 13, 2022 at 11:58 PM Atish Kumar Patra
wrote:
> On Thu, May 12, 2022 at 11:29 PM Frank Chang
> wrote:
> >
> > On Thu, May 12, 2022 at 6:01 AM Atish Patra wrote:
> >>
> >> From: Atish Patra
> >>
> >> mcycle/minstret are actually
Reviewed-by: Frank Chang
On Sat, May 14, 2022 at 6:15 AM Atish Patra wrote:
> timecmp update function should be invoked with hartid for which
> timecmp is being updated. The following patch passes the incorrect
> hartid to the update function.
>
> Fixes: e2f01f3c2e13 ("
}
>
> return RISCV_EXCP_NONE;
> }
>
> static int read_hpmcounter(CPURISCVState *env, int csrno, target_ulong
> *val)
> {
> -int ctr_index;
> +uint16_t ctr_index;
>
> if (env->priv == PRV_M) {
> -ctr_index = csrno - CSR_MHP
On Thu, May 5, 2022 at 4:50 AM Edgar E. Iglesias
wrote:
>
> On Tue, May 3, 2022 at 7:12 PM Edgar E. Iglesias
> wrote:
>
>> On Tue, May 3, 2022 at 5:06 PM Frank Chang
>> wrote:
>>
>>> On Tue, May 3, 2022 at 5:35 PM Edgar E. Iglesias <
>>> edga
Hi Anup,
I found that Atish has already submitted a patch to implement the
mcountinhibit CSR:
https://www.mail-archive.com/qemu-devel@nongnu.org/msg879349.html
Regards,
Frank Chang
On Fri, Apr 29, 2022 at 11:44 PM Anup Patel wrote:
> The mcountinhibit CSR is mandatory for priv spec v1
On Tue, May 3, 2022 at 5:35 PM Edgar E. Iglesias
wrote:
> On Tue, May 3, 2022 at 3:16 AM Frank Chang wrote:
>
>> On Mon, May 2, 2022 at 6:29 PM Edgar E. Iglesias <
>> edgar.igles...@gmail.com> wrote:
>>
>>> On Thu, Apr 28, 2022 at 5:43 PM wrote:
>>&
On Mon, May 2, 2022 at 6:29 PM Edgar E. Iglesias
wrote:
> On Thu, Apr 28, 2022 at 5:43 PM wrote:
>
>> From: Frank Chang
>>
>> Add Xilinx AXI CDMA model, which follows
>> AXI Central Direct Memory Access v4.1 spec:
>> https://docs.xilinx.com/v/u/en-US/pg034
On Sat, Apr 30, 2022 at 12:30 PM Anup Patel wrote:
> On Sat, Apr 30, 2022 at 8:39 AM Frank Chang
> wrote:
> >
> > Hi Anup,
> >
> > If we want to limit the generated ISA string to/after a specific
> privilege spec version.
> > Shouldn't we als
Reviewed-by: Frank Chang
On Fri, Apr 29, 2022 at 11:34 AM Anup Patel wrote:
> When hypervisor and VS CSRs are accessed from VS-mode or VU-mode,
> the riscv_csrrw_check() function should generate virtual instruction
> trap instead illegal instruction trap.
>
> Fixes: 533c91e8f22c
Reviewed-by: Frank Chang
On Fri, Apr 29, 2022 at 11:36 AM Anup Patel wrote:
> Currently, the [m|s]tval CSRs are set with trapping instruction encoding
> only for illegal instruction traps taken at the time of instruction
> decoding.
>
> In RISC-V world, a valid instructions
Reviewed-by: Frank Chang
On Fri, Apr 29, 2022 at 11:44 PM Anup Patel wrote:
> The mcountinhibit CSR is mandatory for priv spec v1.11 or higher. For
> implementation that don't want to implement can simply have a dummy
> mcountinhibit which always zero.
>
> Fixes: a4b2fa433125
in which the
extension is supported.
(This is possible if user specifies the privileged spec version through the
command line.)
The ISA string therefore won't include the enabled extension.
Regards,
Frank Chang
On Fri, Apr 29, 2022 at 11:49 PM Anup Patel wrote:
> Most of the multi-let
Reviewed-by: Frank Chang
On Fri, Apr 29, 2022 at 11:41 PM Anup Patel wrote:
> The riscv_cpu_realize() sets priv spec verion to v1.12 when it is
> when "env->priv_ver == 0" (i.e. default v1.10) because the enum
> value of priv spec v1.10 is zero.
>
> Due to above
From: Frank Chang
Add Xilinx AXI CDMA model, which follows
AXI Central Direct Memory Access v4.1 spec:
https://docs.xilinx.com/v/u/en-US/pg034-axi-cdma
Supports both Simple DMA and Scatter Gather modes.
Signed-off-by: Frank Chang
Reviewed-by: Jim Shu
---
hw/dma/meson.build
From: Frank Chang
Allow user to set core's marchid, mvendorid, mipid CSRs through
-cpu command line option.
The default values of marchid and mipid are built with QEMU's version
numbers.
Signed-off-by: Frank Chang
Reviewed-by: Jim Shu
Reviewed-by: Alistair Francis
Reviewed-by: Bin Meng
On Fri, Apr 22, 2022 at 8:48 AM Alistair Francis
wrote:
> On Thu, Apr 21, 2022 at 12:17 PM Bin Meng wrote:
> >
> > On Wed, Apr 20, 2022 at 5:57 PM wrote:
> > >
> > > From: Frank Chang
> > >
> > > Allow user to set core's marchid, mvendorid
From: Frank Chang
Allow user to set core's marchid, mvendorid, mipid CSRs through
-cpu command line option.
The default values of marchid and mipid are built with QEMU's version
numbers.
Signed-off-by: Frank Chang
Reviewed-by: Jim Shu
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c
On Tue, Apr 19, 2022 at 2:00 PM Frank Chang wrote:
> On Tue, Apr 19, 2022 at 1:27 PM Anup Patel
> wrote:
>
>> On Tue, Apr 19, 2022 at 10:52 AM Alistair Francis
>> wrote:
>> >
>> > On Fri, Apr 15, 2022 at 7:37 PM wrote:
>> > >
>> >
From: Frank Chang
RISC-V privilege spec defines that mtime is exposed as a memory-mapped
machine-mode read-write register. However, as QEMU uses host monotonic
timer as timer source, this makes mtime to be read-only in RISC-V
ACLINT.
This patch makes mtime to be writable by recording the time
From: Jim Shu
This commit implements reset function of all ACLINT devices.
ACLINT device reset will clear MTIME and MSIP register to 0.
Depend on RISC-V ACLINT spec v1.0-rc4:
https://github.com/riscv/riscv-aclint/blob/v1.0-rc4/riscv-aclint.adoc
Signed-off-by: Jim Shu
Reviewed-by: Frank Chang
From: Frank Chang
RISC-V privilege spec defines that:
* In RV32, memory-mapped writes to mtimecmp modify only one 32-bit part
of the register.
* For RV64, naturally aligned 64-bit memory accesses to the mtime and
mtimecmp registers are additionally supported and are atomic.
It's possible
From: Frank Chang
If device's MemoryRegion doesn't have .impl.[min|max]_access_size
declaration, the default access_size_min would be 1 byte and
access_size_max would be 4 bytes (see: softmmu/memory.c).
This will cause a 64-bit memory access to ACLINT to be splitted into
two 32-bit memory
From: Frank Chang
This patchset makes ACLINT mtime to be writable as RISC-V privilege
spec defines that mtime is exposed as a memory-mapped machine-mode
read-write register. Also, mtimecmp and mtime should be 32/64-bit memory
accessible registers. ACLINT reset function is also added, which
On Wed, Apr 20, 2022 at 3:47 PM Alistair Francis
wrote:
> On Tue, Apr 19, 2022 at 5:04 PM Frank Chang
> wrote:
> >
> > On Tue, Apr 19, 2022 at 2:00 PM Frank Chang
> wrote:
> >>
> >> On Tue, Apr 19, 2022 at 1:27 PM Anup Patel
> wrote:
> >&g
On Wed, Apr 20, 2022 at 3:42 PM Alistair Francis
wrote:
> On Tue, Apr 19, 2022 at 7:10 PM wrote:
> >
> > From: Frank Chang
> >
> > RISC-V privilege spec defines that mtime is exposed as a memory-mapped
> > machine-mode read-write register. However, as Q
From: Jim Shu
This commit implements reset function of all ACLINT devices.
ACLINT device reset will clear MTIME and MSIP register to 0.
Depend on RISC-V ACLINT spec v1.0-rc4:
https://github.com/riscv/riscv-aclint/blob/v1.0-rc4/riscv-aclint.adoc
Signed-off-by: Jim Shu
Reviewed-by: Frank Chang
From: Frank Chang
This patchset makes ACLINT mtime to be writable as RISC-V privilege
spec defines that mtime is exposed as a memory-mapped machine-mode
read-write register. Also, mtimecmp and mtime should be 32/64-bit memory
accessible registers. ACLINT reset function is also added, which
From: Frank Chang
RISC-V privilege spec defines that:
* In RV32, memory-mapped writes to mtimecmp modify only one 32-bit part
of the register.
* For RV64, naturally aligned 64-bit memory accesses to the mtime and
mtimecmp registers are additionally supported and are atomic.
It's possible
From: Frank Chang
RISC-V privilege spec defines that mtime is exposed as a memory-mapped
machine-mode read-write register. However, as QEMU uses host monotonic
timer as timer source, this makes mtime to be read-only in RISC-V
ACLINT.
This patch makes mtime to be writable by recording the time
From: Frank Chang
If device's MemoryRegion doesn't have .impl.[min|max]_access_size
declaration, the default access_size_min would be 1 byte and
access_size_max would be 4 bytes (see: softmmu/memory.c).
This will cause a 64-bit memory access to ACLINT to be splitted into
two 32-bit memory
On Tue, Apr 19, 2022 at 2:00 PM Frank Chang wrote:
> On Tue, Apr 19, 2022 at 1:27 PM Anup Patel
> wrote:
>
>> On Tue, Apr 19, 2022 at 10:52 AM Alistair Francis
>> wrote:
>> >
>> > On Fri, Apr 15, 2022 at 7:37 PM wrote:
>> > >
>> >
On Tue, Apr 19, 2022 at 1:27 PM Anup Patel wrote:
> On Tue, Apr 19, 2022 at 10:52 AM Alistair Francis
> wrote:
> >
> > On Fri, Apr 15, 2022 at 7:37 PM wrote:
> > >
> > > From: Frank Chang
> > >
> > > Allow user to set core's marchid,
From: Frank Chang
Allow user to set core's marchid, mvendorid, mipid CSRs through
-cpu command line option.
Signed-off-by: Frank Chang
Reviewed-by: Jim Shu
---
target/riscv/cpu.c | 4
target/riscv/cpu.h | 4
target/riscv/csr.c | 38 ++
3 files
",
> + "riscv,none");
> +}
> name = riscv_isa_string(>soc[socket].harts[cpu]);
> qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name);
> g_free(name);
> --
> 2.35.1
>
>
>
Reviewed-by: Frank Chang
letter_exts[] = "IEMAFDQLCBJTPVNH";
>
> What about K?
>
> Why not use IEMAFDQCBKJTPVNH instead?
>
> Alistair
>
The RISC-V ISA Manual (version 20191213) is quite old.
Where "L" was not removed and "K" was not introduced.
It seems Unprivileged spec is not
Hi Tomasz,
Could you please send this patchset to qemu-ri...@nongnu.org, too?
Regards,
Frank Chang
On Thu, Mar 17, 2022 at 6:24 AM Tomasz Jeznach
wrote:
> This is the series of patches to introduce RISC-V IOMMU emulation in QEMU.
>
> The Rivos IOMMU device implementation is based o
notifier:
4576704: arm/boot: split load_dtb() from arm_load_kernel()
ac9d32e: hw/arm/boot: arm_load_kernel implemented as a machine init done
notifier
Regards,
Frank Chang
On Thu, Mar 17, 2022 at 6:24 AM Tomasz Jeznach
wrote:
> Enable rivos-iommu device support in riscv:virt machine emulat
Reviewed-by: Frank Chang
On Fri, Mar 25, 2022 at 5:00 PM Weiwei Li wrote:
> for some cases, scale is always equal or less than 0, since lmul is not
> larger than 3
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
> ---
> target/riscv/insn_trans/trans_rvv.c.
Reviewed-by: Frank Chang
On Fri, Mar 25, 2022 at 5:00 PM Weiwei Li wrote:
> LEN is not used for GEN_VEXT_VMV_WHOLE macro, so vmvr.v can share
> the same helper
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
> ---
> target/riscv/helper.h
60 ++
> 1 file changed, 60 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index ddda4906ffb7..937ccdda997b 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -34,6 +34,11 @@
>
> /* RISC-V C
t; +new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL);
> +g_free(old);
> +old = new;
> +}
> +}
> +
> +*isa_str = new;
> +}
> +
> char *riscv_isa_string(RISCVCPU *cpu)
> {
> int i;
> @@ -910,6 +969,7 @@ char *riscv_isa_string(RISCVCPU *cpu)
> }
> }
> *p = '\0';
> +riscv_isa_string_ext(cpu, _str, maxlen);
> return isa_str;
> }
>
> --
> 2.25.1
>
>
>
Reviewed-by: Frank Chang
IP (1 << IRQ_S_GEXT)
> +#define MIP_LCOFIP (1 << IRQ_PMU_OVF)
>
> /* sip masks */
> #define SIP_SSIP MIP_SSIP
> #define SIP_STIP MIP_STIP
> #define SIP_SEIP
de "exec/exec-all.h"
> #include "tcg/tcg-op.h"
> #include "trace.h"
> #include "semihosting/common-semi.h"
> +#include "cpu.h"
>
Redundant: #include "cpu.h"
Regards,
Frank Chang
> +#include "cpu_bits.h"
h
> },
> +[CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> +[CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> +[CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> +[CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> +[CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> +[CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> +[CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> +[CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> +[CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> +[CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> +[CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> +[CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> +[CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> +[CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> +[CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> +[CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> +[CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> #endif /* !CONFIG_USER_ONLY */
> };
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index 2a48bcf81d3d..d706a97e65c8 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -300,6 +300,9 @@ const VMStateDescription vmstate_riscv_cpu = {
> VMSTATE_UINTTL(env.scounteren, RISCVCPU),
> VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
> VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU),
> +VMSTATE_UINTTL_ARRAY(env.mhpmcounter_val, RISCVCPU,
> RV_MAX_MHPMCOUNTERS),
> +VMSTATE_UINTTL_ARRAY(env.mhpmcounterh_val, RISCVCPU,
> RV_MAX_MHPMCOUNTERS),
> +VMSTATE_UINTTL_ARRAY(env.mhpmevent_val, RISCVCPU,
> RV_MAX_MHPMEVENTS),
> VMSTATE_UINTTL(env.sscratch, RISCVCPU),
> VMSTATE_UINTTL(env.mscratch, RISCVCPU),
> VMSTATE_UINT64(env.mfromhost, RISCVCPU),
> --
> 2.30.2
>
>
>
Hi Atish,
I encountered the compilation error when compiling user-mode QEMU
checked out from the branch in your repo:
error: ‘CPURISCVState {aka struct CPURISCVState}’ has no member named
‘mhpmevent_val’
error: ‘CPURISCVState {aka struct CPURISCVState}’ has no member named
‘mhpmeventh_val’
error: ‘CPURISCVState {aka struct CPURISCVState}’ has no member named
‘pmu_ctrs’
error: ‘CPURISCVState {aka struct CPURISCVState}’ has no member named ‘priv’
error: ‘CPURISCVState {aka struct CPURISCVState}’ has no member named
‘mcounteren’
Also, some functions are defined but not used in user-mode QEMU:
error: ‘read_scountovf’ defined but not used [-Werror=unused-function]
error: ‘write_mhpmcounterh’ defined but not used [-Werror=unused-function]
error: ‘write_mhpmcounter’ defined but not used [-Werror=unused-function]
... etc
I think you need to add the #if !defined(CONFIG_USER_ONLY) macros
to prevent using the variables which are available only in system-mode QEMU
and excluding the functions which are called only in system-mode QEMU.
Regards,
Frank Chang
On Fri, Mar 11, 2022 at 2:42 AM Atish Kumar Patra
wrote:
> On Wed, Mar 9, 2022 at 5:47 AM Frank Chang wrote:
> >
> > Atish Patra 於 2022年3月9日 週三 上午8:53寫道：
> >>
> >> The Linux kernel parses the ISA extensions from "riscv,isa" DT
> >> pr
ot;,
> TARGET_LONG_BITS);
> -for (i = 0; i < sizeof(riscv_exts); i++) {
> -if (cpu->env.misa_ext & RV(riscv_exts[i])) {
> -*p++ = qemu_tolower(riscv_exts[i]);
> +for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) {
> +if (cp
Also, I think "Zifencei" and "Zicsr" should also be covered as well,
and all extensions should follow the order defined in Table 28.11:
https://github.com/riscv/riscv-isa-manual/blob/master/src/naming.tex#L141
"The table also defines the canonical order in which extension nam
;does not permit any"-part is wrong, therefore we should raise a
> store page fault.
>
> In fact, I can't predict what will happen, because the code in
> target/riscv/cpu_helper.c does
> not really prioritize page faults or PMP faults. it returns one of them,
> once they are enco
Typo in patch title:
s/extenstion/extension/g
Regards,
Frank Chang
On Sat, Feb 26, 2022 at 3:45 PM Frank Chang wrote:
>
>
> Atish Patra 於 2022年2月23日 週三 上午6:39寫道：
>
>> The Linux kernel parses the ISA extensions from "riscv,isa" DT
>> property. It used to
On Sun, Mar 6, 2022 at 2:12 PM Atish Kumar Patra
wrote:
>
>
> On Sat, Mar 5, 2022 at 9:36 PM Frank Chang wrote:
>
>> On Sun, Mar 6, 2022 at 7:42 AM Atish Kumar Patra
>> wrote:
>>
>>>
>>>
>>> On Sat, Mar 5, 2022 at 10:05 AM Heiko Stueb
On Sun, Mar 6, 2022 at 7:42 AM Atish Kumar Patra
wrote:
>
>
> On Sat, Mar 5, 2022 at 10:05 AM Heiko Stuebner wrote:
>
>> Hi,
>>
>> Am Donnerstag, 3. März 2022, 19:58:38 CET schrieb Atish Patra:
>> > On Fri, Feb 25, 2022 at 11:46 PM Frank Chang
>> w
},
> +{ "svinval", cpu->cfg.ext_svinval },
> +{ "svnapot", cpu->cfg.ext_svnapot },
>
We still have other sub-extensions, e.g. Zfh, Zba, Zbb, Zbc, Zbs... etc.
Do you mind adding them as well?
Also, I think the order of ISA strings should be alp
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