On Fri, Apr 26, 2024 at 04:55:55PM +0100, Jonathan Cameron wrote:
> On Wed, 24 Apr 2024 10:33:33 -0700
> Ira Weiny wrote:
>
> > Markus Armbruster wrote:
> > > nifan@gmail.com writes:
> > >
> > > > From: Fan Ni
> > > >
> > > > Since fabric manager emulation is not supported yet, the
On Mon, Apr 22, 2024 at 01:04:48PM +0100, Jonathan Cameron wrote:
> On Sat, 20 Apr 2024 16:35:46 -0400
> Gregory Price wrote:
>
> > On Fri, Apr 19, 2024 at 11:43:14AM -0700, fan wrote:
> > > On Fri, Apr 19, 2024 at 02:24:36PM -0400, Gregory Price wrote:
> > &g
On Fri, Apr 19, 2024 at 11:43:14AM -0700, fan wrote:
> On Fri, Apr 19, 2024 at 02:24:36PM -0400, Gregory Price wrote:
> >
> > added review to all patches, will hopefully be able to add a Tested-by
> > tag early next week, along with a v1 RFC for MHD bit-tracking.
> >
&
On Thu, Apr 18, 2024 at 04:10:51PM -0700, nifan@gmail.com wrote:
> A git tree of this series can be found here (with one extra commit on top
> for printing out accepted/pending extent list):
> https://github.com/moking/qemu/tree/dcd-v7
>
> v6->v7:
>
> 1. Fixed the dvsec range register issue
the change, we relax the constraints. As long as the DPA range of
> the extent is covered by accepted extents, we allow the release.
>
> Reviewed-by: Jonathan Cameron
> Signed-off-by: Fan Ni
> ---
> hw/mem/cxl_type3.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(
) in the device, the release can be
> performed.
>
> Signed-off-by: Fan Ni
> ---
> hw/cxl/cxl-mailbox-utils.c | 21 -
> 1 file changed, 8 insertions(+), 13 deletions(-)
>
Hmmm. This will complicate MHD accounting, but it looks ok to me as-is.
Reviewed-b
--
> hw/cxl/cxl-mailbox-utils.c | 394
> hw/mem/cxl_type3.c | 11 +
> include/hw/cxl/cxl_device.h | 4 +
> 3 files changed, 409 insertions(+)
>
Reviewed-by: Gregory Price
> qapi/cxl.json | 69
> 6 files changed, 489 insertions(+), 13 deletions(-)
>
Reviewed-by: Gregory Price
ude/hw/cxl/cxl_device.h | 8 ++
> 3 files changed, 160 insertions(+), 36 deletions(-)
>
A couple general comments in line for discussion, but patch looks good
otherwise. Notes are mostly on improvements we could make that should
not block this patch.
Reviewed-by: Gregory Price
>
meron
> Signed-off-by: Fan Ni
> ---
> hw/cxl/cxl-mailbox-utils.c | 3 ++
> hw/mem/cxl_type3.c | 76 +
> include/hw/cxl/cxl_device.h | 7
> 3 files changed, 86 insertions(+)
>
Reviewed-by: Gregory Price
-by: Jonathan Cameron
> Signed-off-by: Fan Ni
> ---
> hw/cxl/cxl-mailbox-utils.c | 73 -
> hw/mem/cxl_type3.c | 1 +
> include/hw/cxl/cxl_device.h | 22 +++
> 3 files changed, 95 insertions(+), 1 deletion(-)
>
Reviewed-by: Gregory Price
> echo $region > /sys/bus/cxl/drivers/cxl_region/bind
>
> Reviewed-by: Jonathan Cameron
> Signed-off-by: Fan Ni
> ---
> hw/mem/cxl_type3.c | 49 ++
> 1 file changed, 49 insertions(+)
>
Reviewed-by: Gregory Price
.
>
> Reviewed-by: Jonathan Cameron
> Signed-off-by: Fan Ni
> ---
> hw/cxl/cxl-mailbox-utils.c | 4 ++--
> hw/mem/cxl_type3.c | 8
> include/hw/cxl/cxl_device.h | 2 +-
> 3 files changed, 7 insertions(+), 7 deletions(-)
>
Reviewed-by: Gregory Price
mmand per
> specification.
>
> Reviewed-by: Jonathan Cameron
> Signed-off-by: Fan Ni
> ---
> hw/cxl/cxl-mailbox-utils.c | 96 +
> include/hw/cxl/cxl_device.h | 16 +++
> 2 files changed, 112 insertions(+)
>
Reviewed-by: Gregory Price
the output payload for the host to get the info.
>
> Reviewed-by: Jonathan Cameron
> Signed-off-by: Fan Ni
> ---
> hw/cxl/cxl-mailbox-utils.c | 5 -
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
Reviewed-by: Gregory Price
c
> +++ b/hw/mem/cxl_type3.c
> @@ -44,7 +44,7 @@ enum {
> };
Reviewed-by: Gregory Price
On Wed, Apr 17, 2024 at 12:59:51PM +0100, Jonathan Cameron wrote:
> On Tue, 16 Apr 2024 09:37:09 -0700
> fan wrote:
>
> >
> > Currently, we do not allow releasing an extent when it is still pending,
> > which aligns with the case you mentioned above "not release for reuse", I
> > think.
> > Can
On Tue, Apr 16, 2024 at 03:58:22PM +0100, Jonathan Cameron wrote:
> On Mon, 15 Apr 2024 13:06:04 -0700
> fan wrote:
>
> > From ce75be83e915fbc4dd6e489f976665b81174002b Mon Sep 17 00:00:00 2001
> > From: Fan Ni
> > Date: Tue, 20 Feb 2024 09:48:31 -0800
> > Subject: [PATCH 09/13] hw/cxl/events:
On Tue, Apr 16, 2024 at 04:00:56PM +0100, Jonathan Cameron wrote:
> On Mon, 15 Apr 2024 10:37:00 -0700
> fan wrote:
>
> > On Fri, Apr 12, 2024 at 06:54:42PM -0400, Gregory Price wrote:
> > > On Mon, Mar 25, 2024 at 12:02:28PM -0700, nifan@gmail.com wrote
On Mon, Mar 25, 2024 at 12:02:28PM -0700, nifan@gmail.com wrote:
> From: Fan Ni
>
> All dpa ranges in the DC regions are invalid to access until an extent
> covering the range has been added. Add a bitmap for each region to
> record whether a DC block in the region has been backed by DC
gt; and for which the second page turned out to be mmio.
I love when I get to say this: I knew it! :D
https://lore.kernel.org/qemu-devel/zbvvb4j+ahkln...@memverge.com/
Great fix, much appreciate the effort!
Reviewed-by: Gregory Price
> In this case we
> truncate the block, and the p
On Fri, Apr 05, 2024 at 06:44:52PM +0100, Jonathan Cameron wrote:
> On Fri, 5 Apr 2024 12:07:45 -0400
> Gregory Price wrote:
>
> > 3. (C) Upon Device receiving Release Dynamic Capacity Request
> >a. check for a pending release request. If exists, error.
>
> Not
On Fri, Apr 05, 2024 at 01:27:19PM +0100, Jonathan Cameron wrote:
> On Wed, 3 Apr 2024 14:16:25 -0400
> Gregory Price wrote:
>
> A few follow up comments.
>
> >
> > > +error_setg(errp, "no valid extents to send to process");
> > > +
On Mon, Mar 25, 2024 at 12:02:27PM -0700, nifan@gmail.com wrote:
> From: Fan Ni
>
> To simulate FM functionalities for initiating Dynamic Capacity Add
> (Opcode 5604h) and Dynamic Capacity Release (Opcode 5605h) as in CXL spec
> r3.1 7.6.7.6.5 and 7.6.7.6.6, we implemented two QMP interfaces
we could
instead add an explicit `initialize_state=true` option to the
device and ditch the extra program.
Signed-off-by: Gregory Price
---
hw/cxl/Kconfig| 1 +
hw/cxl/meson.build| 1 +
hw/cxl/mhsld/.gitignore | 1 +
hw/cxl/mhsld/Kconfig | 4 +
hw/cxl/mh
On Thu, Feb 29, 2024 at 04:25:44PM +, Jonathan Cameron wrote:
> If qemu is started with a proximity node containing CPUs alone,
> it will provide one of these structures to say memory in this
> node is directly connected to itself.
>
> This description is arguably pointless even if there is
On Fri, Feb 02, 2024 at 04:33:20PM +, Peter Maydell wrote:
> On Fri, 2 Feb 2024 at 16:26, Jonathan Cameron
> wrote:
> > #7 0x55ab1929 in bql_lock_impl (file=0x56049122
> > "../../accel/tcg/cputlb.c", line=2033) at ../../system/cpus.c:524
> > #8 bql_lock_impl
On Thu, Feb 01, 2024 at 06:04:26PM +, Peter Maydell wrote:
> On Thu, 1 Feb 2024 at 17:25, Alex Bennée wrote:
> >
> > Jonathan Cameron writes:
> > >> > #21 0x55ca3e5d in do_st8_mmu (cpu=0x578e0cb0, addr=23937,
> > >> > val=18386491784638059520, oi=6, ra=140736029817822) at
> >
On Thu, Feb 01, 2024 at 05:07:31PM +, Peter Maydell wrote:
> On Thu, 1 Feb 2024 at 17:04, Gregory Price wrote:
> >
> > On Thu, Feb 01, 2024 at 04:45:30PM +, Alex Bennée wrote:
>
> > > No thats different - we are actually writing to the MMIO region here
On Thu, Feb 01, 2024 at 04:45:30PM +, Alex Bennée wrote:
> Jonathan Cameron writes:
>
> > On Thu, 1 Feb 2024 16:00:56 +
> > Peter Maydell wrote:
> >
> >> On Thu, 1 Feb 2024 at 15:17, Alex Bennée wrote:
> >> >
> >> > Peter Maydell writes:
> >> > > So, that looks like:
> >> > > * we
On Tue, Jan 09, 2024 at 01:27:28PM -0800, Hao Xiang wrote:
> On Tue, Jan 9, 2024 at 11:58 AM Gregory Price
> wrote:
> >
> > If you drop this line:
> >
> > -numa node,memdev=vmem0,nodeid=1
>
> We tried this as well and it works after going through the cxl
On Tue, Jan 09, 2024 at 11:33:04AM -0800, Hao Xiang wrote:
> On Mon, Jan 8, 2024 at 5:13 PM Gregory Price
> wrote:
>
> Sounds like the technical details are explained on the other thread.
> From what I understand now, if we don't go through a complex CXL
> setup, it w
On Mon, Jan 08, 2024 at 05:05:38PM -0800, Hao Xiang wrote:
> On Mon, Jan 8, 2024 at 2:47 PM Hao Xiang wrote:
> >
> > On Mon, Jan 8, 2024 at 9:15 AM Gregory Price
> > wrote:
> > >
> > > On Fri, Jan 05, 2024 at 09:59:19PM -0800, Hao Xiang wrote:
> &g
On Fri, Jan 05, 2024 at 09:59:19PM -0800, Hao Xiang wrote:
> On Wed, Jan 3, 2024 at 1:56 PM Gregory Price
> wrote:
> >
> > For a variety of performance reasons, this will not work the way you
> > want it to. You are essentially telling QEMU to map the vmem0 into
On Sun, Dec 31, 2023 at 11:53:15PM -0800, Ho-Ren (Jack) Chuang wrote:
> Introduce a new configuration option 'host-mem-type=' in the
> '-object memory-backend-ram', allowing users to specify
> from which type of memory to allocate.
>
> Users can specify 'cxlram' as an argument, and QEMU will then
er.
To save some list spam, I can't say i've reviewed and tested the entire
set, but this patch series to help model the Niagara work so please add
my tags as appropriate to the above.
Reviewed-by: Gregory Price
Tested-by: Gregory Price
~Gregory
Niagara uses which presently limits its compatibility to
linux hosts. Change build to only build it on linux.
Add Kconfig file for skhynix directory, and make niagara depend on
CXL_MEM_DEVICE and LINUX. Add an explicit flag for niagara.
Signed-off-by: Gregory Price
---
hw/cxl/Kconfig
Niagara uses which presently limits its compatibility to
linux hosts. Change build to only build it on linux.
Add Kconfig file for skhynix directory, and make niagara depend on
CXL_MEM_DEVICE. Add an explicit flag for niagara.
Signed-off-by: Gregory Price
---
hw/cxl/Kconfig
On Wed, Sep 20, 2023 at 01:46:18PM +0100, Jonathan Cameron wrote:
> On Mon, 18 Sep 2023 13:36:56 -0400
> Gregory Price wrote:
>
> > Create a new device to emulate the SK hynix Niagara MHSLD platform.
> >
>
> Hi Gregory,
>
> Seems this doesn't drop in
of sections
section_size : size of a section in 128mb increments
shmid : shmid produced by ipcmk
Example:
$shmid1=ipcmk -M 131072
./init_niagara 4 32 1 $shmid1
Signed-off-by: Gregory Price
Signed-off-by: Junhee Ryu
Signed-off-by: Kwangjin Ko
---
hw/cxl/Kconfig
v4 update: Kconfig and meson fixes
Since Niagara uses , it presently can only be built
for linux. Also addings missing Kconfig files and options
to turn it off, and turns it off by default if VENDOR or
CXL_MEM_DEVICE are turned off.
Gregory Price (1):
cxl/vendor: SK hynix Niagara Multi-Headed
For multi-headed type 3 devices, this command reports logical device
mappings for each head. Implement a callback which can be
initialized by MHD devices to field these commands.
Reports "unsupported" if the command is called but the callback is
not implemented.
Signed-off-by: Gre
When memory accesses are made, some MHSLD's would validate the address
is within the scope of allocated sections. To do this, the base device
must call an optional function set by inherited devices.
Signed-off-by: Gregory Price
---
hw/mem/cxl_type3.c | 15 +++
include/hw
of sections
section_size : size of a section in 128mb increments
shmid : shmid produced by ipcmk
Example:
$shmid1=ipcmk -M 131072
./init_niagara 4 32 1 $shmid1
Signed-off-by: Gregory Price
---
hw/cxl/Kconfig | 4 +
hw/cxl/meson.build
For devices built on top of ct3, we need the init, realize, and
exit functions exposed to correctly start up and tear down.
Signed-off-by: Gregory Price
---
hw/mem/cxl_type3.c | 6 +++---
include/hw/cxl/cxl_device.h | 4
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git
Preparation for allowing devices to define their own CCI commands
Signed-off-by: Gregory Price
---
hw/cxl/cxl-mailbox-utils.c | 30 +-
include/hw/cxl/cxl_mailbox.h | 18 ++
2 files changed, 31 insertions(+), 17 deletions(-)
create mode 100644
Call CXL_TYPE3 once at top of function to avoid multiple invocations.
Signed-off-by: Gregory Price
---
hw/mem/cxl_type3.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index fd9d134d46..80d596ee10 100644
--- a/hw/mem
CXL commands to be passed through
the mailbox driver, so users should enable
`CONFIG_CXL_MEM_RAW_COMMANDS=y` on the kernel of their QEMU instance
if they wish to test it.
Signed-off-by: Gregory Price
Gregory Price (6):
cxl/mailbox: move mailbox effect definitions to a header
cxl/type3
On Wed, Sep 06, 2023 at 02:04:45PM +0100, Jonathan Cameron wrote:
> On Thu, 31 Aug 2023 21:29:14 -0400
> Gregory Price wrote:
>
> Hi Gregory,
>
> Some comments inline, but I'm happy to add this to my staging tree in the
> meantime
> as it stands (might be a few days u
On Tue, Sep 05, 2023 at 11:04:56AM +0200, Philippe Mathieu-Daudé wrote:
> On 1/9/23 03:29, Gregory Price wrote:
> > v2:
> > - 5 patch series, first 4 are pull-aheads that can be merged separately
> >
> > This patch set includes an emulation of the SK hynix Niagara MHS
On Tue, Sep 05, 2023 at 10:59:15AM +0200, Philippe Mathieu-Daudé wrote:
> Hi Gregory,
>
> On 1/9/23 03:29, Gregory Price wrote:
> > For devices built on top of ct3, we need the init, realize, and
> > exit functions exposed to correctly start up and tear down.
>
> Yo
On Mon, Sep 04, 2023 at 06:02:14PM +0100, Jonathan Cameron wrote:
> On Thu, 31 Aug 2023 21:29:13 -0400
> Gregory Price wrote:
>
> > When memory accesses are made, some MHSLD's would validate the address
> > is within the scope of allocated sections. To do this, the base
When memory accesses are made, some MHSLD's would validate the address
is within the scope of allocated sections. To do this, the base device
must call an optional function set by inherited devices.
Signed-off-by: Gregory Price
---
hw/mem/cxl_type3.c | 15 +++
include/hw
Preparation for allowing devices to define their own CCI commands
Signed-off-by: Gregory Price
---
hw/cxl/cxl-mailbox-utils.c | 35 +++
include/hw/cxl/cxl_mailbox.h | 18 ++
2 files changed, 37 insertions(+), 16 deletions(-)
create mode 100644
allowing raw CXL commands to be passed through the mailbox
driver, so users should enable `CONFIG_CXL_MEM_RAW_COMMANDS=y` on the
kernel of their QEMU instance if they wish to test it
Signed-off-by: Gregory Price
Gregory Price (5):
cxl/mailbox: move mailbox effect definitions to a header
cxl/type3
Call CXL_TYPE3 once at top of function to avoid multiple invocations.
Signed-off-by: Gregory Price
---
hw/mem/cxl_type3.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index fd9d134d46..80d596ee10 100644
--- a/hw/mem
For devices built on top of ct3, we need the init, realize, and
exit functions exposed to correctly start up and tear down.
Signed-off-by: Gregory Price
---
hw/mem/cxl_type3.c | 8
include/hw/cxl/cxl_device.h | 5 +
2 files changed, 9 insertions(+), 4 deletions(-)
diff
of sections
section_size : size of a section in 128mb increments
shmid : shmid produced by ipcmk
Example:
$shmid1=ipcmk -M 131072
./init_niagara 4 32 1 $shmid1
Signed-off-by: Gregory Price
Signed-off-by: Junhee Ryu
Signed-off-by: Kwangjin Ko
---
hw/cxl/Kconfig
On Mon, Aug 07, 2023 at 03:56:09PM +0100, Jonathan Cameron wrote:
> On Fri, 21 Jul 2023 12:35:08 -0400
> Gregory Price wrote:
>
> > Implement the MHD GET_INFO cci command and add a shared memory
> > region to the type3 device to host the information.
> >
> > A
On Fri, Aug 04, 2023 at 05:36:23PM +0100, Jonathan Cameron wrote:
> On Tue, 25 Jul 2023 18:39:56 +
> Fan Ni wrote:
>
> > From: Fan Ni
> >
> > Add (file/memory backed) host backend, all the dynamic capacity regions
> > will share a single, large enough host backend. Set up address space for
On Fri, Aug 04, 2023 at 04:14:14PM +0100, Jonathan Cameron wrote:
> On Fri, 21 Jul 2023 12:35:06 -0400
> Gregory Price wrote:
>
> > This enables wrapper devices to customize the base device's CCI
> > (for example, with custom commands outside the specification)
> >
131072
./init_niagara 4 32 1 $shmid1
Signed-off-by: Gregory Price
Signed-off-by: Junhee Ryu
Signed-off-by: Kwangjin Ko
---
hw/cxl/Kconfig | 4 +
hw/cxl/meson.build | 2 +
hw/cxl/vendor/meson.build | 1 +
hw/cxl/vendor/skhynix
.targets.0=cxl.0,cxl-fmw.0.size=4G
Signed-off-by: Gregory Price
---
hw/cxl/cxl-mailbox-utils.c | 53 +
hw/mem/cxl_type3.c | 67 +
include/hw/cxl/cxl_device.h | 14
tools/cxl/cxl_mhd_init.c| 63
This allows devices to have fully customized CCIs, along with complex
devices where wrapper devices can override or add additional CCI
commands without having to replicate full command structures or
pollute a base device with every command that might ever be used.
Signed-off-by: Gregory Price
-by: Gregory Price
---
hw/cxl/cxl-mailbox-utils.c | 19 +++
include/hw/cxl/cxl_device.h | 2 ++
2 files changed, 21 insertions(+)
diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
index ddee3f1718..cad0cd0adb 100644
--- a/hw/cxl/cxl-mailbox-utils.c
+++ b/hw/cxl/cxl
-off-by: Gregory Price
Gregory Price (4):
cxl/mailbox: change CCI cmd set structure to be a member, not a
refernce
cxl/mailbox: interface to add CCI commands to an existing CCI
cxl/type3: minimum MHD cci support
cxl/vendor: SK hynix Niagara Multi-Headed SLD Device
hw/cxl/Kco
-by: Gregory Price
---
hw/cxl/cxl-mailbox-utils.c | 19 +++
include/hw/cxl/cxl_device.h| 2 ++
2 files changed, 21 insertions(+)
diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
index ddee3f1718..cad0cd0adb 100644
--- a/hw/cxl/cxl-mailbox-utils.c
+++ b
This allows devices to have fully customized CCIs, along with complex
devices where wrapper devices can override or add additional CCI
commands without having to replicate full command structures or
pollute a base device with every command that might ever be used.
Signed-off-by: Gregory Price
sizeof(struct CXL_MyCmdsClass),
.class_init = cxl_my_cmds_class_init,
.instance_size = sizeof(CXL_MyCmds_State),
.interfaces = (InterfaceInfo[]) {
{ INTERFACE_CXL_DEVICE },
{ INTERFACE_PCIE_DEVICE },
{}
},
};
Signed-off-by: Gregory Price
---
Gregory Price
On Thu, Jul 20, 2023 at 01:18:33PM +0100, Jonathan Cameron wrote:
> On Wed, 19 Jul 2023 14:49:07 -0400
> Gregory Price wrote:
>
> >
> > Maybe a dangerous suggestion. Right now the CCI's are static:
> >
> > static const struct cxl_cmd cxl_cmd_set[256][256]
&g
On Wed, Jul 19, 2023 at 09:19:47AM +0100, Jonathan Cameron wrote:
> On Tue, 18 Jul 2023 17:30:57 -0400
> Gregory Price wrote:
>
> > On Mon, Jul 17, 2023 at 06:16:39PM +0100, Jonathan Cameron wrote:
> > > @@ -397,8 +401,9 @@ struct CXLType3Dev {
> > &
Implement the MHD GET_INFO cci command and add a shared memory
region to the type3 device to host the information.
Add a helper program to initialize this shared memory region.
For now, limit the number of LD's to the number of heads. Later,
this limitation will need to be lifted for MH-MLDs.
On Mon, Jul 17, 2023 at 06:16:39PM +0100, Jonathan Cameron wrote:
> @@ -397,8 +401,9 @@ struct CXLType3Dev {
> AddressSpace hostpmem_as;
> CXLComponentState cxl_cstate;
> CXLDeviceState cxl_dstate;
> -CXLCCI cci;
> -
> +CXLCCI cci; /* Primary PCI mailbox CCI */
> +
On Fri, Jun 16, 2023 at 03:43:31PM +0800, Yuquan Wang wrote:
> Hi, Gregory
>
> There is one confusion about CXL in QEMU I hope to consult.
> If you have some time to look at this email, I would have better
> understanding of CXL
> emulation in QEMU.
>
> On docs/system/devices/cxl.rst ,
On Wed, May 17, 2023 at 03:18:59PM +0100, Jonathan Cameron wrote:
> >
> > i.e. an SLD does not require an FM-Owned LD for management, but an MHD,
> > MLD, and DCD all do (at least in theory).
>
> DCD 'might' though I don't think anything in the spec rules that you 'must'
> control the SLD/MLD
On Mon, May 15, 2023 at 05:18:07PM +0100, Jonathan Cameron wrote:
> On Tue, 21 Mar 2023 21:50:33 -0400
> Gregory Price wrote:
>
> >
> > Ambiguity #1:
> >
> > * An SLD contains 1 Logical Device.
> > * An MH-SLD presents multiple SLDs, one per head.
> &
dr
> host_addr, uint64_t data,
> return MEMTX_OK;
> }
>
> -if (dpa_offset > int128_get64(mr->size)) {
> + if (dpa_offset > memory_region_size(mr)) {
> return MEMTX_OK;
> }
> return address_space_write(>hostmem_as, dpa_offset, attrs,
> --
> 2.37.2
>
lgtm
Reviewed-by: Gregory Price
Originally I was planning to kick this off with a patch set, but i've
decided my current prototype does not fit the extensibility requirements
to go from SLD to MH-SLD to MH-MLD.
So instead I'd like to kick off by just discussing the data structures
and laugh/cry a bit about some of the
Breaking this off into a separate thread for archival sake.
There's a bug with handling execution of instructions held in CXL
memory - specifically when an instruction crosses a page boundary.
The result of this is that type-3 devices cannot use KVM at all at the
moment, and require the
On Wed, Feb 15, 2023 at 10:03:27AM +, Jonathan Cameron wrote:
> On Tue, 14 Feb 2023 16:54:02 -0500
> Gregory Price wrote:
>
> > Just clarifying one thing: Even with the patch, KVM blows up.
> > Disabling KVM fixes this entirely. I haven't tested without KVM but
On Fri, Feb 17, 2023 at 04:16:17PM +, Jonathan Cameron via wrote:
> On Tue, 31 Jan 2023 16:38:47 +
> Jonathan Cameron via wrote:
>
> > From: Gregory Price
> >
> > This commit enables each CXL Type-3 device to contain one volatile
> > memory
On Fri, Feb 17, 2023 at 11:14:18AM +, Jonathan Cameron wrote:
> On Thu, 16 Feb 2023 15:52:31 -0500
> Gregory Price wrote:
>
> >
> > I agree, it's certainly "not pretty".
> >
> > I'd go so far as to call the baby ugly :]. Like i said: "
On Thu, Feb 16, 2023 at 06:00:57PM +, Jonathan Cameron wrote:
> On Wed, 15 Feb 2023 04:10:20 -0500
> Gregory Price wrote:
>
> > On Wed, Feb 15, 2023 at 03:18:54PM +, Jonathan Cameron via wrote:
> > > On Wed, 8 Feb 2023 16:28:44 -0600
> > > zhiting zhu
On Wed, Feb 15, 2023 at 03:18:54PM +, Jonathan Cameron via wrote:
> On Wed, 8 Feb 2023 16:28:44 -0600
> zhiting zhu wrote:
>
> > Hi,
> >
> > I saw a PoC:
> > https://lore.kernel.org/qemu-devel/20220525121422.3...@huawei.com/T/ to
> > implement memory pooling and fabric manager on qemu.
On Tue, Jan 31, 2023 at 04:38:47PM +, Jonathan Cameron wrote:
> From: Gregory Price
>
> This commit enables each CXL Type-3 device to contain one volatile
> memory region and one persistent region.
>
> ... snip ...
>
I have no objections to the changes made. I'll
On Tue, Jan 31, 2023 at 04:38:46PM +, Jonathan Cameron wrote:
> From: Gregory Price
>
> Defines are starting to exceed line length limits, align them for
> cleanliness before making modifications.
>
> Signed-off-by: Gregory Price
> Signed-off-by: Jonathan Cameron
>
Tested and reviewed this series (except my own patches, obviously).
Reviewed-by: Gregory Price
Tested-by: Gregory Price
On Mon, Jan 30, 2023 at 02:36:55PM +, Jonathan Cameron wrote:
> V3: Thanks to Michael Tsirkin
> - Update tests/data/acpi/q35/DSDT.cxl to reflect dr
On Mon, Jan 30, 2023 at 01:24:51PM +, Jonathan Cameron wrote:
>
> > diff --git a/tests/qtest/cxl-test.c b/tests/qtest/cxl-test.c
> > index e59ba22387..6893f54e28 100644
> > --- a/tests/qtest/cxl-test.c
> > +++ b/tests/qtest/cxl-test.c
> > @@ -40,32 +40,46 @@
> >"-device
On Mon, Jan 30, 2023 at 01:11:50PM +, Jonathan Cameron wrote:
> On Thu, 5 Jan 2023 14:38:07 +
> Jonathan Cameron wrote:
>
> > On Mon, 28 Nov 2022 10:01:56 -0500
> > Gregory Price wrote:
> >
> > > Defines are starting to exceed line length limits, ali
On Fri, Jan 20, 2023 at 02:41:05PM -0800, Dan Williams wrote:
>
> Which mode are you referring?
>
> The next steps for the kernel enabling relevant to this thread are:
>
> * ram region discovery (platform firmware or kexec established)
> * ram region creation
> * pmem region discovery (from
On Fri, Jan 20, 2023 at 09:38:13AM -0800, Dan Williams wrote:
> As it stands currently that dax device and the cxl device are not
> related since a default dax-device is loaded just based on the presence
> of an EFI_MEMORY_SP address range in the address map. With the new ram
> enabling that
On Thu, Jan 19, 2023 at 04:17:11PM +, Jonathan Cameron wrote:
>
> Whilst I still have no idea if this is the same problem, I have identified
> what goes wrong if there is a module probe ordering issue.
> https://elixir.bootlin.com/linux/v6.2-rc4/source/drivers/cxl/core/pmem.c#L306
>
>
On Thu, Jan 19, 2023 at 03:04:49PM +, Jonathan Cameron wrote:
> Gregory, would you mind checking if
> cxl_nvb is NULL here...
> https://elixir.bootlin.com/linux/v6.2-rc4/source/drivers/cxl/pmem.c#L67
> (printk before it is used should work).
>
> Might also be worth checking cxl_nvd and cxl_ds
On Thu, Jan 19, 2023 at 05:31:12PM +, Jonathan Cameron wrote:
> On Thu, 19 Jan 2023 12:15:45 -0500
> Gregory Price wrote:
>
> > Found a bug, not sure how we missed this, probably happed with rebasing
> > and some fixups. We're presently reporting the volatile region a
Found a bug, not sure how we missed this, probably happed with rebasing
and some fixups. We're presently reporting the volatile region as
non-volatile, 1 line patch.
Jonathan do you want a separate patch shipped or would you rather just
apply a fixup to the commit in your current branch?
diff
On Thu, Jan 19, 2023 at 06:48:11AM -0500, Michael S. Tsirkin wrote:
> >
> > I clearly need to run some more rests as not seen this issue (and I've
> > had a couple of reports of it now). I guess I never tend to be running
> > a completely clean tree on either side + testing is mostly on arm64
>
On Thu, Jan 19, 2023 at 10:19:46AM +, Jonathan Cameron wrote:
> Even if everything else worked, it will currently fail because of the
> issue with pass through decoders.
> (Kernel assumes always pass through for single rp, qemu assumes never
> pass through - both are valid under spec).
> Add
I apparently forgot an intro lol
I tested the DOE linux branch with the 2023-1-11 QEMU branch with both
volatile, non-volatile, and "legacy" (pre-my-patch) non-volatile mode.
1) *In volatile mode, there are no stack traces present (during boot*)
On Wed, Jan 18, 2023 at 02:22:08PM -050
1) No stack traces present
2) Device usage appears to work, but cxl-cli fails to create a region, i
haven't checked why yet (also tried ndctl-75, same results)
3) There seems to be some other regression with the cxl_pmem_init
routine, because I get a stack trace in this setup regardless of
On Fri, Jan 13, 2023 at 09:12:13AM +, Jonathan Cameron wrote:
>
> Just to check, are these different from the on stack problem you reported
> previously? Doesn't look like the fix for that has made it upstream yet.
>
> What kernel are you running?
>
>
The prior issue I saw was related to
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