On Tue, Oct 17, 2023 at 4:04 PM Nabih Estefan
wrote:
> From: Nabih Estefan Diaz
>
> - Add PCS Register check to npcm_gmac-test
>
> Signed-off-by: Nabih Estefan Diaz
>
Reviewed-by: Hao Wu
> ---
> tests/qtest/npcm_gmac-test.c | 134 ++
> can be received by the GMAC device. Without this it won't work
> with TAP NIC device.
>
> Signed-off-by: Hao Wu
>
> hw/net: Handle RX desc full in NPCM GMAC
>
> When RX descriptor list is full, it returns a DMA_STATUS for software to
> handle it. But there's no way to indi
On Tue, Oct 17, 2023 at 4:04 PM Nabih Estefan
wrote:
> From: Nabih Estefan Diaz
>
> - General GMAC Register handling
> - GMAC IRQ Handling
> - Added traces in some methods for debugging
> - Lots of declarations for accessing information on GMAC Descriptors
> (npcm_gmac.h file)
>
> NOTE: With
On Tue, Oct 17, 2023 at 4:04 PM Nabih Estefan
wrote:
> From: Nabih Estefan Diaz
>
> - Implemeted classes for GMAC Receive and Transmit Descriptors
> - Implemented Masks for said descriptors
>
> Signed-off-by: Nabih Estefan Diaz
>
Reviewed-by: Hao Wu
> -
You have an extra "\" in the title.
On Tue, Oct 17, 2023 at 4:04 PM Nabih Estefan
wrote:
> From: Nabih Estefan Diaz
>
> - Created qtest to check initialization of registers in GMAC Module.
> - Implemented test into Build File.
>
> Signed-off-by: Nabih Estefan Diaz
> ---
>
Is this related to this error?
https://lists.gnu.org/archive/html/qemu-devel/2023-09/msg04903.html
On Fri, Sep 22, 2023 at 11:14 AM Chris Rauer wrote:
> The counter register is only 24-bits and counts down. If the timer is
> running but the qtimer to reset it hasn't fired off yet, there is a
>
> Let me take a look at that. I suspect the timer is off by 1 tick due to
> some rounding errors.
Thank you. I'll include the change in the next patch set when I refactor
patch v4 (which might take a while.)
On Sat, Mar 25, 2023 at 4:56 PM Corey Minyard wrote:
> On Fri, Mar 24, 2023 at 04:08:59PM -0700, Hao Wu wrote:
> > From: Havard Skinnemoen
> >
> > This d
best
here. Maybe Corey can shed some light on this one? Thank you!
Best Regards,
On Mon, Mar 27, 2023 at 5:34 AM Cédric Le Goater wrote:
> Hello Hao,
>
> On 3/25/23 00:09, Hao Wu wrote:
> > This patch refactors the IPMI interface so that it can be used by both
> > the BM
, in READ_STATE, ipmi_kcs.c (core
side emulation) reads a message from BMC while npcm7xx_kcs.c
(BMC-side emulation) sends a message to the core.
Signed-off-by: Hao Wu
Reviewed-by: Tyrone Ting
---
docs/system/arm/nuvoton.rst | 1 -
hw/arm/npcm7xx.c | 10 +-
hw/ipmi/meson.build
.
Basically most of the message transaction are moved. The stuff remained
are basically hardware operations like handle_reset and handle_hw_op.
These stuff have different behaviors in core-side and BMC-side
emulation.
Signed-off-by: Hao Wu
---
hw/ipmi/ipmi_bmc_extern.c | 420
ent representing BMC side simulation.
(6) Appy the changes to the entire IPMI library.
Signed-off-by: Hao Wu
---
hw/acpi/ipmi.c | 4 +-
hw/ipmi/ipmi.c | 60 +
hw/ipmi/ipmi_bmc_extern.c | 67 ++
hw/ipmi/ipmi_bmc_sim.c |
with device ipmi-bmc-extern.
For more details of IPMI host device in BMC emulation, see
docs/specs/ipmi.rst.
Signed-off-by: Hao Wu
---
configs/devices/arm-softmmu/default.mak | 2 +
hw/ipmi/Kconfig | 4 +
hw/ipmi/ipmi_extern.c | 18 ++-
hw/ipmi
-by: Havard Skinnemoen
Signed-off-by: Hao Wu
---
docs/specs/ipmi.rst | 70 +
1 file changed, 70 insertions(+)
diff --git a/docs/specs/ipmi.rst b/docs/specs/ipmi.rst
index e0badc7f15..b06ad74728 100644
--- a/docs/specs/ipmi.rst
+++ b/docs/specs/ipmi.rst
other comments from Corey in the original
patch set.
Hao Wu (4):
hw/ipmi: Refactor IPMI interface
hw/ipmi: Take out common from ipmi_bmc_extern.c
hw/ipmi: Add an IPMI external host device
hw/ipmi: Add a KCS Module for NPCM7XX
Havard Skinnemoen (3):
docs: enable sphinx blockdiag
From: Havard Skinnemoen
This document is an attempt to briefly document the existing IPMI
emulation support on the main processor. It provides the necessary
background for the BMC-side IPMI emulation proposed by the next patch.
Signed-off-by: Havard Skinnemoen
Signed-off-by: Hao Wu
---
docs
From: Havard Skinnemoen
This allows use to add block diagrams in documentations,
such as the block diagram in docs/specs/impi.rst.
Signed-off-by: Havard Skinnemoen
Signed-off-by: Hao Wu
---
docs/conf.py | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/docs/conf.py b
Nuvoton's PSPI is a general purpose SPI module which enables
connections to SPI-based peripheral devices.
Signed-off-by: Hao Wu
Reviewed-by: Chris Rauer
Reviewed-by: Philippe Mathieu-Daude
---
MAINTAINERS| 6 +-
hw/ssi/meson.build | 2 +-
hw/ssi/npcm_pspi.c
Signed-off-by: Hao Wu
Reviewed-by: Titus Rwantare
Reviewed-by: Philippe Mathieu-Daude
---
docs/system/arm/nuvoton.rst | 2 +-
hw/arm/npcm7xx.c| 25 +++--
include/hw/arm/npcm7xx.h| 2 ++
3 files changed, 26 insertions(+), 3 deletions(-)
diff --git a/docs
Havard is no longer working on the Nuvoton systems for a while
and won't be able to do any work on it in the future. So I'll
take over maintaining the Nuvoton system from him.
Signed-off-by: Hao Wu
Acked-by: Havard Skinnemoen
Reviewed-by: Philippe Mathieu-Daude
---
MAINTAINERS | 2 +-
1 file
to match the datasheet.
-- Changes from v1 --
A few minor updates for npcm-pspi.c according to
Phillipe Mathieu-Daude's review.
Thanks!
Hao Wu (3):
MAINTAINERS: Add myself to maintainers and remove Havard
hw/ssi: Add Nuvoton PSPI Module
hw/arm: Attach PSPI module to NPCM7XX SoC
MAINTAINERS
Thanks for pointing that out. I'll send another version to fix that.
On Tue, Feb 7, 2023 at 11:48 PM Philippe Mathieu-Daudé
wrote:
> On 7/2/23 20:45, Hao Wu wrote:
> > Nuvoton's PSPI is a general purpose SPI module which enables
> > connections to SPI-based peripheral devices.
Havard is no longer working on the Nuvoton systems for a while
and won't be able to do any work on it in the future. So I'll
take over maintaining the Nuvoton system from him.
Signed-off-by: Hao Wu
Acked-by: Havard Skinnemoen
Reviewed-by: Philippe Mathieu-Daude
---
MAINTAINERS | 2 +-
1 file
Signed-off-by: Hao Wu
Reviewed-by: Titus Rwantare
Reviewed-by: Philippe Mathieu-Daude
---
docs/system/arm/nuvoton.rst | 2 +-
hw/arm/npcm7xx.c| 25 +++--
include/hw/arm/npcm7xx.h| 2 ++
3 files changed, 26 insertions(+), 3 deletions(-)
diff --git a/docs
-pspi.c according to
Phillipe Mathieu-Daude's review.
Thanks!
Hao Wu (3):
MAINTAINERS: Add myself to maintainers and remove Havard
hw/ssi: Add Nuvoton PSPI Module
hw/arm: Attach PSPI module to NPCM7XX SoC
MAINTAINERS | 8 +-
docs/system/arm/nuvoton.rst | 2 +-
hw/arm
Nuvoton's PSPI is a general purpose SPI module which enables
connections to SPI-based peripheral devices.
Signed-off-by: Hao Wu
Reviewed-by: Chris Rauer
Reviewed-by: Philippe Mathieu-Daude
---
MAINTAINERS| 6 +-
hw/ssi/meson.build | 2 +-
hw/ssi/npcm_pspi.c
On Tue, Feb 7, 2023 at 10:46 AM Hao Wu wrote:
> Thanks for your review!
>
> On Mon, Feb 6, 2023 at 11:13 PM Philippe Mathieu-Daudé
> wrote:
>
>> On 7/2/23 00:34, Hao Wu wrote:
>> > Nuvoton's PSPI is a general purpose SPI module which enables
>> > conn
Thanks for your review!
On Mon, Feb 6, 2023 at 11:13 PM Philippe Mathieu-Daudé
wrote:
> On 7/2/23 00:34, Hao Wu wrote:
> > Nuvoton's PSPI is a general purpose SPI module which enables
> > connections to SPI-based peripheral devices.
> >
> > Signed-off-by: Hao Wu
&
This patch set adds peripheral SPI (PSPI) modules
to NPCM7XX SoCs. These modules can be used to
connect any SPI peripheral devices to the SoC.
This module will also be used in the next generation
NPCM8XX SoCs which haven't been merged yet.
Thanks!
Hao Wu (3):
MAINTAINERS: Add myself
Signed-off-by: Hao Wu
Reviewed-by: Titus Rwantare
---
docs/system/arm/nuvoton.rst | 2 +-
hw/arm/npcm7xx.c| 25 +++--
include/hw/arm/npcm7xx.h| 2 ++
3 files changed, 26 insertions(+), 3 deletions(-)
diff --git a/docs/system/arm/nuvoton.rst b/docs/system
Nuvoton's PSPI is a general purpose SPI module which enables
connections to SPI-based peripheral devices.
Signed-off-by: Hao Wu
Reviewed-by: Chris Rauer
---
MAINTAINERS| 6 +-
hw/ssi/meson.build | 2 +-
hw/ssi/npcm_pspi.c | 216
Havard is no longer working on the Nuvoton systems for a while
and won't be able to do any work on it in the future. So I'll
take over maintaining the Nuvoton system from him.
Signed-off-by: Hao Wu
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b
Hi,
It seems like this patch set is reviewed but never merged. Who should take
this patch set? What are our next steps for them?
Thanks!
On Mon, Jan 31, 2022 at 2:29 PM Patrick Venture wrote:
> From: Hao Wu
>
> SB Temperature Sensor Interface (SB-TSI) is an SMBus compatible
&g
On Mon, Oct 3, 2022 at 10:01 PM Joel Stanley wrote:
> openpower.xyz was retired some time ago. The OpenBMC Jenkins is where
> images can be found these days.
>
> Signed-off-by: Joel Stanley
>
Reviewed-by: Hao Wu
> ---
> docs/system/arm/nuvoton.rst | 4 ++--
> 1 fi
On Wed, Aug 24, 2022 at 3:35 AM Bin Meng wrote:
> From: Bin Meng
>
> The test cases 'test_{tx,rx}' call socketpair() which does not exist
> on win32. Exclude them.
>
> Signed-off-by: Bin Meng
>
Reviewed-by: Hao Wu
> ---
>
> tests/qtest/npcm7xx_emc-test.c | 8
Add cortex A35 core and enable it for virt board.
Signed-off-by: Hao Wu
Reviewed-by: Joe Komlodi
---
docs/system/arm/virt.rst | 1 +
hw/arm/virt.c| 1 +
target/arm/cpu64.c | 80
3 files changed, 82 insertions(+)
diff --git a/docs
Hi,
This is used by a new series of Nuvoton SoC (NPCM8XX) which contains 4
Cortex A-35 cores.
I'll update the missing fields in a follow-up patch set.
On Thu, Aug 18, 2022 at 7:59 AM Peter Maydell
wrote:
> On Mon, 15 Aug 2022 at 22:35, Hao Wu wrote:
> >
> > Add cortex A35
Add cortex A35 core and enable it for virt board.
Signed-off-by: Hao Wu
Reviewed-by: Joe Komlodi
---
docs/system/arm/virt.rst | 1 +
hw/arm/virt.c| 1 +
target/arm/cpu64.c | 69
3 files changed, 71 insertions(+)
diff --git a/docs
This patch allows the user to attach an external drive as a property
for an onboard at24c eeprom device. It uses an unit number to
distinguish different devices.
Signed-off-by: Hao Wu
---
hw/arm/npcm7xx_boards.c | 15 ++-
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git
We allow at24c_eeprom_init to take a I2CBus* as parameter. This allows
us to attach an EEPROM device behind an I2C mux which is not
possible with the old method.
Signed-off-by: Hao Wu
---
hw/arm/npcm7xx_boards.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git
Our sensor test requires both reading and writing from a sensor's
QOM property. So we need to make the input of ADC module R/W instead
of write only for that to work.
Signed-off-by: Hao Wu
Reviewed-by: Titus Rwantare
Reviewed-by: Peter Maydell
---
hw/adc/npcm7xx_adc.c | 2 +-
1 file changed
Originally we read in from SMBus when RXF_STS is cleared. However,
the driver clears RXF_STS before setting RXF_CTL, causing the SM bus
module to read incorrect amount of bytes in FIFO mode when the number
of bytes read changed. This patch fixes this issue.
Signed-off-by: Hao Wu
Reviewed
The correct bit for the CONV bit in NPCM7XX ADC is bit 13. This patch
fixes that in the module, and also lower the IRQ when the guest
is done handling an interrupt event from the ADC module.
Signed-off-by: Hao Wu
Reviewed-by: Patrick Venture
Reviewed-by: Peter Maydell
---
hw/adc/npcm7xx_adc.c
From: Patrick Venture
Adds supported i2c devices to the quanta-gbc-bmc board.
Signed-off-by: Patrick Venture
Reviewed-by: Hao Wu
---
hw/arm/npcm7xx_boards.c | 82 -
1 file changed, 49 insertions(+), 33 deletions(-)
diff --git a/hw/arm/npcm7xx_boards.c
The ACK bit in NPCM7XX SMBus module should be cleared each time it
sends out a NACK signal. This patch fixes the bug that it fails to
do so.
Signed-off-by: Hao Wu
Reviewed-by: Titus Rwantare
Reviewed-by: Peter Maydell
---
hw/i2c/npcm7xx_smbus.c | 2 +-
1 file changed, 1 insertion(+), 1
This type is used to represent block devs that are not suitable to
be represented by other existing types.
A sample use is to represent an at24c eeprom device defined in
hw/nvram/eeprom_at24c.c. The block device can be used to contain the
content of the said eeprom device.
Signed-off-by: Hao Wu
variable in patch 5.
-- Changes since v1:
1. Rewrote patch 5 to implement the function in NPCM7xx board file instead
of the EEPROM device file.
2. Slightly modify patch 6 to adapt to the changes and QEMU comment style.
3. Squash patch 7 into patch 5 to make it compile.
4. Add a new patch 7.
Hao
The correct bit for the CONV bit in NPCM7XX ADC is bit 13. This patch
fixes that in the module, and also lower the IRQ when the guest
is done handling an interrupt event from the ADC module.
Signed-off-by: Hao Wu
Reviewed-by: Patrick Venture
Reviewed-by: Peter Maydell
---
hw/adc/npcm7xx_adc.c
The ACK bit in NPCM7XX SMBus module should be cleared each time it
sends out a NACK signal. This patch fixes the bug that it fails to
do so.
Signed-off-by: Hao Wu
Reviewed-by: Titus Rwantare
Reviewed-by: Peter Maydell
---
hw/i2c/npcm7xx_smbus.c | 2 +-
1 file changed, 1 insertion(+), 1
This type is used to represent block devs that are not suitable to
be represented by other existing types.
A sample use is to represent an at24c eeprom device defined in
hw/nvram/eeprom_at24c.c. The block device can be used to contain the
content of the said eeprom device.
Signed-off-by: Hao Wu
Our sensor test requires both reading and writing from a sensor's
QOM property. So we need to make the input of ADC module R/W instead
of write only for that to work.
Signed-off-by: Hao Wu
Reviewed-by: Titus Rwantare
Reviewed-by: Peter Maydell
---
hw/adc/npcm7xx_adc.c | 2 +-
1 file changed
Originally we read in from SMBus when RXF_STS is cleared. However,
the driver clears RXF_STS before setting RXF_CTL, causing the SM bus
module to read incorrect amount of bytes in FIFO mode when the number
of bytes read changed. This patch fixes this issue.
Signed-off-by: Hao Wu
Reviewed
variable in patch 5.
-- Changes since v1:
1. Rewrote patch 5 to implement the function in NPCM7xx board file instead
of the EEPROM device file.
2. Slightly modify patch 6 to adapt to the changes and QEMU comment style.
3. Squash patch 7 into patch 5 to make it compile.
4. Add a new patch 7.
Hao
From: Patrick Venture
Adds supported i2c devices to the quanta-gbc-bmc board.
Signed-off-by: Patrick Venture
Reviewed-by: Hao Wu
---
hw/arm/npcm7xx_boards.c | 82 -
1 file changed, 49 insertions(+), 33 deletions(-)
diff --git a/hw/arm/npcm7xx_boards.c
The correct bit for the CONV bit in NPCM7XX ADC is bit 13. This patch
fixes that in the module, and also lower the IRQ when the guest
is done handling an interrupt event from the ADC module.
Signed-off-by: Hao Wu
Reviewed-by: Patrick Venture
Reviewed-by: Peter Maydell
---
hw/adc/npcm7xx_adc.c
This patch allows the user to attach an external drive as a property
for an onboard at24c eeprom device. It uses an unit number to
distinguish different devices.
Signed-off-by: Hao Wu
---
hw/arm/npcm7xx_boards.c | 15 ++-
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git
The ACK bit in NPCM7XX SMBus module should be cleared each time it
sends out a NACK signal. This patch fixes the bug that it fails to
do so.
Signed-off-by: Hao Wu
Reviewed-by: Titus Rwantare
Reviewed-by: Peter Maydell
---
hw/i2c/npcm7xx_smbus.c | 2 +-
1 file changed, 1 insertion(+), 1
Our sensor test requires both reading and writing from a sensor's
QOM property. So we need to make the input of ADC module R/W instead
of write only for that to work.
Signed-off-by: Hao Wu
Reviewed-by: Titus Rwantare
Reviewed-by: Peter Maydell
---
hw/adc/npcm7xx_adc.c | 2 +-
1 file changed
We allow at24c_eeprom_init to take a I2CBus* as parameter. This allows
us to attach an EEPROM device behind an I2C mux which is not
possible with the old method.
Signed-off-by: Hao Wu
---
hw/arm/npcm7xx_boards.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git
Originally we read in from SMBus when RXF_STS is cleared. However,
the driver clears RXF_STS before setting RXF_CTL, causing the SM bus
module to read incorrect amount of bytes in FIFO mode when the number
of bytes read changed. This patch fixes this issue.
Signed-off-by: Hao Wu
Reviewed
This type is used to represent block devs that are not suitable to
be represented by other existing types.
A sample use is to represent an at24c eeprom device defined in
hw/nvram/eeprom_at24c.c. The block device can be used to contain the
content of the said eeprom device.
Signed-off-by: Hao Wu
variable in patch 5.
-- Changes since v1:
1. Rewrote patch 5 to implement the function in NPCM7xx board file instead
of the EEPROM device file.
2. Slightly modify patch 6 to adapt to the changes and QEMU comment style.
3. Squash patch 7 into patch 5 to make it compile.
4. Add a new patch 7.
Hao
Creating 1GB image for a simple qtest is unnecessary
and could lead to failures. We reduce the image size
to 1MB to reduce the test overhead.
Signed-off-by: Hao Wu
---
tests/qtest/npcm7xx_sdhci-test.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/qtest/npcm7xx_sdhci
:
>
>
> On Thu, May 26, 2022 at 8:54 AM Peter Maydell
> wrote:
>
>> On Fri, 25 Feb 2022 at 17:45, Hao Wu wrote:
>> >
>> > From: Shengtan Mao
>> >
>> > Reviewed-by: Hao Wu
>> > Reviewed-by: Chris Rauer
>> > Signed-off-by: Shen
On Tue, May 31, 2022 at 6:18 AM Miaoqian Lin wrote:
> g_strdup_printf() allocated memory for path, we should free it with
> g_free() when no longer needed.
>
> Signed-off-by: Miaoqian Lin
>
Reviewed-by: Hao Wu
> ---
> tests/qtest/npcm7xx_pwm-test.c | 3 +++
> 1 fi
Thu, 21 Apr 2022 at 17:29, Hao Wu wrote:
> >
> > Thanks for all the comments you gave! I'll go over and address them
> recently.
> >
> > For this question, The actual CPU should be cortex A35. However, I don't
> see
> > them supported in QEMU. If I inserted CPU
35-arm-cpu'
What should I do here?
On Thu, Apr 21, 2022 at 3:45 AM Peter Maydell
wrote:
> On Tue, 5 Apr 2022 at 23:37, Hao Wu wrote:
> >
> > NPCM8XX BMCs are the successors of the NPCM7XX BMCs. They feature
> > quad-core ARM Cortex A35 that supports both 32 bits and 6
Similar to the Aspeed code in include/misc/aspeed_scu.h, we define
the PWRON STRAP fields in their corresponding module for NPCM7XX.
Signed-off-by: Hao Wu
Reviewed-by: Patrick Venture
---
include/hw/misc/npcm7xx_gcr.h | 30 ++
1 file changed, 30 insertions(+)
diff
This patch uses the defined fields to describe PWRON STRAPs for
better readability.
Signed-off-by: Hao Wu
Reviewed-by: Patrick Venture
---
hw/arm/npcm7xx_boards.c | 24 +++-
1 file changed, 19 insertions(+), 5 deletions(-)
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm
.
-- Changes since v1
* Fix errors and apply suggestions Peter made on v1.
Hao Wu (2):
hw/misc: Add PWRON STRAP bit fields in GCR module
hw/arm: Use bit fields for NPCM7XX PWRON STRAPs
hw/arm/npcm7xx_boards.c | 24 +++-
include/hw/misc/npcm7xx_gcr.h | 30
Similar to the Aspeed code in include/misc/aspeed_scu.h, we define
the PWRON STRAP fields in their corresponding module for NPCM7XX.
Signed-off-by: Hao Wu
Reviewed-by: Patrick Venture
---
include/hw/misc/npcm7xx_gcr.h | 30 ++
1 file changed, 30 insertions(+)
diff
This patch uses the defined fields to describe PWRON STRAPs for
better readability.
Signed-off-by: Hao Wu
Reviewed-by: Patrick Venture
---
hw/arm/npcm7xx_boards.c | 24 +++-
1 file changed, 19 insertions(+), 5 deletions(-)
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm
.
Hao Wu (2):
hw/misc: Add PWRON STRAP bit fields in GCR module
hw/arm: Use bit fields for NPCM7XX PWRON STRAPs
hw/arm/npcm7xx_boards.c | 24 +++-
include/hw/misc/npcm7xx_gcr.h | 30 ++
2 files changed, 49 insertions(+), 5 deletions
The bootrom is a minimal bootrom that can be used to bring up
an NPCM845 Linux kernel. Its source code can be found at
github.com/google/vbootrom/tree/master/npcm8xx
Signed-off-by: Hao Wu
Reviwed-by: Titus Rwantare
---
pc-bios/npcm8xx_bootrom.bin | Bin 0 -> 608 bytes
1 file changed
Signed-off-by: Hao Wu
Reviwed-by: Patrick Venture
---
hw/arm/meson.build | 2 +-
hw/arm/npcm8xx_boards.c | 257 +++
include/hw/arm/npcm8xx.h | 20 +++
3 files changed, 278 insertions(+), 1 deletion(-)
create mode 100644 hw/arm/npcm8xx_boards.c
NPCM8XX boot block stores the DRAM size in SCRPAD_B register in GCR
module. Since we don't simulate a detailed memory controller, we
need to store this information directly similar to the NPCM7XX's
INCTR3 register.
Signed-off-by: Hao Wu
Reviwed-by: Titus Rwantare
---
hw/misc/npcm_gcr.c
The PCS exists in NPCM8XX's GMAC1 and is used to control the SGMII
PHY. This implementation contains all the default registers and
the soft reset feature that are required to load the Linux kernel
driver. Further features have not been implemented yet.
Signed-off-by: Hao Wu
Reviewed-by: Titus
The NPCM8xx GCR device can be accessed with 64-bit memory operations.
This patch supports that.
Signed-off-by: Hao Wu
Reviewed-by: Patrick Venture
---
hw/misc/npcm_gcr.c | 98 +---
hw/misc/trace-events | 4 +-
2 files changed, 77 insertions(+), 25
This property allows certain boards like NPCM8xx to boot the kernel
directly into non-secure mode. This is necessary since we do not
support secure boot features for NPCM8xx now.
Signed-off-by: Hao Wu
Reviewed-by: Patrick Venture
---
hw/intc/arm_gic_common.c | 2 ++
1 file changed, 2
NPCM8XX has a different set of global control registers than 7XX.
This patch supports that.
Signed-off-by: Hao Wu
Reviwed-by: Titus Rwantare
---
MAINTAINERS | 9 +-
hw/misc/meson.build | 2 +-
hw/misc/npcm7xx_gcr.c
NPCM8XX SoC is the successor of the NPCM7XX. It features quad-core
Cortex-A35 (Armv8, 64-bit) CPUs and some additional peripherals.
Signed-off-by: Hao Wu
Reviewed-by: Patrick Venture
---
docs/system/arm/nuvoton.rst | 20 +++-
1 file changed, 15 insertions(+), 5 deletions
.
Implementation of these clocks might be required when implementing
these modules.
Signed-off-by: Hao Wu
Reviewed-by: Titus Rwantare
---
hw/misc/meson.build | 2 +-
hw/misc/{npcm7xx_clk.c => npcm_clk.c} | 238 ++
hw/misc/trace-eve
The file contains a basic NPCM8XX SOC file. It's forked
from the NPCM7XX SOC with some changes.
Signed-off-by: Hao Wu
Reviwed-by: Patrick Venture
Reviwed-by: Titus Rwantare
---
configs/devices/aarch64-softmmu/default.mak | 1 +
hw/arm/Kconfig | 11 +
hw/arm
This allows different FIUs to have different flash sizes, useful
in NPCM8XX which has multiple different sized FIU modules.
Signed-off-by: Hao Wu
Reviewed-by: Patrick Venture
---
hw/arm/npcm7xx.c | 6 ++
hw/ssi/npcm7xx_fiu.c | 6 ++
include/hw/ssi/npcm7xx_fiu.h | 1
be found at:
https://github.com/Nuvoton-Israel/openbmc/tree/npcm-v2.10/meta-evb/meta-evb-nuvoton/meta-evb-npcm845
The patch set can boot the evaluation board image built from the source
above to login prompt.
Hao Wu (11):
docs/system/arm: Add Description for NPCM8XX SoC
hw/ssi: Make flash size
gt; > (Detected with the clang leak sanitizer.)
> >
> > Signed-off-by: Peter Maydell
> > ---
> > hw/misc/npcm7xx_clk.c | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
>
> Reviewed-by: Richard Henderson
>
> Reviewed-by: Hao Wu
> r~
>
>
From: Shengtan Mao
Reviewed-by: Hao Wu
Reviewed-by: Chris Rauer
Signed-off-by: Shengtan Mao
Signed-off-by: Patrick Venture
---
v5
* use memcmp to compare whether strings are expected
v4
* use strncmp instead of strcmp
v3:
* fixup compilation from missing macro value
v2:
* update
I have sent an updated version that uses memcmp()
On Fri, Feb 25, 2022 at 3:44 AM Peter Maydell
wrote:
> On Thu, 24 Feb 2022 at 19:03, Hao Wu wrote:
> >
> > From: Shengtan Mao
> >
> > Reviewed-by: Hao Wu
> > Reviewed-by: Chris Rauer
> > Sign
From: Shengtan Mao
Reviewed-by: Hao Wu
Reviewed-by: Chris Rauer
Signed-off-by: Shengtan Mao
Signed-off-by: Patrick Venture
Signed-off-by: Hao Wu
---
v4:
* use strncmp to compare fixed length strings
v3:
* fixup compilation from missing macro value
v2:
* update copyright year
* check
issue.
On Tue, Feb 22, 2022 at 5:28 PM Patrick Venture wrote:
>
>
> On Mon, Feb 21, 2022 at 5:30 AM Peter Maydell
> wrote:
>
>> On Wed, 16 Feb 2022 at 17:30, Peter Maydell
>> wrote:
>> >
>> > On Tue, 8 Feb 2022 at 18:18, Patrick Venture
>> wro
On Tue, Feb 8, 2022 at 9:23 AM Peter Maydell
wrote:
> For arm boards with an i2c bus which a user could reasonably
> want to plug arbitrary devices, add 'imply I2C_DEVICES' to the
> Kconfig stanza.
>
> Signed-off-by: Peter Maydell
>
Reviewed-by: Hao Wu
> ---
> A
ing PMBus devices or devices which need GPIO lines to be
> connected).
>
> Signed-off-by: Peter Maydell
>
Reviewed-by: Hao Wu
> ---
> Feel free to suggest other i2c devices that should be marked
> as in the group; as I say, I erred on the side of not putting
> devi
On Thu, Jan 27, 2022 at 6:55 AM Corey Minyard wrote:
> On Wed, Jan 26, 2022 at 04:09:03PM -0800, Hao Wu wrote:
> > Hi,
> >
> > Sorry for the late reply. I'm not sure what "auto-increment" means here.
>
> The question is: When a value is read, does the ad
AM Patrick Venture wrote:
>
>
> On Mon, Jan 17, 2022 at 6:05 AM Corey Minyard wrote:
>
>> On Sun, Jan 09, 2022 at 06:17:34PM -0800, Patrick Venture wrote:
>> > On Fri, Jan 7, 2022 at 7:04 PM Patrick Venture
>> wrote:
>> >
>> > > From: Hao Wu
&g
_abort);
> > }
> >
> > -static void sdhci_attach_drive(SDHCIState *sdhci)
> > +static void sdhci_attach_drive(SDHCIState *sdhci, int unit)
> > {
> > -DriveInfo *di = drive_get_next(IF_SD);
> > +DriveInfo *di =
This type is used to represent block devs that are not suitable to
be represented by other existing types.
Signed-of-by: Hao Wu
---
blockdev.c| 3 ++-
include/sysemu/blockdev.h | 1 +
meson | 2 +-
3 files changed, 4 insertions(+), 2 deletions(-)
diff --git
Our sensor test requires both reading and writing from a sensor's
QOM property. So we need to make the input of ADC module R/W instead
of write only for that to work.
Signed-off-by: Hao Wu
Reviewed-by: Titus Rwantare
Reviewed-by: Peter Maydell
---
hw/adc/npcm7xx_adc.c | 2 +-
1 file changed
From: Patrick Venture
Adds supported i2c devices to the quanta-gbc-bmc board.
Signed-off-by: Patrick Venture
Reviewed-by: Hao Wu
---
hw/arm/npcm7xx_boards.c | 82 -
1 file changed, 49 insertions(+), 33 deletions(-)
diff --git a/hw/arm/npcm7xx_boards.c
with the same unit number,
the following error will occur: `Device with id 'none85' exists`.
Signed-off-by: Hao Wu
---
hw/arm/npcm7xx_boards.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
index dec7d16ae5
The ACK bit in NPCM7XX SMBus module should be cleared each time it
sends out a NACK signal. This patch fixes the bug that it fails to
do so.
Signed-off-by: Hao Wu
Reviewed-by: Titus Rwantare
Reviewed-by: Peter Maydell
---
hw/i2c/npcm7xx_smbus.c | 2 +-
1 file changed, 1 insertion(+), 1
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