在 2020/7/3 下午6:37, Peter Maydell 写道:
On Fri, 3 Jul 2020 at 10:44, Heyi Guo wrote:
vms->psci_conduit being disabled only means PSCI is not implemented by
qemu; it doesn't mean PSCI is not supported on this virtual machine.
Actually vms->psci_conduit is set to disabled when vms-&
re, which will definitely provide PSCI.
The issue can be reproduced when running qemu in TCG mode with secure
enabled, while using ARM trusted firmware + qemu virt UEFI as firmware
binaries, and we can see secondary cores will not be waken up.
Signed-off-by: Heyi Guo
---
Cc: Shannon Zhao
Cc: "Mich
On 2020/3/19 22:46, Igor Mammedov wrote:
On Wed, 18 Mar 2020 14:48:18 +0800
Heyi Guo wrote:
Common VM users sometimes care about CPU speed, so we add two new
options to allow VM vendors to present CPU speed to their users.
Normally these information can be fetched from host smbios.
it's
be 0 instead of 2000 in previous versions
- Use uint64_t type to check value overflow
- Add test case to check smbios type 4 CPU speed
Cc: "Michael S. Tsirkin"
Cc: Igor Mammedov
Cc: Philippe Mathieu-Daudé
Cc: Thomas Huth
Cc: Laurent Vivier
Cc: Paolo Bonzini
Heyi Guo (2):
hw/smbios:
ly for the max speed and current speed of processor, for
"max speed" identifies a capability of the system, and "current speed"
identifies the processor's speed at boot (see smbios spec), but some
applications do not tell the differences.
Signed-off-by: Heyi Guo
---
Cc: "Michael
t
doesn't really run on aarch64 platform for smbios test can't run on
uefi only platform yet.
Signed-off-by: Heyi Guo
---
Cc: "Michael S. Tsirkin"
Cc: Igor Mammedov
Cc: Thomas Huth
Cc: Laurent Vivier
Cc: Paolo Bonzini
---
tests/qtest/bios-tables-test.c | 42
On 2020/3/3 16:33, Igor Mammedov wrote:
On Tue, 3 Mar 2020 11:18:56 +0800
Heyi Guo wrote:
One comment from myself after going through the code...
On 2020/3/3 9:01, Heyi Guo wrote:
Common VM users sometimes care about CPU speed, so we add two new
options to allow VM vendors to present CPU
One comment from myself after going through the code...
On 2020/3/3 9:01, Heyi Guo wrote:
Common VM users sometimes care about CPU speed, so we add two new
options to allow VM vendors to present CPU speed to their users.
Normally these information can be fetched from host smbios.
Strictly
On 2020/3/2 21:52, Igor Mammedov wrote:
On Mon, 2 Mar 2020 17:29:10 +0800
Heyi Guo wrote:
Common VM users sometimes care about CPU speed, so we add two new
options to allow VM vendors to present CPU speed to their users.
Normally these information can be fetched from host smbios.
Strictly
ly for the max speed and current speed of processor, for
"max speed" identifies a capability of the system, and "current speed"
identifies the processor's speed at boot (see smbios spec), but some
applications do not tell the differences.
Signed-off-by: Heyi Guo
Reviewed-by: Igor Mam
ly for the max speed and current speed of processor, for
"max speed" identifies a capability of the system, and "current speed"
identifies the processor's speed at boot (see smbios spec), but some
applications do not tell the differences.
Signed-off-by: Heyi Guo
---
Cc: "Michael
On 2020/3/2 16:20, Igor Mammedov wrote:
On Sat, 29 Feb 2020 08:17:48 +0800
Heyi Guo wrote:
Hi Igor,
On 2020/2/28 17:39, Igor Mammedov wrote:
On Thu, 27 Feb 2020 17:12:21 +0800
Heyi Guo wrote:
On 2020/2/25 17:24, Philippe Mathieu-Daudé wrote:
On 2/25/20 8:50 AM, Heyi Guo wrote
Hi Igor,
On 2020/2/28 17:39, Igor Mammedov wrote:
On Thu, 27 Feb 2020 17:12:21 +0800
Heyi Guo wrote:
On 2020/2/25 17:24, Philippe Mathieu-Daudé wrote:
On 2/25/20 8:50 AM, Heyi Guo wrote:
Common VM users sometimes care about CPU speed, so we add two new
options to allow VM vendors
On 2020/2/25 17:24, Philippe Mathieu-Daudé wrote:
On 2/25/20 8:50 AM, Heyi Guo wrote:
Common VM users sometimes care about CPU speed, so we add two new
options to allow VM vendors to present CPU speed to their users.
Normally these information can be fetched from host smbios.
Strictly
ly for the max speed and current speed of processor, for
"max speed" identifies a capability of the system, and "current speed"
identifies the processor's speed at boot (see smbios spec), but some
applications do not tell the differences.
Signed-off-by: Heyi Guo
---
Cc: "Michael S
Hi Peter,
Do you have any other comments? If not, could you help to merge into
your tree?
Thanks,
Heyi
On 2020/2/4 9:43, Heyi Guo wrote:
Remove conflict _ADR objects, and fix and refine PCI device definition in
ACPI/DSDT.
History:
v3 -> v2:
- update commit message for patch 4/7.
- rem
On 2020/2/7 18:52, James Morse wrote:
Hi guys,
On 06/02/2020 17:30, Marc Zyngier wrote:
On 2020-02-06 01:20, Heyi Guo wrote:
On 2020/2/5 21:15, Marc Zyngier wrote:
My concern is that SDEI implies having EL3. EL3 not being virtualizable
with KVM, you end-up baking SDEI in *hardware
On 2020/2/7 1:30, Marc Zyngier wrote:
On 2020-02-06 01:20, Heyi Guo wrote:
Hi Marc,
On 2020/2/5 21:15, Marc Zyngier wrote:
Hi Heyi,
On 2020-02-04 08:26, Heyi Guo wrote:
Update Marc's email address.
+cc Gavin as he is posting a RFC for ARM NMI.
Hi Marc,
Really sorry for missing
Hi Marc,
On 2020/2/5 21:15, Marc Zyngier wrote:
Hi Heyi,
On 2020-02-04 08:26, Heyi Guo wrote:
Update Marc's email address.
+cc Gavin as he is posting a RFC for ARM NMI.
Hi Marc,
Really sorry for missing to update your email address, for the initial
topic was raised long time ago and I
e existing firmware directly, but how
can we achieve that? Either I don't think it is good to modify the
firmware code too much, for firmware should be kept simple and reliable.
Does James or Marc have any idea?
Thanks,
Heyi
在 2019/12/20 21:44, Peter Maydell 写道:
On Tue, 5 Nov 2019 at 09:12, Heyi
We are going to change ARM virt ACPI DSDT table, which will cause make
check to fail, so temporarily add related golden masters to ignore
list.
Signed-off-by: Heyi Guo
Reviewed-by: Michael S. Tsirkin
---
Cc: Peter Maydell
Cc: "Michael S. Tsirkin"
Cc: Igor Mammedov
Cc: Shannon Zhao
The sub device "RP0" under PCI0 in ACPI/DSDT does not contain any
method or property other than "_ADR", so it is safe to remove it.
Signed-off-by: Heyi Guo
Acked-by: "Michael S. Tsirkin"
---
Cc: Peter Maydell
Cc: "Michael S. Tsirkin"
Cc: I
343:
A device object must contain either an _HID object or an _ADR object,
but should not contain both.
(https://uefi.org/sites/default/files/resources/ACPI_6_3_May16.pdf)
Signed-off-by: Heyi Guo
Acked-by: Igor Mammedov
Acked-by: Michael S. Tsirkin
---
Cc: Shannon Zhao
Cc: Peter Maydell
Cc
Signed-off-by: Heyi Guo
Reviewed-by: Michael S. Tsirkin
---
Cc: Peter Maydell
Cc: "Michael S. Tsirkin"
Cc: Igor Mammedov
Cc: Shannon Zhao
Cc: qemu-...@nongnu.org
Cc: qemu-devel@nongnu.org
---
hw/arm/virt-acpi-build.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/arm/virt-a
) instead.
Signed-off-by: Heyi Guo
Reviewed-by: Michael S. Tsirkin
---
Cc: Peter Maydell
Cc: "Michael S. Tsirkin"
Cc: Igor Mammedov
Cc: Shannon Zhao
Cc: qemu-...@nongnu.org
Cc: qemu-devel@nongnu.org
---
hw/arm/virt-acpi-build.c | 10 +-
1 file changed, 5 insertions(+), 5 deletion
uot;, "DSDT", 2, "BOCHS ", "BXPCDSDT",
0x0001)
Device (PWRB)
{
Name (_HID, "PNP0C0C" /* Power Button Device */) // _HID:
Hardware ID
-Name (_ADR, Zero) // _ADR: Address
Name (_UID, Zero) // _UID: Un
Using _UID of 0 for all PCI interrupt link devices absolutely violates
the spec. Simply increase one by one.
Signed-off-by: Heyi Guo
Reviewed-by: Michael S. Tsirkin
---
Cc: Peter Maydell
Cc: "Michael S. Tsirkin"
Cc: Igor Mammedov
Cc: Shannon Zhao
Cc: qemu-...@nongnu.org
Cc:
test.c to post ACPI related
patches.
- update commit messages for removing "RP0" and "_ADR".
- add 3 more cleanup patches.
Cc: Peter Maydell
Cc: "Michael S. Tsirkin"
Cc: Igor Mammedov
Cc: Shannon Zhao
Cc: qemu-...@nongnu.org
Cc: qemu-devel@nongnu.org
Heyi
在 2020/2/3 22:03, Peter Maydell 写道:
On Mon, 3 Feb 2020 at 13:33, Heyi Guo wrote:
在 2020/2/3 14:43, Michael S. Tsirkin 写道:
On Mon, Feb 03, 2020 at 08:14:58AM +0800, Heyi Guo wrote:
Remove conflict _ADR objects, and fix and refine PCI device definition in
ACPI/DSDT.
Cc: Peter Maydell
Cc
在 2020/2/3 14:43, Michael S. Tsirkin 写道:
On Mon, Feb 03, 2020 at 08:14:58AM +0800, Heyi Guo wrote:
Remove conflict _ADR objects, and fix and refine PCI device definition in
ACPI/DSDT.
Cc: Peter Maydell
Cc: "Michael S. Tsirkin"
Cc: Igor Mammedov
Cc: Shannon Zhao
Cc: qemu-...@non
quot; /* PNP Motherboard Resources */) //
_HID: Hardware ID
@@ -9131,7 +1925,6 @@ DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPCDSDT",
0x0001)
Device (PWRB)
{
Name (_HID, "PNP0C0C" /* Power Button Device */)
343:
A device object must contain either an _HID object or an _ADR object,
but should not contain both.
(https://uefi.org/sites/default/files/resources/ACPI_6_3_May16.pdf)
Signed-off-by: Heyi Guo
Acked-by: Igor Mammedov
---
Cc: Shannon Zhao
Cc: Peter Maydell
Cc: "Michael S. Tsirkin"
Using _UID of 0 for all PCI interrupt link devices absolutely violates
the spec. Simply increase one by one.
Signed-off-by: Heyi Guo
---
Cc: Peter Maydell
Cc: "Michael S. Tsirkin"
Cc: Igor Mammedov
Cc: Shannon Zhao
Cc: qemu-...@nongnu.org
Cc: qemu-devel@nongnu.org
---
hw/arm
The sub device "RP0" under PCI0 in ACPI/DSDT does not contain any
method or property other than "_ADR", so it is safe to remove it.
Signed-off-by: Heyi Guo
Acked-by: "Michael S. Tsirkin"
---
Cc: Peter Maydell
Cc: "Michael S. Tsirkin"
Cc: I
We are going to change ARM virt ACPI DSDT table, which will cause make
check to fail, so temporarily add related golden masters to ignore
list.
Signed-off-by: Heyi Guo
---
Cc: Peter Maydell
Cc: "Michael S. Tsirkin"
Cc: Igor Mammedov
Cc: Shannon Zhao
Cc: qemu-...@nongnu.org
Cc:
Signed-off-by: Heyi Guo
---
Cc: Peter Maydell
Cc: "Michael S. Tsirkin"
Cc: Igor Mammedov
Cc: Shannon Zhao
Cc: qemu-...@nongnu.org
Cc: qemu-devel@nongnu.org
---
hw/arm/virt-acpi-build.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/vir
The address field in each _PRT mapping package should be constructed
with high word for device# and low word for function#, so it is wrong
to use bus_no as the high word. Enumerate all possible slots
(i.e. PCI_SLOT_MAX) instead.
Signed-off-by: Heyi Guo
---
Cc: Peter Maydell
Cc: "Mich
to post ACPI related
patches.
- update commit messages for removing "RP0" and "_ADR".
- add 3 more cleanup patches.
Heyi Guo (7):
bios-tables-test: prepare to change ARM virt ACPI DSDT
arm/virt/acpi: remove meaningless sub device "PR0" from PCI0
arm/virt/acpi:
Update comments in tests/qtest/bios-tables-test.c to reflect the
current path of bios-tables-test-allowed-diff.h, which is now under
tests/qtest/ as well.
Signed-off-by: Heyi Guo
---
Cc: "Michael S. Tsirkin"
Cc: Igor Mammedov
Cc: Thomas Huth
Cc: Laurent Vivier
Cc: Paolo Bonzini
According to ACPI spec, _ADR should be used for device which is on a
bus that has a standard enumeration algorithm. It does not make sense
to have a _ADR object for devices which already have _HID and will be
enumerated by OSPM.
Signed-off-by: Heyi Guo
---
Cc: Shannon Zhao
Cc: Peter Maydell
Remove useless device node and conflict _ADR objects in ACPI/DSDT.
Cc: Peter Maydell
Cc: "Michael S. Tsirkin"
Cc: Igor Mammedov
Cc: Shannon Zhao
Cc: qemu-...@nongnu.org
Cc: qemu-devel@nongnu.org
Heyi Guo (2):
arm/virt/acpi: remove meaningless sub device "PR0" from
The sub device "PR0" under PCI0 in ACPI/DSDT does not make any sense,
so simply remote it.
Signed-off-by: Heyi Guo
---
Cc: Peter Maydell
Cc: "Michael S. Tsirkin"
Cc: Igor Mammedov
Cc: Shannon Zhao
Cc: qemu-...@nongnu.org
Cc: qemu-devel@nongnu.org
---
hw/arm/virt-acpi-bu
Cc: Peter Maydell
Cc: "Michael S. Tsirkin"
Cc: Igor Mammedov
Suggested-by: Igor Mammedov
Reviewed-by: Igor Mammedov
Signed-off-by: Heyi Guo
---
hw/arm/virt-acpi-build.c | 16
tests/data/acpi/virt/DSDT | Bin 18470 -> 18462 bytes
tests/data/acpi/
:
- Fix "make check" errors by updating tests/data/acpi/virt/DSDT*.
v5:
- Refine commit message of patch 1/2
v4:
- Improve the code indention.
Cc: Shannon Zhao
Cc: Peter Maydell
Cc: "Michael S. Tsirkin"
Cc: Igor Mammedov
Heyi Guo (2):
hw/arm/acpi: simplify AML bit and/o
;
Cc: Igor Mammedov
Reviewed-by: Michael S. Tsirkin
Reviewed-by: Igor Mammedov
Signed-off-by: Heyi Guo
---
hw/arm/virt-acpi-build.c | 7 ++-
tests/data/acpi/virt/DSDT | Bin 18462 -> 18462 bytes
tests/data/acpi/virt/DSDT.memhp | Bin 19799 -> 19799 bytes
tests/data/ac
index as lower bit for each allocated event
number, so that we can get property easily from valid input event
number, as well as the QemuSDE instance.
Signed-off-by: Heyi Guo
Signed-off-by: Jingyi Wang
Cc: Peter Maydell
Cc: Dave Martin
Cc: Marc Zyngier
Cc: Mark Rutland
Cc: James Morse
Signed-off-by: Heyi Guo
Cc: Peter Maydell
Cc: Dave Martin
Cc: Marc Zyngier
Cc: Mark Rutland
Cc: James Morse
---
target/arm/Makefile.objs | 2 ++
target/arm/sdei-stub.c | 49
2 files changed, 51 insertions(+)
create mode 100644 target/arm/sdei
post_load().
Signed-off-by: Heyi Guo
Cc: Peter Maydell
Cc: Dave Martin
Cc: Marc Zyngier
Cc: Mark Rutland
Cc: James Morse
---
target/arm/sdei.c | 130 +-
target/arm/sdei_int.h | 3 +
2 files changed, 132 insertions(+), 1 deletion(-)
diff --git a/target
r
enabling this cap, all HVC calls unhandled by kvm will be forwarded to
user space.
Signed-off-by: Heyi Guo
Cc: Peter Maydell
Cc: "Michael S. Tsirkin"
Cc: Cornelia Huck
Cc: Paolo Bonzini
Cc: Dave Martin
Cc: Marc Zyngier
Cc: Mark Rutland
Cc: James Morse
---
linux-headers/linux/kvm.
Import Linux header file include/uapi/linux/arm_sdei.h from kernel v5.4-rc5.
This is to prepare for qemu SDEI emulation.
Signed-off-by: Heyi Guo
Cc: Peter Maydell
Cc: Dave Martin
Cc: Marc Zyngier
Cc: Mark Rutland
Cc: James Morse
Cc: "Michael S. Tsirkin"
Cc: Cornelia Huck
Other qemu modules related with the interrupt bind operation may want
to be notified when guest requests to bind interrupt to sdei event, so
we add register and unregister interfaces.
Signed-off-by: Heyi Guo
Cc: Peter Maydell
Cc: Dave Martin
Cc: Marc Zyngier
Cc: Mark Rutland
Cc: James Morse
Add support to handle guest exit of hypercall, and forward to SDEI
dispatcher if SDEI is enabled and it is an SDEI request.
Signed-off-by: Heyi Guo
Cc: Peter Maydell
Cc: Dave Martin
Cc: Marc Zyngier
Cc: Mark Rutland
Cc: James Morse
---
target/arm/kvm.c | 17 +
1 file
This is to prepare for qemu SDEI emulation.
Signed-off-by: Heyi Guo
Cc: Peter Maydell
Cc: Dave Martin
Cc: Marc Zyngier
Cc: Mark Rutland
Cc: James Morse
Cc: "Michael S. Tsirkin"
Cc: Cornelia Huck
Cc: Paolo Bonzini
---
Notes:
v2:
- Update update-linux-header
are case).
Return:
args[0..3]: x0..x3 as defined in SMCCC. We rely on KVM to extract
args[0..3] and write them to x0..x3 when hypercall exit
returns.
Signed-off-by: Heyi Guo
Signed-off-by: Jingyi Wang
Cc: Peter Maydell
Cc: Dave Martin
Cc: Marc Zyngier
Cc: M
rk Rutland
Cc: James Morse
Cc: "Michael S. Tsirkin"
Cc: Cornelia Huck
Cc: Paolo Bonzini
Cc: Shannon Zhao
Cc: Igor Mammedov
v2:
- Import import linux/arm_sdei.h to standard-headers
- Drop SDEI table definition and add comments
- Some bugfix and code refinement
Heyi Guo (14):
upd
to default one (i.e. ARM GIC).
qemu_irq_remove_intercept() is the new interface to do the above
job.
Signed-off-by: Heyi Guo
Cc: Peter Maydell
Cc: Dave Martin
Cc: Marc Zyngier
Cc: Mark Rutland
Cc: James Morse
---
hw/core/irq.c| 11 +++
include/hw/irq.h | 8 ++--
2 files
For this is a logical device which is not attached to system bus, we
cannot use DeviceClass->reset interface directly. Instead we register
our own reset callback to reset SDEI services when system resets.
Signed-off-by: Heyi Guo
Signed-off-by: Jingyi Wang
Cc: Peter Maydell
Cc: Dave Martin
Add SDEI table if SDEI is enabled, so that guest OS can get aware and
utilize the interfaces.
Signed-off-by: Heyi Guo
Cc: Peter Maydell
Cc: Dave Martin
Cc: Marc Zyngier
Cc: Mark Rutland
Cc: James Morse
Cc: Shannon Zhao
Cc: "Michael S. Tsirkin"
Cc: Igor Mammedov
---
Not
Add an external interface to trigger an SDEI event bound to an
interrupt by providing GIC interrupt ID.
Signed-off-by: Heyi Guo
Cc: Peter Maydell
Cc: Dave Martin
Cc: Marc Zyngier
Cc: Mark Rutland
Cc: James Morse
---
target/arm/sdei.c | 37 +
target/arm
Integrate SDEI support for arm/aarch64 targets by default, if KVM is
enabled.
Signed-off-by: Heyi Guo
Cc: Peter Maydell
Cc: Dave Martin
Cc: Marc Zyngier
Cc: Mark Rutland
Cc: James Morse
---
default-configs/arm-softmmu.mak | 1 +
hw/arm/Kconfig | 4
target/arm
are case).
Return:
args[0..3]: x0..x3 as defined in SMCCC. We rely on KVM to extract
args[0..3] and write them to x0..x3 when hypercall exit
returns.
Signed-off-by: Heyi Guo
Signed-off-by: Jingyi Wang
Cc: Peter Maydell
Cc: Dave Martin
Cc: Marc Zyngier
Cc: M
Other qemu modules related with the interrupt bind operation may want
to be notified when guest requests to bind interrupt to sdei event, so
we add register and unregister interfaces.
Signed-off-by: Heyi Guo
Cc: Peter Maydell
Cc: Dave Martin
Cc: Marc Zyngier
Cc: Mark Rutland
Cc: James Morse
post_load().
Signed-off-by: Heyi Guo
Cc: Peter Maydell
Cc: Dave Martin
Cc: Marc Zyngier
Cc: Mark Rutland
Cc: James Morse
---
target/arm/sdei.c | 137 --
target/arm/sdei_int.h | 3 ++
2 files changed, 137 insertions(+), 3 deletions(-)
diff --git
For this is a logical device which is not attached to system bus, we
cannot use DeviceClass->reset interface directly. Instead we register
our own reset callback to reset SDEI services when system resets.
Signed-off-by: Heyi Guo
Signed-off-by: Jingyi Wang
Cc: Peter Maydell
Cc: Dave Martin
Add SDEI table if SDEI is enabled, so that guest OS can get aware and
utilize the interfaces.
Signed-off-by: Heyi Guo
Cc: Peter Maydell
Cc: Dave Martin
Cc: Marc Zyngier
Cc: Mark Rutland
Cc: James Morse
Cc: Shannon Zhao
Cc: "Michael S. Tsirkin"
Cc: Igor Mammedov
---
hw/arm
to default one (i.e. ARM GIC).
qemu_irq_remove_intercept() is the new interface to do the above
job.
Signed-off-by: Heyi Guo
Cc: Peter Maydell
Cc: Dave Martin
Cc: Marc Zyngier
Cc: Mark Rutland
Cc: James Morse
---
hw/core/irq.c| 11 +++
include/hw/irq.h | 8 ++--
2 files
and
framework first. We can refine the code for several rounds after the
big things have been determined.
Please give your comments and suggestions.
Thanks,
HG
Cc: Peter Maydell
Cc: Dave Martin
Cc: Marc Zyngier
Cc: Mark Rutland
Cc: James Morse
Heyi Guo (12):
linux-headers: import arm_sdei.h
index as lower bit for each allocated event
number, so that we can get property easily from valid input event
number, as well as the QemuSDE instance.
Signed-off-by: Heyi Guo
Signed-off-by: Jingyi Wang
Cc: Peter Maydell
Cc: Dave Martin
Cc: Marc Zyngier
Cc: Mark Rutland
Cc: James Morse
Add support to handle guest exit of hypercall, and forward to SDEI
dispatcher if SDEI is enabled and it is an SDEI request.
Signed-off-by: Heyi Guo
Cc: Peter Maydell
Cc: Dave Martin
Cc: Marc Zyngier
Cc: Mark Rutland
Cc: James Morse
---
target/arm/kvm.c | 17 +
1 file
Add an external interface to trigger an SDEI event bound to an
interrupt by providing GIC interrupt ID.
Signed-off-by: Heyi Guo
Cc: Peter Maydell
Cc: Dave Martin
Cc: Marc Zyngier
Cc: Mark Rutland
Cc: James Morse
---
target/arm/sdei.c | 38 ++
target/arm
e also use
an additional argument to pass exception bit mask, to request KVM to
forward all hypercalls except the classes specified in the bit mask.
Currently only PSCI can be set as exception, so that we can still keep
consistent with the original PSCI processing flow.
Signed-off-by: Heyi Guo
Cc: Pet
Check KVM hypercall forward capability and enable it, and set global
flag "sdei_enabled" to true if everything works well.
Signed-off-by: Heyi Guo
Cc: Peter Maydell
Cc: Dave Martin
Cc: Marc Zyngier
Cc: Mark Rutland
Cc: James Morse
---
target/arm/sdei.c | 17 +
Import Linux header file include/uapi/linux/arm_sdei.h from kernel
v5.3 release.
This is to prepare for qemu SDEI emulation.
Signed-off-by: Heyi Guo
Cc: Peter Maydell
Cc: Dave Martin
Cc: Marc Zyngier
Cc: Mark Rutland
Cc: James Morse
Cc: "Michael S. Tsirkin"
Cc: Cornelia Huck
Hi Eric and Michael,
Appreciate your sharing of this information. But sorry I'm still a little
confused due to my poor English...
On 2019/4/11 20:19, Auger Eric wrote:
Hi Heyi,
On 4/11/19 1:30 PM, Heyi Guo wrote:
Hi Eric,
Could you help to confirm?
Practically I have not tried anything
Hi Eric,
Could you help to confirm?
Thanks,
Heyi
On 2019/4/7 9:59, Heyi Guo wrote:
Hi Eric,
My real interesting is about the hotplug of PCIe switch, which means we don't
need to provide lots of PCIe root ports or PCIe down stream ports at the
beginning, but we can extend the capacity
19/3/27 1:12, Steven Price wrote:
Hi Heyi,
On 26/03/2019 13:53, Heyi Guo wrote:
I also tested save/restore operations, and observed that clock in guest
would not jump after restoring either. If we consider guest clock not
being synchronized with real wall clock as an issue, does it mean
save/
On 2019/4/7 21:16, Peter Maydell wrote:
On Sun, 7 Apr 2019 at 09:19, Heyi Guo wrote:
This patch is based on the discussion in TianoCore edk2-devel mailing
list:
https://lists.01.org/pipermail/edk2-devel/2019-March/037986.html
The conclusion is that we need an individual UART for UEFI
: Peter Maydell
Cc: Laszlo Ersek
Signed-off-by: Heyi Guo
---
hw/arm/virt.c | 29 +++--
include/hw/arm/virt.h | 1 +
2 files changed, 24 insertions(+), 6 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index ce2664a..cbc5a66 100644
--- a/hw/arm/virt.c
+++ b
ys, either they can't be hot-plugged into an non-existing
Upstream Port or another place...
Thanks,
Heyi
On 2019/4/4 15:39, Auger Eric wrote:
Hi Heyi,
On 4/3/19 8:50 PM, Michael S. Tsirkin wrote:
On Wed, Apr 03, 2019 at 03:32:09PM +0800, Heyi Guo wrote:
Hi folks,
In physical world, a P
Hi folks,
In physical world, a PCIe switch including one upstream port and several
downstream ports is a single physical device, however we treat each port as a
device in qemu world. In qemu docs/pcie.txt, we have below statements:
Line 230: Be aware that PCI Express Downstream Ports can't be
Guo wrote:
Hi Steven,
Thanks for your explanation. Please see my comments below.
On 2019/3/21 0:29, Steven Price wrote:
On 19/03/2019 14:39, Heyi Guo wrote:
Hi Christoffer and Steve,
On 2019/3/15 16:59, Christoffer Dall wrote:
Hi Steve,
On Wed, Mar 13, 2019 at 10:11:30AM +, Steven Price
Hi Steven,
Thanks for your explanation. Please see my comments below.
On 2019/3/21 0:29, Steven Price wrote:
On 19/03/2019 14:39, Heyi Guo wrote:
Hi Christoffer and Steve,
On 2019/3/15 16:59, Christoffer Dall wrote:
Hi Steve,
On Wed, Mar 13, 2019 at 10:11:30AM +, Steven Price wrote
Hi Christoffer and Steve,
On 2019/3/15 16:59, Christoffer Dall wrote:
Hi Steve,
On Wed, Mar 13, 2019 at 10:11:30AM +, Steven Price wrote:
Personally I think what we need is:
* Either a patch like the one from Heyi Guo (save/restore CNTVCT_EL0) or
alternatively hooking up
Hi Peter and Steven,
On 2019/3/13 18:11, Steven Price wrote:
On 12/03/2019 14:12, Marc Zyngier wrote:
Hi Peter,
On 12/03/2019 10:08, Peter Maydell wrote:
On Tue, 12 Mar 2019 at 06:10, Heyi Guo wrote:
When we stop a VM for more than 30 seconds and then resume it, by qemu
monitor command
dell wrote:
On Tue, 12 Mar 2019 at 06:10, Heyi Guo wrote:
When we stop a VM for more than 30 seconds and then resume it, by qemu
monitor command "stop" and "cont", Linux on VM will complain of "soft
lockup - CPU#x stuck for xxs!" as below:
[ 2783.809517] watchdog:
Hi Richard,
On 2019/3/12 22:59, Richard Henderson wrote:
On 3/12/19 12:57 AM, Heyi Guo wrote:
int kvm_arm_vcpu_init(CPUState *cs)
{
ARMCPU *cpu = ARM_CPU(cs);
struct kvm_vcpu_init init;
+/*
+ * Only add change state handler for arch timer once, for KVM will help
Hi all,
I'm sorry this patch failed the docker-mingw@fedora build test. I'm going to
move the code to target/arm/kvm.c.
Please ignore this one.
Thanks,
Heyi
On 2019/3/12 14:09, Heyi Guo wrote:
When we stop a VM for more than 30 seconds and then resume it, by qemu
monitor command "
his patch is to fix this issue by saving the value of CNTVCT_EL0 when
stopping and restoring it when resuming.
Cc: Peter Maydell
Signed-off-by: Heyi Guo
---
target/arm/kvm.c | 66
1 file changed, 66 insertions(+)
diff --git a/target/arm/
his patch is to fix this issue by saving the value of CNTVCT_EL0 when
stopping and restoring it when resuming.
Cc: Peter Maydell
Signed-off-by: Heyi Guo
---
target/arm/cpu.c | 65
1 file changed, 65 insertions(+)
diff --git a/target/arm/
On 2019/3/7 0:34, Igor Mammedov wrote:
On Wed, 6 Mar 2019 21:36:56 +0800
Heyi Guo wrote:
The last argument of AML bit and/or statement is the target variable,
so we don't need to use a NULL target and then an additional store
operation; a single bit and/or statement is enough.
s: a single
r Mammedov
Signed-off-by: Heyi Guo
---
hw/arm/virt-acpi-build.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index cebec4c..b6fef28 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -265,7 +265,12 @@ s
Suggested-by: Igor Mammedov
Reviewed-by: Igor Mammedov
Signed-off-by: Heyi Guo
---
hw/arm/virt-acpi-build.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index d7e2e48..cebec4c 100644
--- a/hw/arm/virt-ac
:
- Refine commit message of patch 1/2
v4:
- Improve the code indention.
Cc: Shannon Zhao
Cc: Peter Maydell
Cc: "Michael S. Tsirkin"
Cc: Igor Mammedov
Heyi Guo (2):
hw/arm/acpi: simplify AML bit and/or statement
hw/arm/acpi: enable SHPC native hot plug
hw/arm/virt-acpi-bu
Got it; thanks.
Heyi
On 2019/3/7 0:20, Igor Mammedov wrote:
On Wed, 6 Mar 2019 21:09:11 +0800
Heyi Guo wrote:
Sorry, I didn't know the indention policy of qemu code. So we need to indent
the 2nd line just after the parentheses it belongs to?
See "[PATCH v6 0/2] CODING_STYLE: tr
d-by: Igor Mammedov
Signed-off-by: Heyi Guo
---
hw/arm/virt-acpi-build.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index d7e2e48..cebec4c 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
After the introduction of generic PCIe root port and PCIe-PCI bridge,
we will also have SHPC controller on ARM, so just enable SHPC native
hot plug.
Cc: Shannon Zhao
Cc: Peter Maydell
Cc: "Michael S. Tsirkin"
Cc: Igor Mammedov
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Heyi Gu
:
- Improve the code indention.
Cc: Shannon Zhao
Cc: Peter Maydell
Cc: "Michael S. Tsirkin"
Cc: Igor Mammedov
Heyi Guo (2):
hw/arm/acpi: simplify AML bit and/or statement
hw/arm/acpi: enable SHPC native hot plug
hw/arm/virt-acpi-build.c | 21 +
1 file c
Sorry, I didn't know the indention policy of qemu code. So we need to indent
the 2nd line just after the parentheses it belongs to?
Will change that and send next version.
Thanks,
Heyi
On 2019/3/6 18:33, Igor Mammedov wrote:
On Wed, 6 Mar 2019 06:03:48 +0800
Heyi Guo wrote:
The last
After the introduction of generic PCIe root port and PCIe-PCI bridge,
we will also have SHPC controller on ARM, so just enalbe SHPC native
hot plug.
Cc: Shannon Zhao
Cc: Peter Maydell
Cc: "Michael S. Tsirkin"
Cc: Igor Mammedov
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Heyi Gu
d-by: Igor Mammedov
Signed-off-by: Heyi Guo
---
hw/arm/virt-acpi-build.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 04b62c7..1c84e87 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -265,
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