support for having both 32 and 64 bit RISC-V CPUs in one QEMU machine

Hi, I have a situation when I need to use third-party 32-bit RISC-V CPU when rest is all 64-bit RISC-V CPUs. I have seen that some steps were already made in the direction to enable such configuration

50% of all time spent in victim_tlb_hit() !? (or case when OVPSim beats QEMU hands down)

Hi. I came across a case when OVPSim shamelessly outperforms QEMU. In 8 CPUs test, OPVSim single-thread is faster than QEMU tcg-single 4 times, and faster than QEMU mttcg by ~30%. I constructed a simple test case that reproduces it. When I profiled the test I saw that ~50% of all time QEMU

MTTCG vCPU time

Hi. I am looking for some advice. I model custom HW with 100+ CPUs. The CPUs are working on different parts of one big workload and sometimes have common SW synchronizations points, however, in between those synch points vCPUs seem to run with very different pace depending on how underlying OS

trace_exec_tb(tb, pc) does not have cpu index

Hi. I am wondering why trace events like trace_exec_tb(tb, pc) do not have cpu index, how to make sense of the trace in case of multiple vCPUs? I have changed it to trace_exec_tb(tb, pc, cpu->cpu_index) to read my trace, and now wondering should not it be there by default? Am I missing

How to synchronize CPUs on MMIO read?

Hi. I need to model some custom HW that synchronizes CPUs when they read MMIO register N: MMIO read does not return until another CPU writes to MMIO register M. I modeled this behavior with a) on MMIO read of N, save CPU into a list of waiting CPUs and put it asleep with