Re: [PATCH v3 3/4] tests: acpi: q35: add test for hmat nodes without initiators

2022-06-29 Thread Igor Mammedov
On Wed, 29 Jun 2022 11:35:10 +0200
Brice Goglin  wrote:

> Build a machine with 4 cores and 3 NUMA nodes.
> 1st NUMA is local to cores #0-1.
> 2nd NUMA is local to cores #2-3.
> 3rd NUMA has no initiator.
> HMAT SLLB says memory access performance of 3rd NUMA is lower,
> but it's identical for all cores hence all cores are its best initiator.
[...]

only commit message got fixed, the rest of comments weren't addressed (see prev 
rev)

> 
> Signed-off-by: Brice Goglin 
> Reviewed-by: Jonathan Cameron 
> ---
>   tests/qtest/bios-tables-test.c | 45 ++
>   1 file changed, 45 insertions(+)
> 
> diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
> index 359916c228..1252b166ff 100644
> --- a/tests/qtest/bios-tables-test.c
> +++ b/tests/qtest/bios-tables-test.c
> @@ -1461,6 +1461,50 @@ static void test_acpi_piix4_tcg_acpi_hmat(void)
>   test_acpi_tcg_acpi_hmat(MACHINE_PC);
>   }
>   
> +static void test_acpi_q35_tcg_acpi_hmat_noinitiator(void)
> +{
> +test_data data;
> +
> +memset(, 0, sizeof(data));
> +data.machine = MACHINE_Q35;
> +data.variant = ".acpihmat-noinitiator";
> +test_acpi_one(" -machine hmat=on"
> +  " -smp 4"
> +  " -m 128M"
> +  " -object memory-backend-ram,size=32M,id=ram0"
> +  " -object memory-backend-ram,size=32M,id=ram1"
> +  " -object memory-backend-ram,size=64M,id=ram2"
> +  " -numa node,nodeid=0,memdev=ram0,cpus=0-1"
> +  " -numa node,nodeid=1,memdev=ram1,cpus=2-3"
> +  " -numa node,nodeid=2,memdev=ram2"
> +  " -numa hmat-lb,initiator=0,target=0,hierarchy=memory,"
> +  "data-type=access-latency,latency=10"
> +  " -numa hmat-lb,initiator=0,target=0,hierarchy=memory,"
> +  "data-type=access-bandwidth,bandwidth=10485760"
> +  " -numa hmat-lb,initiator=0,target=1,hierarchy=memory,"
> +  "data-type=access-latency,latency=20"
> +  " -numa hmat-lb,initiator=0,target=1,hierarchy=memory,"
> +  "data-type=access-bandwidth,bandwidth=5242880"
> +  " -numa hmat-lb,initiator=0,target=2,hierarchy=memory,"
> +  "data-type=access-latency,latency=30"
> +  " -numa hmat-lb,initiator=0,target=2,hierarchy=memory,"
> +  "data-type=access-bandwidth,bandwidth=1048576"
> +  " -numa hmat-lb,initiator=1,target=0,hierarchy=memory,"
> +  "data-type=access-latency,latency=20"
> +  " -numa hmat-lb,initiator=1,target=0,hierarchy=memory,"
> +  "data-type=access-bandwidth,bandwidth=5242880"
> +  " -numa hmat-lb,initiator=1,target=1,hierarchy=memory,"
> +  "data-type=access-latency,latency=10"
> +  " -numa hmat-lb,initiator=1,target=1,hierarchy=memory,"
> +  "data-type=access-bandwidth,bandwidth=10485760"
> +  " -numa hmat-lb,initiator=1,target=2,hierarchy=memory,"
> +  "data-type=access-latency,latency=30"
> +  " -numa hmat-lb,initiator=1,target=2,hierarchy=memory,"
> +  "data-type=access-bandwidth,bandwidth=1048576",
> +  );
> +free_test_data();
> +}
> +
>   static void test_acpi_erst(const char *machine)
>   {
>   gchar *tmp_path = g_dir_make_tmp("qemu-test-erst.XX", NULL);
> @@ -1803,6 +1847,7 @@ int main(int argc, char *argv[])
>   qtest_add_func("acpi/q35/dimmpxm", test_acpi_q35_tcg_dimm_pxm);
>   qtest_add_func("acpi/piix4/acpihmat", 
> test_acpi_piix4_tcg_acpi_hmat);
>   qtest_add_func("acpi/q35/acpihmat", test_acpi_q35_tcg_acpi_hmat);
> +qtest_add_func("acpi/q35/acpihmat-noinitiator", 
> test_acpi_q35_tcg_acpi_hmat_noinitiator);
>   qtest_add_func("acpi/piix4/acpierst", test_acpi_piix4_acpi_erst);
>   qtest_add_func("acpi/q35/acpierst", test_acpi_q35_acpi_erst);
>   qtest_add_func("acpi/q35/applesmc", test_acpi_q35_applesmc);




Re: [PATCH 3/4] tests: acpi: q35: add test for hmat nodes without initiators

2022-06-28 Thread Igor Mammedov
On Thu, 23 Jun 2022 16:59:29 +0200
Brice Goglin  wrote:

maybe add a description of what you are testing


something along:
  machine with X numa nodes configured like this or that ...



> expected HMAT:
> 
> [000h    4]Signature : "HMAT"[Heterogeneous 
> Memory Attributes Table]
> [004h 0004   4] Table Length : 0120
> [008h 0008   1] Revision : 02
> [009h 0009   1] Checksum : 4F
> [00Ah 0010   6]   Oem ID : "BOCHS "
> [010h 0016   8] Oem Table ID : "BXPC"
> [018h 0024   4] Oem Revision : 0001
> [01Ch 0028   4]  Asl Compiler ID : "BXPC"
> [020h 0032   4]Asl Compiler Revision : 0001
> 
> [024h 0036   4] Reserved : 
> 
> [028h 0040   2]   Structure Type :  [Memory Proximity Domain 
> Attributes]
> [02Ah 0042   2] Reserved : 
> [02Ch 0044   4]   Length : 0028
> [030h 0048   2]Flags (decoded below) : 0001
>  Processor Proximity Domain Valid : 1
> [032h 0050   2]Reserved1 : 
> [034h 0052   4] Attached Initiator Proximity Domain : 
> [038h 0056   4]  Memory Proximity Domain : 
> [03Ch 0060   4]Reserved2 : 
> [040h 0064   8]Reserved3 : 
> [048h 0072   8]Reserved4 : 
> 
> [050h 0080   2]   Structure Type :  [Memory Proximity Domain 
> Attributes]
> [052h 0082   2] Reserved : 
> [054h 0084   4]   Length : 0028
> [058h 0088   2]Flags (decoded below) : 0001
>  Processor Proximity Domain Valid : 1
> [05Ah 0090   2]Reserved1 : 
> [05Ch 0092   4] Attached Initiator Proximity Domain : 0001
> [060h 0096   4]  Memory Proximity Domain : 0001
> [064h 0100   4]Reserved2 : 
> [068h 0104   8]Reserved3 : 
> [070h 0112   8]Reserved4 : 
> 
> [078h 0120   2]   Structure Type :  [Memory Proximity Domain 
> Attributes]
> [07Ah 0122   2] Reserved : 
> [07Ch 0124   4]   Length : 0028
> [080h 0128   2]Flags (decoded below) : 
>  Processor Proximity Domain Valid : 0
> [082h 0130   2]Reserved1 : 
> [084h 0132   4] Attached Initiator Proximity Domain : 0080
> [088h 0136   4]  Memory Proximity Domain : 0002
> [08Ch 0140   4]Reserved2 : 
> [090h 0144   8]Reserved3 : 
> [098h 0152   8]Reserved4 : 
> 
> [0A0h 0160   2]   Structure Type : 0001 [System Locality Latency 
> and Bandwidth Information]
> [0A2h 0162   2] Reserved : 
> [0A4h 0164   4]   Length : 0040
> [0A8h 0168   1]Flags (decoded below) : 00
>  Memory Hierarchy : 0
> [0A9h 0169   1]Data Type : 00
> [0AAh 0170   2]Reserved1 : 
> [0ACh 0172   4] Initiator Proximity Domains # : 0002
> [0B0h 0176   4]   Target Proximity Domains # : 0003
> [0B4h 0180   4]Reserved2 : 
> [0B8h 0184   8]  Entry Base Unit : 2710
> [0C0h 0192   4] Initiator Proximity Domain List : 
> [0C4h 0196   4] Initiator Proximity Domain List : 0001
> [0C8h 0200   4] Target Proximity Domain List : 
> [0CCh 0204   4] Target Proximity Domain List : 0001
> [0D0h 0208   4] Target Proximity Domain List : 0002
> [0D4h 0212   2]Entry : 0001
> [0D6h 0214   2]Entry : 0002
> [0D8h 0216   2]Entry : 0003
> [0DAh 0218   2]Entry : 0002
> [0DCh 0220   2]Entry : 0001
> [0DEh 0222   2]Entry : 0003
> 
> [0E0h 0224   2]   Structure Type : 0001 [System Locality Latency 
> and Bandwidth Information]
> [0E2h 0226   2] Reserved : 
> [0E4h 0228   4]   Length : 0040
> [0E8h 0232   1]Flags (decoded below) : 00
>  Memory Hierarchy : 0
> [0E9h 0233   1]Data Type : 03
> [0EAh 0234   2]Reserved1 : 
> [0ECh 0236   4] Initiator Proximity Domains # : 0002
> [0F0h 0240   4]   Target Proximity Domains # : 0003
> [0F4h 0244   4]Reserved2 : 
> [0F8h 0248   8]  Entry Base Unit : 0001
> [100h 0256   4] Initiator Proximity Domain List : 
> [104h 0260   4] Initiator Proximity Domain List : 0001
> [108h 0264   4] Target Proximity 

Re: [PATCH 2/4] tests: acpi: add and whitelist *.hmat-noinitiator expected blobs

2022-06-28 Thread Igor Mammedov
On Thu, 23 Jun 2022 16:59:01 +0200
Brice Goglin  wrote:

> .. which will be used by follow up hmat-noinitiator test-case.
> 
> Signed-off-by: Brice Goglin 

Acked-by: Igor Mammedov 

> ---
>   tests/data/acpi/q35/APIC.acpihmat-noinitiator | 0
>   tests/data/acpi/q35/DSDT.acpihmat-noinitiator | 0
>   tests/data/acpi/q35/FACP.acpihmat-noinitiator | 0
>   tests/data/acpi/q35/HMAT.acpihmat-noinitiator | 0
>   tests/data/acpi/q35/SRAT.acpihmat-noinitiator | 0
>   tests/qtest/bios-tables-test-allowed-diff.h   | 5 +
>   6 files changed, 5 insertions(+)
>   create mode 100644 tests/data/acpi/q35/APIC.acpihmat-noinitiator
>   create mode 100644 tests/data/acpi/q35/DSDT.acpihmat-noinitiator
>   create mode 100644 tests/data/acpi/q35/FACP.acpihmat-noinitiator
>   create mode 100644 tests/data/acpi/q35/HMAT.acpihmat-noinitiator
>   create mode 100644 tests/data/acpi/q35/SRAT.acpihmat-noinitiator
> 
> diff --git a/tests/data/acpi/q35/APIC.acpihmat-noinitiator 
> b/tests/data/acpi/q35/APIC.acpihmat-noinitiator
> new file mode 100644
> index 00..e69de29bb2
> diff --git a/tests/data/acpi/q35/DSDT.acpihmat-noinitiator 
> b/tests/data/acpi/q35/DSDT.acpihmat-noinitiator
> new file mode 100644
> index 00..e69de29bb2
> diff --git a/tests/data/acpi/q35/FACP.acpihmat-noinitiator 
> b/tests/data/acpi/q35/FACP.acpihmat-noinitiator
> new file mode 100644
> index 00..e69de29bb2
> diff --git a/tests/data/acpi/q35/HMAT.acpihmat-noinitiator 
> b/tests/data/acpi/q35/HMAT.acpihmat-noinitiator
> new file mode 100644
> index 00..e69de29bb2
> diff --git a/tests/data/acpi/q35/SRAT.acpihmat-noinitiator 
> b/tests/data/acpi/q35/SRAT.acpihmat-noinitiator
> new file mode 100644
> index 00..e69de29bb2
> diff --git a/tests/qtest/bios-tables-test-allowed-diff.h 
> b/tests/qtest/bios-tables-test-allowed-diff.h
> index dfb8523c8b..ae025e3a3e 100644
> --- a/tests/qtest/bios-tables-test-allowed-diff.h
> +++ b/tests/qtest/bios-tables-test-allowed-diff.h
> @@ -1 +1,6 @@
>   /* List of comma-separated changed AML files to ignore */
> +"tests/data/acpi/q35/APIC.acpihmat-noinitiator",
> +"tests/data/acpi/q35/DSDT.acpihmat-noinitiator",
> +"tests/data/acpi/q35/FACP.acpihmat-noinitiator",
> +"tests/data/acpi/q35/HMAT.acpihmat-noinitiator",
> +"tests/data/acpi/q35/SRAT.acpihmat-noinitiator",




Re: [PATCH 0/4] hmat acpi: Don't require initiator value in -numa

2022-06-28 Thread Igor Mammedov
On Thu, 23 Jun 2022 16:56:58 +0200
Brice Goglin  wrote:


here should be a brief introduction to series
[and changelog if it's not the first revision]


> Brice Goglin (4):
>hmat acpi: Don't require initiator value in -numa
>tests: acpi: add and whitelist *.hmat-noinitiator expected blobs
>tests: acpi: q35: add test for hmat nodes without initiators
>tests: acpi: q35: update expected blobs *.hmat-noinitiators
> 
>   hw/core/machine.c |   4 +-
>   tests/data/acpi/q35/APIC.acpihmat-noinitiator | Bin 0 -> 144 bytes
>   tests/data/acpi/q35/DSDT.acpihmat-noinitiator | Bin 0 -> 8553 bytes
>   tests/data/acpi/q35/FACP.acpihmat-noinitiator | Bin 0 -> 244 bytes
>   tests/data/acpi/q35/HMAT.acpihmat-noinitiator | Bin 0 -> 288 bytes
>   tests/data/acpi/q35/SRAT.acpihmat-noinitiator | Bin 0 -> 312 bytes
>   tests/qtest/bios-tables-test.c|  45 ++
>   7 files changed, 46 insertions(+), 3 deletions(-)
>   create mode 100644 tests/data/acpi/q35/APIC.acpihmat-noinitiator
>   create mode 100644 tests/data/acpi/q35/DSDT.acpihmat-noinitiator
>   create mode 100644 tests/data/acpi/q35/FACP.acpihmat-noinitiator
>   create mode 100644 tests/data/acpi/q35/HMAT.acpihmat-noinitiator
>   create mode 100644 tests/data/acpi/q35/SRAT.acpihmat-noinitiator
> 




Re: [PATCH 1/4] hmat acpi: Don't require initiator value in -numa

2022-06-28 Thread Igor Mammedov
On Thu, 23 Jun 2022 16:58:28 +0200
Brice Goglin  wrote:

> The "Memory Proximity Domain Attributes" structure of the ACPI HMAT
> has a "Processor Proximity Domain Valid" flag that is currently
> always set because Qemu -numa requires an initiator=X value
> when hmat=on. Unsetting this flag allows to create more complex
> memory topologies by having multiple best initiators for a single
> memory target.
> 
> This patch allows -numa without initiator=X when hmat=on by keeping
> the default value MAX_NODES in numa_state->nodes[i].initiator.
> All places reading numa_state->nodes[i].initiator already check
> whether it's different from MAX_NODES before using it.
> 
> Tested with
> qemu-system-x86_64 -accel kvm \
>   -machine pc,hmat=on \
>   -drive if=pflash,format=raw,file=./OVMF.fd \
>   -drive media=disk,format=qcow2,file=efi.qcow2 \
>   -smp 4 \
>   -m 3G \
>   -object memory-backend-ram,size=1G,id=ram0 \
>   -object memory-backend-ram,size=1G,id=ram1 \
>   -object memory-backend-ram,size=1G,id=ram2 \
>   -numa node,nodeid=0,memdev=ram0,cpus=0-1 \
>   -numa node,nodeid=1,memdev=ram1,cpus=2-3 \
>   -numa node,nodeid=2,memdev=ram2 \
>   -numa 
> hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-latency,latency=10
>  \
>   -numa 
> hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-bandwidth,bandwidth=10485760
>  \
>   -numa 
> hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-latency,latency=20
>  \
>   -numa 
> hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-bandwidth,bandwidth=5242880
>  \
>   -numa 
> hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-latency,latency=30
>  \
>   -numa 
> hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-bandwidth,bandwidth=1048576
>  \
>   -numa 
> hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-latency,latency=20
>  \
>   -numa 
> hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-bandwidth,bandwidth=5242880
>  \
>   -numa 
> hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-latency,latency=10
>  \
>   -numa 
> hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-bandwidth,bandwidth=10485760
>  \
>   -numa 
> hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-latency,latency=30
>  \
>   -numa 
> hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-bandwidth,bandwidth=1048576
> which reports NUMA node2 at same distance from both node0 and node1 as seen 
> in lstopo:
> Machine (2966MB total) + Package P#0
>NUMANode P#2 (979MB)
>Group0
>  NUMANode P#0 (980MB)
>  Core P#0 + PU P#0
>  Core P#1 + PU P#1
>Group0
>  NUMANode P#1 (1007MB)
>  Core P#2 + PU P#2
>  Core P#3 + PU P#3
> 
> Before this patch, we had to add ",initiator=X" to "-numa 
> node,nodeid=2,memdev=ram2".
> The lstopo output difference between initiator=1 and no initiator is:
> @@ -1,10 +1,10 @@
>   Machine (2966MB total) + Package P#0
> +  NUMANode P#2 (979MB)
> Group0
>   NUMANode P#0 (980MB)
>   Core P#0 + PU P#0
>   Core P#1 + PU P#1
> Group0
>   NUMANode P#1 (1007MB)
> -NUMANode P#2 (979MB)
>   Core P#2 + PU P#2
>   Core P#3 + PU P#3
> 
> Corresponding changes in the HMAT MPDA structure:
> @@ -49,10 +49,10 @@
>   [078h 0120   2]   Structure Type :  [Memory Proximity 
> Domain Attributes]
>   [07Ah 0122   2] Reserved : 
>   [07Ch 0124   4]   Length : 0028
> -[080h 0128   2]Flags (decoded below) : 0001
> -Processor Proximity Domain Valid : 1
> +[080h 0128   2]Flags (decoded below) : 
> +Processor Proximity Domain Valid : 0
>   [082h 0130   2]Reserved1 : 
> -[084h 0132   4] Attached Initiator Proximity Domain : 0001
> +[084h 0132   4] Attached Initiator Proximity Domain : 0080
 
where does this value come from?


>   [088h 0136   4]  Memory Proximity Domain : 0002
>   [08Ch 0140   4]Reserved2 : 
>   [090h 0144   8]Reserved3 : 
> 
> Final HMAT SLLB structures:
> [0A0h 0160   2]   Structure Type : 0001 [System Locality Latency 
> and Bandwidth Information]
> [0A2h 0162   2] Reserved : 
> [0A4h 0164   4]   Length : 0040
> [0A8h 0168   1]Flags (decoded below) : 00
>  Memory Hierarchy : 0
> [0A9h 0169   1]Data Type : 00
> [0AAh 0170   2]Reserved1 : 
> [0ACh 0172   4] Initiator Proximity Domains # : 0002
> [0B0h 0176   4]   Target Proximity Domains # : 0003
> [0B4h 0180   4]Reserved2 : 
> [0B8h 0184   8]  Entry Base Unit : 2710
> [0C0h 0192   4] Initiator Proximity Domain List : 
> [0C4h 0196   4] Initiator Proximity Domain 

Re: [PATCH v5 4/5] i386/pc: relocate 4g start to 1T where applicable

2022-06-28 Thread Igor Mammedov
On Mon, 20 Jun 2022 19:13:46 +0100
Joao Martins  wrote:

> On 6/20/22 17:36, Joao Martins wrote:
> > On 6/20/22 15:27, Igor Mammedov wrote:  
> >> On Fri, 17 Jun 2022 14:33:02 +0100
> >> Joao Martins  wrote:  
> >>> On 6/17/22 13:32, Igor Mammedov wrote:  
> >>>> On Fri, 17 Jun 2022 13:18:38 +0100
> >>>> Joao Martins  wrote:
> >>>>> On 6/16/22 15:23, Igor Mammedov wrote:
> >>>>>> On Fri, 20 May 2022 11:45:31 +0100
> >>>>>> Joao Martins  wrote:
> >>>>>>> +hwaddr above_4g_mem_start,
> >>>>>>> +uint64_t pci_hole64_size)
> >>>>>>> +{
> >>>>>>> +PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
> >>>>>>> +X86MachineState *x86ms = X86_MACHINE(pcms);
> >>>>>>> +MachineState *machine = MACHINE(pcms);
> >>>>>>> +ram_addr_t device_mem_size = 0;
> >>>>>>> +hwaddr base;
> >>>>>>> +
> >>>>>>> +if (!x86ms->above_4g_mem_size) {
> >>>>>>> +   /*
> >>>>>>> +* 32-bit pci hole goes from
> >>>>>>> +* end-of-low-ram (@below_4g_mem_size) to IOAPIC.
> >>>>>>> +*/
> >>>>>>> +return IO_APIC_DEFAULT_ADDRESS - 1;  
> >>>>>>
> >>>>>> lack of above_4g_mem, doesn't mean absence of device_mem_size or 
> >>>>>> anything else
> >>>>>> that's located above it.
> >>>>>>   
> >>>>>
> >>>>> True. But the intent is to fix 32-bit boundaries as one of the qtests 
> >>>>> was failing
> >>>>> otherwise. We won't hit the 1T hole, hence a nop.
> >>>>
> >>>> I don't get the reasoning, can you clarify it pls?
> >>>> 
> >>>
> >>> I was trying to say that what lead me here was a couple of qtests 
> >>> failures (from v3->v4).
> >>>
> >>> I was doing this before based on pci_hole64. phys-bits=32 was for example 
> >>> one
> >>> of the test failures, and pci-hole64 sits above what 32-bit can 
> >>> reference.  
> >>
> >> if user sets phys-bits=32, then nothing above 4Gb should work (be usable)
> >> (including above-4g-ram, hotplug region or pci64 hole or sgx or cxl)
> >>
> >> and this doesn't look to me as AMD specific issue
> >>
> >> perhaps do a phys-bits check as a separate patch
> >> that will error out if max_used_gpa is above phys-bits limit
> >> (maybe at machine_done time)
> >> (i.e. defining max_gpa and checking if compatible with configured cpu
> >> are 2 different things)
> >>
> >> (it might be possible that tests need to be fixed too to account for it)
> >>  
> > 
> > My old notes (from v3) tell me with such a check these tests were exiting 
> > early thanks to
> > that error:
> > 
> >  1/56 qemu:qtest+qtest-x86_64 / qtest-x86_64/qom-test   ERROR   
> > 0.07s
> >   killed by signal 6 SIGABRT
> >  4/56 qemu:qtest+qtest-x86_64 / qtest-x86_64/test-hmp   ERROR   
> > 0.07s
> >   killed by signal 6 SIGABRT
> >  7/56 qemu:qtest+qtest-x86_64 / qtest-x86_64/boot-serial-test   ERROR   
> > 0.07s
> >   killed by signal 6 SIGABRT
> > 44/56 qemu:qtest+qtest-x86_64 / qtest-x86_64/test-x86-cpuid-compat  ERROR   
> > 0.09s
> >   killed by signal 6 SIGABRT
> > 45/56 qemu:qtest+qtest-x86_64 / qtest-x86_64/numa-test  ERROR   
> > 0.17s
> >   killed by signal 6 SIGABRT
> > 
> > But the real reason these fail is not at all related to CPU phys bits,
> > but because we just don't handle the case where no pci_hole64 is supposed 
> > to exist (which
> > is what that other check is trying to do) e.g. A VM with -m 1G would
> > observe the same thing i.e. the computations after that conditional are all 
> > for the pci
> > hole64, which acounts for SGX/CXL/hotplug or etc which consequently means 
> > it's *errousnly*
> > bigger than phys-bits=32 (by definition). So the error_report is just 
> > telling me that
> > pc_max_used_gpa() is just incorrect without the !x86ms->above_4g_mem_size 
> > check.
> > 
&

Re: [PATCH] hmat acpi: Don't require initiator value in -numa when hmat=on

2022-06-20 Thread Igor Mammedov
On Mon, 20 Jun 2022 17:24:18 +0200
Brice Goglin  wrote:

> Le 20/06/2022 à 15:27, Igor Mammedov a écrit Machine (2966MB total) + 
> Package P#0
> >> NUMANode P#2 (979MB)
> >> Group0
> >>   NUMANode P#0 (980MB)
> >>   Core P#0 + PU P#0
> >>   Core P#1 + PU P#1
> >> Group0
> >>   NUMANode P#1 (1007MB)
> >>   Core P#2 + PU P#2
> >>   Core P#3 + PU P#3  
> > here should be a dis-assembled dump of generated HMAT table  
> 
> 
> Hello
> 
> Like what I added at the end of 
> https://github.com/bgoglin/qemu/commit/d9b3f5cb1514adafa644afcc2a363f2dc9795a32
>  
> ?
yep, only full version including headers.

(install acpica-tools on host and then when
you run your test with 'make V=1 check-qtest', it will dump
diff on console for you)

> > + a test case, see tests/qtest/bios-tables-test.c
> > for the process (at tho top) and test examples  
> 
> 
> https://github.com/bgoglin/qemu/commit/643dfa2de8b3e1f5b5675825e5d1be5c93a9549c
> 
> This passes make check V=1 but I am really not sure about what I did. 
> The doc is far from easy for new contributors. Only HMAT matters here, 

improvements to doc comment are welcome

> but it looks like it wanted some other tables too.

if test can't find a table with data.variant, it defaults to checking
against suffix-less variant if such exists.

you will need to provide all tables for your config that differ from
default one (i.e. not only HMAT one).

also CI runs on memory constrained systems, so limit RAM usage
to possible minimum (see other numa tests)

> Also I don't know 
> about pc vs piix4 vs q35, what "tcg" is, etc.

your case is not tcg or kvm specific, so put it in generic x86 section
(just like you did) and I'd pick q35 as used machine (though it should
work with pc too)

> 
> Advices appreciated.
> 
> 
> How are we supposed to send patches that contain binary changes?

here is a recent example of adding a new test:
https://mail.gnu.org/archive/html/qemu-devel/2022-06/msg01320.html
https://mail.gnu.org/archive/html/qemu-devel/2022-06/msg01320.html
https://mail.gnu.org/archive/html/qemu-devel/2022-06/msg01320.html

idea of splitting it on several patches is to keeps
series bisect-able
  1. whitelist changes/add empty files if necessary,
  2. add test which will spit warnings and one can see what has been 
changed/added
  3. update expected blobs and remove whitelisting, so any unexpected change
 will trigger test failure

(compile after each step to make sure patches are split correctly)

> 
> Brice
> 
> 
> 




Re: [PATCH v5 4/5] i386/pc: relocate 4g start to 1T where applicable

2022-06-20 Thread Igor Mammedov
On Fri, 17 Jun 2022 14:33:02 +0100
Joao Martins  wrote:

> On 6/17/22 13:32, Igor Mammedov wrote:
> > On Fri, 17 Jun 2022 13:18:38 +0100
> > Joao Martins  wrote:  
> >> On 6/16/22 15:23, Igor Mammedov wrote:  
> >>> On Fri, 20 May 2022 11:45:31 +0100
> >>> Joao Martins  wrote:  
> >>>> +hwaddr above_4g_mem_start,
> >>>> +uint64_t pci_hole64_size)
> >>>> +{
> >>>> +PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
> >>>> +X86MachineState *x86ms = X86_MACHINE(pcms);
> >>>> +MachineState *machine = MACHINE(pcms);
> >>>> +ram_addr_t device_mem_size = 0;
> >>>> +hwaddr base;
> >>>> +
> >>>> +if (!x86ms->above_4g_mem_size) {
> >>>> +   /*
> >>>> +* 32-bit pci hole goes from
> >>>> +* end-of-low-ram (@below_4g_mem_size) to IOAPIC.
> >>>> +*/
> >>>> +return IO_APIC_DEFAULT_ADDRESS - 1;
> >>>
> >>> lack of above_4g_mem, doesn't mean absence of device_mem_size or anything 
> >>> else
> >>> that's located above it.
> >>> 
> >>
> >> True. But the intent is to fix 32-bit boundaries as one of the qtests was 
> >> failing
> >> otherwise. We won't hit the 1T hole, hence a nop.  
> > 
> > I don't get the reasoning, can you clarify it pls?
> >   
> 
> I was trying to say that what lead me here was a couple of qtests failures 
> (from v3->v4).
> 
> I was doing this before based on pci_hole64. phys-bits=32 was for example one
> of the test failures, and pci-hole64 sits above what 32-bit can reference.

if user sets phys-bits=32, then nothing above 4Gb should work (be usable)
(including above-4g-ram, hotplug region or pci64 hole or sgx or cxl)

and this doesn't look to me as AMD specific issue

perhaps do a phys-bits check as a separate patch
that will error out if max_used_gpa is above phys-bits limit
(maybe at machine_done time)
(i.e. defining max_gpa and checking if compatible with configured cpu
are 2 different things)

(it might be possible that tests need to be fixed too to account for it)

> >>  Unless we plan on using
> >> pc_max_used_gpa() for something else other than this.  
> > 
> > Even if '!above_4g_mem_sizem', we can still have hotpluggable memory region
> > present and that can  hit 1Tb. The same goes for pci64_hole if it's 
> > configured
> > large enough on CLI.
> >   
> So hotpluggable memory seems to assume it sits above 4g mem.
> 
> pci_hole64 likewise as it uses similar computations as hotplug.
> 
> Unless I am misunderstanding something here.
> 
> > Looks like guesstimate we could use is taking pci64_hole_end as max used GPA
> >   
> I think this was what I had before (v3[0]) and did not work.

that had been tied to host's phys-bits directly, all in one patch
and duplicating existing pc_pci_hole64_start().
 
> Let me revisit this edge case again.
> 
> [0] 
> https://lore.kernel.org/all/20220223184455.9057-5-joao.m.mart...@oracle.com/
> 




Re: [PATCH] hmat acpi: Don't require initiator value in -numa when hmat=on

2022-06-20 Thread Igor Mammedov
On Wed, 6 Apr 2022 14:29:56 +0200
Brice Goglin  wrote:

> From: Brice Goglin 
> 
> The "Memory Proximity Domain Attributes" structure of the ACPI HMAT
> has a "Processor Proximity Domain Valid" flag that is currently
> always set because Qemu -numa requires initiator=X when hmat=on.
>
> Unsetting this flag allows to create more complex memory topologies
> by having multiple best initiators for a single memory target.
> 
> This patch allows -numa with initiator=X when hmat=on by keeping
> the default value MAX_NODES in numa_state->nodes[i].initiator.
> All places reading numa_state->nodes[i].initiator already check
> whether it's different from MAX_NODES before using it. And
> hmat_build_table_structs() already unset the Valid flag when needed.
> 
> Tested with
> qemu-system-x86_64 -accel kvm \
>   -machine pc,hmat=on \
>   -drive if=pflash,format=raw,file=./OVMF.fd \
>   -drive media=disk,format=qcow2,file=efi.qcow2 \
>   -smp 4 \
>   -m 3G \
>   -object memory-backend-ram,size=1G,id=ram0 \
>   -object memory-backend-ram,size=1G,id=ram1 \
>   -object memory-backend-ram,size=1G,id=ram2 \
>   -numa node,nodeid=0,memdev=ram0,cpus=0-1 \
>   -numa node,nodeid=1,memdev=ram1,cpus=2-3 \
>   -numa node,nodeid=2,memdev=ram2 \
>   -numa 
> hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-latency,latency=10
>  \
>   -numa 
> hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-bandwidth,bandwidth=10485760
>  \
>   -numa 
> hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-latency,latency=20
>  \
>   -numa 
> hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-bandwidth,bandwidth=5242880
>  \
>   -numa 
> hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-latency,latency=30
>  \
>   -numa 
> hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-bandwidth,bandwidth=1048576
>  \
>   -numa 
> hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-latency,latency=20
>  \
>   -numa 
> hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-bandwidth,bandwidth=5242880
>  \
>   -numa 
> hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-latency,latency=10
>  \
>   -numa 
> hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-bandwidth,bandwidth=10485760
>  \
>   -numa 
> hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-latency,latency=30
>  \
>   -numa 
> hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-bandwidth,bandwidth=1048576
>  \
> 

> This exposes NUMA node2 at same distance from both node0 and node1 as seen in 
> lstopo:
> 
> Machine (2966MB total) + Package P#0
>NUMANode P#2 (979MB)
>Group0
>  NUMANode P#0 (980MB)
>  Core P#0 + PU P#0
>  Core P#1 + PU P#1
>Group0
>  NUMANode P#1 (1007MB)
>  Core P#2 + PU P#2
>  Core P#3 + PU P#3

here should be a dis-assembled dump of generated HMAT table
+ a test case, see tests/qtest/bios-tables-test.c
for the process (at tho top) and test examples

> 
> Signed-off-by: Brice Goglin 
> ---
>   hw/core/machine.c | 4 +---
>   1 file changed, 1 insertion(+), 3 deletions(-)
> 
> diff --git a/hw/core/machine.c b/hw/core/machine.c
> index d856485cb4..9884ef7ac6 100644
> --- a/hw/core/machine.c
> +++ b/hw/core/machine.c
> @@ -1012,9 +1012,7 @@ static void numa_validate_initiator(NumaState 
> *numa_state)
>   
>   for (i = 0; i < numa_state->num_nodes; i++) {
>   if (numa_info[i].initiator == MAX_NODES) {
> -error_report("The initiator of NUMA node %d is missing, use "
> - "'-numa node,initiator' option to declare it", i);
> -exit(1);
> +continue;
>   }
>   
>   if (!numa_info[numa_info[i].initiator].present) {




Re: [PATCH v1] MAINTAINERS: Collect memory device files in "Memory devices"

2022-06-17 Thread Igor Mammedov
On Fri, 17 Jun 2022 14:31:51 +0200
David Hildenbrand  wrote:

> Xiao Guangrong doesn't have enough time to actively review or contribute
> to our NVDIMM implementation. Let's dissolve the "NVDIMM" section, moving
> relevant ACPI parts to "ACPI/SMBIOS" and moving memory device stuff into a
> new "Memory devices" section. Make that new section cover other memory
> device stuff as well.
> 
> We can now drop the "hw/mem/*" rule from "ACPI/SMBIOS". Note that
> hw/acpi/nvdimm.c is already covered by "ACPI/SMBIOS".
> 
> The following files in hw/mem don't fall into the TYPE_MEMPORY_DEVICE
> category:
> * hw/mem/cxl_type3.c is CXL specific and belongs to "Compute Express Link"
> * hw/mem/sparse-mem.c is already covered by "Device Fuzzing"
> * hw/mem/npcm7xx_mc.c is already covered by "Nuvoton NPCM7xx"
> 
> Thanks Xiao for your work on NVDIMM!
> 
> Cc: Ben Widawsky 
> Cc: Jonathan Cameron 
> Cc: Michael S. Tsirkin 
> Cc: Igor Mammedov 
> Cc: Ani Sinha 
> Cc: Xiao Guangrong 
> Cc: "Philippe Mathieu-Daudé" 
> Cc: Richard Henderson 
> Cc: Peter Maydell 
> Cc: Julia Suvorova 
> Signed-off-by: David Hildenbrand 


Acked-by: Igor Mammedov 

> ---
>  MAINTAINERS | 25 +++--
>  1 file changed, 15 insertions(+), 10 deletions(-)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index aaa649a50d..909e8dbb1b 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1840,7 +1840,6 @@ R: Ani Sinha 
>  S: Supported
>  F: include/hw/acpi/*
>  F: include/hw/firmware/smbios.h
> -F: hw/mem/*
>  F: hw/acpi/*
>  F: hw/smbios/*
>  F: hw/i386/acpi-build.[hc]
> @@ -1851,6 +1850,7 @@ F: tests/qtest/acpi-utils.[hc]
>  F: tests/data/acpi/
>  F: docs/specs/acpi_cpu_hotplug.rst
>  F: docs/specs/acpi_mem_hotplug.rst
> +F: docs/specs/acpi_nvdimm.rst
>  F: docs/specs/acpi_pci_hotplug.rst
>  F: docs/specs/acpi_hw_reduced_hotplug.rst
>  
> @@ -2158,15 +2158,6 @@ F: qapi/rocker.json
>  F: tests/rocker/
>  F: docs/specs/rocker.txt
>  
> -NVDIMM
> -M: Xiao Guangrong 
> -S: Maintained
> -F: hw/acpi/nvdimm.c
> -F: hw/mem/nvdimm.c
> -F: include/hw/mem/nvdimm.h
> -F: docs/nvdimm.txt
> -F: docs/specs/acpi_nvdimm.rst
> -
>  e1000x
>  M: Dmitry Fleytman 
>  S: Maintained
> @@ -2588,6 +2579,7 @@ M: Ben Widawsky 
>  M: Jonathan Cameron 
>  S: Supported
>  F: hw/cxl/
> +F: hw/mem/cxl_type3.c
>  F: include/hw/cxl/
>  
>  Dirty Bitmaps
> @@ -2704,6 +2696,19 @@ F: softmmu/physmem.c
>  F: include/exec/memory-internal.h
>  F: scripts/coccinelle/memory-region-housekeeping.cocci
>  
> +Memory devices
> +M: David Hildenbrand 
> +M: Igor Mammedov 
> +R: Xiao Guangrong 
> +S: Supported
> +F: hw/mem/memory-device.c
> +F: hw/mem/nvdimm.c
> +F: hw/mem/pc-dimm.c
> +F: include/hw/mem/memory-device.h
> +F: include/hw/mem/nvdimm.h
> +F: include/hw/mem/pc-dimm.h
> +F: docs/nvdimm.txt
> +
>  SPICE
>  M: Gerd Hoffmann 
>  S: Odd Fixes




Re: [PATCH v5 4/5] i386/pc: relocate 4g start to 1T where applicable

2022-06-17 Thread Igor Mammedov
On Fri, 17 Jun 2022 13:18:38 +0100
Joao Martins  wrote:

> On 6/16/22 15:23, Igor Mammedov wrote:
> > On Fri, 20 May 2022 11:45:31 +0100
> > Joao Martins  wrote:
> >   
> >> It is assumed that the whole GPA space is available to be DMA
> >> addressable, within a given address space limit, expect for a  
> >^^^ typo?
> >   
> Yes, it should have been 'except'.
> 
> >> tiny region before the 4G. Since Linux v5.4, VFIO validates
> >> whether the selected GPA is indeed valid i.e. not reserved by
> >> IOMMU on behalf of some specific devices or platform-defined
> >> restrictions, and thus failing the ioctl(VFIO_DMA_MAP) with
> >>  -EINVAL.
> >>
> >> AMD systems with an IOMMU are examples of such platforms and
> >> particularly may only have these ranges as allowed:
> >>
> >> - fedf (0  .. 3.982G)
> >>fef0 - 00fc (3.983G .. 1011.9G)
> >>0100 -  (1Tb.. 16Pb[*])
> >>
> >> We already account for the 4G hole, albeit if the guest is big
> >> enough we will fail to allocate a guest with  >1010G due to the
> >> ~12G hole at the 1Tb boundary, reserved for HyperTransport (HT).
> >>
> >> [*] there is another reserved region unrelated to HT that exists
> >> in the 256T boundaru in Fam 17h according to Errata #1286,  
> >   ^ ditto
> >   
> Fixed.
> 
> >> documeted also in "Open-Source Register Reference for AMD Family
> >> 17h Processors (PUB)"
> >>
> >> When creating the region above 4G, take into account that on AMD
> >> platforms the HyperTransport range is reserved and hence it
> >> cannot be used either as GPAs. On those cases rather than
> >> establishing the start of ram-above-4g to be 4G, relocate instead
> >> to 1Tb. See AMD IOMMU spec, section 2.1.2 "IOMMU Logical
> >> Topology", for more information on the underlying restriction of
> >> IOVAs.
> >>
> >> After accounting for the 1Tb hole on AMD hosts, mtree should
> >> look like:
> >>
> >> -7fff (prio 0, i/o):
> >> alias ram-below-4g @pc.ram -7fff
> >> 0100-01ff7fff (prio 0, i/o):
> >>alias ram-above-4g @pc.ram 8000-00ff
> >>
> >> If the relocation is done, we also add the the reserved HT
> >> e820 range as reserved.
> >>
> >> Default phys-bits on Qemu is TCG_PHYS_ADDR_BITS (40) which is enough
> >> to address 1Tb (0xff  ). On AMD platforms, if a
> >> ram-above-4g relocation may be desired and the CPU wasn't configured
> >> with a big enough phys-bits, print an error message to the user
> >> and do not make the relocation of the above-4g-region if phys-bits
> >> is too low.
> >>
> >> Suggested-by: Igor Mammedov 
> >> Signed-off-by: Joao Martins 
> >> ---
> >>  hw/i386/pc.c | 111 +++
> >>  1 file changed, 111 insertions(+)
> >>
> >> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> >> index af52d4ff89ef..652ae8ff9ccf 100644
> >> --- a/hw/i386/pc.c
> >> +++ b/hw/i386/pc.c
> >> @@ -796,6 +796,110 @@ void xen_load_linux(PCMachineState *pcms)
> >>  #define PC_ROM_ALIGN   0x800
> >>  #define PC_ROM_SIZE(PC_ROM_MAX - PC_ROM_MIN_VGA)
> >>  
> >> +/*
> >> + * AMD systems with an IOMMU have an additional hole close to the
> >> + * 1Tb, which are special GPAs that cannot be DMA mapped. Depending
> >> + * on kernel version, VFIO may or may not let you DMA map those ranges.
> >> + * Starting Linux v5.4 we validate it, and can't create guests on AMD 
> >> machines
> >> + * with certain memory sizes. It's also wrong to use those IOVA ranges
> >> + * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse.
> >> + * The ranges reserved for Hyper-Transport are:
> >> + *
> >> + * FD__h - FF__h
> >> + *
> >> + * The ranges represent the following:
> >> + *
> >> + * Base Address   Top Address  Use
> >> + *
> >> + * FD__h FD_F7FF_h Reserved interrupt address space
> >> + * FD_F800_h FD_F8FF_h Interrupt/EOI IntCtl
> >> + * FD_F900_h FD_F90F_h Legacy PIC IACK
> >> + * FD_F910

Re: [PATCH v5 3/5] i386/pc: pass pci_hole64_size to pc_memory_init()

2022-06-17 Thread Igor Mammedov
On Fri, 17 Jun 2022 12:13:45 +0100
Joao Martins  wrote:

> On 6/16/22 14:30, Igor Mammedov wrote:
> > On Fri, 20 May 2022 11:45:30 +0100
> > Joao Martins  wrote:
> >   
> >> Use the pre-initialized pci-host qdev and fetch the
> >> pci-hole64-size into pc_memory_init() newly added argument.
> >> piix needs a bit of care given all the !pci_enabled()
> >> and that the pci_hole64_size is private to i440fx.
> >>
> >> This is in preparation to determine that host-phys-bits are
> >> enough and for pci-hole64-size to be considered to relocate
> >> ram-above-4g to be at 1T (on AMD platforms).  
> > 
> > modulo nit blow
> > 
> > Reviewed-by: Igor Mammedov 
> >   
> 
> I haven't tackled the initialization nit below but I would assume
> you agree with the rest of the patch. Let me know if I should still
> add the Rb tag.

My ack still stands
 
> >>
> >> Signed-off-by: Joao Martins 
> >> ---
> >>  hw/i386/pc.c | 3 ++-
> >>  hw/i386/pc_piix.c| 5 -
> >>  hw/i386/pc_q35.c | 8 +++-
> >>  hw/pci-host/i440fx.c | 7 +++
> >>  include/hw/i386/pc.h | 3 ++-
> >>  include/hw/pci-host/i440fx.h | 1 +
> >>  6 files changed, 23 insertions(+), 4 deletions(-)
> >>
> >> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> >> index f7da1d5dd40d..af52d4ff89ef 100644
> >> --- a/hw/i386/pc.c
> >> +++ b/hw/i386/pc.c
> >> @@ -799,7 +799,8 @@ void xen_load_linux(PCMachineState *pcms)
> >>  void pc_memory_init(PCMachineState *pcms,
> >>  MemoryRegion *system_memory,
> >>  MemoryRegion *rom_memory,
> >> -MemoryRegion **ram_memory)
> >> +MemoryRegion **ram_memory,
> >> +uint64_t pci_hole64_size)
> >>  {
> >>  int linux_boot, i;
> >>  MemoryRegion *option_rom_mr;
> >> diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
> >> index 12d4a279c793..57bb5b8f2aea 100644
> >> --- a/hw/i386/pc_piix.c
> >> +++ b/hw/i386/pc_piix.c
> >> @@ -91,6 +91,7 @@ static void pc_init1(MachineState *machine,
> >>  MemoryRegion *pci_memory;
> >>  MemoryRegion *rom_memory;
> >>  ram_addr_t lowmem;
> >> +uint64_t hole64_size;  
> > 
> > init it to 0 right here to avoid chance of run amok uninitialized variable?
> >   
> I haven't done this given that mst disagreed, plus the fact that the code 
> style of
> the function seems to place the NULL initialization mostly left to else 
> conditional
> clause. Part of the reason I haven't inited @i440fx_dev to NULL here as well 
> (now
> i440fx_host. The location we use hole64_size is also the same location we are 
> using
> @i440fx_host.
> 
> >>  DeviceState *i440fx_dev;
> >>  
> >>  /*
> >> @@ -166,10 +167,12 @@ static void pc_init1(MachineState *machine,
> >>  memory_region_init(pci_memory, NULL, "pci", UINT64_MAX);
> >>  rom_memory = pci_memory;
> >>  i440fx_dev = qdev_new(host_type);
> >> +hole64_size = i440fx_pci_hole64_size(i440fx_dev);
> >>  } else {
> >>  pci_memory = NULL;
> >>  rom_memory = system_memory;
> >>  i440fx_dev = NULL;
> >> +hole64_size = 0;
> >>  }
> >>  
> >>  pc_guest_info_init(pcms);
> >> @@ -186,7 +189,7 @@ static void pc_init1(MachineState *machine,
> >>  /* allocate ram and load rom/bios */
> >>  if (!xen_enabled()) {
> >>  pc_memory_init(pcms, system_memory,
> >> -   rom_memory, _memory);
> >> +   rom_memory, _memory, hole64_size);
> >>  } else {
> >>  pc_system_flash_cleanup_unused(pcms);
> >>  if (machine->kernel_filename != NULL) {
> >> diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
> >> index 8d867bdb274a..4d5c2fbd976b 100644
> >> --- a/hw/i386/pc_q35.c
> >> +++ b/hw/i386/pc_q35.c
> >> @@ -138,6 +138,7 @@ static void pc_q35_init(MachineState *machine)
> >>  MachineClass *mc = MACHINE_GET_CLASS(machine);
> >>  bool acpi_pcihp;
> >>  bool keep_pci_slot_hpc;
> >> +uint64_t pci_hole64_size = 0;
> >>  
> >>  /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory
> >>   * and 256 Mbytes for PCI Express Enhan

Re: [PULL v2 25/86] hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142)

2022-06-17 Thread Igor Mammedov
On Fri, 17 Jun 2022 11:51:44 +0100
Jonathan Cameron  wrote:

> On Thu, 16 Jun 2022 16:45:00 +0200
> Igor Mammedov  wrote:
> 
> > On Mon, 16 May 2022 16:51:34 -0400
> > "Michael S. Tsirkin"  wrote:
> >   
> > > From: Ben Widawsky 
> > > 
> > > CXL host bridges themselves may have MMIO. Since host bridges don't have
> > > a BAR they are treated as special for MMIO.  This patch includes
> > > i386/pc support.
> > > Also hook up the device reset now that we have have the MMIO
> > > space in which the results are visible.
> > > 
> > > Note that we duplicate the PCI express case for the aml_build but
> > > the implementations will diverge when the CXL specific _OSC is
> > > introduced.
> > > 
> > > Signed-off-by: Ben Widawsky 
> > > Co-developed-by: Jonathan Cameron 
> > > Signed-off-by: Jonathan Cameron 
> > > Reviewed-by: Alex Bennée 
> > > Message-Id: <20220429144110.25167-24-jonathan.came...@huawei.com>
> > > Reviewed-by: Michael S. Tsirkin 
> > > Signed-off-by: Michael S. Tsirkin 
> > > ---
> > >  include/hw/cxl/cxl.h| 14 ++
> > >  hw/i386/acpi-build.c| 25 ++-
> > >  hw/i386/pc.c| 27 +++-
> > >  hw/pci-bridge/pci_expander_bridge.c | 66 ++---
> > >  4 files changed, 122 insertions(+), 10 deletions(-)
> > > 
> > > diff --git a/include/hw/cxl/cxl.h b/include/hw/cxl/cxl.h
> > > index 31af92fd5e..8d1a7245d0 100644
> > > --- a/include/hw/cxl/cxl.h
> > > +++ b/include/hw/cxl/cxl.h
> > > @@ -10,6 +10,7 @@
> > >  #ifndef CXL_H
> > >  #define CXL_H
> > >  
> > > +#include "hw/pci/pci_host.h"
> > >  #include "cxl_pci.h"
> > >  #include "cxl_component.h"
> > >  #include "cxl_device.h"
> > > @@ -17,8 +18,21 @@
> > >  #define CXL_COMPONENT_REG_BAR_IDX 0
> > >  #define CXL_DEVICE_REG_BAR_IDX 2
> > >  
> > > +#define CXL_WINDOW_MAX 10
> > > +
> > >  typedef struct CXLState {
> > >  bool is_enabled;
> > > +MemoryRegion host_mr;
> > > +unsigned int next_mr_idx;
> > >  } CXLState;
> > >  
> > > +struct CXLHost {
> > > +PCIHostState parent_obj;
> > > +
> > > +CXLComponentState cxl_cstate;
> > > +};
> > > +
> > > +#define TYPE_PXB_CXL_HOST "pxb-cxl-host"
> > > +OBJECT_DECLARE_SIMPLE_TYPE(CXLHost, PXB_CXL_HOST)
> > > +
> > >  #endif
> > > diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
> > > index dcf6ece3d0..2d81b0f40c 100644
> > > --- a/hw/i386/acpi-build.c
> > > +++ b/hw/i386/acpi-build.c
> > > @@ -28,6 +28,7 @@
> > >  #include "qemu/bitmap.h"
> > >  #include "qemu/error-report.h"
> > >  #include "hw/pci/pci.h"
> > > +#include "hw/cxl/cxl.h"
> > >  #include "hw/core/cpu.h"
> > >  #include "target/i386/cpu.h"
> > >  #include "hw/misc/pvpanic.h"
> > > @@ -1572,10 +1573,21 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
> > >  }
> > >  
> > >  scope = aml_scope("\\_SB");
> > > -dev = aml_device("PC%.02X", bus_num);
> > > +
> > > +if (pci_bus_is_cxl(bus)) {
> > > +dev = aml_device("CL%.02X", bus_num);
> > > +} else {
> > > +dev = aml_device("PC%.02X", bus_num);
> > > +}
> > >  aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
> > >  aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
> > > -if (pci_bus_is_express(bus)) {
> > > +if (pci_bus_is_cxl(bus)) {
> > > +aml_append(dev, aml_name_decl("_HID", 
> > > aml_eisaid("PNP0A08")));
> > > +aml_append(dev, aml_name_decl("_CID", 
> > > aml_eisaid("PNP0A03")));
> > > +
> > > +/* Expander bridges do not have ACPI PCI Hot-plug 
> > > enabled */
> > > +aml_append(dev, build_q35_osc_method(true));
> > > +} else if (pci_bus_is_express(bus)) {
> > >  aml_append(dev, aml_name_decl("

Re: [PULL v2 25/86] hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142)

2022-06-16 Thread Igor Mammedov
On Mon, 16 May 2022 16:51:34 -0400
"Michael S. Tsirkin"  wrote:

> From: Ben Widawsky 
> 
> CXL host bridges themselves may have MMIO. Since host bridges don't have
> a BAR they are treated as special for MMIO.  This patch includes
> i386/pc support.
> Also hook up the device reset now that we have have the MMIO
> space in which the results are visible.
> 
> Note that we duplicate the PCI express case for the aml_build but
> the implementations will diverge when the CXL specific _OSC is
> introduced.
> 
> Signed-off-by: Ben Widawsky 
> Co-developed-by: Jonathan Cameron 
> Signed-off-by: Jonathan Cameron 
> Reviewed-by: Alex Bennée 
> Message-Id: <20220429144110.25167-24-jonathan.came...@huawei.com>
> Reviewed-by: Michael S. Tsirkin 
> Signed-off-by: Michael S. Tsirkin 
> ---
>  include/hw/cxl/cxl.h| 14 ++
>  hw/i386/acpi-build.c| 25 ++-
>  hw/i386/pc.c| 27 +++-
>  hw/pci-bridge/pci_expander_bridge.c | 66 ++---
>  4 files changed, 122 insertions(+), 10 deletions(-)
> 
> diff --git a/include/hw/cxl/cxl.h b/include/hw/cxl/cxl.h
> index 31af92fd5e..8d1a7245d0 100644
> --- a/include/hw/cxl/cxl.h
> +++ b/include/hw/cxl/cxl.h
> @@ -10,6 +10,7 @@
>  #ifndef CXL_H
>  #define CXL_H
>  
> +#include "hw/pci/pci_host.h"
>  #include "cxl_pci.h"
>  #include "cxl_component.h"
>  #include "cxl_device.h"
> @@ -17,8 +18,21 @@
>  #define CXL_COMPONENT_REG_BAR_IDX 0
>  #define CXL_DEVICE_REG_BAR_IDX 2
>  
> +#define CXL_WINDOW_MAX 10
> +
>  typedef struct CXLState {
>  bool is_enabled;
> +MemoryRegion host_mr;
> +unsigned int next_mr_idx;
>  } CXLState;
>  
> +struct CXLHost {
> +PCIHostState parent_obj;
> +
> +CXLComponentState cxl_cstate;
> +};
> +
> +#define TYPE_PXB_CXL_HOST "pxb-cxl-host"
> +OBJECT_DECLARE_SIMPLE_TYPE(CXLHost, PXB_CXL_HOST)
> +
>  #endif
> diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
> index dcf6ece3d0..2d81b0f40c 100644
> --- a/hw/i386/acpi-build.c
> +++ b/hw/i386/acpi-build.c
> @@ -28,6 +28,7 @@
>  #include "qemu/bitmap.h"
>  #include "qemu/error-report.h"
>  #include "hw/pci/pci.h"
> +#include "hw/cxl/cxl.h"
>  #include "hw/core/cpu.h"
>  #include "target/i386/cpu.h"
>  #include "hw/misc/pvpanic.h"
> @@ -1572,10 +1573,21 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
>  }
>  
>  scope = aml_scope("\\_SB");
> -dev = aml_device("PC%.02X", bus_num);
> +
> +if (pci_bus_is_cxl(bus)) {
> +dev = aml_device("CL%.02X", bus_num);
> +} else {
> +dev = aml_device("PC%.02X", bus_num);
> +}
>  aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
>  aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
> -if (pci_bus_is_express(bus)) {
> +if (pci_bus_is_cxl(bus)) {
> +aml_append(dev, aml_name_decl("_HID", 
> aml_eisaid("PNP0A08")));
> +aml_append(dev, aml_name_decl("_CID", 
> aml_eisaid("PNP0A03")));
> +
> +/* Expander bridges do not have ACPI PCI Hot-plug enabled */
> +aml_append(dev, build_q35_osc_method(true));
> +} else if (pci_bus_is_express(bus)) {
>  aml_append(dev, aml_name_decl("_HID", 
> aml_eisaid("PNP0A08")));
>  aml_append(dev, aml_name_decl("_CID", 
> aml_eisaid("PNP0A03")));
>  
> @@ -1595,6 +1607,15 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
>  aml_append(dev, aml_name_decl("_CRS", crs));
>  aml_append(scope, dev);
>  aml_append(dsdt, scope);
> +
> +/* Handle the ranges for the PXB expanders */
> +if (pci_bus_is_cxl(bus)) {
> +MemoryRegion *mr = >cxl_devices_state->host_mr;
> +uint64_t base = mr->addr;
> +
> +crs_range_insert(crs_range_set.mem_ranges, base,
> + base + memory_region_size(mr) - 1);
> +}
>  }
>  }
>  
> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> index 45e2d6092f..03d14f6564 100644
> --- a/hw/i386/pc.c
> +++ b/hw/i386/pc.c
> @@ -75,6 +75,7 @@
>  #include "acpi-build.h"
>  #include "hw/mem/pc-dimm.h"
>  #include "hw/mem/nvdimm.h"
> +#include "hw/cxl/cxl.h"
>  #include "qapi/error.h"
>  #include "qapi/qapi-visit-common.h"
>  #include "qapi/qapi-visit-machine.h"
> @@ -816,6 +817,7 @@ void pc_memory_init(PCMachineState *pcms,
>  MachineClass *mc = MACHINE_GET_CLASS(machine);
>  PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
>  X86MachineState *x86ms = X86_MACHINE(pcms);
> +hwaddr cxl_base;
>  
>  assert(machine->ram_size == x86ms->below_4g_mem_size +
>  x86ms->above_4g_mem_size);
> @@ -905,6 +907,26 @@ void pc_memory_init(PCMachineState *pcms,
>  >device_memory->mr);
>  }
>  
> +if (machine->cxl_devices_state->is_enabled) 

Re: [PATCH v5 5/5] i386/pc: restrict AMD only enforcing of valid IOVAs to new machine type

2022-06-16 Thread Igor Mammedov
On Fri, 20 May 2022 11:45:32 +0100
Joao Martins  wrote:

> The added enforcing is only relevant in the case of AMD where the
> range right before the 1TB is restricted and cannot be DMA mapped
> by the kernel consequently leading to IOMMU INVALID_DEVICE_REQUEST
> or possibly other kinds of IOMMU events in the AMD IOMMU.
> 
> Although, there's a case where it may make sense to disable the
> IOVA relocation/validation when migrating from a
> non-valid-IOVA-aware qemu to one that supports it.
> 
> Relocating RAM regions to after the 1Tb hole has consequences for
> guest ABI because we are changing the memory mapping, so make
> sure that only new machine enforce but not older ons.

is old machine with so much ram going to work and not explode
even without iommu?

> Signed-off-by: Joao Martins 
> ---
>  hw/i386/pc.c | 7 +--
>  hw/i386/pc_piix.c| 2 ++
>  hw/i386/pc_q35.c | 2 ++
>  include/hw/i386/pc.h | 1 +
>  4 files changed, 10 insertions(+), 2 deletions(-)
> 
> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> index 652ae8ff9ccf..62f9af91f19f 100644
> --- a/hw/i386/pc.c
> +++ b/hw/i386/pc.c
> @@ -862,6 +862,7 @@ static hwaddr x86_max_phys_addr(PCMachineState *pcms,
>  static void x86_update_above_4g_mem_start(PCMachineState *pcms,
>uint64_t pci_hole64_size)
>  {
> +PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
>  X86MachineState *x86ms = X86_MACHINE(pcms);
>  CPUX86State *env = _CPU(first_cpu)->env;
>  hwaddr start = x86ms->above_4g_mem_start;
> @@ -870,9 +871,10 @@ static void x86_update_above_4g_mem_start(PCMachineState 
> *pcms,
>  /*
>   * The HyperTransport range close to the 1T boundary is unique to AMD
>   * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation
> - * to above 1T to AMD vCPUs only.
> + * to above 1T to AMD vCPUs only. @enforce_valid_iova is only false in
> + * older machine types (<= 7.0) for compatibility purposes.
>   */
> -if (!IS_AMD_CPU(env)) {
> +if (!IS_AMD_CPU(env) || !pcmc->enforce_valid_iova) {
>  return;
>  }
>  
> @@ -1881,6 +1883,7 @@ static void pc_machine_class_init(ObjectClass *oc, void 
> *data)
>  pcmc->has_reserved_memory = true;
>  pcmc->kvmclock_enabled = true;
>  pcmc->enforce_aligned_dimm = true;
> +pcmc->enforce_valid_iova = true;
>  /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K 
> reported
>   * to be used at the moment, 32K should be enough for a while.  */
>  pcmc->acpi_data_size = 0x2 + 0x8000;
> diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
> index 57bb5b8f2aea..74176a210d56 100644
> --- a/hw/i386/pc_piix.c
> +++ b/hw/i386/pc_piix.c
> @@ -437,9 +437,11 @@ DEFINE_I440FX_MACHINE(v7_1, "pc-i440fx-7.1", NULL,
>  
>  static void pc_i440fx_7_0_machine_options(MachineClass *m)
>  {
> +PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
>  pc_i440fx_7_1_machine_options(m);
>  m->alias = NULL;
>  m->is_default = false;
> +pcmc->enforce_valid_iova = false;
>  compat_props_add(m->compat_props, hw_compat_7_0, hw_compat_7_0_len);
>  compat_props_add(m->compat_props, pc_compat_7_0, pc_compat_7_0_len);
>  }
> diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
> index 4d5c2fbd976b..bc38a6ba4c67 100644
> --- a/hw/i386/pc_q35.c
> +++ b/hw/i386/pc_q35.c
> @@ -381,8 +381,10 @@ DEFINE_Q35_MACHINE(v7_1, "pc-q35-7.1", NULL,
>  
>  static void pc_q35_7_0_machine_options(MachineClass *m)
>  {
> +PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
>  pc_q35_7_1_machine_options(m);
>  m->alias = NULL;
> +pcmc->enforce_valid_iova = false;
>  compat_props_add(m->compat_props, hw_compat_7_0, hw_compat_7_0_len);
>  compat_props_add(m->compat_props, pc_compat_7_0, pc_compat_7_0_len);
>  }
> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> index 9c847faea2f8..22119131eca7 100644
> --- a/include/hw/i386/pc.h
> +++ b/include/hw/i386/pc.h
> @@ -117,6 +117,7 @@ struct PCMachineClass {
>  bool has_reserved_memory;
>  bool enforce_aligned_dimm;
>  bool broken_reserved_end;
> +bool enforce_valid_iova;
>  
>  /* generate legacy CPU hotplug AML */
>  bool legacy_cpu_hotplug;




Re: [PATCH v5 4/5] i386/pc: relocate 4g start to 1T where applicable

2022-06-16 Thread Igor Mammedov
On Fri, 20 May 2022 11:45:31 +0100
Joao Martins  wrote:

> It is assumed that the whole GPA space is available to be DMA
> addressable, within a given address space limit, expect for a
   ^^^ typo?

> tiny region before the 4G. Since Linux v5.4, VFIO validates
> whether the selected GPA is indeed valid i.e. not reserved by
> IOMMU on behalf of some specific devices or platform-defined
> restrictions, and thus failing the ioctl(VFIO_DMA_MAP) with
>  -EINVAL.
> 
> AMD systems with an IOMMU are examples of such platforms and
> particularly may only have these ranges as allowed:
> 
>    - fedf (0  .. 3.982G)
>   fef0 - 00fc (3.983G .. 1011.9G)
>   0100 -  (1Tb.. 16Pb[*])
> 
> We already account for the 4G hole, albeit if the guest is big
> enough we will fail to allocate a guest with  >1010G due to the
> ~12G hole at the 1Tb boundary, reserved for HyperTransport (HT).
> 
> [*] there is another reserved region unrelated to HT that exists
> in the 256T boundaru in Fam 17h according to Errata #1286,
  ^ ditto

> documeted also in "Open-Source Register Reference for AMD Family
> 17h Processors (PUB)"
> 
> When creating the region above 4G, take into account that on AMD
> platforms the HyperTransport range is reserved and hence it
> cannot be used either as GPAs. On those cases rather than
> establishing the start of ram-above-4g to be 4G, relocate instead
> to 1Tb. See AMD IOMMU spec, section 2.1.2 "IOMMU Logical
> Topology", for more information on the underlying restriction of
> IOVAs.
> 
> After accounting for the 1Tb hole on AMD hosts, mtree should
> look like:
> 
> -7fff (prio 0, i/o):
>alias ram-below-4g @pc.ram -7fff
> 0100-01ff7fff (prio 0, i/o):
>   alias ram-above-4g @pc.ram 8000-00ff
> 
> If the relocation is done, we also add the the reserved HT
> e820 range as reserved.
> 
> Default phys-bits on Qemu is TCG_PHYS_ADDR_BITS (40) which is enough
> to address 1Tb (0xff  ). On AMD platforms, if a
> ram-above-4g relocation may be desired and the CPU wasn't configured
> with a big enough phys-bits, print an error message to the user
> and do not make the relocation of the above-4g-region if phys-bits
> is too low.
> 
> Suggested-by: Igor Mammedov 
> Signed-off-by: Joao Martins 
> ---
>  hw/i386/pc.c | 111 +++
>  1 file changed, 111 insertions(+)
> 
> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> index af52d4ff89ef..652ae8ff9ccf 100644
> --- a/hw/i386/pc.c
> +++ b/hw/i386/pc.c
> @@ -796,6 +796,110 @@ void xen_load_linux(PCMachineState *pcms)
>  #define PC_ROM_ALIGN   0x800
>  #define PC_ROM_SIZE(PC_ROM_MAX - PC_ROM_MIN_VGA)
>  
> +/*
> + * AMD systems with an IOMMU have an additional hole close to the
> + * 1Tb, which are special GPAs that cannot be DMA mapped. Depending
> + * on kernel version, VFIO may or may not let you DMA map those ranges.
> + * Starting Linux v5.4 we validate it, and can't create guests on AMD 
> machines
> + * with certain memory sizes. It's also wrong to use those IOVA ranges
> + * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse.
> + * The ranges reserved for Hyper-Transport are:
> + *
> + * FD__h - FF__h
> + *
> + * The ranges represent the following:
> + *
> + * Base Address   Top Address  Use
> + *
> + * FD__h FD_F7FF_h Reserved interrupt address space
> + * FD_F800_h FD_F8FF_h Interrupt/EOI IntCtl
> + * FD_F900_h FD_F90F_h Legacy PIC IACK
> + * FD_F910_h FD_F91F_h System Management
> + * FD_F920_h FD_FAFF_h Reserved Page Tables
> + * FD_FB00_h FD_FBFF_h Address Translation
> + * FD_FC00_h FD_FDFF_h I/O Space
> + * FD_FE00_h FD__h Configuration
> + * FE__h FE_1FFF_h Extended Configuration/Device Messages
> + * FE_2000_h FF__h Reserved
> + *
> + * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology",
> + * Table 3: Special Address Controls (GPA) for more information.
> + */
> +#define AMD_HT_START 0xfdUL
> +#define AMD_HT_END   0xffUL
> +#define AMD_ABOVE_1TB_START  (AMD_HT_END + 1)
> +#define AMD_HT_SIZE  (AMD_ABOVE_1TB_START - AMD_HT_START)
> +
> +static hwaddr x86_max_phys_addr(PCMachineState *pcms,

s/x86_max_phys_addr/pc_max_used_gpa/

> +hwaddr above_4g_mem_start,
> +u

Re: [PATCH v5 2/5] i386/pc: create pci-host qdev prior to pc_memory_init()

2022-06-16 Thread Reviewed-by: Igor Mammedov
On Fri, 20 May 2022 11:45:29 +0100
Joao Martins  wrote:

> At the start of pc_memory_init() we usually pass a range of
> 0..UINT64_MAX as pci_memory, when really its 2G (i440fx) or
> 32G (q35). To get the real user value, we need to get pci-host
> passed property for default pci_hole64_size. Thus to get that,
> create the qdev prior to memory init to better make estimations
> on max used/phys addr.
> 
> This is in preparation to determine that host-phys-bits are
> enough and also for pci-hole64-size to be considered to relocate
> ram-above-4g to be at 1T (on AMD platforms).

with comments below fixed
Reviewed-by: Igor Mammedov 
 
> Signed-off-by: Joao Martins 
> ---
>  hw/i386/pc_piix.c| 5 -
>  hw/i386/pc_q35.c | 6 +++---
>  hw/pci-host/i440fx.c | 3 +--
>  include/hw/pci-host/i440fx.h | 2 +-
>  4 files changed, 9 insertions(+), 7 deletions(-)
> 
> diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
> index 578e537b3525..12d4a279c793 100644
> --- a/hw/i386/pc_piix.c
> +++ b/hw/i386/pc_piix.c
> @@ -91,6 +91,7 @@ static void pc_init1(MachineState *machine,
>  MemoryRegion *pci_memory;
>  MemoryRegion *rom_memory;
>  ram_addr_t lowmem;
> +DeviceState *i440fx_dev;
>  
>  /*
>   * Calculate ram split, for memory below and above 4G.  It's a bit
> @@ -164,9 +165,11 @@ static void pc_init1(MachineState *machine,
>  pci_memory = g_new(MemoryRegion, 1);
>  memory_region_init(pci_memory, NULL, "pci", UINT64_MAX);
>  rom_memory = pci_memory;
> +i440fx_dev = qdev_new(host_type);
>  } else {
>  pci_memory = NULL;
>  rom_memory = system_memory;
> +i440fx_dev = NULL;
>  }
>  
>  pc_guest_info_init(pcms);
> @@ -199,7 +202,7 @@ static void pc_init1(MachineState *machine,
>  
>  pci_bus = i440fx_init(host_type,
>pci_type,
> -  _state,
> +  i440fx_dev, _state,
confusing names, suggest to rename i440fx_state -> pci_i440fx and i440fx_dev -> 
i440fx_host
or something like this

>system_memory, system_io, machine->ram_size,
>x86ms->below_4g_mem_size,
>x86ms->above_4g_mem_size,
> diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
> index 42eb8b97079a..8d867bdb274a 100644
> --- a/hw/i386/pc_q35.c
> +++ b/hw/i386/pc_q35.c
> @@ -203,12 +203,12 @@ static void pc_q35_init(MachineState *machine)
>  pcms->smbios_entry_point_type);
>  }
>  
> -/* allocate ram and load rom/bios */
> -pc_memory_init(pcms, get_system_memory(), rom_memory, _memory);
> -
>  /* create pci host bus */
>  q35_host = Q35_HOST_DEVICE(qdev_new(TYPE_Q35_HOST_DEVICE));
>  
> +/* allocate ram and load rom/bios */
> +pc_memory_init(pcms, get_system_memory(), rom_memory, _memory);
> +
>  object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host));
>  object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_RAM_MEM,
>   OBJECT(ram_memory), NULL);
> diff --git a/hw/pci-host/i440fx.c b/hw/pci-host/i440fx.c
> index e08716142b6e..5c1bab5c58ed 100644
> --- a/hw/pci-host/i440fx.c
> +++ b/hw/pci-host/i440fx.c
> @@ -238,6 +238,7 @@ static void i440fx_realize(PCIDevice *dev, Error **errp)
>  }
>  
>  PCIBus *i440fx_init(const char *host_type, const char *pci_type,

does it still need 'host_type'?

> +DeviceState *dev,
>  PCII440FXState **pi440fx_state,
>  MemoryRegion *address_space_mem,
>  MemoryRegion *address_space_io,
> @@ -247,7 +248,6 @@ PCIBus *i440fx_init(const char *host_type, const char 
> *pci_type,
>  MemoryRegion *pci_address_space,
>  MemoryRegion *ram_memory)
>  {
> -DeviceState *dev;
>  PCIBus *b;
>  PCIDevice *d;
>  PCIHostState *s;
> @@ -255,7 +255,6 @@ PCIBus *i440fx_init(const char *host_type, const char 
> *pci_type,
>  unsigned i;
>  I440FXState *i440fx;
>  
> -dev = qdev_new(host_type);
>  s = PCI_HOST_BRIDGE(dev);
>  b = pci_root_bus_new(dev, NULL, pci_address_space,
>   address_space_io, 0, TYPE_PCI_BUS);
> diff --git a/include/hw/pci-host/i440fx.h b/include/hw/pci-host/i440fx.h
> index f068aaba8fda..c4710445e30a 100644
> --- a/include/hw/pci-host/i440fx.h
> +++ b/include/hw/pci-host/i440fx.h
> @@ -36,7 +36,7 @@ struct PCII440FXState {
>  #define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX"
>  
>  PCIBus *i440fx_init(const char *host_type, const char *pci_type,
> -PCII440FXState **pi440fx_state,
> +DeviceState *dev, PCII440FXState **pi440fx_state,
>  MemoryRegion *address_space_mem,
>  MemoryRegion *address_space_io,
>  ram_addr_t ram_size,




Re: [PATCH v5 3/5] i386/pc: pass pci_hole64_size to pc_memory_init()

2022-06-16 Thread Igor Mammedov
On Fri, 20 May 2022 11:45:30 +0100
Joao Martins  wrote:

> Use the pre-initialized pci-host qdev and fetch the
> pci-hole64-size into pc_memory_init() newly added argument.
> piix needs a bit of care given all the !pci_enabled()
> and that the pci_hole64_size is private to i440fx.
> 
> This is in preparation to determine that host-phys-bits are
> enough and for pci-hole64-size to be considered to relocate
> ram-above-4g to be at 1T (on AMD platforms).

modulo nit blow

Reviewed-by: Igor Mammedov 

> 
> Signed-off-by: Joao Martins 
> ---
>  hw/i386/pc.c | 3 ++-
>  hw/i386/pc_piix.c| 5 -
>  hw/i386/pc_q35.c | 8 +++-
>  hw/pci-host/i440fx.c | 7 +++
>  include/hw/i386/pc.h | 3 ++-
>  include/hw/pci-host/i440fx.h | 1 +
>  6 files changed, 23 insertions(+), 4 deletions(-)
> 
> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> index f7da1d5dd40d..af52d4ff89ef 100644
> --- a/hw/i386/pc.c
> +++ b/hw/i386/pc.c
> @@ -799,7 +799,8 @@ void xen_load_linux(PCMachineState *pcms)
>  void pc_memory_init(PCMachineState *pcms,
>  MemoryRegion *system_memory,
>  MemoryRegion *rom_memory,
> -MemoryRegion **ram_memory)
> +MemoryRegion **ram_memory,
> +uint64_t pci_hole64_size)
>  {
>  int linux_boot, i;
>  MemoryRegion *option_rom_mr;
> diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
> index 12d4a279c793..57bb5b8f2aea 100644
> --- a/hw/i386/pc_piix.c
> +++ b/hw/i386/pc_piix.c
> @@ -91,6 +91,7 @@ static void pc_init1(MachineState *machine,
>  MemoryRegion *pci_memory;
>  MemoryRegion *rom_memory;
>  ram_addr_t lowmem;
> +uint64_t hole64_size;

init it to 0 right here to avoid chance of run amok uninitialized variable?

>  DeviceState *i440fx_dev;
>  
>  /*
> @@ -166,10 +167,12 @@ static void pc_init1(MachineState *machine,
>  memory_region_init(pci_memory, NULL, "pci", UINT64_MAX);
>  rom_memory = pci_memory;
>  i440fx_dev = qdev_new(host_type);
> +hole64_size = i440fx_pci_hole64_size(i440fx_dev);
>  } else {
>  pci_memory = NULL;
>  rom_memory = system_memory;
>  i440fx_dev = NULL;
> +hole64_size = 0;
>  }
>  
>  pc_guest_info_init(pcms);
> @@ -186,7 +189,7 @@ static void pc_init1(MachineState *machine,
>  /* allocate ram and load rom/bios */
>  if (!xen_enabled()) {
>  pc_memory_init(pcms, system_memory,
> -   rom_memory, _memory);
> +   rom_memory, _memory, hole64_size);
>  } else {
>  pc_system_flash_cleanup_unused(pcms);
>  if (machine->kernel_filename != NULL) {
> diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
> index 8d867bdb274a..4d5c2fbd976b 100644
> --- a/hw/i386/pc_q35.c
> +++ b/hw/i386/pc_q35.c
> @@ -138,6 +138,7 @@ static void pc_q35_init(MachineState *machine)
>  MachineClass *mc = MACHINE_GET_CLASS(machine);
>  bool acpi_pcihp;
>  bool keep_pci_slot_hpc;
> +uint64_t pci_hole64_size = 0;
>  
>  /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory
>   * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping
> @@ -206,8 +207,13 @@ static void pc_q35_init(MachineState *machine)
>  /* create pci host bus */
>  q35_host = Q35_HOST_DEVICE(qdev_new(TYPE_Q35_HOST_DEVICE));
>  
> +if (pcmc->pci_enabled) {
> +pci_hole64_size = q35_host->mch.pci_hole64_size;
> +}
> +
>  /* allocate ram and load rom/bios */
> -pc_memory_init(pcms, get_system_memory(), rom_memory, _memory);
> +pc_memory_init(pcms, get_system_memory(), rom_memory, _memory,
> +   pci_hole64_size);
>  
>  object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host));
>  object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_RAM_MEM,
> diff --git a/hw/pci-host/i440fx.c b/hw/pci-host/i440fx.c
> index 5c1bab5c58ed..c5cc28250d5c 100644
> --- a/hw/pci-host/i440fx.c
> +++ b/hw/pci-host/i440fx.c
> @@ -237,6 +237,13 @@ static void i440fx_realize(PCIDevice *dev, Error **errp)
>  }
>  }
>  
> +uint64_t i440fx_pci_hole64_size(DeviceState *i440fx_dev)
> +{
> +I440FXState *i440fx = I440FX_PCI_HOST_BRIDGE(i440fx_dev);
> +
> +return i440fx->pci_hole64_size;
> +}
> +
>  PCIBus *i440fx_init(const char *host_type, const char *pci_type,
>  DeviceState *dev,
>  PCII440FXState **pi440fx_state,
> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> index ffcac5121ed9..9c847faea2f8 1

Re: [PATCH v5 1/5] hw/i386: add 4g boundary start to X86MachineState

2022-06-16 Thread Igor Mammedov
On Fri, 20 May 2022 11:45:28 +0100
Joao Martins  wrote:

> Rather than hardcoding the 4G boundary everywhere, introduce a
> X86MachineState property @above_4g_mem_start and use it
so far it's just field not a property /fix commit message/

> accordingly.
> 
> This is in preparation for relocating ram-above-4g to be
> dynamically start at 1T on AMD platforms.

possibly needs to be rebased on top of current master to include cxl_base

with comments fixed

Reviewed-by: Igor Mammedov 

> 
> Signed-off-by: Joao Martins 
> ---
>  hw/i386/acpi-build.c  | 2 +-
>  hw/i386/pc.c  | 9 +
>  hw/i386/sgx.c | 2 +-
>  hw/i386/x86.c | 1 +
>  include/hw/i386/x86.h | 3 +++
>  5 files changed, 11 insertions(+), 6 deletions(-)
> 
> diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
> index c125939ed6f9..3160b20c9574 100644
> --- a/hw/i386/acpi-build.c
> +++ b/hw/i386/acpi-build.c
> @@ -2120,7 +2120,7 @@ build_srat(GArray *table_data, BIOSLinker *linker, 
> MachineState *machine)
>  build_srat_memory(table_data, mem_base, mem_len, i - 1,
>MEM_AFFINITY_ENABLED);
>  }
> -mem_base = 1ULL << 32;
> +mem_base = x86ms->above_4g_mem_start;
>  mem_len = next_base - x86ms->below_4g_mem_size;
>  next_base = mem_base + mem_len;
>  }
> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> index 7c39c913355b..f7da1d5dd40d 100644
> --- a/hw/i386/pc.c
> +++ b/hw/i386/pc.c
> @@ -832,9 +832,10 @@ void pc_memory_init(PCMachineState *pcms,
>   machine->ram,
>   x86ms->below_4g_mem_size,
>   x86ms->above_4g_mem_size);
> -memory_region_add_subregion(system_memory, 0x1ULL,
> +memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start,
>  ram_above_4g);
> -e820_add_entry(0x1ULL, x86ms->above_4g_mem_size, E820_RAM);
> +e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size,
> +   E820_RAM);
>  }
>  
>  if (pcms->sgx_epc.size != 0) {
> @@ -875,7 +876,7 @@ void pc_memory_init(PCMachineState *pcms,
>  machine->device_memory->base = 
> sgx_epc_above_4g_end(>sgx_epc);
>  } else {
>  machine->device_memory->base =
> -0x1ULL + x86ms->above_4g_mem_size;
> +x86ms->above_4g_mem_start + x86ms->above_4g_mem_size;
>  }
>  
>  machine->device_memory->base =
> @@ -1019,7 +1020,7 @@ uint64_t pc_pci_hole64_start(void)
>  } else if (pcms->sgx_epc.size != 0) {
>  hole64_start = sgx_epc_above_4g_end(>sgx_epc);
>  } else {
> -hole64_start = 0x1ULL + x86ms->above_4g_mem_size;
> +hole64_start = x86ms->above_4g_mem_start + x86ms->above_4g_mem_size;
>  }
>  
>  return ROUND_UP(hole64_start, 1 * GiB);
> diff --git a/hw/i386/sgx.c b/hw/i386/sgx.c
> index a44d66ba2afc..09d9c7c73d9f 100644
> --- a/hw/i386/sgx.c
> +++ b/hw/i386/sgx.c
> @@ -295,7 +295,7 @@ void pc_machine_init_sgx_epc(PCMachineState *pcms)
>  return;
>  }
>  
> -sgx_epc->base = 0x1ULL + x86ms->above_4g_mem_size;
> +sgx_epc->base = x86ms->above_4g_mem_start + x86ms->above_4g_mem_size;
>  
>  memory_region_init(_epc->mr, OBJECT(pcms), "sgx-epc", UINT64_MAX);
>  memory_region_add_subregion(get_system_memory(), sgx_epc->base,
> diff --git a/hw/i386/x86.c b/hw/i386/x86.c
> index 78b05ab7a2d1..af3c790a2830 100644
> --- a/hw/i386/x86.c
> +++ b/hw/i386/x86.c
> @@ -1373,6 +1373,7 @@ static void x86_machine_initfn(Object *obj)
>  x86ms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6);
>  x86ms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8);
>  x86ms->bus_lock_ratelimit = 0;
> +x86ms->above_4g_mem_start = 0x1ULL;

s/0x.../4 * GiB/

>  }
>  
>  static void x86_machine_class_init(ObjectClass *oc, void *data)
> diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h
> index 9089bdd99c3a..df82c5fd4252 100644
> --- a/include/hw/i386/x86.h
> +++ b/include/hw/i386/x86.h
> @@ -56,6 +56,9 @@ struct X86MachineState {
>  /* RAM information (sizes, addresses, configuration): */
>  ram_addr_t below_4g_mem_size, above_4g_mem_size;
>  
> +/* Start address of the initial RAM above 4G */
> +uint64_t above_4g_mem_start;
> +
>  /* CPU and apic information: */
>  bool apic_xrupt_override;
>  unsigned pci_irq_mask;




Re: [QEMU PATCH v2 6/6] acpi/nvdimm: Define trace events for NVDIMM and substitute nvdimm_debug()

2022-06-16 Thread Igor Mammedov
On Mon, 30 May 2022 11:40:47 +0800
Robert Hoo  wrote:

suggest to put this patch as the 1st in series
(well you can rebase it on current master and
post that right away for merging since it doesn't
really depend on other patches, and post new patches on
top (whenever they are ready) will use tracing)

> Signed-off-by: Robert Hoo 
> Reviewed-by: Jingqi Liu 
> ---
>  hw/acpi/nvdimm.c| 38 ++
>  hw/acpi/trace-events| 14 ++
>  include/hw/mem/nvdimm.h |  8 
>  3 files changed, 32 insertions(+), 28 deletions(-)
> 
> diff --git a/hw/acpi/nvdimm.c b/hw/acpi/nvdimm.c
> index 50ee85866b..fc777990e6 100644
> --- a/hw/acpi/nvdimm.c
> +++ b/hw/acpi/nvdimm.c
> @@ -35,6 +35,7 @@
>  #include "hw/nvram/fw_cfg.h"
>  #include "hw/mem/nvdimm.h"
>  #include "qemu/nvdimm-utils.h"
> +#include "trace.h"
>  
>  /*
>   * define Byte Addressable Persistent Memory (PM) Region according to
> @@ -558,8 +559,8 @@ static void nvdimm_dsm_func_read_fit(NVDIMMState *state, 
> NvdimmDsmIn *in,
>  
>  fit = fit_buf->fit;
>  
> -nvdimm_debug("Read FIT: offset 0x%x FIT size 0x%x Dirty %s.\n",
> - read_fit->offset, fit->len, fit_buf->dirty ? "Yes" : "No");
> +trace_acpi_nvdimm_read_fit(read_fit->offset, fit->len,
> +   fit_buf->dirty ? "Yes" : "No");
>  
>  if (read_fit->offset > fit->len) {
>  func_ret_status = NVDIMM_DSM_RET_STATUS_INVALID;
> @@ -667,7 +668,7 @@ static void nvdimm_dsm_label_size(NVDIMMDevice *nvdimm, 
> hwaddr dsm_mem_addr)
>  label_size = nvdimm->label_size;
>  mxfer = nvdimm_get_max_xfer_label_size();
>  
> -nvdimm_debug("label_size 0x%x, max_xfer 0x%x.\n", label_size, mxfer);
> +trace_acpi_nvdimm_label_info(label_size, mxfer);
>  
>  label_size_out.func_ret_status = 
> cpu_to_le32(NVDIMM_DSM_RET_STATUS_SUCCESS);
>  label_size_out.label_size = cpu_to_le32(label_size);
> @@ -683,20 +684,18 @@ static uint32_t nvdimm_rw_label_data_check(NVDIMMDevice 
> *nvdimm,
>  uint32_t ret = NVDIMM_DSM_RET_STATUS_INVALID;
>  
>  if (offset + length < offset) {
> -nvdimm_debug("offset 0x%x + length 0x%x is overflow.\n", offset,
> - length);
> +trace_acpi_nvdimm_label_overflow(offset, length);
>  return ret;
>  }
>  
>  if (nvdimm->label_size < offset + length) {
> -nvdimm_debug("position 0x%x is beyond label data (len = %" PRIx64 
> ").\n",
> - offset + length, nvdimm->label_size);
> +trace_acpi_nvdimm_label_oversize(offset + length, 
> nvdimm->label_size);
>  return ret;
>  }
>  
>  if (length > nvdimm_get_max_xfer_label_size()) {
> -nvdimm_debug("length (0x%x) is larger than max_xfer (0x%x).\n",
> - length, nvdimm_get_max_xfer_label_size());
> +trace_acpi_nvdimm_label_xfer_exceed(length,
> +
> nvdimm_get_max_xfer_label_size());
>  return ret;
>  }
>  
> @@ -718,8 +717,8 @@ static void nvdimm_dsm_get_label_data(NVDIMMDevice 
> *nvdimm,
>  get_label_data->offset = le32_to_cpu(get_label_data->offset);
>  get_label_data->length = le32_to_cpu(get_label_data->length);
>  
> -nvdimm_debug("Read Label Data: offset 0x%x length 0x%x.\n",
> - get_label_data->offset, get_label_data->length);
> +trace_acpi_nvdimm_read_label(get_label_data->offset,
> + get_label_data->length);
>  
>  status = nvdimm_rw_label_data_check(nvdimm, get_label_data->offset,
>  get_label_data->length);
> @@ -755,8 +754,8 @@ static void nvdimm_dsm_set_label_data(NVDIMMDevice 
> *nvdimm,
>  set_label_data->offset = le32_to_cpu(set_label_data->offset);
>  set_label_data->length = le32_to_cpu(set_label_data->length);
>  
> -nvdimm_debug("Write Label Data: offset 0x%x length 0x%x.\n",
> - set_label_data->offset, set_label_data->length);
> +trace_acpi_nvdimm_write_label(set_label_data->offset,
> +  set_label_data->length);
>  
>  status = nvdimm_rw_label_data_check(nvdimm, set_label_data->offset,
>  set_label_data->length);
> @@ -833,7 +832,7 @@ static void nvdimm_dsm_device(uint32_t nv_handle, 
> NvdimmDsmIn *dsm_in,
>  static uint64_t
>  nvdimm_method_read(void *opaque, hwaddr addr, unsigned size)
>  {
> -nvdimm_debug("BUG: we never read NVDIMM Method IO Port.\n");
> +trace_acpi_nvdimm_read_io_port();
>  return 0;
>  }
>  
> @@ -843,20 +842,19 @@ nvdimm_dsm_handle(void *opaque, NvdimmMthdIn 
> *method_in, hwaddr dsm_mem_addr)
>  NVDIMMState *state = opaque;
>  NvdimmDsmIn *dsm_in = (NvdimmDsmIn *)method_in->args;
>  
> -nvdimm_debug("dsm memory address 0x%" HWADDR_PRIx ".\n", dsm_mem_addr);
> +trace_acpi_nvdimm_dsm_mem_addr(dsm_mem_addr);
>  
>  dsm_in->revision = 

Re: [QEMU PATCH v2 4/6] nvdimm: Implement ACPI NVDIMM Label Methods

2022-06-16 Thread Igor Mammedov
On Mon, 30 May 2022 11:40:45 +0800
Robert Hoo  wrote:

> Recent ACPI spec [1] has defined NVDIMM Label Methods _LS{I,R,W}, which
> depricates corresponding _DSM Functions defined by PMEM _DSM Interface spec
> [2].
> 
> In this implementation, we do 2 things
> 1. Generalize the QEMU<->ACPI BIOS NVDIMM interface, wrap it with ACPI
> method dispatch, _DSM is one of the branches. This also paves the way for
> adding other ACPI methods for NVDIMM.
> 2. Add _LS{I,R,W} method in each NVDIMM device in SSDT.
> ASL form of SSDT changes can be found in next test/qtest/bios-table-test
> commit message.
> 
> [1] ACPI Spec v6.4, 6.5.10 NVDIMM Label Methods
> https://uefi.org/sites/default/files/resources/ACPI_Spec_6_4_Jan22.pdf
> [2] Intel PMEM _DSM Interface Spec v2.0, 3.10 Deprecated Functions
> https://pmem.io/documents/IntelOptanePMem_DSM_Interface-V2.0.pdf
> 
> Signed-off-by: Robert Hoo 
> Reviewed-by: Jingqi Liu 
> ---
>  hw/acpi/nvdimm.c| 424 +++-

This patch is too large and doing to many things to be reviewable.
It needs to be split into smaller distinct chunks.
(however hold your horses and read on)

The patch it is too intrusive and my hunch is that it breaks
ABI and needs a bunch of compat knobs to work properly and
that I'd like to avoid unless there is not other way around
the problem.

I was skeptical about this approach during v1 review and
now I'm pretty much sure it's over-engineered and we can
just repack data we receive from existing label _DSM functions
to provide _LS{I,R,W} like it was suggested in v1.
It will be much simpler and affect only AML side without
complicating ABI and without any compat cruft and will work
with ping-pong migration without any issues.


>  include/hw/mem/nvdimm.h |   6 +
>  2 files changed, 338 insertions(+), 92 deletions(-)
> 
> diff --git a/hw/acpi/nvdimm.c b/hw/acpi/nvdimm.c
> index 59b42afcf1..50ee85866b 100644
> --- a/hw/acpi/nvdimm.c
> +++ b/hw/acpi/nvdimm.c
> @@ -416,17 +416,22 @@ static void nvdimm_build_nfit(NVDIMMState *state, 
> GArray *table_offsets,
>  
>  #define NVDIMM_DSM_MEMORY_SIZE  4096
>  
> -struct NvdimmDsmIn {
> +struct NvdimmMthdIn {
>  uint32_t handle;
> +uint32_t method;
> +uint8_t  args[4088];
> +} QEMU_PACKED;
> +typedef struct NvdimmMthdIn NvdimmMthdIn;
> +struct NvdimmDsmIn {
>  uint32_t revision;
>  uint32_t function;
>  /* the remaining size in the page is used by arg3. */
>  union {
> -uint8_t arg3[4084];
> +uint8_t arg3[4080];
>  };
>  } QEMU_PACKED;
>  typedef struct NvdimmDsmIn NvdimmDsmIn;
> -QEMU_BUILD_BUG_ON(sizeof(NvdimmDsmIn) != NVDIMM_DSM_MEMORY_SIZE);
> +QEMU_BUILD_BUG_ON(sizeof(NvdimmMthdIn) != NVDIMM_DSM_MEMORY_SIZE);
>  
>  struct NvdimmDsmOut {
>  /* the size of buffer filled by QEMU. */
> @@ -470,7 +475,8 @@ struct NvdimmFuncGetLabelDataIn {
>  } QEMU_PACKED;
>  typedef struct NvdimmFuncGetLabelDataIn NvdimmFuncGetLabelDataIn;
>  QEMU_BUILD_BUG_ON(sizeof(NvdimmFuncGetLabelDataIn) +
> -  offsetof(NvdimmDsmIn, arg3) > NVDIMM_DSM_MEMORY_SIZE);
> +  offsetof(NvdimmDsmIn, arg3) + offsetof(NvdimmMthdIn, args) 
> >
> +  NVDIMM_DSM_MEMORY_SIZE);
>  
>  struct NvdimmFuncGetLabelDataOut {
>  /* the size of buffer filled by QEMU. */
> @@ -488,14 +494,16 @@ struct NvdimmFuncSetLabelDataIn {
>  } QEMU_PACKED;
>  typedef struct NvdimmFuncSetLabelDataIn NvdimmFuncSetLabelDataIn;
>  QEMU_BUILD_BUG_ON(sizeof(NvdimmFuncSetLabelDataIn) +
> -  offsetof(NvdimmDsmIn, arg3) > NVDIMM_DSM_MEMORY_SIZE);
> +  offsetof(NvdimmDsmIn, arg3) + offsetof(NvdimmMthdIn, args) 
> >
> +  NVDIMM_DSM_MEMORY_SIZE);
>  
>  struct NvdimmFuncReadFITIn {
>  uint32_t offset; /* the offset into FIT buffer. */
>  } QEMU_PACKED;
>  typedef struct NvdimmFuncReadFITIn NvdimmFuncReadFITIn;
>  QEMU_BUILD_BUG_ON(sizeof(NvdimmFuncReadFITIn) +
> -  offsetof(NvdimmDsmIn, arg3) > NVDIMM_DSM_MEMORY_SIZE);
> +  offsetof(NvdimmDsmIn, arg3) + offsetof(NvdimmMthdIn, args) 
> >
> +  NVDIMM_DSM_MEMORY_SIZE);
>  
>  struct NvdimmFuncReadFITOut {
>  /* the size of buffer filled by QEMU. */
> @@ -636,7 +644,8 @@ static uint32_t nvdimm_get_max_xfer_label_size(void)
>   * the max data ACPI can write one time which is transferred by
>   * 'Set Namespace Label Data' function.
>   */
> -max_set_size = dsm_memory_size - offsetof(NvdimmDsmIn, arg3) -
> +max_set_size = dsm_memory_size - offsetof(NvdimmMthdIn, args) -
> +   offsetof(NvdimmDsmIn, arg3) -
> sizeof(NvdimmFuncSetLabelDataIn);
>  
>  return MIN(max_get_size, max_set_size);
> @@ -697,16 +706,15 @@ static uint32_t nvdimm_rw_label_data_check(NVDIMMDevice 
> *nvdimm,
>  /*
>   * DSM Spec Rev1 4.5 Get Namespace Label Data (Function Index 5).
>   */
> -static void nvdimm_dsm_get_label_data(NVDIMMDevice *nvdimm, NvdimmDsmIn *in,
> -   

Re: [QEMU PATCH v2 3/6] acpi/nvdimm: NVDIMM _DSM Spec supports revision 2

2022-06-16 Thread Igor Mammedov
On Mon, 30 May 2022 11:40:44 +0800
Robert Hoo  wrote:

> The Intel Optane PMem DSM Interface, Version 2.0 [1], is the up-to-date
> spec for NVDIMM _DSM definition, which supports revision_id == 2.
> 
> Nevertheless, Rev.2 of NVDIMM _DSM has no functional change on those Label
> Data _DSM Functions, which are the only ones implemented for vNVDIMM.
> So, simple change to support this revision_id == 2 case.
> 
> [1] https://pmem.io/documents/IntelOptanePMem_DSM_Interface-V2.0.pdf

pls enumerate functions that QEMU implement and that are supported by rev=2,
do we really need rev2 ?

also don't we need make sure that rev1 only function are excluded?
/spec above says, functions 3-6 are deprecated and limited to rev1 only/
"
Warning: This function has been deprecated in preference to the ACPI 6.2 _LSW 
(Label Storage Write)
NVDIMM Device Interface and is only supported with Arg1 – Revision Id = 1. It 
is included here for
backwards compatibility with existing Arg1 - Revision Id = 1 implementations.
"

> 
> Signed-off-by: Robert Hoo 
> Reviewed-by: Jingqi Liu 
> ---
>  hw/acpi/nvdimm.c | 10 +++---
>  1 file changed, 7 insertions(+), 3 deletions(-)
> 
> diff --git a/hw/acpi/nvdimm.c b/hw/acpi/nvdimm.c
> index 0ab247a870..59b42afcf1 100644
> --- a/hw/acpi/nvdimm.c
> +++ b/hw/acpi/nvdimm.c
> @@ -849,9 +849,13 @@ nvdimm_dsm_write(void *opaque, hwaddr addr, uint64_t 
> val, unsigned size)
>  nvdimm_debug("Revision 0x%x Handler 0x%x Function 0x%x.\n", in->revision,
>   in->handle, in->function);
>  
> -if (in->revision != 0x1 /* Currently we only support DSM Spec Rev1. */) {
> -nvdimm_debug("Revision 0x%x is not supported, expect 0x%x.\n",
> - in->revision, 0x1);
> +/*
> + * Current NVDIMM _DSM Spec supports Rev1 and Rev2
> + * Intel® OptanePersistent Memory Module DSM Interface, Revision 2.0
> + */
> +if (in->revision != 0x1 && in->revision != 0x2) {
> +nvdimm_debug("Revision 0x%x is not supported, expect 0x1 or 0x2.\n",
> + in->revision);
>  nvdimm_dsm_no_payload(NVDIMM_DSM_RET_STATUS_UNSUPPORT, dsm_mem_addr);
>  goto exit;
>  }




Re: [QEMU PATCH v2 1/6] tests/acpi: allow SSDT changes

2022-06-16 Thread Igor Mammedov
On Mon, 30 May 2022 11:40:42 +0800
Robert Hoo  wrote:

> Signed-off-by: Robert Hoo 
> Reviewed-by: Jingqi Liu 

Reviewed-by: Igor Mammedov 

> ---
>  tests/qtest/bios-tables-test-allowed-diff.h | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/tests/qtest/bios-tables-test-allowed-diff.h 
> b/tests/qtest/bios-tables-test-allowed-diff.h
> index dfb8523c8b..eb8bae1407 100644
> --- a/tests/qtest/bios-tables-test-allowed-diff.h
> +++ b/tests/qtest/bios-tables-test-allowed-diff.h
> @@ -1 +1,3 @@
>  /* List of comma-separated changed AML files to ignore */
> +"tests/data/acpi/pc/SSDT.dimmpxm",
> +"tests/data/acpi/q35/SSDT.dimmpxm",




Re: regarding QEMU ACPI table generation and passing acpi tables/methods to guest OS

2022-06-15 Thread Igor Mammedov
On Wed, 15 Jun 2022 18:23:28 +0530
ritul guru  wrote:

> Came across below link about QEMU to pass acpi tables to guest OS.
> https://wiki.qemu.org/Features/ACPITableGeneration

that link a bit outdated (project was completed but than later QEMU
moved on to built-in library for composing ACPI tables)

> Can I get more docs with respect to acpi tables/devices passing to guest OS
> from hypervisor or dom0?
> 
> Looking for an example how an asl file which gets added in the SSDT table
> can be passed to the guest OS with the help of QEMU.


You can look at AML library QEMU utilizes currently to build DSDT/SSDT tables
  ./hw/acpi/aml-build.c
  ./include/hw/acpi/aml-build.h

and see build_dsdt* functions for examples how it's used to compose tables.

> 
> 
> 
> *Thanks & RegardsRitul Guru+91-9916513186*




Re: [PATCH] hw/mem/nvdimm: fix error message for 'unarmed' flag

2022-06-14 Thread Igor Mammedov
On Tue, 14 Jun 2022 11:50:43 +0200
David Hildenbrand  wrote:

> On 14.06.22 10:54, Igor Mammedov wrote:
> > On Mon, 13 Jun 2022 16:09:53 +0100
> > Stefan Hajnoczi  wrote:
> >   
> >> On Mon, Jun 13, 2022 at 05:01:10PM +0200, Julia Suvorova wrote:  
> >>> On Tue, May 31, 2022 at 5:32 PM Stefan Hajnoczi  
> >>> wrote:
> >>>>
> >>>> On Tue, May 31, 2022 at 04:51:47PM +0200, Julia Suvorova wrote:
> >>>>> In the ACPI specification [1], the 'unarmed' bit is set when a device
> >>>>> cannot accept a persistent write. This means that when a memdev is
> >>>>> read-only, the 'unarmed' flag must be turned on. The logic is correct,
> >>>>> just changing the error message.
> >>>>>
> >>>>> [1] ACPI NFIT NVDIMM Region Mapping Structure "NVDIMM State Flags" Bit 3
> >>>>>
> >>>>> Signed-off-by: Julia Suvorova 
> >>>>> ---
> >>>>>  hw/mem/nvdimm.c | 2 +-
> >>>>>  1 file changed, 1 insertion(+), 1 deletion(-)
> >>>>
> >>>> Reviewed-by: Stefan Hajnoczi 
> >>>
> >>> It seems like Xiao is not active, whose tree should this patch go to?
> 
> Is that a temporary or a permanent thing? Do we know?
> 
> > 
> > Perhaps David can add himself as maintainer (i.e. put it
> > under memory mantanership umbrella) and merge it   
> 
> Maybe it makes sense to combine NVDIMM with pc-dimm.c and
> memory-device.c into a "MEMORY DEVICE" section. Then, remove "hw/mem/*"
> from "ACPI/SMBIOS".
just keep me on supporter list for them so I won't miss
patches that needs reviewing.

> cxl_type3.c, npcm7xx_mc.c and sparse-mem.c in /hw/mem/ are a bit
> different. We could add cxl_type3.c to "Compute Express Link".
> npcm7xx_mc.c and sparse-mem.c should be already covered. 
for cxl I'd add Michael as it's mostly all PCI stuff




Re: [PATCH] hw/mem/nvdimm: fix error message for 'unarmed' flag

2022-06-14 Thread Igor Mammedov
On Mon, 13 Jun 2022 16:09:53 +0100
Stefan Hajnoczi  wrote:

> On Mon, Jun 13, 2022 at 05:01:10PM +0200, Julia Suvorova wrote:
> > On Tue, May 31, 2022 at 5:32 PM Stefan Hajnoczi  
> > wrote:  
> > >
> > > On Tue, May 31, 2022 at 04:51:47PM +0200, Julia Suvorova wrote:  
> > > > In the ACPI specification [1], the 'unarmed' bit is set when a device
> > > > cannot accept a persistent write. This means that when a memdev is
> > > > read-only, the 'unarmed' flag must be turned on. The logic is correct,
> > > > just changing the error message.
> > > >
> > > > [1] ACPI NFIT NVDIMM Region Mapping Structure "NVDIMM State Flags" Bit 3
> > > >
> > > > Signed-off-by: Julia Suvorova 
> > > > ---
> > > >  hw/mem/nvdimm.c | 2 +-
> > > >  1 file changed, 1 insertion(+), 1 deletion(-)  
> > >
> > > Reviewed-by: Stefan Hajnoczi   
> > 
> > It seems like Xiao is not active, whose tree should this patch go to?  

Perhaps David can add himself as maintainer (i.e. put it
under memory mantanership umbrella) and merge it 

> 
> Michael or Igor can merge it:
> 
>   $ scripts/get_maintainer.pl -f hw/mem/nvdimm.c
>   Xiao Guangrong  (maintainer:NVDIMM)
>   "Michael S. Tsirkin"  (supporter:ACPI/SMBIOS)
>   Igor Mammedov  (supporter:ACPI/SMBIOS)
>   Ani Sinha  (reviewer:ACPI/SMBIOS)
>   qemu-devel@nongnu.org (open list:All patches CC here)
> 
> Stefan




Re: [PATCH v3 1/1] Fix the coredump when memory backend id conflicts with default_ram_id

2022-06-13 Thread Igor Mammedov
On Mon, 13 Jun 2022 12:44:02 +0200
Li Zhang  wrote:

> When no memory backend is specified in machine options,
> a default memory device will be added with default_ram_id.
> However, if a memory backend object is added in QEMU options
> and id is the same as default_ram_id, a coredump happens.
> 
> Command line:
> qemu-system-x86_64 -name guest=vmtest,debug-threads=on \
> -machine pc-q35-6.0,accel=kvm,usb=off,vmport=off \
> -smp 16,sockets=16,cores=1,threads=1 \
> -m 4G \
> -object memory-backend-ram,id=pc.ram,size=4G \
> -no-user-config -nodefaults -nographic
> 
> Stack trace of thread 16903:
> #0  0x7fb109a9318b raise (libc.so.6 + 0x3a18b)
> #1  0x7fb109a94585 abort (libc.so.6 + 0x3b585)
> #2  0x558c34bc89be error_handle_fatal (qemu-system-x86_64 + 0x9c89be)
> #3  0x558c34bc8aee error_setv (qemu-system-x86_64 + 0x9c8aee)
> #4  0x558c34bc8ccf error_setg_internal (qemu-system-x86_64 + 0x9c8ccf)
> #5  0x558c349f6899 object_property_try_add (qemu-system-x86_64 + 
> 0x7f6899)
> #6  0x558c349f7df8 object_property_try_add_child (qemu-system-x86_64 
> + 0x7f7df8)
> #7  0x558c349f7e91 object_property_add_child (qemu-system-x86_64 + 
> 0x7f7e91)
> #8  0x558c3454686d create_default_memdev (qemu-system-x86_64 + 
> 0x34686d)
> #9  0x558c34546f58 qemu_init_board (qemu-system-x86_64 + 0x346f58)
> #10 0x558c345471b9 qmp_x_exit_preconfig (qemu-system-x86_64 + 
> 0x3471b9)
> #11 0x558c345497d9 qemu_init (qemu-system-x86_64 + 0x3497d9)
> #12 0x558c344e54c2 main (qemu-system-x86_64 + 0x2e54c2)
> #13 0x7fb109a7e34d __libc_start_main (libc.so.6 + 0x2534d)
> #14 0x558c344e53ba _start (qemu-system-x86_64 + 0x2e53ba)
> 
> Signed-off-by: Li Zhang 

Acked-by: Igor Mammedov 


CCing David as he probably would be the one to merge it

> ---
>  hw/core/machine.c | 12 
>  1 file changed, 12 insertions(+)
> 
> diff --git a/hw/core/machine.c b/hw/core/machine.c
> index a673302cce..9ede63b01c 100644
> --- a/hw/core/machine.c
> +++ b/hw/core/machine.c
> @@ -1265,9 +1265,21 @@ MemoryRegion *machine_consume_memdev(MachineState 
> *machine,
>  static bool create_default_memdev(MachineState *ms, const char *path, Error 
> **errp)
>  {
>  Object *obj;
> +ObjectProperty *prop;
>  MachineClass *mc = MACHINE_GET_CLASS(ms);
>  bool r = false;
>  
> +prop = object_property_find(object_get_objects_root(), 
> mc->default_ram_id);
> +if (prop) {
> +error_report("A memory backend with id '%s' already exists, "
> + "cannot create default RAM backend with the same id. "
> + "Either change id of the offending backend or "
> + "provide system RAM backend explicitly using "
> + "'-machine memory-backend' option. " ,
> + mc->default_ram_id);
> +exit(EXIT_FAILURE);
> +}
> +
>  obj = object_new(path ? TYPE_MEMORY_BACKEND_FILE : 
> TYPE_MEMORY_BACKEND_RAM);
>  if (path) {
>  if (!object_property_set_str(obj, "mem-path", path, errp)) {




Re: [PATCH 2/3] hw/acpi/aml-build: Fix {socket, cluster, core} IDs in PPTT

2022-06-09 Thread Igor Mammedov
On Thu, 26 May 2022 22:40:05 +0800
Gavin Shan  wrote:

> Hi Igor,
> 
> On 5/26/22 8:25 PM, Igor Mammedov wrote:
> > On Wed, 18 May 2022 17:21:40 +0800
> > Gavin Shan  wrote:
> >   
> >> The {socket, cluster, core} IDs detected from Linux guest aren't
> >> matching with what have been provided in PPTT. The flag used for
> >> 'ACPI Processor ID valid' is missed for {socket, cluster, core}
> >> nodes.  
> > 
> > To permit this flag set  on no leaf nodes we have to have
> > a corresponding containers built for them in DSDT so that
> > 'ACPI Processor ID' could be matched with containers '_UID's.
> > If we don not build such containers then setting this flag is
> > not correct. And I don't recall QEMU building CPU hierarchy
> > in DSDT.
> >   
> 
> It's true that we don't have containers in DSDT. In Linux implementation,
> the corresponding IDs are fetched if 'ACPI Processor ID valid' is set in
> PPTT node (entry), without checking DSDT table.

linux can makeup container IDs and it is fine as long as it
does that consistently

> I don't know how the PPTT entry is linked to DSDT for _UID, after rechecking
> ACPI specification. I was thinking 'Private Resources' fields are used for
> the linking, but I should be wrong after checking PPTT tables on my host.
> I'm not sure if you have idea how PPTT entry (node) is linked with one
> specific device in DSDT table?

from spec description of 'ACPI Processor ID valid' flag:
"
For non-leaf entries in the processor topology, the ACPI Pro-
cessor ID entry can relate to a Processor container in the
namespace. The processor container will have a matching ID
value returned through the _UID method. As not every pro-
cessor hierarchy node structure in PPTT may have a matching
processor container, this flag indicates whether the ACPI pro-
cessor ID points to valid entry.
"

i.e. nothing to do with private resources
on can set this flag for a container only if there is
a container device in DSDT with _UID matching 'ACPI Processor ID'
in PPTT entry. Other possibility for setting this flag
is that processor is described in MADT (which is unlikely for
for a container)

> On my host, one of the cluster node resides at offset 10B0h and it's ID
> has been marked as valid. The 'Private Resources' fields point to the
> type-1 cache structures, which resides in PPTT table either. The cluster
> ID ('0x109') isn't appearing in DSDT table.

looks like they are cheating or spec is wrong

PS:
one of the reasons we added PPTT table is to avoid building
CPU topology hierarchy in DSDT.

> 
> [C9Ch 3228   1]Subtable Type : 01 [Cache Type]
> [C9Dh 3229   1]   Length : 18
> [C9Eh 3230   2] Reserved : 
> [CA0h 3232   4]Flags (decoded below) : 005F
>Size valid : 1
>  Number of Sets valid : 1
>   Associativity valid : 1
> Allocation Type valid : 1
>  Cache Type valid : 1
>Write Policy valid : 0
>   Line Size valid : 1
>Cache ID valid : 0
> :
> :
> [CB4h 3252   1]Subtable Type : 01 [Cache Type]
> [CB5h 3253   1]   Length : 18
> [CB6h 3254   2] Reserved : 
> [CB8h 3256   4]Flags (decoded below) : 007F
>Size valid : 1
>  Number of Sets valid : 1
>   Associativity valid : 1
> Allocation Type valid : 1
>  Cache Type valid : 1
>Write Policy valid : 1
>   Line Size valid : 1
>Cache ID valid : 0
> [CBCh 3260   4]  Next Level of Cache : 0CCC
>   :
>   :
> [10B0h 4272   1]Subtable Type : 00 [Processor Hierarchy Node]
> [10B1h 4273   1]   Length : 1C
> [10B2h 4274   2] Reserved : 
> [10B4h 4276   4]Flags (decoded below) : 0002
>  Physical package : 0
>   ACPI Processor ID valid : 1
> Processor is a thread : 0
>Node is a leaf : 0
>  Identical Implementation : 0
> [10B8h 4280   4]   Parent : 0C6C
> [10BCh 4284   4]ACPI Processor ID : 0109
> [10C0h 4288   4]  Private Resource 

Re: [PATCH v2 1/1] Fix the coredump when memory backend id conflicts with default_ram_id

2022-06-09 Thread Igor Mammedov
On Fri, 20 May 2022 11:56:02 +0200
Li Zhang  wrote:

> When no memory backend is specified in machine options,
> a default memory device will be added with default_ram_id.
> However, if a memory backend object is added in QEMU options
> and id is the same as default_ram_id, a coredump happens.
> 
> Command line:
> qemu-system-x86_64 -name guest=vmtest,debug-threads=on \
> -machine pc-q35-6.0,accel=kvm,usb=off,vmport=off \
> -smp 16,sockets=16,cores=1,threads=1 \
> -m 4G \
> -object memory-backend-ram,id=pc.ram,size=4G \
> -no-user-config -nodefaults -nographic
> 
> Stack trace of thread 16903:
> #0  0x7fb109a9318b raise (libc.so.6 + 0x3a18b)
> #1  0x7fb109a94585 abort (libc.so.6 + 0x3b585)
> #2  0x558c34bc89be error_handle_fatal (qemu-system-x86_64 + 0x9c89be)
> #3  0x558c34bc8aee error_setv (qemu-system-x86_64 + 0x9c8aee)
> #4  0x558c34bc8ccf error_setg_internal (qemu-system-x86_64 + 0x9c8ccf)
> #5  0x558c349f6899 object_property_try_add (qemu-system-x86_64 + 
> 0x7f6899)
> #6  0x558c349f7df8 object_property_try_add_child (qemu-system-x86_64 
> + 0x7f7df8)
> #7  0x558c349f7e91 object_property_add_child (qemu-system-x86_64 + 
> 0x7f7e91)
> #8  0x558c3454686d create_default_memdev (qemu-system-x86_64 + 
> 0x34686d)
> #9  0x558c34546f58 qemu_init_board (qemu-system-x86_64 + 0x346f58)
> #10 0x558c345471b9 qmp_x_exit_preconfig (qemu-system-x86_64 + 
> 0x3471b9)
> #11 0x558c345497d9 qemu_init (qemu-system-x86_64 + 0x3497d9)
> #12 0x558c344e54c2 main (qemu-system-x86_64 + 0x2e54c2)
> #13 0x7fb109a7e34d __libc_start_main (libc.so.6 + 0x2534d)
> #14 0x558c344e53ba _start (qemu-system-x86_64 + 0x2e53ba)
> 
> Signed-off-by: Li Zhang 
> ---
>  hw/core/machine.c | 8 
>  1 file changed, 8 insertions(+)
> 
> diff --git a/hw/core/machine.c b/hw/core/machine.c
> index b03d9192ba..3867af7a8a 100644
> --- a/hw/core/machine.c
> +++ b/hw/core/machine.c
> @@ -1290,9 +1290,17 @@ MemoryRegion *machine_consume_memdev(MachineState 
> *machine,
>  static bool create_default_memdev(MachineState *ms, const char *path, Error 
> **errp)
>  {
>  Object *obj;
> +ObjectProperty *prop;
>  MachineClass *mc = MACHINE_GET_CLASS(ms);
>  bool r = false;
>  
> +prop = object_property_find(object_get_objects_root(), 
> mc->default_ram_id);
> +if (prop) {
> +error_report("Memory backend id conflicts with default_ram_id %s",
> + mc->default_ram_id);

maybe something like this would be better:
 A memory backend with id '%s' already exists, cannot create default RAM 
backend with the same id.
 Either change id of the offending backend or provide system RAM backend 
explicitly using
 '-machine memory-backend' option.
 

> +exit(EXIT_FAILURE);
> +}
> +
>  obj = object_new(path ? TYPE_MEMORY_BACKEND_FILE : 
> TYPE_MEMORY_BACKEND_RAM);
>  if (path) {
>  if (!object_property_set_str(obj, "mem-path", path, errp)) {




Re: [PATCH v2 00/35] pc/q35: refactor ISA and SMBUS AML generation

2022-06-09 Thread Igor Mammedov
On Thu, 9 Jun 2022 11:30:14 +0200
Igor Mammedov  wrote:

> On Wed,  8 Jun 2022 09:53:05 -0400
> Igor Mammedov  wrote:
> 
> > Changelog:
> >   since v1:
> > * add tis 2.0  clarification to commit message (Ani Sinha)
> > * rebase on top of pci tree
> > * pick up acks  
> 
> tests fail due to new cxl testcase,
> so I need to fixup whitelisting/blob updating patches and
> then I'll resend series as v3

turns out CXL test affects only 2 patches, so no need to
resend whole series, I just posted v3 as replies to
the affected patches.

and pushed fixed up rebase to
  https://gitlab.com/imammedo/qemu acpi_misc_buses_AcpiDevAmlIf_v3


> 
> > 
> > Series is excerpt form larger refactoring that does
> > the same for PCI devices, but it's too large at this
> > point, so I've split off a relatively self-contained
> > ISA/SMBUS patches into a smaller separate series, and
> > PCI refactoring will follow up on top of this series
> > using the same AcpiDevAmlIf interface.
> > 
> > Series consolidates and unifies how pc/q35 machine
> > generates AML for ISA and SMBUS devices. It adds
> > a new more generic interface 'AcpiDevAmlIf' that
> > replaces ISA specific ISADeviceClass::build_aml
> > hook and should allow to use the same approach
> > (i.e. ask a device to provide its own AML) but
> > not limited to ISA bus.
> > Series applies AcpiDevAmlIf interface to a few
> > ISA devices that were already using
> > ISADeviceClass::build_aml and to devices /tpm,
> > applesmc,pvpanic,ipmi/ that were generated in
> > custom way. The AML generation for the later
> > class is normalized to behave like any other
> > ISA device that were using ISADeviceClass::build_aml
> > and converted to interface 'AcpiDevAmlIf'.
> > It simplifies process of building DSDT and
> > eliminates custom probing/wiring for those devices
> > as AML for them is generated at the time ISA/SMBUS
> > is enumerated.
> > 
> > Changes to DSDT tables QEMU generates are mostly
> > contextual where devices scattered across DSDT
> > are consolidated under respective device that
> > hosts bus they are attached to.
> > 
> > PS:
> >  + series adds several ACPI tests for devices
> >that were missing them.
> > 
> > Igor Mammedov (35):
> >   acpi: add interface to build device specific AML
> >   acpi: make isa_build_aml() support AcpiDevAmlIf interface
> >   acpi: fdc-isa: replace ISADeviceClass::build_aml with
> > AcpiDevAmlIfClass:build_dev_aml
> >   acpi: parallel port: replace ISADeviceClass::build_aml with
> > AcpiDevAmlIfClass:build_dev_aml
> >   acpi: serial-is: replace ISADeviceClass::build_aml with
> > AcpiDevAmlIfClass:build_dev_aml
> >   acpi: mc146818rtc: replace ISADeviceClass::build_aml with
> > AcpiDevAmlIfClass:build_dev_aml
> >   acpi: pckbd: replace ISADeviceClass::build_aml with
> > AcpiDevAmlIfClass:build_dev_aml
> >   isa-bus: drop no longer used ISADeviceClass::build_aml
> >   tests: acpi: add and whitelist DSDT.ipmismbus expected blob
> >   tests: acpi: q35: add test for smbus-ipmi device
> >   tests: acpi: update expected blob DSDT.ipmismbus
> >   tests: acpi: whitelist DSDT.ipmismbus expected blob
> >   ipmi: acpi: use relative path to resource source
> >   tests: acpi: update expected DSDT.ipmismbus blob
> >   acpi: ich9-smb: add support for AcpiDevAmlIf interface
> >   acpi: ipmi: use AcpiDevAmlIf interface to build IPMI device
> > descriptors
> >   q35: acpi: drop not needed PCMachineClass::do_not_add_smb_acpi
> >   tests: acpi: white-list to be re-factored pc/q35 DSDT
> >   acpi: pc: isa bridge: use AcpiDevAmlIf interface to build ISA device
> > descriptors
> >   acpi: q35: isa bridge: use AcpiDevAmlIf interface to build ISA device
> > descriptors
> >   tests: acpi: update expected blobs
> >   tests: acpi: add and white-list DSDT.applesmc expected blob
> >   tests: acpi: add applesmc testcase
> >   acpi: applesmc: use AcpiDevAmlIfClass:build_dev_aml to provide
> > device's AML
> >   tests: acpi: update expected blobs
> >   tests: acpi: white-lists expected DSDT.pvpanic-isa blob
> >   tests: acpi: add pvpanic-isa: testcase
> >   acpi: pvpanic-isa: use AcpiDevAmlIfClass:build_dev_aml to provide
> > device's AML
> >   tests: acpi: update expected DSDT.pvpanic-isa blob
> >   tests: acpi: white-list DSDT.tis.tpm2/DSDT.tis.tpm12 expected blobs
> >   acpi: pc/q35: tpm-tis: fix TPM device scope
> >   acpi: pc/q35: remove not needed 'if' condition on pci bus
> >   acpi: 

[PATCH v3 21/35] tests: acpi: update expected blobs

2022-06-09 Thread Igor Mammedov
   })
+}

-Device (RTC)
-{
-Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */)  // _HID: 
Hardware ID
-Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
+Device (RTC)
 {
-IO (Decode16,
-0x0070, // Range Minimum
-0x0070, // Range Maximum
-0x01,   // Alignment
-0x08,   // Length
-)
-IRQNoFlags ()
-{8}
-})
+Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */)  // 
_HID: Hardware ID
+Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource 
Settings
+{
+IO (Decode16,
+0x0070, // Range Minimum
+0x0070, // Range Maximum
+0x01,   // Alignment
+0x08,   // Length
+)
+    IRQNoFlags ()
+{8}
+})
+}
 }
 }

Signed-off-by: Igor Mammedov 
---
v3:
   update DSDT.cxl blob as well

---
 tests/qtest/bios-tables-test-allowed-diff.h |  32 
 tests/data/acpi/pc/DSDT | Bin 6002 -> 5987 bytes
 tests/data/acpi/pc/DSDT.acpierst| Bin 5969 -> 5954 bytes
 tests/data/acpi/pc/DSDT.acpihmat| Bin 7327 -> 7312 bytes
 tests/data/acpi/pc/DSDT.bridge  | Bin 8668 -> 8653 bytes
 tests/data/acpi/pc/DSDT.cphp| Bin 6466 -> 6451 bytes
 tests/data/acpi/pc/DSDT.dimmpxm | Bin 7656 -> 7641 bytes
 tests/data/acpi/pc/DSDT.hpbridge| Bin 5969 -> 5954 bytes
 tests/data/acpi/pc/DSDT.hpbrroot| Bin 3084 -> 3069 bytes
 tests/data/acpi/pc/DSDT.ipmikcs | Bin 6074 -> 6059 bytes
 tests/data/acpi/pc/DSDT.memhp   | Bin 7361 -> 7346 bytes
 tests/data/acpi/pc/DSDT.nohpet  | Bin 5860 -> 5845 bytes
 tests/data/acpi/pc/DSDT.numamem | Bin 6008 -> 5993 bytes
 tests/data/acpi/pc/DSDT.roothp  | Bin 6210 -> 6195 bytes
 tests/data/acpi/q35/DSDT| Bin 8289 -> 8274 bytes
 tests/data/acpi/q35/DSDT.acpierst   | Bin 8306 -> 8291 bytes
 tests/data/acpi/q35/DSDT.acpihmat   | Bin 9614 -> 9599 bytes
 tests/data/acpi/q35/DSDT.bridge | Bin 11003 -> 10988 bytes
 tests/data/acpi/q35/DSDT.cphp   | Bin 8753 -> 8738 bytes
 tests/data/acpi/q35/DSDT.cxl| Bin 9615 -> 9600 bytes
 tests/data/acpi/q35/DSDT.dimmpxm| Bin 9943 -> 9928 bytes
 tests/data/acpi/q35/DSDT.ipmibt | Bin 8364 -> 8349 bytes
 tests/data/acpi/q35/DSDT.ipmismbus  | Bin 8378 -> 8363 bytes
 tests/data/acpi/q35/DSDT.ivrs   | Bin 8306 -> 8291 bytes
 tests/data/acpi/q35/DSDT.memhp  | Bin 9648 -> 9633 bytes
 tests/data/acpi/q35/DSDT.mmio64 | Bin 9419 -> 9404 bytes
 tests/data/acpi/q35/DSDT.multi-bridge   | Bin 8583 -> 8568 bytes
 tests/data/acpi/q35/DSDT.nohpet | Bin 8147 -> 8132 bytes
 tests/data/acpi/q35/DSDT.numamem| Bin 8295 -> 8280 bytes
 tests/data/acpi/q35/DSDT.tis.tpm12  | Bin 8900 -> 8885 bytes
 tests/data/acpi/q35/DSDT.tis.tpm2   | Bin 8921 -> 8906 bytes
 tests/data/acpi/q35/DSDT.viot   | Bin 9398 -> 9383 bytes
 tests/data/acpi/q35/DSDT.xapic  | Bin 35652 -> 35637 bytes
 33 files changed, 32 deletions(-)

diff --git a/tests/qtest/bios-tables-test-allowed-diff.h 
b/tests/qtest/bios-tables-test-allowed-diff.h
index 666e257bf9..dfb8523c8b 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,33 +1 @@
 /* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/pc/DSDT",
-"tests/data/acpi/pc/DSDT.acpierst",
-"tests/data/acpi/pc/DSDT.acpihmat",
-"tests/data/acpi/pc/DSDT.bridge",
-"tests/data/acpi/pc/DSDT.cphp",
-"tests/data/acpi/pc/DSDT.dimmpxm",
-"tests/data/acpi/pc/DSDT.hpbridge",
-"tests/data/acpi/pc/DSDT.ipmikcs",
-"tests/data/acpi/pc/DSDT.memhp",
-"tests/data/acpi/pc/DSDT.nohpet",
-"tests/data/acpi/pc/DSDT.numamem",
-"tests/data/acpi/pc/DSDT.roothp",
-"tests/data/acpi/pc/DSDT.hpbrroot",
-"tests/data/acpi/q35/DSDT",
-"tests/data/acpi/q35/DSDT.acpierst",
-"tests/data/acpi/q35/DSDT.acpihmat",
-"tests/data/acpi/q35/DSDT.bridge",
-"tests/data/acpi/q35/DSDT.cphp",
-"tests/data/acpi/q35/DSDT.dimmpxm",
-"tests/data/acpi/q35/DSDT.ipmibt",
-

[PATCH v3 18/35] tests: acpi: white-list to be re-factored pc/q35 DSDT

2022-06-09 Thread Igor Mammedov
Signed-off-by: Igor Mammedov 
---
v3:
   - count in DSDT.cxl that just was merged upstream
---
 tests/qtest/bios-tables-test-allowed-diff.h | 32 +
 1 file changed, 32 insertions(+)

diff --git a/tests/qtest/bios-tables-test-allowed-diff.h 
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..666e257bf9 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,33 @@
 /* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/pc/DSDT",
+"tests/data/acpi/pc/DSDT.acpierst",
+"tests/data/acpi/pc/DSDT.acpihmat",
+"tests/data/acpi/pc/DSDT.bridge",
+"tests/data/acpi/pc/DSDT.cphp",
+"tests/data/acpi/pc/DSDT.dimmpxm",
+"tests/data/acpi/pc/DSDT.hpbridge",
+"tests/data/acpi/pc/DSDT.ipmikcs",
+"tests/data/acpi/pc/DSDT.memhp",
+"tests/data/acpi/pc/DSDT.nohpet",
+"tests/data/acpi/pc/DSDT.numamem",
+"tests/data/acpi/pc/DSDT.roothp",
+"tests/data/acpi/pc/DSDT.hpbrroot",
+"tests/data/acpi/q35/DSDT",
+"tests/data/acpi/q35/DSDT.acpierst",
+"tests/data/acpi/q35/DSDT.acpihmat",
+"tests/data/acpi/q35/DSDT.bridge",
+"tests/data/acpi/q35/DSDT.cphp",
+"tests/data/acpi/q35/DSDT.dimmpxm",
+"tests/data/acpi/q35/DSDT.ipmibt",
+"tests/data/acpi/q35/DSDT.ivrs",
+"tests/data/acpi/q35/DSDT.memhp",
+"tests/data/acpi/q35/DSDT.mmio64",
+"tests/data/acpi/q35/DSDT.multi-bridge",
+"tests/data/acpi/q35/DSDT.nohpet",
+"tests/data/acpi/q35/DSDT.numamem",
+"tests/data/acpi/q35/DSDT.tis.tpm12",
+"tests/data/acpi/q35/DSDT.tis.tpm2",
+"tests/data/acpi/q35/DSDT.viot",
+"tests/data/acpi/q35/DSDT.xapic",
+"tests/data/acpi/q35/DSDT.ipmismbus",
+"tests/data/acpi/q35/DSDT.cxl",
-- 
2.31.1




Re: [PATCH v2 00/35] pc/q35: refactor ISA and SMBUS AML generation

2022-06-09 Thread Igor Mammedov
On Wed,  8 Jun 2022 09:53:05 -0400
Igor Mammedov  wrote:

> Changelog:
>   since v1:
> * add tis 2.0  clarification to commit message (Ani Sinha)
> * rebase on top of pci tree
> * pick up acks

tests fail due to new cxl testcase,
so I need to fixup whitelisting/blob updating patches and
then I'll resend series as v3

> 
> Series is excerpt form larger refactoring that does
> the same for PCI devices, but it's too large at this
> point, so I've split off a relatively self-contained
> ISA/SMBUS patches into a smaller separate series, and
> PCI refactoring will follow up on top of this series
> using the same AcpiDevAmlIf interface.
> 
> Series consolidates and unifies how pc/q35 machine
> generates AML for ISA and SMBUS devices. It adds
> a new more generic interface 'AcpiDevAmlIf' that
> replaces ISA specific ISADeviceClass::build_aml
> hook and should allow to use the same approach
> (i.e. ask a device to provide its own AML) but
> not limited to ISA bus.
> Series applies AcpiDevAmlIf interface to a few
> ISA devices that were already using
> ISADeviceClass::build_aml and to devices /tpm,
> applesmc,pvpanic,ipmi/ that were generated in
> custom way. The AML generation for the later
> class is normalized to behave like any other
> ISA device that were using ISADeviceClass::build_aml
> and converted to interface 'AcpiDevAmlIf'.
> It simplifies process of building DSDT and
> eliminates custom probing/wiring for those devices
> as AML for them is generated at the time ISA/SMBUS
> is enumerated.
> 
> Changes to DSDT tables QEMU generates are mostly
> contextual where devices scattered across DSDT
> are consolidated under respective device that
> hosts bus they are attached to.
> 
> PS:
>  + series adds several ACPI tests for devices
>that were missing them.
> 
> Igor Mammedov (35):
>   acpi: add interface to build device specific AML
>   acpi: make isa_build_aml() support AcpiDevAmlIf interface
>   acpi: fdc-isa: replace ISADeviceClass::build_aml with
> AcpiDevAmlIfClass:build_dev_aml
>   acpi: parallel port: replace ISADeviceClass::build_aml with
> AcpiDevAmlIfClass:build_dev_aml
>   acpi: serial-is: replace ISADeviceClass::build_aml with
> AcpiDevAmlIfClass:build_dev_aml
>   acpi: mc146818rtc: replace ISADeviceClass::build_aml with
> AcpiDevAmlIfClass:build_dev_aml
>   acpi: pckbd: replace ISADeviceClass::build_aml with
> AcpiDevAmlIfClass:build_dev_aml
>   isa-bus: drop no longer used ISADeviceClass::build_aml
>   tests: acpi: add and whitelist DSDT.ipmismbus expected blob
>   tests: acpi: q35: add test for smbus-ipmi device
>   tests: acpi: update expected blob DSDT.ipmismbus
>   tests: acpi: whitelist DSDT.ipmismbus expected blob
>   ipmi: acpi: use relative path to resource source
>   tests: acpi: update expected DSDT.ipmismbus blob
>   acpi: ich9-smb: add support for AcpiDevAmlIf interface
>   acpi: ipmi: use AcpiDevAmlIf interface to build IPMI device
> descriptors
>   q35: acpi: drop not needed PCMachineClass::do_not_add_smb_acpi
>   tests: acpi: white-list to be re-factored pc/q35 DSDT
>   acpi: pc: isa bridge: use AcpiDevAmlIf interface to build ISA device
> descriptors
>   acpi: q35: isa bridge: use AcpiDevAmlIf interface to build ISA device
> descriptors
>   tests: acpi: update expected blobs
>   tests: acpi: add and white-list DSDT.applesmc expected blob
>   tests: acpi: add applesmc testcase
>   acpi: applesmc: use AcpiDevAmlIfClass:build_dev_aml to provide
> device's AML
>   tests: acpi: update expected blobs
>   tests: acpi: white-lists expected DSDT.pvpanic-isa blob
>   tests: acpi: add pvpanic-isa: testcase
>   acpi: pvpanic-isa: use AcpiDevAmlIfClass:build_dev_aml to provide
> device's AML
>   tests: acpi: update expected DSDT.pvpanic-isa blob
>   tests: acpi: white-list DSDT.tis.tpm2/DSDT.tis.tpm12 expected blobs
>   acpi: pc/q35: tpm-tis: fix TPM device scope
>   acpi: pc/q35: remove not needed 'if' condition on pci bus
>   acpi: tpm-tis: use AcpiDevAmlIfClass:build_dev_aml to provide device's
> AML
>   tests: acpi: update expected DSDT.tis.tpm2/DSDT.tis.tpm12 blobs
>   x86: acpi-build: do not include hw/isa/isa.h directly
> 
>  include/hw/acpi/acpi_aml_interface.h  |  40 ++
>  include/hw/acpi/ipmi.h|   9 +-
>  include/hw/i386/pc.h  |   1 -
>  include/hw/isa/isa.h  |  15 ---
>  include/hw/misc/pvpanic.h |   9 --
>  hw/acpi/acpi_interface.c  |   8 ++
>  hw/acpi/ipmi-stub.c   |   2 +-
>  hw/acpi/ipmi.c|  53 +++-
>  hw/acpi/meson.build   |   2 +-
>  hw/block/fdc-isa.c|  16

[PATCH v2 25/35] tests: acpi: update expected blobs

2022-06-08 Thread Igor Mammedov
@@ -145,6 +145,23 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC", 
0x0001)
 {
 Name (_ADR, 0x001F)  // _ADR: Address
 OperationRegion (PIRQ, PCI_Config, 0x60, 0x0C)
+Device (SMC)
+{
+Name (_HID, EisaId ("APP0001"))  // _HID: Hardware ID
+Name (_STA, 0x0B)  // _STA: Status
+Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource 
Settings
+{
+IO (Decode16,
+0x0300, // Range Minimum
+0x0300, // Range Maximum
+0x01,   // Alignment
+0x20,   // Length
+)
+IRQNoFlags ()
+{6}
+})
+}
+
 Device (KBD)
 {
 Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard 
(101/102-key, PS/2 Mouse) */)  // _HID: Hardware ID
@@ -3246,26 +3263,6 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC", 
0x0001)
 }
 }

-Scope (\_SB.PCI0.ISA)
-{
-Device (SMC)
-{
-Name (_HID, EisaId ("APP0001"))  // _HID: Hardware ID
-Name (_STA, 0x0B)  // _STA: Status
-Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
-{
-IO (Decode16,
-0x0300, // Range Minimum
-0x0300, // Range Maximum
-0x01,   // Alignment
-0x20,   // Length
-)
-IRQNoFlags ()
-    {6}
-    })
-}
-}
-
 Scope (\_SB)
 {
 Scope (PCI0)

Signed-off-by: Igor Mammedov 
---
 tests/qtest/bios-tables-test-allowed-diff.h |   1 -
 tests/data/acpi/q35/DSDT.applesmc   | Bin 0 -> 8320 bytes
 2 files changed, 1 deletion(-)

diff --git a/tests/qtest/bios-tables-test-allowed-diff.h 
b/tests/qtest/bios-tables-test-allowed-diff.h
index e893029d87..dfb8523c8b 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,2 +1 @@
 /* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/q35/DSDT.applesmc",
diff --git a/tests/data/acpi/q35/DSDT.applesmc 
b/tests/data/acpi/q35/DSDT.applesmc
index 
e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..00092aacc6ce44dd8792b00a0fa183e5b06d33c6
 100644
GIT binary patch
literal 8320
zcmb7JOKcm*8J^`!tL0K!Qk3OaY{E&)_r?xN%s)PQXYx!=g
zYz~?&&#

[PATCH v2 33/35] acpi: tpm-tis: use AcpiDevAmlIfClass:build_dev_aml to provide device's AML

2022-06-08 Thread Igor Mammedov
.. and clean up not longer needed conditionals in DSTD build code
tpm-tis AML will be fetched and included when ISA bridge will
build its own AML code (including attached devices).

Expected AML change:
the device under separate _SB.PCI0.ISA scope is moved directly
under Device(ISA) node.

Signed-off-by: Igor Mammedov 
Reviewed-by: Ani Sinha 
Acked-by: Gerd Hoffmann 
---
 hw/i386/acpi-build.c | 34 --
 hw/tpm/tpm_tis_isa.c | 32 
 2 files changed, 32 insertions(+), 34 deletions(-)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 1204b6da05..0b65fc99cd 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1804,40 +1804,6 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
 Aml *scope = aml_scope("PCI0");
 /* Scan all PCI buses. Generate tables to support hotplug. */
 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en);
-
-#ifdef CONFIG_TPM
-if (TPM_IS_TIS_ISA(tpm)) {
-dev = aml_device("ISA.TPM");
-if (misc->tpm_version == TPM_VERSION_2_0) {
-aml_append(dev, aml_name_decl("_HID",
-  aml_string("MSFT0101")));
-aml_append(dev,
-   aml_name_decl("_STR",
- aml_string("TPM 2.0 Device")));
-} else {
-aml_append(dev, aml_name_decl("_HID",
-  aml_eisaid("PNP0C31")));
-}
-aml_append(dev, aml_name_decl("_UID", aml_int(1)));
-
-aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
-crs = aml_resource_template();
-aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
-   TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
-/*
-FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs,
-Rewrite to take IRQ from TPM device model and
-fix default IRQ value there to use some unused IRQ
- */
-/* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */
-aml_append(dev, aml_name_decl("_CRS", crs));
-
-tpm_build_ppi_acpi(tpm, dev);
-
-aml_append(scope, dev);
-}
-#endif
-
 aml_append(sb_scope, scope);
 }
 }
diff --git a/hw/tpm/tpm_tis_isa.c b/hw/tpm/tpm_tis_isa.c
index 3477afd735..91e3792248 100644
--- a/hw/tpm/tpm_tis_isa.c
+++ b/hw/tpm/tpm_tis_isa.c
@@ -30,6 +30,7 @@
 #include "tpm_prop.h"
 #include "tpm_tis.h"
 #include "qom/object.h"
+#include "hw/acpi/acpi_aml_interface.h"
 
 struct TPMStateISA {
 /*< private >*/
@@ -138,10 +139,39 @@ static void tpm_tis_isa_realizefn(DeviceState *dev, Error 
**errp)
 }
 }
 
+static void build_tpm_tis_isa_aml(AcpiDevAmlIf *adev, Aml *scope)
+{
+Aml *dev, *crs;
+TPMStateISA *isadev = TPM_TIS_ISA(adev);
+TPMIf *ti = TPM_IF(isadev);
+
+dev = aml_device("TPM");
+if (tpm_tis_isa_get_tpm_version(ti) == TPM_VERSION_2_0) {
+aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));
+aml_append(dev, aml_name_decl("_STR", aml_string("TPM 2.0 Device")));
+} else {
+aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C31")));
+}
+aml_append(dev, aml_name_decl("_UID", aml_int(1)));
+aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
+crs = aml_resource_template();
+aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, TPM_TIS_ADDR_SIZE,
+  AML_READ_WRITE));
+/*
+ * FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs,
+ * fix default TPM_TIS_IRQ value there to use some unused IRQ
+ */
+/* aml_append(crs, aml_irq_no_flags(isadev->state.irq_num)); */
+aml_append(dev, aml_name_decl("_CRS", crs));
+tpm_build_ppi_acpi(ti, dev);
+aml_append(scope, dev);
+}
+
 static void tpm_tis_isa_class_init(ObjectClass *klass, void *data)
 {
 DeviceClass *dc = DEVICE_CLASS(klass);
 TPMIfClass *tc = TPM_IF_CLASS(klass);
+AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass);
 
 device_class_set_props(dc, tpm_tis_isa_properties);
 dc->vmsd  = _tpm_tis_isa;
@@ -151,6 +181,7 @@ static void tpm_tis_isa_class_init(ObjectClass *klass, void 
*data)
 tc->request_completed = tpm_tis_isa_request_completed;
 tc->get_version = tpm_tis_isa_get_tpm_version;
 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+adevc->build_dev_aml = build_tpm_tis_isa_aml;
 }
 
 static const TypeInfo tpm_tis_isa_info = {
@@ -161,6 +192,7 @@ static const TypeInfo tpm_tis_isa_info = {
 .class_init  = tpm_tis_isa_class_init,
 .interfaces = (InterfaceInfo[]) {
 { TYPE_TPM_IF },
+{ TYPE_ACPI_DEV_AML_IF },
 { }
 }
 };
-- 
2.31.1




[PATCH v2 19/35] acpi: pc: isa bridge: use AcpiDevAmlIf interface to build ISA device descriptors

2022-06-08 Thread Igor Mammedov
replaces ad-hoc build_isa_devices_aml() with generic AcpiDevAmlIf
way to build bridge AML including all devices that are attached to
its ISA bus.

Later when PCI is converted to AcpiDevAmlIf, build_piix4_isa_bridge()
will also be dropped since PCI parts itself will take care of
building device prologue/epilogue AML for each enumerated PCI
device.

Expected AML change is contextual, where ISA devices are moved
from separately declared _SB.PCI0.ISA scope , directly under
Device(ISA) node.

Signed-off-by: Igor Mammedov 
Acked-by: Gerd Hoffmann 
---
 hw/i386/acpi-build.c | 16 +++-
 hw/isa/piix3.c   | 17 +
 2 files changed, 28 insertions(+), 5 deletions(-)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index d943354999..f903f30b7e 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1280,15 +1280,22 @@ static void build_piix4_isa_bridge(Aml *table)
 {
 Aml *dev;
 Aml *scope;
+Object *obj;
+bool ambiguous;
+
+/*
+ * temporarily fish out isa bridge, build_piix4_isa_bridge() will be 
dropped
+ * once PCI is converted to AcpiDevAmlIf and would be ble to generate
+ * AML for bridge itself
+ */
+obj = object_resolve_path_type("", TYPE_PIIX3_PCI_DEVICE, );
+assert(obj && !ambiguous);
 
 scope =  aml_scope("_SB.PCI0");
 dev = aml_device("ISA");
 aml_append(dev, aml_name_decl("_ADR", aml_int(0x0001)));
 
-/* PIIX PCI to ISA irq remapping */
-aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG,
- aml_int(0x60), 0x04));
-
+call_dev_aml_func(DEVICE(obj), dev);
 aml_append(scope, dev);
 aml_append(table, scope);
 }
@@ -1476,7 +1483,6 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
 build_hpet_aml(dsdt);
 }
 build_piix4_isa_bridge(dsdt);
-build_isa_devices_aml(dsdt);
 if (pm->pcihp_bridge_en || pm->pcihp_root_en) {
 build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base);
 }
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
index dab901c9ad..bfccd666d4 100644
--- a/hw/isa/piix3.c
+++ b/hw/isa/piix3.c
@@ -32,6 +32,7 @@
 #include "sysemu/reset.h"
 #include "sysemu/runstate.h"
 #include "migration/vmstate.h"
+#include "hw/acpi/acpi_aml_interface.h"
 
 #define XEN_PIIX_NUM_PIRQS  128ULL
 
@@ -286,10 +287,24 @@ static void piix3_realize(PCIDevice *dev, Error **errp)
 qemu_register_reset(piix3_reset, d);
 }
 
+static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope)
+{
+BusChild *kid;
+BusState *bus = qdev_get_child_bus(DEVICE(adev), "isa.0");
+
+/* PIIX PCI to ISA irq remapping */
+aml_append(scope, aml_operation_region("P40C", AML_PCI_CONFIG,
+ aml_int(0x60), 0x04));
+QTAILQ_FOREACH(kid, >children, sibling) {
+call_dev_aml_func(DEVICE(kid->child), scope);
+}
+}
+
 static void pci_piix3_class_init(ObjectClass *klass, void *data)
 {
 DeviceClass *dc = DEVICE_CLASS(klass);
 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass);
 
 dc->desc= "ISA bridge";
 dc->vmsd= _piix3;
@@ -304,6 +319,7 @@ static void pci_piix3_class_init(ObjectClass *klass, void 
*data)
  * pc_piix.c's pc_init1()
  */
 dc->user_creatable = false;
+adevc->build_dev_aml = build_pci_isa_aml;
 }
 
 static const TypeInfo piix3_pci_type_info = {
@@ -314,6 +330,7 @@ static const TypeInfo piix3_pci_type_info = {
 .class_init = pci_piix3_class_init,
 .interfaces = (InterfaceInfo[]) {
 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
+{ TYPE_ACPI_DEV_AML_IF },
 { },
 },
 };
-- 
2.31.1




[PATCH v2 35/35] x86: acpi-build: do not include hw/isa/isa.h directly

2022-06-08 Thread Igor Mammedov
the last remaining dependency on ISA in acpi-build.c
is iapc_boot_arch_8042() which pulls in in isa.h
in its own header hw/input/i8042.h. Clean up
not longer needed direct inclusion of isa.h in
acpi-build.c

Signed-off-by: Igor Mammedov 
Acked-by: Gerd Hoffmann 
---
 hw/i386/acpi-build.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 0b65fc99cd..f41e14a469 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -37,7 +37,6 @@
 #include "hw/acpi/cpu.h"
 #include "hw/nvram/fw_cfg.h"
 #include "hw/acpi/bios-linker-loader.h"
-#include "hw/isa/isa.h"
 #include "hw/acpi/acpi_aml_interface.h"
 #include "hw/input/i8042.h"
 #include "hw/acpi/memory_hotplug.h"
-- 
2.31.1




[PATCH v2 31/35] acpi: pc/q35: tpm-tis: fix TPM device scope

2022-06-08 Thread Igor Mammedov
tpm-tis 2.0, is not a PCI device but ISA one, move it
under ISA scope to fix incorrect placement.

Fixes: 24cf5413aa0 (acpi: Make TPM 2.0 with TIS available as MSFT0101)
Signed-off-by: Igor Mammedov 
Reviewed-by: Ani Sinha 
Acked-by: Gerd Hoffmann 
---
 hw/i386/acpi-build.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index bbe02b068e..6b496480d2 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1813,15 +1813,14 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
 
 #ifdef CONFIG_TPM
 if (TPM_IS_TIS_ISA(tpm)) {
+dev = aml_device("ISA.TPM");
 if (misc->tpm_version == TPM_VERSION_2_0) {
-dev = aml_device("TPM");
 aml_append(dev, aml_name_decl("_HID",
   aml_string("MSFT0101")));
 aml_append(dev,
aml_name_decl("_STR",
  aml_string("TPM 2.0 Device")));
 } else {
-dev = aml_device("ISA.TPM");
 aml_append(dev, aml_name_decl("_HID",
   aml_eisaid("PNP0C31")));
 }
-- 
2.31.1




[PATCH v2 34/35] tests: acpi: update expected DSDT.tis.tpm2/DSDT.tis.tpm12 blobs

2022-06-08 Thread Igor Mammedov
expected move of tmp-tis device description directly under
Device(ISA) node.

for tpm-tis 2.0:

  @@ -145,6 +145,189 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC", 
0x0001)
   {
   Name (_ADR, 0x001F)  // _ADR: Address
   OperationRegion (PIRQ, PCI_Config, 0x60, 0x0C)
  +Device (TPM)
  +{
  +Name (_HID, "MSFT0101" /* TPM 2.0 Security Device */)  // 
_HID: Hardware ID
  +Name (_STR, "TPM 2.0 Device")  // _STR: Description String
  +Name (_UID, One)  // _UID: Unique ID
  +Name (_STA, 0x0F)  // _STA: Status
...
  +}

  @@ -3281,189 +3464,6 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC", 
0x0001)
   Method (PCNT, 0, NotSerialized)
   {
   }
  -
  -Device (TPM)
  -{
  -Name (_HID, "MSFT0101" /* TPM 2.0 Security Device */)  // 
_HID: Hardware ID
  -Name (_STR, "TPM 2.0 Device")  // _STR: Description String
  -Name (_UID, One)  // _UID: Unique ID
  -Name (_STA, 0x0F)  // _STA: Status
...
  -}

for tpm-tis 1.2:

  @@ -145,6 +145,188 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC", 
0x0001)
   {
   Name (_ADR, 0x001F)  // _ADR: Address
   OperationRegion (PIRQ, PCI_Config, 0x60, 0x0C)
  +Device (TPM)
  +{
  +Name (_HID, EisaId ("PNP0C31"))  // _HID: Hardware ID
  +Name (_UID, One)  // _UID: Unique ID
  +Name (_STA, 0x0F)  // _STA: Status
...
  +}

  @@ -3281,188 +3463,6 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC", 
0x0001)
   Method (PCNT, 0, NotSerialized)
   {
   }
  -
  -Device (ISA.TPM)
  -{
  -    Name (_HID, EisaId ("PNP0C31"))  // _HID: Hardware ID
  -Name (_UID, One)  // _UID: Unique ID
  -Name (_STA, 0x0F)  // _STA: Status
...
  -}

Signed-off-by: Igor Mammedov 
Acked-by: Ani Sinha 
---
 tests/qtest/bios-tables-test-allowed-diff.h |   2 --
 tests/data/acpi/q35/DSDT.tis.tpm12  | Bin 8885 -> 8880 bytes
 tests/data/acpi/q35/DSDT.tis.tpm2   | Bin 8906 -> 8906 bytes
 3 files changed, 2 deletions(-)

diff --git a/tests/qtest/bios-tables-test-allowed-diff.h 
b/tests/qtest/bios-tables-test-allowed-diff.h
index 7b3bf9a207..dfb8523c8b 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,3 +1 @@
 /* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/q35/DSDT.tis.tpm2",
-"tests/data/acpi/q35/DSDT.tis.tpm12",
diff --git a/tests/data/acpi/q35/DSDT.tis.tpm12 
b/tests/data/acpi/q35/DSDT.tis.tpm12
index 
0b5c97fdb5da8b7b55d6b5f2af498a447fda7bf8..a97d884c50485f848054c6ac95ecfa055ff59e5b
 100644
GIT binary patch
delta 89
zcmdn$y1|vpCDCo#F$WJq@Cp+yp#>9pgFT9bJNW7#QRk
vq8kD{g94ej61aFa$Fi`>ak*;6fK&_kYEI5ka^Z|_a#hs>Y1z!rg5>c

diff --git a/tests/data/acpi/q35/DSDT.tis.tpm2 
b/tests/data/acpi/q35/DSDT.tis.tpm2
index 
4e16b126cc1c32f2346078fa69c5261c245d15e8..1f5392919b5ea69696b49ff13aab5c37d0615919
 100644
GIT binary patch
delta 85
zcmX@*ddii{CDCo#F$WJq@Cp+yp#>9pgFT9bJNW7#QRk
nq8kD{g94ej61aFam$R_Sad~OSfK&@OX-{rba@owyl*0r7A8!`n

-- 
2.31.1




[PATCH v2 06/35] acpi: mc146818rtc: replace ISADeviceClass::build_aml with AcpiDevAmlIfClass:build_dev_aml

2022-06-08 Thread Igor Mammedov
Signed-off-by: Igor Mammedov 
Acked-by: Gerd Hoffmann 
---
 hw/rtc/mc146818rtc.c | 14 +-
 1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/hw/rtc/mc146818rtc.c b/hw/rtc/mc146818rtc.c
index f235c2ddbe..ef9765bb8f 100644
--- a/hw/rtc/mc146818rtc.c
+++ b/hw/rtc/mc146818rtc.c
@@ -26,7 +26,7 @@
 #include "qemu/cutils.h"
 #include "qemu/module.h"
 #include "qemu/bcd.h"
-#include "hw/acpi/aml-build.h"
+#include "hw/acpi/acpi_aml_interface.h"
 #include "hw/irq.h"
 #include "hw/qdev-properties.h"
 #include "hw/qdev-properties-system.h"
@@ -1017,9 +1017,9 @@ static void rtc_reset_hold(Object *obj)
 qemu_irq_lower(s->irq);
 }
 
-static void rtc_build_aml(ISADevice *isadev, Aml *scope)
+static void rtc_build_aml(AcpiDevAmlIf *adev, Aml *scope)
 {
-RTCState *s = MC146818_RTC(isadev);
+RTCState *s = MC146818_RTC(adev);
 Aml *dev;
 Aml *crs;
 
@@ -1043,13 +1043,13 @@ static void rtc_class_initfn(ObjectClass *klass, void 
*data)
 {
 DeviceClass *dc = DEVICE_CLASS(klass);
 ResettableClass *rc = RESETTABLE_CLASS(klass);
-ISADeviceClass *isa = ISA_DEVICE_CLASS(klass);
+AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass);
 
 dc->realize = rtc_realizefn;
 dc->vmsd = _rtc;
 rc->phases.enter = rtc_reset_enter;
 rc->phases.hold = rtc_reset_hold;
-isa->build_aml = rtc_build_aml;
+adevc->build_dev_aml = rtc_build_aml;
 device_class_set_props(dc, mc146818rtc_properties);
 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
 }
@@ -1059,6 +1059,10 @@ static const TypeInfo mc146818rtc_info = {
 .parent= TYPE_ISA_DEVICE,
 .instance_size = sizeof(RTCState),
 .class_init= rtc_class_initfn,
+.interfaces = (InterfaceInfo[]) {
+{ TYPE_ACPI_DEV_AML_IF },
+{ },
+},
 };
 
 static void mc146818rtc_register_types(void)
-- 
2.31.1




[PATCH v2 30/35] tests: acpi: white-list DSDT.tis.tpm2/DSDT.tis.tpm12 expected blobs

2022-06-08 Thread Igor Mammedov
Signed-off-by: Igor Mammedov 
Acked-by: Ani Sinha 
---
 tests/qtest/bios-tables-test-allowed-diff.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/tests/qtest/bios-tables-test-allowed-diff.h 
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..7b3bf9a207 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,3 @@
 /* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/q35/DSDT.tis.tpm2",
+"tests/data/acpi/q35/DSDT.tis.tpm12",
-- 
2.31.1




[PATCH v2 29/35] tests: acpi: update expected DSDT.pvpanic-isa blob

2022-06-08 Thread Igor Mammedov
@@ -145,6 +145,37 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC", 
0x0001)
 {
 Name (_ADR, 0x001F)  // _ADR: Address
 OperationRegion (PIRQ, PCI_Config, 0x60, 0x0C)
+Device (PEVT)
+{
+Name (_HID, "QEMU0001")  // _HID: Hardware ID
+Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource 
Settings
+{
+IO (Decode16,
+0x0505, // Range Minimum
+0x0505, // Range Maximum
+0x01,   // Alignment
+0x01,   // Length
+)
+})
+OperationRegion (PEOR, SystemIO, 0x0505, One)
+Field (PEOR, ByteAcc, NoLock, Preserve)
+{
+PEPT,   8
+}
+
+Name (_STA, 0x0F)  // _STA: Status
+Method (RDPT, 0, NotSerialized)
+{
+Local0 = PEPT /* \_SB_.PCI0.ISA_.PEVT.PEPT */
+Return (Local0)
+}
+
+Method (WRPT, 1, NotSerialized)
+{
+PEPT = Arg0
+}
+}
+
 Device (KBD)
 {
 Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard 
(101/102-key, PS/2 Mouse) */)  // _HID: Hardware ID
@@ -3246,40 +3277,6 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC", 
0x0001)
 }
 }

-Scope (\_SB.PCI0.ISA)
-{
-Device (PEVT)
-{
-Name (_HID, "QEMU0001")  // _HID: Hardware ID
-Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
-{
-IO (Decode16,
-0x0505, // Range Minimum
-0x0505, // Range Maximum
-0x01,   // Alignment
-0x01,   // Length
-)
-})
-OperationRegion (PEOR, SystemIO, 0x0505, One)
-Field (PEOR, ByteAcc, NoLock, Preserve)
-{
-PEPT,   8
-}
-
-Name (_STA, 0x0F)  // _STA: Status
-Method (RDPT, 0, NotSerialized)
-{
-Local0 = PEPT /* \_SB_.PCI0.ISA_.PEVT.PEPT */
-Return (Local0)
-}
-
-Method (WRPT, 1, NotSerialized)
-{
-PEPT = Arg0
-}
-}
-}
-
 Scope (\_SB)
 {
 Scope (PCI0)

Signed-off-by: Igor Mammedov 
---
 tests/qtest/bios-tables-test-allowed-diff.h |   1 -
 tests/data/acpi/q35/DSDT.pvpanic-isa| Bin 0 -> 8375 bytes
 2 files changed, 1 deletion(-)

diff --git a/tests/qtest/bios-tables-test-allowed-diff.h 
b/tests/qtest/bios-tables-test-allowed-diff.h
index d5cd7aa4f5..dfb8523c8b 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,2 +1 @@
 /* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/q35/DSDT.pvpanic-isa",
diff --git a/tests/data/acpi/q35/DSDT.pvpanic-isa 
b/tests/data/acpi/q35/DSDT.pvpanic-isa
index 
e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..cc545b5d2505246d33f83d2482273968aa1be032
 100644
GIT binary patch
literal 8375
zcmb7JOKcm*8J^`!tK~{sQk3LZY{E&?~(R|lb;iIo;;J^}
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z#ReTV5l7ms#3Q74mGmx8?~bK+k4W#1(tBg#Eo^9gXZ

[PATCH v2 32/35] acpi: pc/q35: remove not needed 'if' condition on pci bus

2022-06-08 Thread Igor Mammedov
Signed-off-by: Igor Mammedov 
Reviewed-by: Ani Sinha 
Acked-by: Gerd Hoffmann 
---
 hw/i386/acpi-build.c | 10 ++
 1 file changed, 2 insertions(+), 8 deletions(-)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 6b496480d2..1204b6da05 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1797,16 +1797,10 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
 
 sb_scope = aml_scope("\\_SB");
 {
-Object *pci_host;
-PCIBus *bus = NULL;
-
-pci_host = acpi_get_i386_pci_host();
+Object *pci_host = acpi_get_i386_pci_host();
 
 if (pci_host) {
-bus = PCI_HOST_BRIDGE(pci_host)->bus;
-}
-
-if (bus) {
+PCIBus *bus = PCI_HOST_BRIDGE(pci_host)->bus;
 Aml *scope = aml_scope("PCI0");
 /* Scan all PCI buses. Generate tables to support hotplug. */
 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en);
-- 
2.31.1




[PATCH v2 16/35] acpi: ipmi: use AcpiDevAmlIf interface to build IPMI device descriptors

2022-06-08 Thread Igor Mammedov
convert ad-hoc way we use to generate AML for ISA/SMB IPMI devices
to a generic approach (i.e. make devices provide its own AML blobs
like it is done with other ISA devices (ex. KBD))

Signed-off-by: Igor Mammedov 
Acked-by: Gerd Hoffmann 
---
 include/hw/acpi/ipmi.h |  9 ++--
 hw/acpi/ipmi-stub.c|  2 +-
 hw/acpi/ipmi.c | 49 +-
 hw/i386/acpi-build.c   | 17 ++-
 hw/ipmi/isa_ipmi_bt.c  |  4 
 hw/ipmi/isa_ipmi_kcs.c |  4 
 hw/ipmi/smbus_ipmi.c   |  4 
 7 files changed, 42 insertions(+), 47 deletions(-)

diff --git a/include/hw/acpi/ipmi.h b/include/hw/acpi/ipmi.h
index c38483565c..6c8079c97a 100644
--- a/include/hw/acpi/ipmi.h
+++ b/include/hw/acpi/ipmi.h
@@ -9,13 +9,8 @@
 #ifndef HW_ACPI_IPMI_H
 #define HW_ACPI_IPMI_H
 
-#include "hw/acpi/aml-build.h"
+#include "hw/acpi/acpi_aml_interface.h"
 
-/*
- * Add ACPI IPMI entries for all registered IPMI devices whose parent
- * bus matches the given bus.  The resource is the ACPI resource that
- * contains the IPMI device, this is required for the I2C CRS.
- */
-void build_acpi_ipmi_devices(Aml *table, BusState *bus);
+void build_ipmi_dev_aml(AcpiDevAmlIf *adev, Aml *scope);
 
 #endif /* HW_ACPI_IPMI_H */
diff --git a/hw/acpi/ipmi-stub.c b/hw/acpi/ipmi-stub.c
index f525f71c2d..befaf0a882 100644
--- a/hw/acpi/ipmi-stub.c
+++ b/hw/acpi/ipmi-stub.c
@@ -10,6 +10,6 @@
 #include "qemu/osdep.h"
 #include "hw/acpi/ipmi.h"
 
-void build_acpi_ipmi_devices(Aml *table, BusState *bus)
+void build_ipmi_dev_aml(AcpiDevAmlIf *adev, Aml *scope)
 {
 }
diff --git a/hw/acpi/ipmi.c b/hw/acpi/ipmi.c
index c30b44fcf5..a20e57d465 100644
--- a/hw/acpi/ipmi.c
+++ b/hw/acpi/ipmi.c
@@ -62,46 +62,27 @@ static Aml *aml_ipmi_crs(IPMIFwInfo *info)
 return crs;
 }
 
-static Aml *aml_ipmi_device(IPMIFwInfo *info)
+void build_ipmi_dev_aml(AcpiDevAmlIf *adev, Aml *scope)
 {
 Aml *dev;
-uint16_t version = ((info->ipmi_spec_major_revision << 8)
-| (info->ipmi_spec_minor_revision << 4));
+IPMIFwInfo info = {};
+IPMIInterface *ii = IPMI_INTERFACE(adev);
+IPMIInterfaceClass *iic = IPMI_INTERFACE_GET_CLASS(ii);
+uint16_t version;
 
-assert(info->ipmi_spec_minor_revision <= 15);
+iic->get_fwinfo(ii, );
+assert(info.ipmi_spec_minor_revision <= 15);
+version = ((info.ipmi_spec_major_revision << 8)
+  | (info.ipmi_spec_minor_revision << 4));
 
-dev = aml_device("MI%d", info->uuid);
+dev = aml_device("MI%d", info.uuid);
 aml_append(dev, aml_name_decl("_HID", aml_eisaid("IPI0001")));
 aml_append(dev, aml_name_decl("_STR", aml_string("ipmi_%s",
- info->interface_name)));
-aml_append(dev, aml_name_decl("_UID", aml_int(info->uuid)));
-aml_append(dev, aml_name_decl("_CRS", aml_ipmi_crs(info)));
-aml_append(dev, aml_name_decl("_IFT", aml_int(info->interface_type)));
+ info.interface_name)));
+aml_append(dev, aml_name_decl("_UID", aml_int(info.uuid)));
+aml_append(dev, aml_name_decl("_CRS", aml_ipmi_crs()));
+aml_append(dev, aml_name_decl("_IFT", aml_int(info.interface_type)));
 aml_append(dev, aml_name_decl("_SRV", aml_int(version)));
 
-return dev;
-}
-
-void build_acpi_ipmi_devices(Aml *scope, BusState *bus)
-{
-
-BusChild *kid;
-
-QTAILQ_FOREACH(kid, >children,  sibling) {
-IPMIInterface *ii;
-IPMIInterfaceClass *iic;
-IPMIFwInfo info;
-Object *obj = object_dynamic_cast(OBJECT(kid->child),
-  TYPE_IPMI_INTERFACE);
-
-if (!obj) {
-continue;
-}
-
-ii = IPMI_INTERFACE(obj);
-iic = IPMI_INTERFACE_GET_CLASS(obj);
-memset(, 0, sizeof(info));
-iic->get_fwinfo(ii, );
-aml_append(scope, aml_ipmi_device());
-}
+aml_append(scope, dev);
 }
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 88506d563f..5b963cca32 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -39,6 +39,7 @@
 #include "hw/nvram/fw_cfg.h"
 #include "hw/acpi/bios-linker-loader.h"
 #include "hw/isa/isa.h"
+#include "hw/acpi/acpi_aml_interface.h"
 #include "hw/input/i8042.h"
 #include "hw/acpi/memory_hotplug.h"
 #include "sysemu/tpm.h"
@@ -73,7 +74,6 @@
 #include "hw/i386/intel_iommu.h"
 #include "hw/virtio/virtio-iommu.h"
 
-#include "hw/acpi/ipmi.h"
 #include "hw/acpi/hmat.h"
 #include "hw/acpi/viot.h"
 #include "hw/acpi/cxl.h"
@@ -873,7 +873,6 @@ static void build_isa_devices_aml(Aml *table)
 assert(obj &a

[PATCH v2 27/35] tests: acpi: add pvpanic-isa: testcase

2022-06-08 Thread Igor Mammedov
Signed-off-by: Igor Mammedov 
Acked-by: Gerd Hoffmann 
---
 tests/qtest/bios-tables-test.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 7d238218ca..56498bbcc8 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -1636,6 +1636,17 @@ static void test_acpi_q35_applesmc(void)
 free_test_data();
 }
 
+static void test_acpi_q35_pvpanic_isa(void)
+{
+test_data data = {
+.machine = MACHINE_Q35,
+.variant = ".pvpanic-isa",
+};
+
+test_acpi_one("-device pvpanic", );
+free_test_data();
+}
+
 static void test_oem_fields(test_data *data)
 {
 int i;
@@ -1795,6 +1806,7 @@ int main(int argc, char *argv[])
 qtest_add_func("acpi/piix4/acpierst", test_acpi_piix4_acpi_erst);
 qtest_add_func("acpi/q35/acpierst", test_acpi_q35_acpi_erst);
 qtest_add_func("acpi/q35/applesmc", test_acpi_q35_applesmc);
+qtest_add_func("acpi/q35/pvpanic-isa", test_acpi_q35_pvpanic_isa);
 qtest_add_func("acpi/microvm", test_acpi_microvm_tcg);
 qtest_add_func("acpi/microvm/usb", test_acpi_microvm_usb_tcg);
 qtest_add_func("acpi/microvm/rtc", test_acpi_microvm_rtc_tcg);
-- 
2.31.1




[PATCH v2 15/35] acpi: ich9-smb: add support for AcpiDevAmlIf interface

2022-06-08 Thread Igor Mammedov
wire AcpiDevAmlIf interface to build ich9-smb and its slave
devices AML. It will be used by followup patches to switch
from creating AML in ad-hoc way to a more systematic one
that will scan present devices and ask them to provide
their AML code like it's done with ISA devices.

This patch is a partial conversion, as it only fetches
AML from slave devices attached to its I2C bus.

The conversion will be completed when PCI bus is
switched to use AcpiDevAmlIf and build_smb0() could be
dropped.

Signed-off-by: Igor Mammedov 
Acked-by: Gerd Hoffmann 
---
 hw/i2c/smbus_ich9.c | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/hw/i2c/smbus_ich9.c b/hw/i2c/smbus_ich9.c
index 44dd5653b7..ee50ba1f2c 100644
--- a/hw/i2c/smbus_ich9.c
+++ b/hw/i2c/smbus_ich9.c
@@ -29,6 +29,7 @@
 
 #include "hw/i386/ich9.h"
 #include "qom/object.h"
+#include "hw/acpi/acpi_aml_interface.h"
 
 OBJECT_DECLARE_SIMPLE_TYPE(ICH9SMBState, ICH9_SMB_DEVICE)
 
@@ -94,10 +95,22 @@ static void ich9_smbus_realize(PCIDevice *d, Error **errp)
  >smb.io);
 }
 
+static void build_ich9_smb_aml(AcpiDevAmlIf *adev, Aml *scope)
+{
+BusChild *kid;
+ICH9SMBState *s = ICH9_SMB_DEVICE(adev);
+BusState *bus = BUS(s->smb.smbus);
+
+QTAILQ_FOREACH(kid, >children, sibling) {
+call_dev_aml_func(DEVICE(kid->child), scope);
+}
+}
+
 static void ich9_smb_class_init(ObjectClass *klass, void *data)
 {
 DeviceClass *dc = DEVICE_CLASS(klass);
 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass);
 
 k->vendor_id = PCI_VENDOR_ID_INTEL;
 k->device_id = PCI_DEVICE_ID_INTEL_ICH9_6;
@@ -112,6 +125,7 @@ static void ich9_smb_class_init(ObjectClass *klass, void 
*data)
  * pc_q35_init()
  */
 dc->user_creatable = false;
+adevc->build_dev_aml = build_ich9_smb_aml;
 }
 
 static void ich9_smb_set_irq(PMSMBus *pmsmb, bool enabled)
@@ -143,6 +157,7 @@ static const TypeInfo ich9_smb_info = {
 .class_init = ich9_smb_class_init,
 .interfaces = (InterfaceInfo[]) {
 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
+{ TYPE_ACPI_DEV_AML_IF },
 { },
 },
 };
-- 
2.31.1




[PATCH v2 21/35] tests: acpi: update expected blobs

2022-06-08 Thread Igor Mammedov
   })
+}

-Device (RTC)
-{
-Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */)  // _HID: 
Hardware ID
-Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
+Device (RTC)
 {
-IO (Decode16,
-0x0070, // Range Minimum
-0x0070, // Range Maximum
-0x01,   // Alignment
-0x08,   // Length
-)
-IRQNoFlags ()
-{8}
-})
+Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */)  // 
_HID: Hardware ID
+Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource 
Settings
+{
+IO (Decode16,
+0x0070, // Range Minimum
+0x0070, // Range Maximum
+0x01,   // Alignment
+0x08,   // Length
+)
+    IRQNoFlags ()
+{8}
+})
+}
 }
 }

Signed-off-by: Igor Mammedov 
---
 tests/qtest/bios-tables-test-allowed-diff.h |  31 
 tests/data/acpi/pc/DSDT | Bin 6002 -> 5987 bytes
 tests/data/acpi/pc/DSDT.acpierst| Bin 5969 -> 5954 bytes
 tests/data/acpi/pc/DSDT.acpihmat| Bin 7327 -> 7312 bytes
 tests/data/acpi/pc/DSDT.bridge  | Bin 8668 -> 8653 bytes
 tests/data/acpi/pc/DSDT.cphp| Bin 6466 -> 6451 bytes
 tests/data/acpi/pc/DSDT.dimmpxm | Bin 7656 -> 7641 bytes
 tests/data/acpi/pc/DSDT.hpbridge| Bin 5969 -> 5954 bytes
 tests/data/acpi/pc/DSDT.hpbrroot| Bin 3084 -> 3069 bytes
 tests/data/acpi/pc/DSDT.ipmikcs | Bin 6074 -> 6059 bytes
 tests/data/acpi/pc/DSDT.memhp   | Bin 7361 -> 7346 bytes
 tests/data/acpi/pc/DSDT.nohpet  | Bin 5860 -> 5845 bytes
 tests/data/acpi/pc/DSDT.numamem | Bin 6008 -> 5993 bytes
 tests/data/acpi/pc/DSDT.roothp  | Bin 6210 -> 6195 bytes
 tests/data/acpi/q35/DSDT| Bin 8289 -> 8274 bytes
 tests/data/acpi/q35/DSDT.acpierst   | Bin 8306 -> 8291 bytes
 tests/data/acpi/q35/DSDT.acpihmat   | Bin 9614 -> 9599 bytes
 tests/data/acpi/q35/DSDT.bridge | Bin 11003 -> 10988 bytes
 tests/data/acpi/q35/DSDT.cphp   | Bin 8753 -> 8738 bytes
 tests/data/acpi/q35/DSDT.dimmpxm| Bin 9943 -> 9928 bytes
 tests/data/acpi/q35/DSDT.ipmibt | Bin 8364 -> 8349 bytes
 tests/data/acpi/q35/DSDT.ipmismbus  | Bin 8378 -> 8363 bytes
 tests/data/acpi/q35/DSDT.ivrs   | Bin 8306 -> 8291 bytes
 tests/data/acpi/q35/DSDT.memhp  | Bin 9648 -> 9633 bytes
 tests/data/acpi/q35/DSDT.mmio64 | Bin 9419 -> 9404 bytes
 tests/data/acpi/q35/DSDT.multi-bridge   | Bin 8583 -> 8568 bytes
 tests/data/acpi/q35/DSDT.nohpet | Bin 8147 -> 8132 bytes
 tests/data/acpi/q35/DSDT.numamem| Bin 8295 -> 8280 bytes
 tests/data/acpi/q35/DSDT.tis.tpm12  | Bin 8900 -> 8885 bytes
 tests/data/acpi/q35/DSDT.tis.tpm2   | Bin 8921 -> 8906 bytes
 tests/data/acpi/q35/DSDT.viot   | Bin 9398 -> 9383 bytes
 tests/data/acpi/q35/DSDT.xapic  | Bin 35652 -> 35637 bytes
 32 files changed, 31 deletions(-)

diff --git a/tests/qtest/bios-tables-test-allowed-diff.h 
b/tests/qtest/bios-tables-test-allowed-diff.h
index d95f4b25c4..dfb8523c8b 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,32 +1 @@
 /* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/pc/DSDT",
-"tests/data/acpi/pc/DSDT.acpierst",
-"tests/data/acpi/pc/DSDT.acpihmat",
-"tests/data/acpi/pc/DSDT.bridge",
-"tests/data/acpi/pc/DSDT.cphp",
-"tests/data/acpi/pc/DSDT.dimmpxm",
-"tests/data/acpi/pc/DSDT.hpbridge",
-"tests/data/acpi/pc/DSDT.ipmikcs",
-"tests/data/acpi/pc/DSDT.memhp",
-"tests/data/acpi/pc/DSDT.nohpet",
-"tests/data/acpi/pc/DSDT.numamem",
-"tests/data/acpi/pc/DSDT.roothp",
-"tests/data/acpi/pc/DSDT.hpbrroot",
-"tests/data/acpi/q35/DSDT",
-"tests/data/acpi/q35/DSDT.acpierst",
-"tests/data/acpi/q35/DSDT.acpihmat",
-"tests/data/acpi/q35/DSDT.bridge",
-"tests/data/acpi/q35/DSDT.cphp",
-"tests/data/acpi/q35/DSDT.dimmpxm",
-"tests/data/acpi/q35/DSDT.ipmibt",
-"tests/data/acpi/q35/DSDT.ivrs",
-"tests/data/acpi/q35/DSDT.memhp",
-"tests/

[PATCH v2 28/35] acpi: pvpanic-isa: use AcpiDevAmlIfClass:build_dev_aml to provide device's AML

2022-06-08 Thread Igor Mammedov
.. and clean up not longer needed conditionals in DSTD build code
pvpanic-isa AML will be fetched and included when ISA bridge will
build its own AML code (including attached devices).

Expected AML change:
   the device under separate _SB.PCI0.ISA scope is moved directly
   under Device(ISA) node.

Signed-off-by: Igor Mammedov 
Acked-by: Gerd Hoffmann 
---
 include/hw/misc/pvpanic.h |  9 -
 hw/i386/acpi-build.c  | 37 --
 hw/misc/pvpanic-isa.c | 42 +++
 3 files changed, 42 insertions(+), 46 deletions(-)

diff --git a/include/hw/misc/pvpanic.h b/include/hw/misc/pvpanic.h
index 7f16cc9b16..e520566ab0 100644
--- a/include/hw/misc/pvpanic.h
+++ b/include/hw/misc/pvpanic.h
@@ -33,13 +33,4 @@ struct PVPanicState {
 
 void pvpanic_setup_io(PVPanicState *s, DeviceState *dev, unsigned size);
 
-static inline uint16_t pvpanic_port(void)
-{
-Object *o = object_resolve_path_type("", TYPE_PVPANIC_ISA_DEVICE, NULL);
-if (!o) {
-return 0;
-}
-return object_property_get_uint(o, PVPANIC_IOPORT_PROP, NULL);
-}
-
 #endif
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index b96705c688..bbe02b068e 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -31,7 +31,6 @@
 #include "hw/cxl/cxl.h"
 #include "hw/core/cpu.h"
 #include "target/i386/cpu.h"
-#include "hw/misc/pvpanic.h"
 #include "hw/timer/hpet.h"
 #include "hw/acpi/acpi-defs.h"
 #include "hw/acpi/acpi.h"
@@ -120,7 +119,6 @@ typedef struct AcpiMiscInfo {
 #endif
 const unsigned char *dsdt_code;
 unsigned dsdt_size;
-uint16_t pvpanic_port;
 } AcpiMiscInfo;
 
 typedef struct AcpiBuildPciBusHotplugState {
@@ -305,7 +303,6 @@ static void acpi_get_misc_info(AcpiMiscInfo *info)
 #ifdef CONFIG_TPM
 info->tpm_version = tpm_get_version(tpm_find());
 #endif
-info->pvpanic_port = pvpanic_port();
 }
 
 /*
@@ -1798,40 +1795,6 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
 aml_append(dsdt, scope);
 }
 
-if (misc->pvpanic_port) {
-scope = aml_scope("\\_SB.PCI0.ISA");
-
-dev = aml_device("PEVT");
-aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
-
-crs = aml_resource_template();
-aml_append(crs,
-aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
-);
-aml_append(dev, aml_name_decl("_CRS", crs));
-
-aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
-  aml_int(misc->pvpanic_port), 1));
-field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
-aml_append(field, aml_named_field("PEPT", 8));
-aml_append(dev, field);
-
-/* device present, functioning, decoding, shown in UI */
-aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
-
-method = aml_method("RDPT", 0, AML_NOTSERIALIZED);
-aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
-aml_append(method, aml_return(aml_local(0)));
-aml_append(dev, method);
-
-method = aml_method("WRPT", 1, AML_NOTSERIALIZED);
-aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
-aml_append(dev, method);
-
-aml_append(scope, dev);
-aml_append(dsdt, scope);
-}
-
 sb_scope = aml_scope("\\_SB");
 {
 Object *pci_host;
diff --git a/hw/misc/pvpanic-isa.c b/hw/misc/pvpanic-isa.c
index b84d4d458d..ccec50f61b 100644
--- a/hw/misc/pvpanic-isa.c
+++ b/hw/misc/pvpanic-isa.c
@@ -22,6 +22,7 @@
 #include "qom/object.h"
 #include "hw/isa/isa.h"
 #include "standard-headers/linux/pvpanic.h"
+#include "hw/acpi/acpi_aml_interface.h"
 
 OBJECT_DECLARE_SIMPLE_TYPE(PVPanicISAState, PVPANIC_ISA_DEVICE)
 
@@ -63,6 +64,41 @@ static void pvpanic_isa_realizefn(DeviceState *dev, Error 
**errp)
 isa_register_ioport(d, >mr, s->ioport);
 }
 
+static void build_pvpanic_isa_aml(AcpiDevAmlIf *adev, Aml *scope)
+{
+Aml *crs, *field, *method;
+PVPanicISAState *s = PVPANIC_ISA_DEVICE(adev);
+Aml *dev = aml_device("PEVT");
+
+aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
+
+crs = aml_resource_template();
+aml_append(crs,
+aml_io(AML_DECODE16, s->ioport, s->ioport, 1, 1)
+);
+aml_append(dev, aml_name_decl("_CRS", crs));
+
+aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
+  aml_int(s->ioport), 1));
+field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
+aml_append(field, aml_named_field("PEPT", 8));
+aml_append(dev, f

[PATCH v2 18/35] tests: acpi: white-list to be re-factored pc/q35 DSDT

2022-06-08 Thread Igor Mammedov
Signed-off-by: Igor Mammedov 
---
 tests/qtest/bios-tables-test-allowed-diff.h | 31 +
 1 file changed, 31 insertions(+)

diff --git a/tests/qtest/bios-tables-test-allowed-diff.h 
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..d95f4b25c4 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,32 @@
 /* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/pc/DSDT",
+"tests/data/acpi/pc/DSDT.acpierst",
+"tests/data/acpi/pc/DSDT.acpihmat",
+"tests/data/acpi/pc/DSDT.bridge",
+"tests/data/acpi/pc/DSDT.cphp",
+"tests/data/acpi/pc/DSDT.dimmpxm",
+"tests/data/acpi/pc/DSDT.hpbridge",
+"tests/data/acpi/pc/DSDT.ipmikcs",
+"tests/data/acpi/pc/DSDT.memhp",
+"tests/data/acpi/pc/DSDT.nohpet",
+"tests/data/acpi/pc/DSDT.numamem",
+"tests/data/acpi/pc/DSDT.roothp",
+"tests/data/acpi/pc/DSDT.hpbrroot",
+"tests/data/acpi/q35/DSDT",
+"tests/data/acpi/q35/DSDT.acpierst",
+"tests/data/acpi/q35/DSDT.acpihmat",
+"tests/data/acpi/q35/DSDT.bridge",
+"tests/data/acpi/q35/DSDT.cphp",
+"tests/data/acpi/q35/DSDT.dimmpxm",
+"tests/data/acpi/q35/DSDT.ipmibt",
+"tests/data/acpi/q35/DSDT.ivrs",
+"tests/data/acpi/q35/DSDT.memhp",
+"tests/data/acpi/q35/DSDT.mmio64",
+"tests/data/acpi/q35/DSDT.multi-bridge",
+"tests/data/acpi/q35/DSDT.nohpet",
+"tests/data/acpi/q35/DSDT.numamem",
+"tests/data/acpi/q35/DSDT.tis.tpm12",
+"tests/data/acpi/q35/DSDT.tis.tpm2",
+"tests/data/acpi/q35/DSDT.viot",
+"tests/data/acpi/q35/DSDT.xapic",
+"tests/data/acpi/q35/DSDT.ipmismbus",
-- 
2.31.1




[PATCH v2 24/35] acpi: applesmc: use AcpiDevAmlIfClass:build_dev_aml to provide device's AML

2022-06-08 Thread Igor Mammedov
  .. and clean up not longer needed conditionals in DSTD build
code. applesmc AML will be fetched and included when ISA bridge
will build its own AML code (incl. attached devices).

Expected AML change:
the device under separate _SB.PCI0.ISA scope is moved directly
under Device(ISA) node.

Signed-off-by: Igor Mammedov 
Acked-by: Gerd Hoffmann 
---
 include/hw/isa/isa.h | 14 --
 hw/i386/acpi-build.c | 22 --
 hw/misc/applesmc.c   | 29 +
 3 files changed, 29 insertions(+), 36 deletions(-)

diff --git a/include/hw/isa/isa.h b/include/hw/isa/isa.h
index 5c5a3d43a7..6f9380007d 100644
--- a/include/hw/isa/isa.h
+++ b/include/hw/isa/isa.h
@@ -16,20 +16,6 @@ OBJECT_DECLARE_TYPE(ISADevice, ISADeviceClass, ISA_DEVICE)
 #define TYPE_ISA_BUS "ISA"
 OBJECT_DECLARE_SIMPLE_TYPE(ISABus, ISA_BUS)
 
-#define TYPE_APPLE_SMC "isa-applesmc"
-#define APPLESMC_MAX_DATA_LENGTH   32
-#define APPLESMC_PROP_IO_BASE "iobase"
-
-static inline uint16_t applesmc_port(void)
-{
-Object *obj = object_resolve_path_type("", TYPE_APPLE_SMC, NULL);
-
-if (obj) {
-return object_property_get_uint(obj, APPLESMC_PROP_IO_BASE, NULL);
-}
-return 0;
-}
-
 #define TYPE_ISADMA "isa-dma"
 
 typedef struct IsaDmaClass IsaDmaClass;
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index f7f1671407..b96705c688 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -121,7 +121,6 @@ typedef struct AcpiMiscInfo {
 const unsigned char *dsdt_code;
 unsigned dsdt_size;
 uint16_t pvpanic_port;
-uint16_t applesmc_io_base;
 } AcpiMiscInfo;
 
 typedef struct AcpiBuildPciBusHotplugState {
@@ -307,7 +306,6 @@ static void acpi_get_misc_info(AcpiMiscInfo *info)
 info->tpm_version = tpm_get_version(tpm_find());
 #endif
 info->pvpanic_port = pvpanic_port();
-info->applesmc_io_base = applesmc_port();
 }
 
 /*
@@ -1800,26 +1798,6 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
 aml_append(dsdt, scope);
 }
 
-if (misc->applesmc_io_base) {
-scope = aml_scope("\\_SB.PCI0.ISA");
-dev = aml_device("SMC");
-
-aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001")));
-/* device present, functioning, decoding, not shown in UI */
-aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
-
-crs = aml_resource_template();
-aml_append(crs,
-aml_io(AML_DECODE16, misc->applesmc_io_base, 
misc->applesmc_io_base,
-   0x01, APPLESMC_MAX_DATA_LENGTH)
-);
-aml_append(crs, aml_irq_no_flags(6));
-aml_append(dev, aml_name_decl("_CRS", crs));
-
-aml_append(scope, dev);
-aml_append(dsdt, scope);
-}
-
 if (misc->pvpanic_port) {
 scope = aml_scope("\\_SB.PCI0.ISA");
 
diff --git a/hw/misc/applesmc.c b/hw/misc/applesmc.c
index 81cd6b6423..5f9c742e50 100644
--- a/hw/misc/applesmc.c
+++ b/hw/misc/applesmc.c
@@ -37,10 +37,14 @@
 #include "qemu/module.h"
 #include "qemu/timer.h"
 #include "qom/object.h"
+#include "hw/acpi/acpi_aml_interface.h"
 
 /* #define DEBUG_SMC */
 
 #define APPLESMC_DEFAULT_IOBASE0x300
+#define TYPE_APPLE_SMC "isa-applesmc"
+#define APPLESMC_MAX_DATA_LENGTH   32
+#define APPLESMC_PROP_IO_BASE "iobase"
 
 enum {
 APPLESMC_DATA_PORT   = 0x00,
@@ -347,14 +351,35 @@ static Property applesmc_isa_properties[] = {
 DEFINE_PROP_END_OF_LIST(),
 };
 
+static void build_applesmc_aml(AcpiDevAmlIf *adev, Aml *scope)
+{
+Aml *crs;
+AppleSMCState *s = APPLE_SMC(adev);
+uint32_t iobase = s->iobase;
+Aml *dev = aml_device("SMC");
+
+aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001")));
+/* device present, functioning, decoding, not shown in UI */
+aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
+crs = aml_resource_template();
+aml_append(crs,
+aml_io(AML_DECODE16, iobase, iobase, 0x01, APPLESMC_MAX_DATA_LENGTH)
+);
+aml_append(crs, aml_irq_no_flags(6));
+aml_append(dev, aml_name_decl("_CRS", crs));
+aml_append(scope, dev);
+}
+
 static void qdev_applesmc_class_init(ObjectClass *klass, void *data)
 {
 DeviceClass *dc = DEVICE_CLASS(klass);
+AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass);
 
 dc->realize = applesmc_isa_realize;
 dc->reset = qdev_applesmc_isa_reset;
 device_class_set_props(dc, applesmc_isa_properties);
 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+adevc->build_dev_aml = build_applesmc_aml;
 }
 
 static const TypeInfo applesmc_isa_info = {
@@ -362,6 +387,10 @@ static const TypeInfo applesmc_isa_info = {
 .parent= TYPE_ISA_DEVICE,
 .instance_size = sizeof(AppleSMCState),
 .class_init= qdev_applesmc_class_init,
+.interfaces = (InterfaceInfo[]) {
+{ TYPE_ACPI_DEV_AML_IF },
+{ },
+},
 };
 
 static void applesmc_register_types(void)
-- 
2.31.1




[PATCH v2 26/35] tests: acpi: white-lists expected DSDT.pvpanic-isa blob

2022-06-08 Thread Igor Mammedov
Signed-off-by: Igor Mammedov 
---
 tests/qtest/bios-tables-test-allowed-diff.h | 1 +
 tests/data/acpi/q35/DSDT.pvpanic-isa| 0
 2 files changed, 1 insertion(+)
 create mode 100644 tests/data/acpi/q35/DSDT.pvpanic-isa

diff --git a/tests/qtest/bios-tables-test-allowed-diff.h 
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..d5cd7aa4f5 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,2 @@
 /* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/q35/DSDT.pvpanic-isa",
diff --git a/tests/data/acpi/q35/DSDT.pvpanic-isa 
b/tests/data/acpi/q35/DSDT.pvpanic-isa
new file mode 100644
index 00..e69de29bb2
-- 
2.31.1




[PATCH v2 10/35] tests: acpi: q35: add test for smbus-ipmi device

2022-06-08 Thread Igor Mammedov
expected new device node:

Device (MI1)
{
Name (_HID, EisaId ("IPI0001"))  // _HID: Hardware ID
Name (_STR, "ipmi_smbus")  // _STR: Description String
Name (_UID, One)  // _UID: Unique ID
Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
{
I2cSerialBusV2 (0x, ControllerInitiated, 0x000186A0,
AddressingMode7Bit, "\\_SB.PCI0.SMB0",
0x00, ResourceProducer, , Exclusive,
)
})
Name (_IFT, 0x04)  // _IFT: IPMI Interface Type
Name (_SRV, 0x0200)  // _SRV: IPMI Spec Revision
}

Signed-off-by: Igor Mammedov 
Acked-by: Gerd Hoffmann 
---
 tests/qtest/bios-tables-test.c | 16 
 1 file changed, 16 insertions(+)

diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index a4a46e97f0..d896840270 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -955,6 +955,21 @@ static void test_acpi_q35_tcg_ipmi(void)
 free_test_data();
 }
 
+static void test_acpi_q35_tcg_smbus_ipmi(void)
+{
+test_data data;
+
+memset(, 0, sizeof(data));
+data.machine = MACHINE_Q35;
+data.variant = ".ipmismbus";
+data.required_struct_types = ipmi_required_struct_types;
+data.required_struct_types_len = ARRAY_SIZE(ipmi_required_struct_types);
+test_acpi_one("-device ipmi-bmc-sim,id=bmc0"
+  " -device smbus-ipmi,bmc=bmc0",
+  );
+free_test_data();
+}
+
 static void test_acpi_piix4_tcg_ipmi(void)
 {
 test_data data;
@@ -1743,6 +1758,7 @@ int main(int argc, char *argv[])
 qtest_add_func("acpi/q35/mmio64", test_acpi_q35_tcg_mmio64);
 qtest_add_func("acpi/piix4/ipmi", test_acpi_piix4_tcg_ipmi);
 qtest_add_func("acpi/q35/ipmi", test_acpi_q35_tcg_ipmi);
+qtest_add_func("acpi/q35/smbus/ipmi", test_acpi_q35_tcg_smbus_ipmi);
 qtest_add_func("acpi/piix4/cpuhp", test_acpi_piix4_tcg_cphp);
 qtest_add_func("acpi/q35/cpuhp", test_acpi_q35_tcg_cphp);
 qtest_add_func("acpi/piix4/memhp", test_acpi_piix4_tcg_memhp);
-- 
2.31.1




[PATCH v2 17/35] q35: acpi: drop not needed PCMachineClass::do_not_add_smb_acpi

2022-06-08 Thread Igor Mammedov
by default we do not version ACPI AML as it's considered
a part of firmware. Drop do_not_add_smb_acpi that blocked
SMBUS AML description on 3.1 and older machine types without
providing justification.

Signed-off-by: Igor Mammedov 
Acked-by: Gerd Hoffmann 
---
we can keep this bit if anyone can prove/report adverse effect
on VM.
---
 include/hw/i386/pc.h | 1 -
 hw/i386/acpi-build.c | 2 +-
 hw/i386/pc_piix.c| 1 -
 hw/i386/pc_q35.c | 1 -
 4 files changed, 1 insertion(+), 4 deletions(-)

diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index ffcac5121e..dee38cfac4 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -104,7 +104,6 @@ struct PCMachineClass {
 bool rsdp_in_ram;
 int legacy_acpi_table_size;
 unsigned acpi_data_size;
-bool do_not_add_smb_acpi;
 int pci_root_uid;
 
 /* SMBIOS compat: */
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 5b963cca32..d943354999 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1530,7 +1530,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
 build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base);
 }
 build_q35_pci0_int(dsdt);
-if (pcms->smbus && !pcmc->do_not_add_smb_acpi) {
+if (pcms->smbus) {
 build_smb0(dsdt, ICH9_SMB_DEV, ICH9_SMB_FUNC);
 }
 }
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 578e537b35..7f777f7aed 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -564,7 +564,6 @@ static void pc_i440fx_3_1_machine_options(MachineClass *m)
 
 pc_i440fx_4_0_machine_options(m);
 m->is_default = false;
-pcmc->do_not_add_smb_acpi = true;
 m->smbus_no_migration_support = true;
 m->alias = NULL;
 pcmc->pvh_enabled = false;
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 42eb8b9707..f96cbd04e2 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -514,7 +514,6 @@ static void pc_q35_3_1_machine_options(MachineClass *m)
 
 pc_q35_4_0_machine_options(m);
 m->default_kernel_irqchip_split = false;
-pcmc->do_not_add_smb_acpi = true;
 m->smbus_no_migration_support = true;
 m->alias = NULL;
 pcmc->pvh_enabled = false;
-- 
2.31.1




[PATCH v2 23/35] tests: acpi: add applesmc testcase

2022-06-08 Thread Igor Mammedov
Signed-off-by: Igor Mammedov 
Acked-by: Gerd Hoffmann 
---
 tests/qtest/bios-tables-test.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index d896840270..7d238218ca 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -1625,6 +1625,17 @@ static void test_acpi_q35_slic(void)
 free_test_data();
 }
 
+static void test_acpi_q35_applesmc(void)
+{
+test_data data = {
+.machine = MACHINE_Q35,
+.variant = ".applesmc",
+};
+
+test_acpi_one("-device isa-applesmc", );
+free_test_data();
+}
+
 static void test_oem_fields(test_data *data)
 {
 int i;
@@ -1783,6 +1794,7 @@ int main(int argc, char *argv[])
 qtest_add_func("acpi/q35/acpihmat", test_acpi_q35_tcg_acpi_hmat);
 qtest_add_func("acpi/piix4/acpierst", test_acpi_piix4_acpi_erst);
 qtest_add_func("acpi/q35/acpierst", test_acpi_q35_acpi_erst);
+qtest_add_func("acpi/q35/applesmc", test_acpi_q35_applesmc);
 qtest_add_func("acpi/microvm", test_acpi_microvm_tcg);
 qtest_add_func("acpi/microvm/usb", test_acpi_microvm_usb_tcg);
 qtest_add_func("acpi/microvm/rtc", test_acpi_microvm_rtc_tcg);
-- 
2.31.1




[PATCH v2 14/35] tests: acpi: update expected DSDT.ipmismbus blob

2022-06-08 Thread Igor Mammedov
expected AML change:
 Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
 {
I2cSerialBusV2 (0x, ControllerInitiated, 0x000186A0,
-   AddressingMode7Bit, "\\_SB.PCI0.SMB0",
+   AddressingMode7Bit, "^",
0x00, ResourceProducer, , Exclusive,
)
  })

Signed-off-by: Igor Mammedov 
---
 tests/qtest/bios-tables-test-allowed-diff.h |   1 -
 tests/data/acpi/q35/DSDT.ipmismbus  | Bin 8391 -> 8378 bytes
 2 files changed, 1 deletion(-)

diff --git a/tests/qtest/bios-tables-test-allowed-diff.h 
b/tests/qtest/bios-tables-test-allowed-diff.h
index b4687d1cc8..dfb8523c8b 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,2 +1 @@
 /* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/q35/DSDT.ipmismbus",
diff --git a/tests/data/acpi/q35/DSDT.ipmismbus 
b/tests/data/acpi/q35/DSDT.ipmismbus
index 
07ba873b79caadd73ed9721fcbeee84c57676e2a..415fe08a407690c0e118743d872de79d22f01a4c
 100644
GIT binary patch
delta 85
zcmX@^xXY2tCD80n^Yqk0Lq6G-v9sr

delta 98
zcmdnxc-)c8CD$MJ|5
sqMMx9CjXGsR#xLu?vrC+1VW%jHiiXlAVv}39!S?_OQ}XS01jdo-v9sr

-- 
2.31.1




[PATCH v2 09/35] tests: acpi: add and whitelist DSDT.ipmismbus expected blob

2022-06-08 Thread Igor Mammedov
.. which will be used by follow up smbus-ipmi test-case

Signed-off-by: Igor Mammedov 
---
 tests/qtest/bios-tables-test-allowed-diff.h | 1 +
 tests/data/acpi/q35/DSDT.ipmismbus  | 0
 2 files changed, 1 insertion(+)
 create mode 100644 tests/data/acpi/q35/DSDT.ipmismbus

diff --git a/tests/qtest/bios-tables-test-allowed-diff.h 
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..b4687d1cc8 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,2 @@
 /* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/q35/DSDT.ipmismbus",
diff --git a/tests/data/acpi/q35/DSDT.ipmismbus 
b/tests/data/acpi/q35/DSDT.ipmismbus
new file mode 100644
index 00..e69de29bb2
-- 
2.31.1




[PATCH v2 05/35] acpi: serial-is: replace ISADeviceClass::build_aml with AcpiDevAmlIfClass:build_dev_aml

2022-06-08 Thread Igor Mammedov
Signed-off-by: Igor Mammedov 
Acked-by: Gerd Hoffmann 
---
 hw/char/serial-isa.c | 14 +-
 1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/hw/char/serial-isa.c b/hw/char/serial-isa.c
index 7a7ed239cd..141a6cb168 100644
--- a/hw/char/serial-isa.c
+++ b/hw/char/serial-isa.c
@@ -27,7 +27,7 @@
 #include "qapi/error.h"
 #include "qemu/module.h"
 #include "sysemu/sysemu.h"
-#include "hw/acpi/aml-build.h"
+#include "hw/acpi/acpi_aml_interface.h"
 #include "hw/char/serial.h"
 #include "hw/isa/isa.h"
 #include "hw/qdev-properties.h"
@@ -83,9 +83,9 @@ static void serial_isa_realizefn(DeviceState *dev, Error 
**errp)
 isa_register_ioport(isadev, >io, isa->iobase);
 }
 
-static void serial_isa_build_aml(ISADevice *isadev, Aml *scope)
+static void serial_isa_build_aml(AcpiDevAmlIf *adev, Aml *scope)
 {
-ISASerialState *isa = ISA_SERIAL(isadev);
+ISASerialState *isa = ISA_SERIAL(adev);
 Aml *dev;
 Aml *crs;
 
@@ -122,11 +122,11 @@ static Property serial_isa_properties[] = {
 static void serial_isa_class_initfn(ObjectClass *klass, void *data)
 {
 DeviceClass *dc = DEVICE_CLASS(klass);
-ISADeviceClass *isa = ISA_DEVICE_CLASS(klass);
+AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass);
 
 dc->realize = serial_isa_realizefn;
 dc->vmsd = _isa_serial;
-isa->build_aml = serial_isa_build_aml;
+adevc->build_dev_aml = serial_isa_build_aml;
 device_class_set_props(dc, serial_isa_properties);
 set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
 }
@@ -146,6 +146,10 @@ static const TypeInfo serial_isa_info = {
 .instance_size = sizeof(ISASerialState),
 .instance_init = serial_isa_initfn,
 .class_init= serial_isa_class_initfn,
+.interfaces = (InterfaceInfo[]) {
+{ TYPE_ACPI_DEV_AML_IF },
+{ },
+},
 };
 
 static void serial_register_types(void)
-- 
2.31.1




[PATCH v2 07/35] acpi: pckbd: replace ISADeviceClass::build_aml with AcpiDevAmlIfClass:build_dev_aml

2022-06-08 Thread Igor Mammedov
Signed-off-by: Igor Mammedov 
Acked-by: Gerd Hoffmann 
---
 hw/input/pckbd.c | 14 +-
 1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/hw/input/pckbd.c b/hw/input/pckbd.c
index 4efdf75620..45c40fe3f3 100644
--- a/hw/input/pckbd.c
+++ b/hw/input/pckbd.c
@@ -29,7 +29,7 @@
 #include "qapi/error.h"
 #include "hw/isa/isa.h"
 #include "migration/vmstate.h"
-#include "hw/acpi/aml-build.h"
+#include "hw/acpi/acpi_aml_interface.h"
 #include "hw/input/ps2.h"
 #include "hw/irq.h"
 #include "hw/input/i8042.h"
@@ -767,9 +767,9 @@ static void i8042_realizefn(DeviceState *dev, Error **errp)
 qemu_register_reset(kbd_reset, s);
 }
 
-static void i8042_build_aml(ISADevice *isadev, Aml *scope)
+static void i8042_build_aml(AcpiDevAmlIf *adev, Aml *scope)
 {
-ISAKBDState *isa_s = I8042(isadev);
+ISAKBDState *isa_s = I8042(adev);
 Aml *kbd;
 Aml *mou;
 Aml *crs;
@@ -807,12 +807,12 @@ static Property i8042_properties[] = {
 static void i8042_class_initfn(ObjectClass *klass, void *data)
 {
 DeviceClass *dc = DEVICE_CLASS(klass);
-ISADeviceClass *isa = ISA_DEVICE_CLASS(klass);
+AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass);
 
 device_class_set_props(dc, i8042_properties);
 dc->realize = i8042_realizefn;
 dc->vmsd = _kbd_isa;
-isa->build_aml = i8042_build_aml;
+adevc->build_dev_aml = i8042_build_aml;
 set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
 }
 
@@ -822,6 +822,10 @@ static const TypeInfo i8042_info = {
 .instance_size = sizeof(ISAKBDState),
 .instance_init = i8042_initfn,
 .class_init= i8042_class_initfn,
+.interfaces = (InterfaceInfo[]) {
+{ TYPE_ACPI_DEV_AML_IF },
+{ },
+},
 };
 
 static void i8042_register_types(void)
-- 
2.31.1




[PATCH v2 13/35] ipmi: acpi: use relative path to resource source

2022-06-08 Thread Igor Mammedov
smbus-ipmi AML description needs to specify a path to its parent
node in _CRS. The rest of IPMI inplementations (ISA based)
do not need path at all. Instead of passing through a full path
use relative path to point to smbus-ipmi's parent node, it will
let follow up patches to create IPMI device AML in a generic
way instead of current ad-hoc way. (i.e. AML will be generated
the same way it's done for other ISA device, and smbus will be
converted to generate AML for its slave devices the same way
as ISA)

expected AML change:
 Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
 {
I2cSerialBusV2 (0x, ControllerInitiated, 0x000186A0,
-   AddressingMode7Bit, "\\_SB.PCI0.SMB0",
+   AddressingMode7Bit, "^",
0x00, ResourceProducer, , Exclusive,
)
  })

Signed-off-by: Igor Mammedov 
Acked-by: Gerd Hoffmann 
---
 include/hw/acpi/ipmi.h |  2 +-
 hw/acpi/ipmi-stub.c|  2 +-
 hw/acpi/ipmi.c | 12 ++--
 hw/i386/acpi-build.c   |  4 ++--
 4 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/include/hw/acpi/ipmi.h b/include/hw/acpi/ipmi.h
index c14ad682ac..c38483565c 100644
--- a/include/hw/acpi/ipmi.h
+++ b/include/hw/acpi/ipmi.h
@@ -16,6 +16,6 @@
  * bus matches the given bus.  The resource is the ACPI resource that
  * contains the IPMI device, this is required for the I2C CRS.
  */
-void build_acpi_ipmi_devices(Aml *table, BusState *bus, const char *resource);
+void build_acpi_ipmi_devices(Aml *table, BusState *bus);
 
 #endif /* HW_ACPI_IPMI_H */
diff --git a/hw/acpi/ipmi-stub.c b/hw/acpi/ipmi-stub.c
index 8634fb325c..f525f71c2d 100644
--- a/hw/acpi/ipmi-stub.c
+++ b/hw/acpi/ipmi-stub.c
@@ -10,6 +10,6 @@
 #include "qemu/osdep.h"
 #include "hw/acpi/ipmi.h"
 
-void build_acpi_ipmi_devices(Aml *table, BusState *bus, const char *resource)
+void build_acpi_ipmi_devices(Aml *table, BusState *bus)
 {
 }
diff --git a/hw/acpi/ipmi.c b/hw/acpi/ipmi.c
index 96e48eba15..c30b44fcf5 100644
--- a/hw/acpi/ipmi.c
+++ b/hw/acpi/ipmi.c
@@ -13,7 +13,7 @@
 #include "hw/acpi/acpi.h"
 #include "hw/acpi/ipmi.h"
 
-static Aml *aml_ipmi_crs(IPMIFwInfo *info, const char *resource)
+static Aml *aml_ipmi_crs(IPMIFwInfo *info)
 {
 Aml *crs = aml_resource_template();
 
@@ -49,7 +49,7 @@ static Aml *aml_ipmi_crs(IPMIFwInfo *info, const char 
*resource)
 break;
 case IPMI_MEMSPACE_SMBUS:
 aml_append(crs, aml_i2c_serial_bus_device(info->base_address,
-  resource));
+  "^"));
 break;
 default:
 abort();
@@ -62,7 +62,7 @@ static Aml *aml_ipmi_crs(IPMIFwInfo *info, const char 
*resource)
 return crs;
 }
 
-static Aml *aml_ipmi_device(IPMIFwInfo *info, const char *resource)
+static Aml *aml_ipmi_device(IPMIFwInfo *info)
 {
 Aml *dev;
 uint16_t version = ((info->ipmi_spec_major_revision << 8)
@@ -75,14 +75,14 @@ static Aml *aml_ipmi_device(IPMIFwInfo *info, const char 
*resource)
 aml_append(dev, aml_name_decl("_STR", aml_string("ipmi_%s",
  info->interface_name)));
 aml_append(dev, aml_name_decl("_UID", aml_int(info->uuid)));
-aml_append(dev, aml_name_decl("_CRS", aml_ipmi_crs(info, resource)));
+aml_append(dev, aml_name_decl("_CRS", aml_ipmi_crs(info)));
 aml_append(dev, aml_name_decl("_IFT", aml_int(info->interface_type)));
 aml_append(dev, aml_name_decl("_SRV", aml_int(version)));
 
 return dev;
 }
 
-void build_acpi_ipmi_devices(Aml *scope, BusState *bus, const char *resource)
+void build_acpi_ipmi_devices(Aml *scope, BusState *bus)
 {
 
 BusChild *kid;
@@ -102,6 +102,6 @@ void build_acpi_ipmi_devices(Aml *scope, BusState *bus, 
const char *resource)
 iic = IPMI_INTERFACE_GET_CLASS(obj);
 memset(, 0, sizeof(info));
 iic->get_fwinfo(ii, );
-aml_append(scope, aml_ipmi_device(, resource));
+aml_append(scope, aml_ipmi_device());
 }
 }
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 1449832aa9..88506d563f 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -873,7 +873,7 @@ static void build_isa_devices_aml(Aml *table)
 assert(obj && !ambiguous);
 
 scope = aml_scope("_SB.PCI0.ISA");
-build_acpi_ipmi_devices(scope, BUS(obj), "\\_SB.PCI0.ISA");
+build_acpi_ipmi_devices(scope, BUS(obj));
 isa_build_aml(ISA_BUS(obj), scope);
 
 aml_append(table, scope);
@@ -1406,7 +1406,7 @@ static void build_smb0(Aml *table, I2CBus *smbus, int 
devnr, int func)
 Aml *dev = aml_device("SMB0");
 
 aml_append(dev, aml_name_decl("_ADR", aml_int(devnr << 16 | func)));
-build_acpi_ipmi_devices(dev, BUS(smbus), "\\_SB.PCI0.SMB0");
+build_acpi_ipmi_devices(dev, BUS(smbus));
 aml_append(scope, dev);
 aml_append(table, scope);
 }
-- 
2.31.1




[PATCH v2 12/35] tests: acpi: whitelist DSDT.ipmismbus expected blob

2022-06-08 Thread Igor Mammedov
Signed-off-by: Igor Mammedov 
---
 tests/qtest/bios-tables-test-allowed-diff.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/tests/qtest/bios-tables-test-allowed-diff.h 
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..b4687d1cc8 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,2 @@
 /* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/q35/DSDT.ipmismbus",
-- 
2.31.1




[PATCH v2 22/35] tests: acpi: add and white-list DSDT.applesmc expected blob

2022-06-08 Thread Igor Mammedov
Signed-off-by: Igor Mammedov 
---
 tests/qtest/bios-tables-test-allowed-diff.h | 1 +
 tests/data/acpi/q35/DSDT.applesmc   | 0
 2 files changed, 1 insertion(+)
 create mode 100644 tests/data/acpi/q35/DSDT.applesmc

diff --git a/tests/qtest/bios-tables-test-allowed-diff.h 
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..e893029d87 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,2 @@
 /* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/q35/DSDT.applesmc",
diff --git a/tests/data/acpi/q35/DSDT.applesmc 
b/tests/data/acpi/q35/DSDT.applesmc
new file mode 100644
index 00..e69de29bb2
-- 
2.31.1




[PATCH v2 08/35] isa-bus: drop no longer used ISADeviceClass::build_aml

2022-06-08 Thread Igor Mammedov
Signed-off-by: Igor Mammedov 
Acked-by: Gerd Hoffmann 
---
 include/hw/isa/isa.h |  1 -
 hw/isa/isa-bus.c | 12 +---
 2 files changed, 1 insertion(+), 12 deletions(-)

diff --git a/include/hw/isa/isa.h b/include/hw/isa/isa.h
index 034d706ba1..5c5a3d43a7 100644
--- a/include/hw/isa/isa.h
+++ b/include/hw/isa/isa.h
@@ -64,7 +64,6 @@ struct IsaDmaClass {
 
 struct ISADeviceClass {
 DeviceClass parent_class;
-void (*build_aml)(ISADevice *dev, Aml *scope);
 };
 
 struct ISABus {
diff --git a/hw/isa/isa-bus.c b/hw/isa/isa-bus.c
index 237e2cee12..1bee1a47f1 100644
--- a/hw/isa/isa-bus.c
+++ b/hw/isa/isa-bus.c
@@ -191,19 +191,9 @@ ISADevice *isa_vga_init(ISABus *bus)
 void isa_build_aml(ISABus *bus, Aml *scope)
 {
 BusChild *kid;
-ISADevice *dev;
-ISADeviceClass *dc;
 
 QTAILQ_FOREACH(kid, >parent_obj.children, sibling) {
-dev = ISA_DEVICE(kid->child);
-dc = ISA_DEVICE_GET_CLASS(dev);
-bool has_build_dev_aml = !!object_dynamic_cast(OBJECT(dev),
-   TYPE_ACPI_DEV_AML_IF);
-if (dc->build_aml) {
-dc->build_aml(dev, scope);
-} else if (has_build_dev_aml) {
-call_dev_aml_func(DEVICE(dev), scope);
-}
+call_dev_aml_func(DEVICE(kid->child), scope);
 }
 }
 
-- 
2.31.1




[PATCH v2 20/35] acpi: q35: isa bridge: use AcpiDevAmlIf interface to build ISA device descriptors

2022-06-08 Thread Igor Mammedov
replaces adhoc build_isa_devices_aml() with generic AcpiDevAmlIf
way to build bridge AML including all devices that are attached
to its ISA bus.

Later when PCI is converted to AcpiDevAmlIf, build_q35_isa_bridge()
will also be dropped since PCI parts itself will take care of
building device prologue/epilogue AML for each enumerated PCI device.

Expected AML change is contextual, where ISA devices are moved from
separately declared _SB.PCI0.ISA scope, directly under Device(ISA)
node.

Signed-off-by: Igor Mammedov 
Acked-by: Gerd Hoffmann 
---
 hw/i386/acpi-build.c | 30 +++---
 hw/isa/lpc_ich9.c| 19 +++
 2 files changed, 30 insertions(+), 19 deletions(-)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index f903f30b7e..f7f1671407 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -864,20 +864,6 @@ static Aml *build_vmbus_device_aml(VMBusBridge 
*vmbus_bridge)
 return dev;
 }
 
-static void build_isa_devices_aml(Aml *table)
-{
-bool ambiguous;
-Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, );
-Aml *scope;
-
-assert(obj && !ambiguous);
-
-scope = aml_scope("_SB.PCI0.ISA");
-isa_build_aml(ISA_BUS(obj), scope);
-
-aml_append(table, scope);
-}
-
 static void build_dbg_aml(Aml *table)
 {
 Aml *field;
@@ -1263,15 +1249,22 @@ static void build_q35_isa_bridge(Aml *table)
 {
 Aml *dev;
 Aml *scope;
+Object *obj;
+bool ambiguous;
+
+/*
+ * temporarily fish out isa bridge, build_q35_isa_bridge() will be dropped
+ * once PCI is converted to AcpiDevAmlIf and would be ble to generate
+ * AML for bridge itself
+ */
+obj = object_resolve_path_type("", TYPE_ICH9_LPC_DEVICE, );
+assert(obj && !ambiguous);
 
 scope =  aml_scope("_SB.PCI0");
 dev = aml_device("ISA");
 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F)));
 
-/* ICH9 PCI to ISA irq remapping */
-aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG,
- aml_int(0x60), 0x0C));
-
+call_dev_aml_func(DEVICE(obj), dev);
 aml_append(scope, dev);
 aml_append(table, scope);
 }
@@ -1531,7 +1524,6 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
 build_hpet_aml(dsdt);
 }
 build_q35_isa_bridge(dsdt);
-build_isa_devices_aml(dsdt);
 if (pm->pcihp_bridge_en) {
 build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base);
 }
diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c
index 5f143dca17..4553b5925b 100644
--- a/hw/isa/lpc_ich9.c
+++ b/hw/isa/lpc_ich9.c
@@ -50,6 +50,7 @@
 #include "hw/core/cpu.h"
 #include "hw/nvram/fw_cfg.h"
 #include "qemu/cutils.h"
+#include "hw/acpi/acpi_aml_interface.h"
 
 /*/
 /* ICH9 LPC PCI to ISA bridge */
@@ -803,12 +804,28 @@ static void ich9_send_gpe(AcpiDeviceIf *adev, 
AcpiEventStatusBits ev)
 acpi_send_gpe_event(>pm.acpi_regs, s->pm.irq, ev);
 }
 
+static void build_ich9_isa_aml(AcpiDevAmlIf *adev, Aml *scope)
+{
+BusChild *kid;
+ICH9LPCState *s = ICH9_LPC_DEVICE(adev);
+BusState *bus = BUS(s->isa_bus);
+
+/* ICH9 PCI to ISA irq remapping */
+aml_append(scope, aml_operation_region("PIRQ", AML_PCI_CONFIG,
+   aml_int(0x60), 0x0C));
+
+QTAILQ_FOREACH(kid, >children, sibling) {
+call_dev_aml_func(DEVICE(kid->child), scope);
+}
+}
+
 static void ich9_lpc_class_init(ObjectClass *klass, void *data)
 {
 DeviceClass *dc = DEVICE_CLASS(klass);
 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass);
+AcpiDevAmlIfClass *amldevc = ACPI_DEV_AML_IF_CLASS(klass);
 
 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 dc->reset = ich9_lpc_reset;
@@ -833,6 +850,7 @@ static void ich9_lpc_class_init(ObjectClass *klass, void 
*data)
 adevc->ospm_status = ich9_pm_ospm_status;
 adevc->send_event = ich9_send_gpe;
 adevc->madt_cpu = pc_madt_cpu_entry;
+amldevc->build_dev_aml = build_ich9_isa_aml;
 }
 
 static const TypeInfo ich9_lpc_info = {
@@ -845,6 +863,7 @@ static const TypeInfo ich9_lpc_info = {
 { TYPE_HOTPLUG_HANDLER },
 { TYPE_ACPI_DEVICE_IF },
 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
+{ TYPE_ACPI_DEV_AML_IF },
 { }
 }
 };
-- 
2.31.1




[PATCH v2 11/35] tests: acpi: update expected blob DSDT.ipmismbus

2022-06-08 Thread Igor Mammedov
basic q35 DSDT with an extra device node:

  Device (MI1)
{
Name (_HID, EisaId ("IPI0001"))  // _HID: Hardware ID
Name (_STR, "ipmi_smbus")  // _STR: Description String
Name (_UID, One)  // _UID: Unique ID
Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
{
  I2cSerialBusV2 (0x, ControllerInitiated, 0x000186A0,
  AddressingMode7Bit, "\\_SB.PCI0.SMB0",
  0x00, ResourceProducer, , Exclusive,
  )
})
Name (_IFT, 0x04)  // _IFT: IPMI Interface Type
Name (_SRV, 0x0200)  // _SRV: IPMI Spec Revision
}

Signed-off-by: Igor Mammedov 
---
 tests/qtest/bios-tables-test-allowed-diff.h |   1 -
 tests/data/acpi/q35/DSDT.ipmismbus  | Bin 0 -> 8391 bytes
 2 files changed, 1 deletion(-)

diff --git a/tests/qtest/bios-tables-test-allowed-diff.h 
b/tests/qtest/bios-tables-test-allowed-diff.h
index b4687d1cc8..dfb8523c8b 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,2 +1 @@
 /* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/q35/DSDT.ipmismbus",
diff --git a/tests/data/acpi/q35/DSDT.ipmismbus 
b/tests/data/acpi/q35/DSDT.ipmismbus
index 
e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..07ba873b79caadd73ed9721fcbeee84c57676e2a
 100644
GIT binary patch
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zewYMsYPjROaBMa#|

[PATCH v2 02/35] acpi: make isa_build_aml() support AcpiDevAmlIf interface

2022-06-08 Thread Igor Mammedov
To allow incremental conversion from ISADeviceClass::build_aml
to AcpiDevAmlIf, add support for the later without removing
the former. Once conversion is complete, another commit will
drop ISADeviceClass::build_aml related code.

Signed-off-by: Igor Mammedov 
Reviewed-by: Ani Sinha 
Acked-by: Gerd Hoffmann 
---
 hw/isa/isa-bus.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/hw/isa/isa-bus.c b/hw/isa/isa-bus.c
index cd5ad3687d..237e2cee12 100644
--- a/hw/isa/isa-bus.c
+++ b/hw/isa/isa-bus.c
@@ -24,6 +24,7 @@
 #include "hw/sysbus.h"
 #include "sysemu/sysemu.h"
 #include "hw/isa/isa.h"
+#include "hw/acpi/acpi_aml_interface.h"
 
 static ISABus *isabus;
 
@@ -196,8 +197,12 @@ void isa_build_aml(ISABus *bus, Aml *scope)
 QTAILQ_FOREACH(kid, >parent_obj.children, sibling) {
 dev = ISA_DEVICE(kid->child);
 dc = ISA_DEVICE_GET_CLASS(dev);
+bool has_build_dev_aml = !!object_dynamic_cast(OBJECT(dev),
+   TYPE_ACPI_DEV_AML_IF);
 if (dc->build_aml) {
 dc->build_aml(dev, scope);
+} else if (has_build_dev_aml) {
+call_dev_aml_func(DEVICE(dev), scope);
 }
 }
 }
-- 
2.31.1




[PATCH v2 04/35] acpi: parallel port: replace ISADeviceClass::build_aml with AcpiDevAmlIfClass:build_dev_aml

2022-06-08 Thread Igor Mammedov
Signed-off-by: Igor Mammedov 
Acked-by: Gerd Hoffmann 
---
 hw/char/parallel.c | 14 +-
 1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/hw/char/parallel.c b/hw/char/parallel.c
index f735a6cd7f..1c9ca47820 100644
--- a/hw/char/parallel.c
+++ b/hw/char/parallel.c
@@ -28,7 +28,7 @@
 #include "qemu/module.h"
 #include "chardev/char-parallel.h"
 #include "chardev/char-fe.h"
-#include "hw/acpi/aml-build.h"
+#include "hw/acpi/acpi_aml_interface.h"
 #include "hw/irq.h"
 #include "hw/isa/isa.h"
 #include "hw/qdev-properties.h"
@@ -570,9 +570,9 @@ static void parallel_isa_realizefn(DeviceState *dev, Error 
**errp)
  s, "parallel");
 }
 
-static void parallel_isa_build_aml(ISADevice *isadev, Aml *scope)
+static void parallel_isa_build_aml(AcpiDevAmlIf *adev, Aml *scope)
 {
-ISAParallelState *isa = ISA_PARALLEL(isadev);
+ISAParallelState *isa = ISA_PARALLEL(adev);
 Aml *dev;
 Aml *crs;
 
@@ -645,11 +645,11 @@ static Property parallel_isa_properties[] = {
 static void parallel_isa_class_initfn(ObjectClass *klass, void *data)
 {
 DeviceClass *dc = DEVICE_CLASS(klass);
-ISADeviceClass *isa = ISA_DEVICE_CLASS(klass);
+AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass);
 
 dc->realize = parallel_isa_realizefn;
 dc->vmsd = _parallel_isa;
-isa->build_aml = parallel_isa_build_aml;
+adevc->build_dev_aml = parallel_isa_build_aml;
 device_class_set_props(dc, parallel_isa_properties);
 set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
 }
@@ -659,6 +659,10 @@ static const TypeInfo parallel_isa_info = {
 .parent= TYPE_ISA_DEVICE,
 .instance_size = sizeof(ISAParallelState),
 .class_init= parallel_isa_class_initfn,
+.interfaces = (InterfaceInfo[]) {
+{ TYPE_ACPI_DEV_AML_IF },
+{ },
+},
 };
 
 static void parallel_register_types(void)
-- 
2.31.1




[PATCH v2 01/35] acpi: add interface to build device specific AML

2022-06-08 Thread Igor Mammedov
There is already ISADeviceClass::build_aml() callback which
builds device specific AML blob for some ISA devices.
To extend the same idea to other devices, add TYPE_ACPI_DEV_AML_IF
Interface that will provide a more generic callback which
will be used not only for ISA but other devices. It will
allow get rid of some data-mining and ad-hoc AML building,
by asking device(s) to generate its own AML blob like it's
done for ISA devices.

Signed-off-by: Igor Mammedov 
Acked-by: Gerd Hoffmann 
---
 include/hw/acpi/acpi_aml_interface.h | 40 
 hw/acpi/acpi_interface.c |  8 ++
 hw/acpi/meson.build  |  2 +-
 3 files changed, 49 insertions(+), 1 deletion(-)
 create mode 100644 include/hw/acpi/acpi_aml_interface.h

diff --git a/include/hw/acpi/acpi_aml_interface.h 
b/include/hw/acpi/acpi_aml_interface.h
new file mode 100644
index 00..ab76f0e55d
--- /dev/null
+++ b/include/hw/acpi/acpi_aml_interface.h
@@ -0,0 +1,40 @@
+#ifndef ACPI_AML_INTERFACE_H
+#define ACPI_AML_INTERFACE_H
+
+#include "qom/object.h"
+#include "hw/acpi/aml-build.h"
+
+#define TYPE_ACPI_DEV_AML_IF "acpi-dev-aml-interface"
+typedef struct AcpiDevAmlIfClass AcpiDevAmlIfClass;
+DECLARE_CLASS_CHECKERS(AcpiDevAmlIfClass, ACPI_DEV_AML_IF, 
TYPE_ACPI_DEV_AML_IF)
+#define ACPI_DEV_AML_IF(obj) \
+ INTERFACE_CHECK(AcpiDevAmlIf, (obj), TYPE_ACPI_DEV_AML_IF)
+
+typedef struct AcpiDevAmlIf AcpiDevAmlIf;
+typedef void (*dev_aml_fn)(AcpiDevAmlIf *adev, Aml *scope);
+
+/**
+ * AcpiDevAmlIfClass:
+ *
+ * build_dev_aml: adds device specific AML blob to provided scope
+ *
+ * Interface is designed for providing generic callback that builds device
+ * specific AML blob.
+ */
+struct AcpiDevAmlIfClass {
+/*  */
+InterfaceClass parent_class;
+
+/*  */
+dev_aml_fn build_dev_aml;
+};
+
+static inline void call_dev_aml_func(DeviceState *dev, Aml *scope)
+{
+if (object_dynamic_cast(OBJECT(dev), TYPE_ACPI_DEV_AML_IF)) {
+AcpiDevAmlIfClass *klass = ACPI_DEV_AML_IF_GET_CLASS(dev);
+klass->build_dev_aml(ACPI_DEV_AML_IF(dev), scope);
+}
+}
+
+#endif
diff --git a/hw/acpi/acpi_interface.c b/hw/acpi/acpi_interface.c
index 6583917b8e..c668d361f6 100644
--- a/hw/acpi/acpi_interface.c
+++ b/hw/acpi/acpi_interface.c
@@ -1,5 +1,6 @@
 #include "qemu/osdep.h"
 #include "hw/acpi/acpi_dev_interface.h"
+#include "hw/acpi/acpi_aml_interface.h"
 #include "qemu/module.h"
 
 void acpi_send_event(DeviceState *dev, AcpiEventStatusBits event)
@@ -18,8 +19,15 @@ static void register_types(void)
 .parent= TYPE_INTERFACE,
 .class_size = sizeof(AcpiDeviceIfClass),
 };
+static const TypeInfo acpi_dev_aml_if_info = {
+.name  = TYPE_ACPI_DEV_AML_IF,
+.parent= TYPE_INTERFACE,
+.class_size = sizeof(AcpiDevAmlIfClass),
+};
+
 
 type_register_static(_dev_if_info);
+type_register_static(_dev_aml_if_info);
 }
 
 type_init(register_types)
diff --git a/hw/acpi/meson.build b/hw/acpi/meson.build
index cea2f5f93a..f8c820ca94 100644
--- a/hw/acpi/meson.build
+++ b/hw/acpi/meson.build
@@ -29,7 +29,7 @@ acpi_ss.add(when: 'CONFIG_PC', if_false: 
files('acpi-x86-stub.c'))
 if have_tpm
   acpi_ss.add(files('tpm.c'))
 endif
-softmmu_ss.add(when: 'CONFIG_ACPI', if_false: files('acpi-stub.c', 
'aml-build-stub.c', 'ghes-stub.c'))
+softmmu_ss.add(when: 'CONFIG_ACPI', if_false: files('acpi-stub.c', 
'aml-build-stub.c', 'ghes-stub.c', 'acpi_interface.c'))
 softmmu_ss.add_all(when: 'CONFIG_ACPI', if_true: acpi_ss)
 softmmu_ss.add(when: 'CONFIG_ALL', if_true: files('acpi-stub.c', 
'aml-build-stub.c',
   'acpi-x86-stub.c', 
'ipmi-stub.c', 'ghes-stub.c',
-- 
2.31.1




[PATCH v2 03/35] acpi: fdc-isa: replace ISADeviceClass::build_aml with AcpiDevAmlIfClass:build_dev_aml

2022-06-08 Thread Igor Mammedov
Signed-off-by: Igor Mammedov 
Acked-by: Gerd Hoffmann 
---
 hw/block/fdc-isa.c   | 16 ++--
 hw/i386/acpi-build.c |  1 -
 2 files changed, 10 insertions(+), 7 deletions(-)

diff --git a/hw/block/fdc-isa.c b/hw/block/fdc-isa.c
index fa20450747..fee1ca68a8 100644
--- a/hw/block/fdc-isa.c
+++ b/hw/block/fdc-isa.c
@@ -32,7 +32,7 @@
 #include "qapi/error.h"
 #include "qemu/error-report.h"
 #include "qemu/timer.h"
-#include "hw/acpi/aml-build.h"
+#include "hw/acpi/acpi_aml_interface.h"
 #include "hw/irq.h"
 #include "hw/isa/isa.h"
 #include "hw/qdev-properties.h"
@@ -214,9 +214,9 @@ int cmos_get_fd_drive_type(FloppyDriveType fd0)
 return val;
 }
 
-static void fdc_isa_build_aml(ISADevice *isadev, Aml *scope)
+static void build_fdc_aml(AcpiDevAmlIf *adev, Aml *scope)
 {
-FDCtrlISABus *isa = ISA_FDC(isadev);
+FDCtrlISABus *isa = ISA_FDC(adev);
 Aml *dev;
 Aml *crs;
 int i;
@@ -241,7 +241,7 @@ static void fdc_isa_build_aml(ISADevice *isadev, Aml *scope)
 aml_append(dev, aml_name_decl("_CRS", crs));
 
 for (i = 0; i < MIN(MAX_FD, ACPI_FDE_MAX_FD); i++) {
-FloppyDriveType type = isa_fdc_get_drive_type(isadev, i);
+FloppyDriveType type = isa_fdc_get_drive_type(ISA_DEVICE(adev), i);
 
 if (type < FLOPPY_DRIVE_TYPE_NONE) {
 fde_buf[i] = cpu_to_le32(1);  /* drive present */
@@ -283,14 +283,14 @@ static Property isa_fdc_properties[] = {
 static void isabus_fdc_class_init(ObjectClass *klass, void *data)
 {
 DeviceClass *dc = DEVICE_CLASS(klass);
-ISADeviceClass *isa = ISA_DEVICE_CLASS(klass);
+AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass);
 
 dc->desc = "virtual floppy controller";
 dc->realize = isabus_fdc_realize;
 dc->fw_name = "fdc";
 dc->reset = fdctrl_external_reset_isa;
 dc->vmsd = _isa_fdc;
-isa->build_aml = fdc_isa_build_aml;
+adevc->build_dev_aml = build_fdc_aml;
 device_class_set_props(dc, isa_fdc_properties);
 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
 }
@@ -313,6 +313,10 @@ static const TypeInfo isa_fdc_info = {
 .instance_size = sizeof(FDCtrlISABus),
 .class_init= isabus_fdc_class_init,
 .instance_init = isabus_fdc_instance_init,
+.interfaces = (InterfaceInfo[]) {
+{ TYPE_ACPI_DEV_AML_IF },
+{ },
+},
 };
 
 static void isa_fdc_register_types(void)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index c125939ed6..1449832aa9 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -40,7 +40,6 @@
 #include "hw/acpi/bios-linker-loader.h"
 #include "hw/isa/isa.h"
 #include "hw/input/i8042.h"
-#include "hw/block/fdc.h"
 #include "hw/acpi/memory_hotplug.h"
 #include "sysemu/tpm.h"
 #include "hw/acpi/tpm.h"
-- 
2.31.1




[PATCH v2 00/35] pc/q35: refactor ISA and SMBUS AML generation

2022-06-08 Thread Igor Mammedov


Changelog:
  since v1:
* add tis 2.0  clarification to commit message (Ani Sinha)
* rebase on top of pci tree
* pick up acks

Series is excerpt form larger refactoring that does
the same for PCI devices, but it's too large at this
point, so I've split off a relatively self-contained
ISA/SMBUS patches into a smaller separate series, and
PCI refactoring will follow up on top of this series
using the same AcpiDevAmlIf interface.

Series consolidates and unifies how pc/q35 machine
generates AML for ISA and SMBUS devices. It adds
a new more generic interface 'AcpiDevAmlIf' that
replaces ISA specific ISADeviceClass::build_aml
hook and should allow to use the same approach
(i.e. ask a device to provide its own AML) but
not limited to ISA bus.
Series applies AcpiDevAmlIf interface to a few
ISA devices that were already using
ISADeviceClass::build_aml and to devices /tpm,
applesmc,pvpanic,ipmi/ that were generated in
custom way. The AML generation for the later
class is normalized to behave like any other
ISA device that were using ISADeviceClass::build_aml
and converted to interface 'AcpiDevAmlIf'.
It simplifies process of building DSDT and
eliminates custom probing/wiring for those devices
as AML for them is generated at the time ISA/SMBUS
is enumerated.

Changes to DSDT tables QEMU generates are mostly
contextual where devices scattered across DSDT
are consolidated under respective device that
hosts bus they are attached to.

PS:
 + series adds several ACPI tests for devices
   that were missing them.

Igor Mammedov (35):
  acpi: add interface to build device specific AML
  acpi: make isa_build_aml() support AcpiDevAmlIf interface
  acpi: fdc-isa: replace ISADeviceClass::build_aml with
AcpiDevAmlIfClass:build_dev_aml
  acpi: parallel port: replace ISADeviceClass::build_aml with
AcpiDevAmlIfClass:build_dev_aml
  acpi: serial-is: replace ISADeviceClass::build_aml with
AcpiDevAmlIfClass:build_dev_aml
  acpi: mc146818rtc: replace ISADeviceClass::build_aml with
AcpiDevAmlIfClass:build_dev_aml
  acpi: pckbd: replace ISADeviceClass::build_aml with
AcpiDevAmlIfClass:build_dev_aml
  isa-bus: drop no longer used ISADeviceClass::build_aml
  tests: acpi: add and whitelist DSDT.ipmismbus expected blob
  tests: acpi: q35: add test for smbus-ipmi device
  tests: acpi: update expected blob DSDT.ipmismbus
  tests: acpi: whitelist DSDT.ipmismbus expected blob
  ipmi: acpi: use relative path to resource source
  tests: acpi: update expected DSDT.ipmismbus blob
  acpi: ich9-smb: add support for AcpiDevAmlIf interface
  acpi: ipmi: use AcpiDevAmlIf interface to build IPMI device
descriptors
  q35: acpi: drop not needed PCMachineClass::do_not_add_smb_acpi
  tests: acpi: white-list to be re-factored pc/q35 DSDT
  acpi: pc: isa bridge: use AcpiDevAmlIf interface to build ISA device
descriptors
  acpi: q35: isa bridge: use AcpiDevAmlIf interface to build ISA device
descriptors
  tests: acpi: update expected blobs
  tests: acpi: add and white-list DSDT.applesmc expected blob
  tests: acpi: add applesmc testcase
  acpi: applesmc: use AcpiDevAmlIfClass:build_dev_aml to provide
device's AML
  tests: acpi: update expected blobs
  tests: acpi: white-lists expected DSDT.pvpanic-isa blob
  tests: acpi: add pvpanic-isa: testcase
  acpi: pvpanic-isa: use AcpiDevAmlIfClass:build_dev_aml to provide
device's AML
  tests: acpi: update expected DSDT.pvpanic-isa blob
  tests: acpi: white-list DSDT.tis.tpm2/DSDT.tis.tpm12 expected blobs
  acpi: pc/q35: tpm-tis: fix TPM device scope
  acpi: pc/q35: remove not needed 'if' condition on pci bus
  acpi: tpm-tis: use AcpiDevAmlIfClass:build_dev_aml to provide device's
AML
  tests: acpi: update expected DSDT.tis.tpm2/DSDT.tis.tpm12 blobs
  x86: acpi-build: do not include hw/isa/isa.h directly

 include/hw/acpi/acpi_aml_interface.h  |  40 ++
 include/hw/acpi/ipmi.h|   9 +-
 include/hw/i386/pc.h  |   1 -
 include/hw/isa/isa.h  |  15 ---
 include/hw/misc/pvpanic.h |   9 --
 hw/acpi/acpi_interface.c  |   8 ++
 hw/acpi/ipmi-stub.c   |   2 +-
 hw/acpi/ipmi.c|  53 +++-
 hw/acpi/meson.build   |   2 +-
 hw/block/fdc-isa.c|  16 ++-
 hw/char/parallel.c|  14 ++-
 hw/char/serial-isa.c  |  14 ++-
 hw/i2c/smbus_ich9.c   |  15 +++
 hw/i386/acpi-build.c  | 171 ++
 hw/i386/pc_piix.c |   1 -
 hw/i386/pc_q35.c  |   1 -
 hw/input/pckbd.c  |  14 ++-
 hw/ipmi/isa_ipmi_bt.c |   4 +
 hw/ipmi/isa_ipmi_kcs.c|   4 +
 hw/ipmi/smbus_ipmi.c  |   4 +
 hw/isa/isa-bus.c  |   9 +-
 hw/isa/lpc_ich9.c |  19 +++
 hw/isa/piix3.c|  17 +++
 hw/misc/applesmc.c

Re: [PATCH 4/5] bios-tables-test: add test for number of cores > 255

2022-06-07 Thread Igor Mammedov
On Mon, 6 Jun 2022 13:38:57 +0200
Julia Suvorova  wrote:

> On Thu, Jun 2, 2022 at 5:20 PM Igor Mammedov  wrote:
> >
> > On Fri, 27 May 2022 18:56:50 +0200
> > Julia Suvorova  wrote:
> >  
> > > The new test is run with a large number of cpus and checks if the
> > > core_count field in smbios_cpu_test (structure type 4) is correct.
> > >
> > > Choose q35 as it allows to run with -smp > 255.
> > >
> > > Signed-off-by: Julia Suvorova 
> > > ---
> > >  tests/qtest/bios-tables-test.c | 35 +-
> > >  1 file changed, 34 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/tests/qtest/bios-tables-test.c 
> > > b/tests/qtest/bios-tables-test.c
> > > index 0ba9d749a5..f2464adaa0 100644
> > > --- a/tests/qtest/bios-tables-test.c
> > > +++ b/tests/qtest/bios-tables-test.c
> > > @@ -100,6 +100,8 @@ typedef struct {
> > >  smbios_entry_point smbios_ep_table;
> > >  uint16_t smbios_cpu_max_speed;
> > >  uint16_t smbios_cpu_curr_speed;
> > > +uint8_t smbios_core_count;
> > > +uint16_t smbios_core_count2;
> > >  uint8_t *required_struct_types;
> > >  int required_struct_types_len;
> > >  QTestState *qts;
> > > @@ -640,8 +642,9 @@ static inline bool smbios_single_instance(uint8_t 
> > > type)
> > >
> > >  static bool smbios_cpu_test(test_data *data, uint32_t addr)
> > >  {
> > > +uint8_t real_cc, expect_cc = data->smbios_core_count;  
> >
> > %s/expect/expected/
> > also I'd s/real_cc/core_count/
> >  
> > > +uint16_t real, real_cc2, expect_cc2 = data->smbios_core_count2;  
> > ditto
> >  
> > >  uint16_t expect_speed[2];
> > > -uint16_t real;
> > >  int offset[2];
> > >  int i;
> > >
> > > @@ -660,6 +663,20 @@ static bool smbios_cpu_test(test_data *data, 
> > > uint32_t addr)
> > >  }
> > >  }
> > >
> > > +real_cc = qtest_readb(data->qts, addr + offsetof(struct 
> > > smbios_type_4, core_count));
> > > +real_cc2 = qtest_readw(data->qts, addr + offsetof(struct 
> > > smbios_type_4, core_count2));
> > > +
> > > +if (expect_cc && (real_cc != expect_cc)) {
> > > +fprintf(stderr, "Unexpected SMBIOS CPU count: real %u expect 
> > > %u\n",
> > > +real_cc, expect_cc);
> > > +return false;  
> >
> > since you are rewriting it anyways, how about
> > if (expect_cc) {
> >   g_assert_cmpuint(...)
> > }
> >
> > instead of printing/propagating error  
> 
> That works. But I still need to return something, unless you want to
> change the original code too.

just change it, as it makes code simpler (maybe a separate patch
that should go before this one)

> 
> Best regards, Julia Suvorova.
> 
> > > +}
> > > +if ((expect_cc == 0xFF) && (real_cc2 != expect_cc2)) {
> > > +fprintf(stderr, "Unexpected SMBIOS CPU count2: real %u expect 
> > > %u\n",
> > > +real_cc2, expect_cc2);
> > > +return false;
> > > +}
> > > +
> > >  return true;
> > >  }
> > >
> > > @@ -905,6 +922,21 @@ static void test_acpi_q35_tcg(void)
> > >  free_test_data();
> > >  }
> > >
> > > +static void test_acpi_q35_tcg_core_count2(void)
> > > +{
> > > +test_data data = {
> > > +.machine = MACHINE_Q35,
> > > +.variant = ".core-count2",
> > > +.required_struct_types = base_required_struct_types,
> > > +.required_struct_types_len = 
> > > ARRAY_SIZE(base_required_struct_types),
> > > +.smbios_core_count = 0xFF,
> > > +.smbios_core_count2 = 275,
> > > +};
> > > +
> > > +test_acpi_one("-machine smbios-entry-point-type=64 -smp 275", );
> > > +free_test_data();
> > > +}
> > > +
> > >  static void test_acpi_q35_tcg_bridge(void)
> > >  {
> > >  test_data data;
> > > @@ -1787,6 +1819,7 @@ int main(int argc, char *argv[])
> > >  qtest_add_func("acpi/piix4/pci-hotplug/off",
> > > test_acpi_piix4_no_acpi_pci_hotplug);
> > >  qtest_add_func("acpi/q35", test_acpi_q35_tcg);
> > > +qtest_add_func("acpi/q35/core-count2", 
> > > test_acpi_q35_tcg_core_count2);
> > >  qtest_add_func("acpi/q35/bridge", test_acpi_q35_tcg_bridge);
> > >  qtest_add_func("acpi/q35/multif-bridge", 
> > > test_acpi_q35_multif_bridge);
> > >  qtest_add_func("acpi/q35/mmio64", test_acpi_q35_tcg_mmio64);  
> >  
> 




Re: [PATCH 2/5] bios-tables-test: teach test to use smbios 3.0 tables

2022-06-07 Thread Igor Mammedov
On Mon, 6 Jun 2022 12:52:00 +0200
Julia Suvorova  wrote:

> On Thu, Jun 2, 2022 at 5:04 PM Igor Mammedov  wrote:
> >
> > On Fri, 27 May 2022 18:56:48 +0200
> > Julia Suvorova  wrote:
> >  
> > > Introduce the 64-bit entry point. Since we no longer have a total
> > > number of structures, stop checking for the new ones at the EOF
> > > structure (type 127).
> > >
> > > Signed-off-by: Julia Suvorova 
> > > ---
> > >  tests/qtest/bios-tables-test.c | 101 -
> > >  1 file changed, 75 insertions(+), 26 deletions(-)
> > >
> > > diff --git a/tests/qtest/bios-tables-test.c 
> > > b/tests/qtest/bios-tables-test.c
> > > index a4a46e97f0..0ba9d749a5 100644
> > > --- a/tests/qtest/bios-tables-test.c
> > > +++ b/tests/qtest/bios-tables-test.c
> > > @@ -75,6 +75,14 @@
> > >  #define OEM_TEST_ARGS  "-machine x-oem-id=" OEM_ID 
> > > ",x-oem-table-id=" \
> > > OEM_TABLE_ID
> > >
> > > +#define SMBIOS_VER21 0
> > > +#define SMBIOS_VER30 1
> > > +
> > > +typedef struct {
> > > +struct smbios_21_entry_point ep21;
> > > +struct smbios_30_entry_point ep30;
> > > +} smbios_entry_point;
> > > +
> > >  typedef struct {
> > >  bool tcg_only;
> > >  const char *machine;
> > > @@ -88,8 +96,8 @@ typedef struct {
> > >  uint64_t rsdp_addr;
> > >  uint8_t rsdp_table[36 /* ACPI 2.0+ RSDP size */];
> > >  GArray *tables;
> > > -uint32_t smbios_ep_addr;
> > > -struct smbios_21_entry_point smbios_ep_table;
> > > +uint64_t smbios_ep_addr[2];
> > > +smbios_entry_point smbios_ep_table;
> > >  uint16_t smbios_cpu_max_speed;
> > >  uint16_t smbios_cpu_curr_speed;
> > >  uint8_t *required_struct_types;
> > > @@ -533,10 +541,10 @@ static void test_acpi_asl(test_data *data)
> > >  free_test_data(_data);
> > >  }
> > >
> > > -static bool smbios_ep_table_ok(test_data *data)
> > > +static bool smbios_ep2_table_ok(test_data *data)
> > >  {
> > > -struct smbios_21_entry_point *ep_table = >smbios_ep_table;
> > > -uint32_t addr = data->smbios_ep_addr;
> > > +struct smbios_21_entry_point *ep_table = >smbios_ep_table.ep21;
> > > +uint32_t addr = data->smbios_ep_addr[SMBIOS_VER21];
> > >
> > >  qtest_memread(data->qts, addr, ep_table, sizeof(*ep_table));
> > >  if (memcmp(ep_table->anchor_string, "_SM_", 4)) {
> > > @@ -559,29 +567,59 @@ static bool smbios_ep_table_ok(test_data *data)
> > >  return true;
> > >  }
> > >
> > > -static void test_smbios_entry_point(test_data *data)
> > > +static bool smbios_ep3_table_ok(test_data *data)
> > > +{
> > > +struct smbios_30_entry_point *ep_table = >smbios_ep_table.ep30;
> > > +uint64_t addr = data->smbios_ep_addr[SMBIOS_VER30];
> > > +
> > > +qtest_memread(data->qts, addr, ep_table, sizeof(*ep_table));
> > > +if (memcmp(ep_table->anchor_string, "_SM3_", 5)) {
> > > +return false;
> > > +}
> > > +
> > > +if (acpi_calc_checksum((uint8_t *)ep_table, sizeof *ep_table)) {
> > > +return false;
> > > +}
> > > +
> > > +return true;
> > > +}
> > > +
> > > +static int test_smbios_entry_point(test_data *data)
> > >  {
> > >  uint32_t off;
> > > +bool found_ep2 = false, found_ep3 = false;
> > >
> > >  /* find smbios entry point structure */
> > >  for (off = 0xf; off < 0x10; off += 0x10) {
> > > -uint8_t sig[] = "_SM_";
> > > +uint8_t sig[] = "_SM3_";  
> >
> > well I'd just add a separate sig3  
> 
> Ok
> 
> > >  int i;
> > >
> > >  for (i = 0; i < sizeof sig - 1; ++i) {
> > >  sig[i] = qtest_readb(data->qts, off + i);
> > >  }
> > >
> > > -if (!memcmp(sig, "_SM_", sizeof sig)) {
> > > +if (!found_ep2 && !memcmp(sig, "_SM_", sizeof sig - 2)) {  
> >
> > keep original v2 code and just add similar chunk for v3,
> > drop found_foo locals,
> > that should make it easier to read/follow
> > (i.e. less conditions 

Re: [PATCH 1/5] hw/smbios: add core_count2 to smbios table type 4

2022-06-07 Thread Igor Mammedov
On Mon, 6 Jun 2022 13:11:36 +0200
Julia Suvorova  wrote:

> On Thu, Jun 2, 2022 at 4:35 PM Igor Mammedov  wrote:
> >
> > On Thu, 2 Jun 2022 16:31:25 +0200
> > Igor Mammedov  wrote:
> >  
> > > On Tue, 31 May 2022 14:40:15 +0200
> > > Julia Suvorova  wrote:
> > >  
> > > > On Sat, May 28, 2022 at 6:34 AM Ani Sinha  wrote:  
> > > > >
> > > > >
> > > > >
> > > > > On Fri, 27 May 2022, Julia Suvorova wrote:
> > > > >  
> > > > > > In order to use the increased number of cpus, we need to bring 
> > > > > > smbios
> > > > > > tables in line with the SMBIOS 3.0 specification. This allows us to
> > > > > > introduce core_count2 which acts as a duplicate of core_count if we 
> > > > > > have
> > > > > > fewer cores than 256, and contains the actual core number per 
> > > > > > socket if
> > > > > > we have more.
> > > > > >
> > > > > > core_enabled2 and thread_count2 fields work the same way.
> > > > > >
> > > > > > Signed-off-by: Julia Suvorova   
> > > > >
> > > > > Other than the comment below,
> > > > > Reviewed-by: Ani Sinha 
> > > > >  
> > > > > > ---
> > > > > >  include/hw/firmware/smbios.h |  3 +++
> > > > > >  hw/smbios/smbios.c   | 11 +--
> > > > > >  2 files changed, 12 insertions(+), 2 deletions(-)
> > > > > >
> > > > > > diff --git a/include/hw/firmware/smbios.h 
> > > > > > b/include/hw/firmware/smbios.h
> > > > > > index 4b7ad77a44..c427ae5558 100644
> > > > > > --- a/include/hw/firmware/smbios.h
> > > > > > +++ b/include/hw/firmware/smbios.h
> > > > > > @@ -187,6 +187,9 @@ struct smbios_type_4 {
> > > > > >  uint8_t thread_count;
> > > > > >  uint16_t processor_characteristics;
> > > > > >  uint16_t processor_family2;
> > > > > > +uint16_t core_count2;
> > > > > > +uint16_t core_enabled2;
> > > > > > +uint16_t thread_count2;  
> >
> > on the other hand,
> > is it ok unconditionally extend type 4 and use v3 structure
> > if qemu was started with v2 smbios?  
> 
> We have a flag for the entry point type, not the smbios version per
> se. Additional fields added to structures were not previously tracked
> (for instance, processor_family2 is v2.6 and status is v2.0). AFAIU it
that's a bug, unless there is a very good reason to keep doing that,
I'd not do that.

> can affect only the total table length and the maximum structure size

table length is fixed depending on used version,
so if we follow it, we should set length and use part of structure
correctly if old version is specified (i.e.
   1. old structure + v30 structure,
   2. copy only a relevant part of v30 structure and
  fixup length when v2 version is asked for
though, I'd prefer #1

> (word). But if you like, I can raise an error (warning) if someone
> tries to start a vm with cpus > 255 and smbios v2.

it's a separate thing, I'd error out
(it will break users that use v2 with too may CPUs but then
they should fix their configuration to use v3)

> Best regards, Julia Suvorova.
> 
> > > > >
> > > > > I would add a comment along the lines of
> > > > > /* section 7.5, table 21 smbios spec version 3.0.0 */  
> > > >
> > > > Ok  
> > >
> > > With Ani's comment fixed
> > >
> > > Reviewed-by: Igor Mammedov 
> > >  
> > > >  
> > > > > >  } QEMU_PACKED;
> > > > > >
> > > > > >  /* SMBIOS type 11 - OEM strings */
> > > > > > diff --git a/hw/smbios/smbios.c b/hw/smbios/smbios.c
> > > > > > index 60349ee402..45d7be6b30 100644
> > > > > > --- a/hw/smbios/smbios.c
> > > > > > +++ b/hw/smbios/smbios.c
> > > > > > @@ -709,8 +709,15 @@ static void 
> > > > > > smbios_build_type_4_table(MachineState *ms, unsigned instance)
> > > > > >  SMBIOS_TABLE_SET_STR(4, serial_number_str, type4.serial);
> > > > > >  SMBIOS_TABLE_SET_STR(4, asset_tag_number_str, type4.asset);
> > > > > >  SMBIOS_TABLE_SET_STR(4, part_number_str, type4.part);
> > > > > > -t->core_count = t->core_enabled = ms->smp.cores;
> > > > > > -t->thread_count = ms->smp.threads;
> > > > > > +
> > > > > > +t->core_count = (ms->smp.cores > 255) ? 0xFF : ms->smp.cores;
> > > > > > +t->core_enabled = t->core_count;
> > > > > > +
> > > > > > +t->core_count2 = t->core_enabled2 = cpu_to_le16(ms->smp.cores);
> > > > > > +
> > > > > > +t->thread_count = (ms->smp.threads > 255) ? 0xFF : 
> > > > > > ms->smp.threads;
> > > > > > +t->thread_count2 = cpu_to_le16(ms->smp.threads);
> > > > > > +
> > > > > >  t->processor_characteristics = cpu_to_le16(0x02); /* Unknown */
> > > > > >  t->processor_family2 = cpu_to_le16(0x01); /* Other */
> > > > > >
> > > > > > --
> > > > > > 2.35.1
> > > > > >
> > > > > >  
> > > > >  
> > > >  
> > >  
> >  
> 




Re: [PATCH 4/5] bios-tables-test: add test for number of cores > 255

2022-06-02 Thread Igor Mammedov
On Fri, 27 May 2022 18:56:50 +0200
Julia Suvorova  wrote:

> The new test is run with a large number of cpus and checks if the
> core_count field in smbios_cpu_test (structure type 4) is correct.
> 
> Choose q35 as it allows to run with -smp > 255.
> 
> Signed-off-by: Julia Suvorova 
> ---
>  tests/qtest/bios-tables-test.c | 35 +-
>  1 file changed, 34 insertions(+), 1 deletion(-)
> 
> diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
> index 0ba9d749a5..f2464adaa0 100644
> --- a/tests/qtest/bios-tables-test.c
> +++ b/tests/qtest/bios-tables-test.c
> @@ -100,6 +100,8 @@ typedef struct {
>  smbios_entry_point smbios_ep_table;
>  uint16_t smbios_cpu_max_speed;
>  uint16_t smbios_cpu_curr_speed;
> +uint8_t smbios_core_count;
> +uint16_t smbios_core_count2;
>  uint8_t *required_struct_types;
>  int required_struct_types_len;
>  QTestState *qts;
> @@ -640,8 +642,9 @@ static inline bool smbios_single_instance(uint8_t type)
>  
>  static bool smbios_cpu_test(test_data *data, uint32_t addr)
>  {
> +uint8_t real_cc, expect_cc = data->smbios_core_count;

%s/expect/expected/
also I'd s/real_cc/core_count/

> +uint16_t real, real_cc2, expect_cc2 = data->smbios_core_count2;
ditto

>  uint16_t expect_speed[2];
> -uint16_t real;
>  int offset[2];
>  int i;
>  
> @@ -660,6 +663,20 @@ static bool smbios_cpu_test(test_data *data, uint32_t 
> addr)
>  }
>  }
>  
> +real_cc = qtest_readb(data->qts, addr + offsetof(struct smbios_type_4, 
> core_count));
> +real_cc2 = qtest_readw(data->qts, addr + offsetof(struct smbios_type_4, 
> core_count2));
> +
> +if (expect_cc && (real_cc != expect_cc)) {
> +fprintf(stderr, "Unexpected SMBIOS CPU count: real %u expect %u\n",
> +real_cc, expect_cc);
> +return false;

since you are rewriting it anyways, how about 
if (expect_cc) {
  g_assert_cmpuint(...)
}

instead of printing/propagating error

> +}
> +if ((expect_cc == 0xFF) && (real_cc2 != expect_cc2)) {
> +fprintf(stderr, "Unexpected SMBIOS CPU count2: real %u expect %u\n",
> +real_cc2, expect_cc2);
> +return false;
> +}
> +
>  return true;
>  }
>  
> @@ -905,6 +922,21 @@ static void test_acpi_q35_tcg(void)
>  free_test_data();
>  }
>  
> +static void test_acpi_q35_tcg_core_count2(void)
> +{
> +test_data data = {
> +.machine = MACHINE_Q35,
> +.variant = ".core-count2",
> +.required_struct_types = base_required_struct_types,
> +.required_struct_types_len = ARRAY_SIZE(base_required_struct_types),
> +.smbios_core_count = 0xFF,
> +.smbios_core_count2 = 275,
> +};
> +
> +test_acpi_one("-machine smbios-entry-point-type=64 -smp 275", );
> +free_test_data();
> +}
> +
>  static void test_acpi_q35_tcg_bridge(void)
>  {
>  test_data data;
> @@ -1787,6 +1819,7 @@ int main(int argc, char *argv[])
>  qtest_add_func("acpi/piix4/pci-hotplug/off",
> test_acpi_piix4_no_acpi_pci_hotplug);
>  qtest_add_func("acpi/q35", test_acpi_q35_tcg);
> +qtest_add_func("acpi/q35/core-count2", 
> test_acpi_q35_tcg_core_count2);
>  qtest_add_func("acpi/q35/bridge", test_acpi_q35_tcg_bridge);
>  qtest_add_func("acpi/q35/multif-bridge", 
> test_acpi_q35_multif_bridge);
>  qtest_add_func("acpi/q35/mmio64", test_acpi_q35_tcg_mmio64);




Re: [PATCH 2/5] bios-tables-test: teach test to use smbios 3.0 tables

2022-06-02 Thread Igor Mammedov
On Fri, 27 May 2022 18:56:48 +0200
Julia Suvorova  wrote:

> Introduce the 64-bit entry point. Since we no longer have a total
> number of structures, stop checking for the new ones at the EOF
> structure (type 127).
> 
> Signed-off-by: Julia Suvorova 
> ---
>  tests/qtest/bios-tables-test.c | 101 -
>  1 file changed, 75 insertions(+), 26 deletions(-)
> 
> diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
> index a4a46e97f0..0ba9d749a5 100644
> --- a/tests/qtest/bios-tables-test.c
> +++ b/tests/qtest/bios-tables-test.c
> @@ -75,6 +75,14 @@
>  #define OEM_TEST_ARGS  "-machine x-oem-id=" OEM_ID ",x-oem-table-id=" \
> OEM_TABLE_ID
>  
> +#define SMBIOS_VER21 0
> +#define SMBIOS_VER30 1
> +
> +typedef struct {
> +struct smbios_21_entry_point ep21;
> +struct smbios_30_entry_point ep30;
> +} smbios_entry_point;
> +
>  typedef struct {
>  bool tcg_only;
>  const char *machine;
> @@ -88,8 +96,8 @@ typedef struct {
>  uint64_t rsdp_addr;
>  uint8_t rsdp_table[36 /* ACPI 2.0+ RSDP size */];
>  GArray *tables;
> -uint32_t smbios_ep_addr;
> -struct smbios_21_entry_point smbios_ep_table;
> +uint64_t smbios_ep_addr[2];
> +smbios_entry_point smbios_ep_table;
>  uint16_t smbios_cpu_max_speed;
>  uint16_t smbios_cpu_curr_speed;
>  uint8_t *required_struct_types;
> @@ -533,10 +541,10 @@ static void test_acpi_asl(test_data *data)
>  free_test_data(_data);
>  }
>  
> -static bool smbios_ep_table_ok(test_data *data)
> +static bool smbios_ep2_table_ok(test_data *data)
>  {
> -struct smbios_21_entry_point *ep_table = >smbios_ep_table;
> -uint32_t addr = data->smbios_ep_addr;
> +struct smbios_21_entry_point *ep_table = >smbios_ep_table.ep21;
> +uint32_t addr = data->smbios_ep_addr[SMBIOS_VER21];
>  
>  qtest_memread(data->qts, addr, ep_table, sizeof(*ep_table));
>  if (memcmp(ep_table->anchor_string, "_SM_", 4)) {
> @@ -559,29 +567,59 @@ static bool smbios_ep_table_ok(test_data *data)
>  return true;
>  }
>  
> -static void test_smbios_entry_point(test_data *data)
> +static bool smbios_ep3_table_ok(test_data *data)
> +{
> +struct smbios_30_entry_point *ep_table = >smbios_ep_table.ep30;
> +uint64_t addr = data->smbios_ep_addr[SMBIOS_VER30];
> +
> +qtest_memread(data->qts, addr, ep_table, sizeof(*ep_table));
> +if (memcmp(ep_table->anchor_string, "_SM3_", 5)) {
> +return false;
> +}
> +
> +if (acpi_calc_checksum((uint8_t *)ep_table, sizeof *ep_table)) {
> +return false;
> +}
> +
> +return true;
> +}
> +
> +static int test_smbios_entry_point(test_data *data)
>  {
>  uint32_t off;
> +bool found_ep2 = false, found_ep3 = false;
>  
>  /* find smbios entry point structure */
>  for (off = 0xf; off < 0x10; off += 0x10) {
> -uint8_t sig[] = "_SM_";
> +uint8_t sig[] = "_SM3_";

well I'd just add a separate sig3

>  int i;
>  
>  for (i = 0; i < sizeof sig - 1; ++i) {
>  sig[i] = qtest_readb(data->qts, off + i);
>  }
>  
> -if (!memcmp(sig, "_SM_", sizeof sig)) {
> +if (!found_ep2 && !memcmp(sig, "_SM_", sizeof sig - 2)) {

keep original v2 code and just add similar chunk for v3,
drop found_foo locals,
that should make it easier to read/follow
(i.e. less conditions to think about and no magic fiddling with the length of 
signature)

>  /* signature match, but is this a valid entry point? */
> -data->smbios_ep_addr = off;
> -if (smbios_ep_table_ok(data)) {
> -break;
> +data->smbios_ep_addr[SMBIOS_VER21] = off;
> +if (smbios_ep2_table_ok(data)) {
> +found_ep2 = true;
> +}
> +} else if (!found_ep3 && !memcmp(sig, "_SM3_", sizeof sig - 1)) {
> +data->smbios_ep_addr[SMBIOS_VER30] = off;
> +if (smbios_ep3_table_ok(data)) {
> +found_ep3 = true;
>  }
>  }
> +
> +if (found_ep2 || found_ep3) {
> +break;
> +}
>  }
>  
> -g_assert_cmphex(off, <, 0x10);
> +g_assert_cmphex(data->smbios_ep_addr[SMBIOS_VER21], <, 0x10);
> +g_assert_cmphex(data->smbios_ep_addr[SMBIOS_VER30], <, 0x10);
> +
> +return found_ep3 ? SMBIOS_VER30 : SMBIOS_VER21;

and use content of data->smbios_ep_addr[] to return found version

>  }
>  
>  static inline bool smbios_single_instance(uint8_t type)
> @@ -625,16 +663,23 @@ static bool smbios_cpu_test(test_data *data, uint32_t 
> addr)
>  return true;
>  }
>  
> -static void test_smbios_structs(test_data *data)
> +static void test_smbios_structs(test_data *data, int ver)
>  {
>  DECLARE_BITMAP(struct_bitmap, SMBIOS_MAX_TYPE+1) = { 0 };
> -struct smbios_21_entry_point *ep_table = >smbios_ep_table;
> -uint32_t addr = le32_to_cpu(ep_table->structure_table_address);
> -int i, 

Re: [PATCH 1/5] hw/smbios: add core_count2 to smbios table type 4

2022-06-02 Thread Igor Mammedov
On Thu, 2 Jun 2022 16:31:25 +0200
Igor Mammedov  wrote:

> On Tue, 31 May 2022 14:40:15 +0200
> Julia Suvorova  wrote:
> 
> > On Sat, May 28, 2022 at 6:34 AM Ani Sinha  wrote:  
> > >
> > >
> > >
> > > On Fri, 27 May 2022, Julia Suvorova wrote:
> > >
> > > > In order to use the increased number of cpus, we need to bring smbios
> > > > tables in line with the SMBIOS 3.0 specification. This allows us to
> > > > introduce core_count2 which acts as a duplicate of core_count if we have
> > > > fewer cores than 256, and contains the actual core number per socket if
> > > > we have more.
> > > >
> > > > core_enabled2 and thread_count2 fields work the same way.
> > > >
> > > > Signed-off-by: Julia Suvorova 
> > >
> > > Other than the comment below,
> > > Reviewed-by: Ani Sinha 
> > >
> > > > ---
> > > >  include/hw/firmware/smbios.h |  3 +++
> > > >  hw/smbios/smbios.c   | 11 +--
> > > >  2 files changed, 12 insertions(+), 2 deletions(-)
> > > >
> > > > diff --git a/include/hw/firmware/smbios.h b/include/hw/firmware/smbios.h
> > > > index 4b7ad77a44..c427ae5558 100644
> > > > --- a/include/hw/firmware/smbios.h
> > > > +++ b/include/hw/firmware/smbios.h
> > > > @@ -187,6 +187,9 @@ struct smbios_type_4 {
> > > >  uint8_t thread_count;
> > > >  uint16_t processor_characteristics;
> > > >  uint16_t processor_family2;
> > > > +uint16_t core_count2;
> > > > +uint16_t core_enabled2;
> > > > +uint16_t thread_count2;

on the other hand,
is it ok unconditionally extend type 4 and use v3 structure
if qemu was started with v2 smbios?

> > >
> > > I would add a comment along the lines of
> > > /* section 7.5, table 21 smbios spec version 3.0.0 */
> > 
> > Ok  
> 
> With Ani's comment fixed 
> 
> Reviewed-by: Igor Mammedov 
> 
> >   
> > > >  } QEMU_PACKED;
> > > >
> > > >  /* SMBIOS type 11 - OEM strings */
> > > > diff --git a/hw/smbios/smbios.c b/hw/smbios/smbios.c
> > > > index 60349ee402..45d7be6b30 100644
> > > > --- a/hw/smbios/smbios.c
> > > > +++ b/hw/smbios/smbios.c
> > > > @@ -709,8 +709,15 @@ static void smbios_build_type_4_table(MachineState 
> > > > *ms, unsigned instance)
> > > >  SMBIOS_TABLE_SET_STR(4, serial_number_str, type4.serial);
> > > >  SMBIOS_TABLE_SET_STR(4, asset_tag_number_str, type4.asset);
> > > >  SMBIOS_TABLE_SET_STR(4, part_number_str, type4.part);
> > > > -t->core_count = t->core_enabled = ms->smp.cores;
> > > > -t->thread_count = ms->smp.threads;
> > > > +
> > > > +t->core_count = (ms->smp.cores > 255) ? 0xFF : ms->smp.cores;
> > > > +t->core_enabled = t->core_count;
> > > > +
> > > > +t->core_count2 = t->core_enabled2 = cpu_to_le16(ms->smp.cores);
> > > > +
> > > > +t->thread_count = (ms->smp.threads > 255) ? 0xFF : ms->smp.threads;
> > > > +t->thread_count2 = cpu_to_le16(ms->smp.threads);
> > > > +
> > > >  t->processor_characteristics = cpu_to_le16(0x02); /* Unknown */
> > > >  t->processor_family2 = cpu_to_le16(0x01); /* Other */
> > > >
> > > > --
> > > > 2.35.1
> > > >
> > > >
> > >
> >   
> 




Re: [PATCH 1/5] hw/smbios: add core_count2 to smbios table type 4

2022-06-02 Thread Igor Mammedov
On Tue, 31 May 2022 14:40:15 +0200
Julia Suvorova  wrote:

> On Sat, May 28, 2022 at 6:34 AM Ani Sinha  wrote:
> >
> >
> >
> > On Fri, 27 May 2022, Julia Suvorova wrote:
> >  
> > > In order to use the increased number of cpus, we need to bring smbios
> > > tables in line with the SMBIOS 3.0 specification. This allows us to
> > > introduce core_count2 which acts as a duplicate of core_count if we have
> > > fewer cores than 256, and contains the actual core number per socket if
> > > we have more.
> > >
> > > core_enabled2 and thread_count2 fields work the same way.
> > >
> > > Signed-off-by: Julia Suvorova   
> >
> > Other than the comment below,
> > Reviewed-by: Ani Sinha 
> >  
> > > ---
> > >  include/hw/firmware/smbios.h |  3 +++
> > >  hw/smbios/smbios.c   | 11 +--
> > >  2 files changed, 12 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/include/hw/firmware/smbios.h b/include/hw/firmware/smbios.h
> > > index 4b7ad77a44..c427ae5558 100644
> > > --- a/include/hw/firmware/smbios.h
> > > +++ b/include/hw/firmware/smbios.h
> > > @@ -187,6 +187,9 @@ struct smbios_type_4 {
> > >  uint8_t thread_count;
> > >  uint16_t processor_characteristics;
> > >  uint16_t processor_family2;
> > > +uint16_t core_count2;
> > > +uint16_t core_enabled2;
> > > +uint16_t thread_count2;  
> >
> > I would add a comment along the lines of
> > /* section 7.5, table 21 smbios spec version 3.0.0 */  
> 
> Ok

With Ani's comment fixed 

Reviewed-by: Igor Mammedov 

> 
> > >  } QEMU_PACKED;
> > >
> > >  /* SMBIOS type 11 - OEM strings */
> > > diff --git a/hw/smbios/smbios.c b/hw/smbios/smbios.c
> > > index 60349ee402..45d7be6b30 100644
> > > --- a/hw/smbios/smbios.c
> > > +++ b/hw/smbios/smbios.c
> > > @@ -709,8 +709,15 @@ static void smbios_build_type_4_table(MachineState 
> > > *ms, unsigned instance)
> > >  SMBIOS_TABLE_SET_STR(4, serial_number_str, type4.serial);
> > >  SMBIOS_TABLE_SET_STR(4, asset_tag_number_str, type4.asset);
> > >  SMBIOS_TABLE_SET_STR(4, part_number_str, type4.part);
> > > -t->core_count = t->core_enabled = ms->smp.cores;
> > > -t->thread_count = ms->smp.threads;
> > > +
> > > +t->core_count = (ms->smp.cores > 255) ? 0xFF : ms->smp.cores;
> > > +t->core_enabled = t->core_count;
> > > +
> > > +t->core_count2 = t->core_enabled2 = cpu_to_le16(ms->smp.cores);
> > > +
> > > +t->thread_count = (ms->smp.threads > 255) ? 0xFF : ms->smp.threads;
> > > +t->thread_count2 = cpu_to_le16(ms->smp.threads);
> > > +
> > >  t->processor_characteristics = cpu_to_le16(0x02); /* Unknown */
> > >  t->processor_family2 = cpu_to_le16(0x01); /* Other */
> > >
> > > --
> > > 2.35.1
> > >
> > >  
> >  
> 




Re: [PATCH 0/2] i386: fixup number of logical CPUs when host-cache-info=on

2022-05-31 Thread Igor Mammedov
Paolo,
 can you pick this up if it looks fine, please?

On Tue, 24 May 2022 11:10:18 -0400
Igor Mammedov  wrote:

> Igor Mammedov (2):
>   x86: cpu: make sure number of addressable IDs for processor cores
> meets the spec
>   x86: cpu: fixup number of addressable IDs for logical processors
> sharing cache
> 
>  target/i386/cpu.c | 20 
>  1 file changed, 16 insertions(+), 4 deletions(-)
> 




Re: [PATCH v5 40/43] hw/loongarch: Add LoongArch ls7a acpi device support

2022-05-30 Thread Igor Mammedov
On Fri, 27 May 2022 06:18:43 +0800
maobibo  wrote:

> On 5/26/22 16:42, Igor Mammedov wrote:
> > On Tue, 24 May 2022 16:18:01 +0800
> > Xiaojuan Yang  wrote:
> > 
> > commit message needs pointers to specification,
> > + in patch comments that point to specific chapters
> > within the spec for newly introduced  registers   
> Igor,
> 
> Thanks for reviewing the patch and guidance, ls7A acpi registers has 
> minimium registers required by ACPI spec, including pm1a stat/en/cnt, 
> pm_tmr and GPE stat/enable registers, there is no smi mode in loongarch 

those only required for legacy 'Fixed Hardware Programming Model'
which is historically used on x86.
For new platforms if you don't have hardware yet it's better to use
'Hardware-Reduced ACPI' approach and reuse code we already have for
aarch64.

> architecture. The  LS7A acpi driver is copied from acpi core driver 
> since register layout of pm1a/pm_tmr/gpe is different from x86 acpi 
> registers.

sorry, I couldn't parse above sentence.

> By the ACPI spec, there is no specific requirement for layout of ACPI 
> registers, later we will reuse acpi core driver if the acpi registers 
> layout can be set dynamically. And we will send the second patch with 
> detailed description with LS7A ACPI module.

regardless of a separate doc patch, this patch should have a minimal
documentation as it have been pointed earlier, otherwise reviewer or
someone who will later have to look on this code, will have no point
of reference and have no idea if this code is correct or not.


Also introducing ACPI hardware without an ACPI tables to complement
it is rather pointless as OSPM won't be able to discover/use it.
It might be better to drop this patch until you have corresponding
ACPI tables to describe it.

> regards
> bibo, mao
> >   
> >> From: Song Gao 
> >>
> >> Signed-off-by: Xiaojuan Yang 
> >> Signed-off-by: Song Gao 
> >> ---
> >>   MAINTAINERS|   2 +
> >>   hw/acpi/Kconfig|   4 +
> >>   hw/acpi/ls7a.c | 374 +
> >>   hw/acpi/meson.build|   1 +
> >>   hw/loongarch/Kconfig   |   2 +
> >>   hw/loongarch/loongson3.c   |  19 +-
> >>   include/hw/acpi/ls7a.h |  53 ++
> >>   include/hw/pci-host/ls7a.h |   6 +
> >>   8 files changed, 458 insertions(+), 3 deletions(-)
> >>   create mode 100644 hw/acpi/ls7a.c
> >>   create mode 100644 include/hw/acpi/ls7a.h
> >>
> >> diff --git a/MAINTAINERS b/MAINTAINERS
> >> index 6e03a8bca8..6f861dec0a 100644
> >> --- a/MAINTAINERS
> >> +++ b/MAINTAINERS
> >> @@ -1138,6 +1138,8 @@ F: include/hw/intc/loongarch_*.h
> >>   F: hw/intc/loongarch_*.c
> >>   F: include/hw/pci-host/ls7a.h
> >>   F: hw/rtc/ls7a_rtc.c
> >> +F: include/hw/acpi/ls7a.h
> >> +F: hw/acpi/ls7a.c
> >>   
> >>   M68K Machines
> >>   -
> >> diff --git a/hw/acpi/Kconfig b/hw/acpi/Kconfig
> >> index 3703aca212..c65965c9b9 100644
> >> --- a/hw/acpi/Kconfig
> >> +++ b/hw/acpi/Kconfig
> >> @@ -13,6 +13,10 @@ config ACPI_X86
> >>   select ACPI_PCIHP
> >>   select ACPI_ERST
> >>   
> >> +config ACPI_LOONGARCH
> >> +bool
> >> +select ACPI
> >> +
> >>   config ACPI_X86_ICH
> >>   bool
> >>   select ACPI_X86
> >> diff --git a/hw/acpi/ls7a.c b/hw/acpi/ls7a.c
> >> new file mode 100644
> >> index 00..cc658422dd
> >> --- /dev/null
> >> +++ b/hw/acpi/ls7a.c
> >> @@ -0,0 +1,374 @@
> >> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> >> +/*
> >> + * LoongArch ACPI implementation
> >> + *
> >> + * Copyright (C) 2021 Loongson Technology Corporation Limited
> >> + */
> >> +
> >> +#include "qemu/osdep.h"
> >> +#include "sysemu/sysemu.h"
> >> +#include "hw/hw.h"
> >> +#include "hw/irq.h"
> >> +#include "sysemu/reset.h"
> >> +#include "sysemu/runstate.h"
> >> +#include "hw/acpi/acpi.h"
> >> +#include "hw/acpi/ls7a.h"
> >> +#include "hw/nvram/fw_cfg.h"
> >> +#include "qemu/config-file.h"
> >> +#include "qapi/opts-visitor.h"
> >> +#include "qapi/qapi-events-run-state.h"
> >> +#include "qapi/error.h"
> >> +#include "hw/pci-host/ls7a.h"
> >> +#include "hw/mem/pc-d

Re: [PATCH 28/35] acpi: pvpanic-isa: use AcpiDevAmlIfClass:build_dev_aml to provide device's AML

2022-05-26 Thread Igor Mammedov
On Wed, 18 May 2022 12:29:25 -0400
"Michael S. Tsirkin"  wrote:

> On Tue, May 17, 2022 at 10:13:51AM +0200, Gerd Hoffmann wrote:
> > That problem isn't new and we already have a bunch of aml_* stubs
> > because of that.  I expect it'll work just fine, at worst we'll
> > have to add a stub or two in case some calls are not covered yet.  
> 
> Right but adding these stubs is a bother, we keep missing some.
> If possible I'd like the solution to be cleaner than the status quo.
> Is adding a wrapper instead of setting a method directly such
> a big problem really?
> 


here is stub based ACPI decoupling for isa devices we currently
have in the tree:

https://gitlab.com/imammedo/qemu/-/commits/decouple_build_aml_v1/

If it looks acceptable to you, I can prep/post it first and
then rebase this series on top to reduce unnecessary churning.
 




Re: [PATCH 0/3] hw/acpi/aml-build: Fix {socket, cluster, core} IDs in PPTT

2022-05-26 Thread Igor Mammedov
On Thu, 26 May 2022 19:37:47 +0800
Gavin Shan  wrote:

> Hi Igor, Yanan and maintainers,
> 
> On 5/18/22 5:21 PM, Gavin Shan wrote:
> > The {socket, cluster, core} IDs detected from Linux guest aren't
> > matching with what have been provided in PPTT. The flag used for
> > 'ACPI Processor ID valid' is missed for {socket, cluster, core}
> > nodes. In this case, Linux guest takes the offset between the
> > node and PPTT header as the corresponding IDs, as the following
> > logs show.
> > 
> > 
> >/home/gavin/sandbox/qemu.main/build/qemu-system-aarch64\
> >-accel kvm -machine virt,gic-version=host -cpu host   \
> >-smp 8,sockets=2,clusters=2,cores=2,threads=1
> >  :
> >  
> ># cd /sys/devices/system/cpu
> ># for i in `seq 0 15`; do cat cpu$i/topology/physical_package_id; done
> >  36  36  36  36  36  36  36  36
> >  336 336 336 336 336 336 336 336
> ># for i in `seq 0 15`; do cat cpu$i/topology/cluster_id; done
> >  56  56  56  56  196 196 196 196
> >  356 356 356 356 496 496 496 496
> ># for i in `seq 0 15`; do cat cpu$i/topology/core_id; done
> >  76  76  136 136 216 216 276 276
> >  376 376 436 436 516 516 576 576
> > 
> > This fixes the issue by setting 'ACPI Processor ID valid' flag for
> > {socket, cluster, core} nodes. With this applied, the IDs are exactly
> > what have been provided in PPTT. I also checked the PPTT table on my
> > host, where the 'ACPI Processor ID valid' is set for cluster/core nodes,
> > but missed from socket nodes.
> > 
> >host# pwd
> >/sys/devices/system/cpu
> >host# cat cpu0/topology/physical_package_id; \
> >  cat cpu0/topology/cluster_id;  \
> >  cat cpu0/topology/core_id
> >36 0 0
> > 
> > Gavin Shan (3):
> >tests/acpi/virt: Allow PPTT ACPI table changes
> >hw/acpi/aml-build: Fix {socket, cluster, core} IDs in PPTT
> >tests/acpi/virt: Update PPTT ACPI table
> > 
> >   hw/acpi/aml-build.c   |   9 ++---
> >   tests/data/acpi/virt/PPTT | Bin 96 -> 96 bytes
> >   2 files changed, 6 insertions(+), 3 deletions(-)
> >   
> 
> Could you help to review this tiny series? Thanks in advance.
done, so far I'm not convinced that it's QEMU's fault. see comment on 2/3

> 
> Thanks,
> Gavin
> 




Re: [PATCH 2/3] hw/acpi/aml-build: Fix {socket, cluster, core} IDs in PPTT

2022-05-26 Thread Igor Mammedov
On Wed, 18 May 2022 17:21:40 +0800
Gavin Shan  wrote:

> The {socket, cluster, core} IDs detected from Linux guest aren't
> matching with what have been provided in PPTT. The flag used for
> 'ACPI Processor ID valid' is missed for {socket, cluster, core}
> nodes.

To permit this flag set  on no leaf nodes we have to have
a corresponding containers built for them in DSDT so that
'ACPI Processor ID' could be matched with containers '_UID's.
If we don not build such containers then setting this flag is
not correct. And I don't recall QEMU building CPU hierarchy
in DSDT.

> In this case, Linux guest takes the offset between the
> node and PPTT header as the corresponding IDs, as the following
> logs show.

perhaps it's kernel which should be fixed to handle
not set 'ACPI Processor ID valid' correctly.

> 
>   /home/gavin/sandbox/qemu.main/build/qemu-system-aarch64\
>   -accel kvm -machine virt,gic-version=host -cpu host\
>   -smp 8,sockets=2,clusters=2,cores=2,threads=1
> :
> 
>   # cd /sys/devices/system/cpu
>   # for i in `seq 0 15`; do cat cpu$i/topology/physical_package_id; done
> 36  36  36  36  36  36  36  36
> 336 336 336 336 336 336 336 336
>   # for i in `seq 0 15`; do cat cpu$i/topology/cluster_id; done
> 56  56  56  56  196 196 196 196
> 356 356 356 356 496 496 496 496
>   # for i in `seq 0 15`; do cat cpu$i/topology/core_id; done
> 76  76  136 136 216 216 276 276
> 376 376 436 436 516 516 576 576
> 
> This fixes the issue by setting 'ACPI Processor ID valid' flag for
> {socket, cluster, core} nodes. With this applied, the IDs are exactly
> what have been provided in PPTT.
> 
>   # for i in `seq 0 15`; do cat cpu$i/topology/physical_package_id; done
>   0 0 0 0 0 0 0 0
>   1 1 1 1 1 1 1 1
>   # for i in `seq 0 15`; do cat cpu$i/topology/cluster_id; done
>   0 0 0 0 1 1 1 1
>   0 0 0 0 1 1 1 1
>   # for i in `seq 0 15`; do cat cpu$i/topology/core_id; done
>   0 0 1 1 0 0 1 1
>   0 0 1 1 0 0 1 1
> 
> Signed-off-by: Gavin Shan 
> ---
>  hw/acpi/aml-build.c | 9 ++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> index e6bfac95c7..89f191fd3b 100644
> --- a/hw/acpi/aml-build.c
> +++ b/hw/acpi/aml-build.c
> @@ -2026,7 +2026,8 @@ void build_pptt(GArray *table_data, BIOSLinker *linker, 
> MachineState *ms,
>  core_id = -1;
>  socket_offset = table_data->len - pptt_start;
>  build_processor_hierarchy_node(table_data,
> -(1 << 0), /* Physical package */
> +(1 << 0) | /* Physical package */
> +(1 << 1),  /* ACPI Processor ID valid */
>  0, socket_id, NULL, 0);
>  }
>  
> @@ -2037,7 +2038,8 @@ void build_pptt(GArray *table_data, BIOSLinker *linker, 
> MachineState *ms,
>  core_id = -1;
>  cluster_offset = table_data->len - pptt_start;
>  build_processor_hierarchy_node(table_data,
> -(0 << 0), /* Not a physical package */
> +(0 << 0) | /* Not a physical package */
> +(1 << 1),  /* ACPI Processor ID valid */
>  socket_offset, cluster_id, NULL, 0);
>  }
>  } else {
> @@ -2055,7 +2057,8 @@ void build_pptt(GArray *table_data, BIOSLinker *linker, 
> MachineState *ms,
>  core_id = cpus->cpus[n].props.core_id;
>  core_offset = table_data->len - pptt_start;
>  build_processor_hierarchy_node(table_data,
> -(0 << 0), /* Not a physical package */
> +(0 << 0) | /* Not a physical package */
> +(1 << 1),  /* ACPI Processor ID valid */
>  cluster_offset, core_id, NULL, 0);
>  }
>  




Re: [PATCH v5 40/43] hw/loongarch: Add LoongArch ls7a acpi device support

2022-05-26 Thread Igor Mammedov
On Tue, 24 May 2022 16:18:01 +0800
Xiaojuan Yang  wrote:

commit message needs pointers to specification,
+ in patch comments that point to specific chapters
within the spec for newly introduced  registers


> From: Song Gao 
> 
> Signed-off-by: Xiaojuan Yang 
> Signed-off-by: Song Gao 
> ---
>  MAINTAINERS|   2 +
>  hw/acpi/Kconfig|   4 +
>  hw/acpi/ls7a.c | 374 +
>  hw/acpi/meson.build|   1 +
>  hw/loongarch/Kconfig   |   2 +
>  hw/loongarch/loongson3.c   |  19 +-
>  include/hw/acpi/ls7a.h |  53 ++
>  include/hw/pci-host/ls7a.h |   6 +
>  8 files changed, 458 insertions(+), 3 deletions(-)
>  create mode 100644 hw/acpi/ls7a.c
>  create mode 100644 include/hw/acpi/ls7a.h
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 6e03a8bca8..6f861dec0a 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1138,6 +1138,8 @@ F: include/hw/intc/loongarch_*.h
>  F: hw/intc/loongarch_*.c
>  F: include/hw/pci-host/ls7a.h
>  F: hw/rtc/ls7a_rtc.c
> +F: include/hw/acpi/ls7a.h
> +F: hw/acpi/ls7a.c
>  
>  M68K Machines
>  -
> diff --git a/hw/acpi/Kconfig b/hw/acpi/Kconfig
> index 3703aca212..c65965c9b9 100644
> --- a/hw/acpi/Kconfig
> +++ b/hw/acpi/Kconfig
> @@ -13,6 +13,10 @@ config ACPI_X86
>  select ACPI_PCIHP
>  select ACPI_ERST
>  
> +config ACPI_LOONGARCH
> +bool
> +select ACPI
> +
>  config ACPI_X86_ICH
>  bool
>  select ACPI_X86
> diff --git a/hw/acpi/ls7a.c b/hw/acpi/ls7a.c
> new file mode 100644
> index 00..cc658422dd
> --- /dev/null
> +++ b/hw/acpi/ls7a.c
> @@ -0,0 +1,374 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +/*
> + * LoongArch ACPI implementation
> + *
> + * Copyright (C) 2021 Loongson Technology Corporation Limited
> + */
> +
> +#include "qemu/osdep.h"
> +#include "sysemu/sysemu.h"
> +#include "hw/hw.h"
> +#include "hw/irq.h"
> +#include "sysemu/reset.h"
> +#include "sysemu/runstate.h"
> +#include "hw/acpi/acpi.h"
> +#include "hw/acpi/ls7a.h"
> +#include "hw/nvram/fw_cfg.h"
> +#include "qemu/config-file.h"
> +#include "qapi/opts-visitor.h"
> +#include "qapi/qapi-events-run-state.h"
> +#include "qapi/error.h"
> +#include "hw/pci-host/ls7a.h"
> +#include "hw/mem/pc-dimm.h"
> +#include "hw/mem/nvdimm.h"
> +#include "migration/vmstate.h"
> +
> +static void ls7a_pm_update_sci_fn(ACPIREGS *regs)
> +{
> +LS7APMState *pm = container_of(regs, LS7APMState, acpi_regs);
> +acpi_update_sci(>acpi_regs, pm->irq);
> +}
> +
> +static uint64_t ls7a_gpe_readb(void *opaque, hwaddr addr, unsigned width)
> +{
> +LS7APMState *pm = opaque;
> +return acpi_gpe_ioport_readb(>acpi_regs, addr);
> +}
> +
> +static void ls7a_gpe_writeb(void *opaque, hwaddr addr, uint64_t val,
> +unsigned width)
> +{
> +LS7APMState *pm = opaque;
> +acpi_gpe_ioport_writeb(>acpi_regs, addr, val);
> +acpi_update_sci(>acpi_regs, pm->irq);
> +}
> +
> +static const MemoryRegionOps ls7a_gpe_ops = {
> +.read = ls7a_gpe_readb,
> +.write = ls7a_gpe_writeb,
> +.valid.min_access_size = 1,
> +.valid.max_access_size = 8,
> +.impl.min_access_size = 1,
> +.impl.max_access_size = 1,
> +.endianness = DEVICE_LITTLE_ENDIAN,
> +};
> +
> +#define VMSTATE_GPE_ARRAY(_field, _state)\
> + {   \
> + .name   = (stringify(_field)),  \
> + .version_id = 0,\
> + .num= ACPI_GPE0_LEN,\
> + .info   = _info_uint8,  \
> + .size   = sizeof(uint8_t),  \
> + .flags  = VMS_ARRAY | VMS_POINTER,  \
> + .offset = vmstate_offset_pointer(_state, _field, uint8_t),  \
> + }
> +
> +static uint64_t ls7a_reset_readw(void *opaque, hwaddr addr, unsigned width)
> +{
> +return 0;
> +}
> +
> +static void ls7a_reset_writew(void *opaque, hwaddr addr, uint64_t val,
> +  unsigned width)
> +{
> +if (val & 1) {
> +qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
> +return;
> +}
> +}
> +
> +static const MemoryRegionOps ls7a_reset_ops = {
> +.read = ls7a_reset_readw,
> +.write = ls7a_reset_writew,
> +.valid.min_access_size = 4,
> +.valid.max_access_size = 4,
> +.endianness = DEVICE_LITTLE_ENDIAN,
> +};
> +
> +const VMStateDescription vmstate_ls7a_pm = {
> +.name = "ls7a_pm",
> +.version_id = 1,
> +.minimum_version_id = 1,
> +.fields = (VMStateField[]) {
> +VMSTATE_UINT16(acpi_regs.pm1.evt.sts, LS7APMState),
> +VMSTATE_UINT16(acpi_regs.pm1.evt.en, LS7APMState),
> +VMSTATE_UINT16(acpi_regs.pm1.cnt.cnt, LS7APMState),
> +VMSTATE_TIMER_PTR(acpi_regs.tmr.timer, LS7APMState),
> +

Re: [PATCH 0/2] i386: fixup number of logical CPUs when host-cache-info=on

2022-05-25 Thread Igor Mammedov
On Tue, 24 May 2022 14:48:29 -0500
"Moger, Babu"  wrote:

> On 5/24/22 10:19, Igor Mammedov wrote:
> > On Tue, 24 May 2022 11:10:18 -0400
> > Igor Mammedov  wrote:
> >
> > CCing AMD folks as that might be of interest to them  
> 
> I am trying to recreate the bug on my AMD system here.. Seeing this message..
> 
> qemu-system-x86_64: -numa node,nodeid=0,memdev=ram-node0: memdev=ram-node0
> is ambiguous
> 
> Here is my command line..
> 
> #qemu-system-x86_64 -name rhel8 -m 4096 -hda vdisk.qcow2 -enable-kvm -net
> nic  -nographic -machine q35,accel=kvm -cpu
> host,host-cache-info=on,l3-cache=off -smp
> 20,sockets=2,dies=1,cores=10,threads=1 -numa
> node,nodeid=0,memdev=ram-node0 -numa node,nodeid=1,memdev=ram-node1 -numa
> cpu,socket-id=0,node-id=0 -numa cpu,socket-id=1,node-id=1
> 
> Am I missing something?
Yep, sorry I've omitted -object memory-backend-foo definitions for
ram-node0 and ram-node1

one can use any memory backend, it doesn't really matter in this case,
for example following should do:
  -object memory-backend-ram,id=ram-node0,size=2G \
  -object memory-backend-ram,id=ram-node1,size=2G 


> 
> 
> >  
> >> Igor Mammedov (2):
> >>   x86: cpu: make sure number of addressable IDs for processor cores
> >> meets the spec
> >>   x86: cpu: fixup number of addressable IDs for logical processors
> >> sharing cache
> >>
> >>  target/i386/cpu.c | 20 
> >>  1 file changed, 16 insertions(+), 4 deletions(-)
> >>  




Re: [PATCH 0/2] i386: fixup number of logical CPUs when host-cache-info=on

2022-05-24 Thread Igor Mammedov
On Tue, 24 May 2022 11:10:18 -0400
Igor Mammedov  wrote:

CCing AMD folks as that might be of interest to them

> Igor Mammedov (2):
>   x86: cpu: make sure number of addressable IDs for processor cores
> meets the spec
>   x86: cpu: fixup number of addressable IDs for logical processors
> sharing cache
> 
>  target/i386/cpu.c | 20 
>  1 file changed, 16 insertions(+), 4 deletions(-)
> 




[PATCH 0/2] i386: fixup number of logical CPUs when host-cache-info=on

2022-05-24 Thread Igor Mammedov


Igor Mammedov (2):
  x86: cpu: make sure number of addressable IDs for processor cores
meets the spec
  x86: cpu: fixup number of addressable IDs for logical processors
sharing cache

 target/i386/cpu.c | 20 
 1 file changed, 16 insertions(+), 4 deletions(-)

-- 
2.31.1




[PATCH 1/2] x86: cpu: make sure number of addressable IDs for processor cores meets the spec

2022-05-24 Thread Igor Mammedov
Accourding Intel's CPUID[EAX=04H] resulting bits 31 - 26 in EAX
should be:
"
  The nearest power-of-2 integer that is not smaller than (1 + EAX[31:26]) 
is the number of unique
Core_IDs reserved for addressing different processor cores in a physical 
package. Core ID is a subset of
bits of the initial APIC ID.
"

ensure that values stored in EAX[31-26] always meets this condition.

Signed-off-by: Igor Mammedov 
---
 target/i386/cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 35c3475e6c..bbe37dce2e 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -5279,7 +5279,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, 
uint32_t count,
 /* QEMU gives out its own APIC IDs, never pass down bits 31..26.  
*/
 *eax &= ~0xFC00;
 if ((*eax & 31) && cs->nr_cores > 1) {
-*eax |= (cs->nr_cores - 1) << 26;
+*eax |= (pow2ceil(cs->nr_cores) - 1) << 26;
 }
 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) {
 *eax = *ebx = *ecx = *edx = 0;
-- 
2.31.1




[PATCH 2/2] x86: cpu: fixup number of addressable IDs for logical processors sharing cache

2022-05-24 Thread Igor Mammedov
When QEMU is started with '-cpu host,host-cache-info=on', it will
passthrough host's number of logical processors sharing cache and
number of processor cores in the physical package. QEMU already
fixes up the later to correctly reflect number of configured cores
for VM, however number of logical processors sharing cache is still
comes from host CPU, which confuses guest started with:

   -machine q35,accel=kvm \
   -cpu host,host-cache-info=on,l3-cache=off \
   -smp 20,sockets=2,dies=1,cores=10,threads=1  \
   -numa node,nodeid=0,memdev=ram-node0 \
   -numa node,nodeid=1,memdev=ram-node1 \
   -numa cpu,socket-id=0,node-id=0 \
   -numa cpu,socket-id=1,node-id=1

on 2 socket Xeon 4210R host with 10 cores per socket
with CPUID[04H]:
  ...
--- cache 3 ---
  cache type   = unified cache (3)
  cache level  = 0x3 (3)
  self-initializing cache level= true
  fully associative cache  = false
  maximum IDs for CPUs sharing cache   = 0x1f (31)
  maximum IDs for cores in pkg = 0xf (15)
  ...
that doesn't match number of logical processors VM was
configured with and as result RHEL 9.0 guest complains:

   sched: CPU #10's llc-sibling CPU #0 is not on the same node! [node: 1 != 0]. 
Ignoring dependency.
   WARNING: CPU: 10 PID: 0 at arch/x86/kernel/smpboot.c:421 
topology_sane.isra.0+0x67/0x80
   ...
   Call Trace:
 set_cpu_sibling_map+0x176/0x590
 start_secondary+0x5b/0x150
 secondary_startup_64_no_verify+0xc2/0xcb

Fix it by capping max number of logical processors to vcpus/socket
as it was configured, which fixes the issue.

Signed-off-by: Igor Mammedov 
Fixes: https://bugzilla.redhat.com/show_bug.cgi?id=2088311
---
PS:
 capping to logical cpus/socket was arbitrarily chosen (maybe
 it should be per die or something else but don't see that in spec)
---
 target/i386/cpu.c | 20 
 1 file changed, 16 insertions(+), 4 deletions(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index bbe37dce2e..ffb274dcf6 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -5276,10 +5276,22 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, 
uint32_t count,
 /* cache info: needed for Core compatibility */
 if (cpu->cache_info_passthrough) {
 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx);
-/* QEMU gives out its own APIC IDs, never pass down bits 31..26.  
*/
-*eax &= ~0xFC00;
-if ((*eax & 31) && cs->nr_cores > 1) {
-*eax |= (pow2ceil(cs->nr_cores) - 1) << 26;
+/*
+ * QEMU has its own number of cores/logical cpus,
+ * set 24..14, 31..26 bit to configured values
+ */
+if (*eax & 31) {
+int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14);
+int vcpus_per_socket = env->nr_dies * cs->nr_cores *
+   cs->nr_threads;
+if (cs->nr_cores > 1) {
+*eax &= ~0xFC00;
+*eax |= (pow2ceil(cs->nr_cores) - 1) << 26;
+}
+if (host_vcpus_per_cache > vcpus_per_socket) {
+*eax &= ~0x3FFC000;
+*eax |= (pow2ceil(vcpus_per_socket) - 1) << 14;
+}
 }
 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) {
 *eax = *ebx = *ecx = *edx = 0;
-- 
2.31.1




Re: [PATCH 28/35] acpi: pvpanic-isa: use AcpiDevAmlIfClass:build_dev_aml to provide device's AML

2022-05-19 Thread Igor Mammedov
On Mon, 16 May 2022 16:46:29 -0400
"Michael S. Tsirkin"  wrote:

> On Mon, May 16, 2022 at 11:26:03AM -0400, Igor Mammedov wrote:
> > .. and clean up not longer needed conditionals in DSTD build code
> > pvpanic-isa AML will be fetched and included when ISA bridge will
> > build its own AML code (including attached devices).
> > 
> > Expected AML change:
> >the device under separate _SB.PCI0.ISA scope is moved directly
> >    under Device(ISA) node.
> > 
> > Signed-off-by: Igor Mammedov 
> > ---
> >  include/hw/misc/pvpanic.h |  9 -
> >  hw/i386/acpi-build.c  | 37 --
> >  hw/misc/pvpanic-isa.c | 42 +++
> >  3 files changed, 42 insertions(+), 46 deletions(-)
> > 
> > diff --git a/include/hw/misc/pvpanic.h b/include/hw/misc/pvpanic.h
> > index 7f16cc9b16..e520566ab0 100644
> > --- a/include/hw/misc/pvpanic.h
> > +++ b/include/hw/misc/pvpanic.h
> > @@ -33,13 +33,4 @@ struct PVPanicState {
> >  
> >  void pvpanic_setup_io(PVPanicState *s, DeviceState *dev, unsigned size);
> >  
> > -static inline uint16_t pvpanic_port(void)
> > -{
> > -Object *o = object_resolve_path_type("", TYPE_PVPANIC_ISA_DEVICE, 
> > NULL);
> > -if (!o) {
> > -return 0;
> > -}
> > -return object_property_get_uint(o, PVPANIC_IOPORT_PROP, NULL);
> > -}
> > -
> >  #endif
> > diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
> > index 517818cd9f..a42f41f373 100644
> > --- a/hw/i386/acpi-build.c
> > +++ b/hw/i386/acpi-build.c
> > @@ -30,7 +30,6 @@
> >  #include "hw/pci/pci.h"
> >  #include "hw/core/cpu.h"
> >  #include "target/i386/cpu.h"
> > -#include "hw/misc/pvpanic.h"
> >  #include "hw/timer/hpet.h"
> >  #include "hw/acpi/acpi-defs.h"
> >  #include "hw/acpi/acpi.h"
> > @@ -117,7 +116,6 @@ typedef struct AcpiMiscInfo {
> >  #endif
> >  const unsigned char *dsdt_code;
> >  unsigned dsdt_size;
> > -uint16_t pvpanic_port;
> >  } AcpiMiscInfo;
> >  
> >  typedef struct AcpiBuildPciBusHotplugState {
> > @@ -302,7 +300,6 @@ static void acpi_get_misc_info(AcpiMiscInfo *info)
> >  #ifdef CONFIG_TPM
> >  info->tpm_version = tpm_get_version(tpm_find());
> >  #endif
> > -info->pvpanic_port = pvpanic_port();
> >  }
> >  
> >  /*
> > @@ -1749,40 +1746,6 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
> >  aml_append(dsdt, scope);
> >  }
> >  
> > -if (misc->pvpanic_port) {
> > -scope = aml_scope("\\_SB.PCI0.ISA");
> > -
> > -dev = aml_device("PEVT");
> > -aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
> > -
> > -crs = aml_resource_template();
> > -aml_append(crs,
> > -aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 
> > 1, 1)
> > -);
> > -aml_append(dev, aml_name_decl("_CRS", crs));
> > -
> > -aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
> > -  aml_int(misc->pvpanic_port), 
> > 1));
> > -field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
> > -aml_append(field, aml_named_field("PEPT", 8));
> > -aml_append(dev, field);
> > -
> > -/* device present, functioning, decoding, shown in UI */
> > -aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
> > -
> > -method = aml_method("RDPT", 0, AML_NOTSERIALIZED);
> > -aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
> > -aml_append(method, aml_return(aml_local(0)));
> > -aml_append(dev, method);
> > -
> > -method = aml_method("WRPT", 1, AML_NOTSERIALIZED);
> > -aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
> > -aml_append(dev, method);
> > -
> > -aml_append(scope, dev);
> > -aml_append(dsdt, scope);
> > -}
> > -
> >  sb_scope = aml_scope("\\_SB");
> >  {
> >  Object *pci_host;
> > diff --git a/hw/misc/pvpanic-isa.c b/hw/misc/pvpanic-isa.c
> > index b84d4d458d..ccec50f61b 100644
> > --- a/hw/misc/pvpanic-isa.c
> > +++ b/hw/misc/pvpa

Re: [PATCH] hostmem: default the amount of prealloc-threads to smp-cpus

2022-05-19 Thread Igor Mammedov
On Wed, 18 May 2022 16:06:47 +0200
Paolo Bonzini  wrote:

> On 5/18/22 15:31, Daniel P. Berrangé wrote:
> > When picking defaults there is never a perfect answer, it
> > is more a matter of the least-worst option.
> > 
> > It is pretty clear that nthreads=1 is terrible for any
> > large VMs. Defaulting it to nvcpus made conceptual sense
> > as the user has implicit said that they expect the VM to
> > be able to consume nvcpus worth of CPU time on the host,
> > so we might as well consume that allotted resource.

that assumes that allocation threads a permitted to actually
use all resources and not limited to 1 pcpu only and then it
also assumes 'more vcpus' => 'large RAM'.

> I agree.  Yes, one could argue that the regression was on the libvirt 
> side, but it's easier to fix it in QEMU.

libvirt already provides means to set threads number,
what needs fixing is setting up reasonable value in config
which depends on how VM is configured and constrains mgmt/host
put on it.

> If we later add the ability to create a memory backend before machine 
> creation (for example with a QMP-only binary), then it's of course okay 
> for those backends to use only one thread and require a manual choice 
> for the # or preallocation threads.

What I'm vehemently against is putting back direct machine
references into backend code. I'm fine with 'prealloc-threads'
property set from machine code (whether it's compat property or
some sugar_prop() crutch in vl.c to appease CLI users).

> 
> Paolo
> 




Re: [PATCH 31/35] acpi: pc/q35: tpm-tis: fix TPM device scope

2022-05-19 Thread Igor Mammedov
On Wed, 18 May 2022 14:33:12 +0530
Ani Sinha  wrote:

> On Mon, May 16, 2022 at 8:57 PM Igor Mammedov  wrote:
> >
> > tpm-tis, is not a PCI device but ISA one, move it
> > under ISA scope to fix incorrect placement.  
> 
> This description is a little misleading. What we fix here is for
> TPM-tis 2.0 only. TPM 1.2 was already previously under ISA scope.

I'll fix it up on respin

> >
> > Fixes: 24cf5413aa0 (acpi: Make TPM 2.0 with TIS available as MSFT0101)
> > Signed-off-by: Igor Mammedov   
> 
> modulo that above comment,
> Reviewed-by: Ani Sinha 
> 
> > ---
> >  hw/i386/acpi-build.c | 3 +--
> >  1 file changed, 1 insertion(+), 2 deletions(-)
> >
> > diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
> > index a42f41f373..85a7313cad 100644
> > --- a/hw/i386/acpi-build.c
> > +++ b/hw/i386/acpi-build.c
> > @@ -1764,15 +1764,14 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
> >
> >  #ifdef CONFIG_TPM
> >  if (TPM_IS_TIS_ISA(tpm)) {
> > +dev = aml_device("ISA.TPM");
> >  if (misc->tpm_version == TPM_VERSION_2_0) {
> > -dev = aml_device("TPM");
> >  aml_append(dev, aml_name_decl("_HID",
> >aml_string("MSFT0101")));
> >  aml_append(dev,
> > aml_name_decl("_STR",
> >   aml_string("TPM 2.0 
> > Device")));
> >  } else {
> > -dev = aml_device("ISA.TPM");
> >  aml_append(dev, aml_name_decl("_HID",
> >aml_eisaid("PNP0C31")));
> >  }
> > --
> > 2.31.1
> >  
> 




Re: [PATCH 01/35] acpi: add interface to build device specific AML

2022-05-19 Thread Igor Mammedov
On Wed, 18 May 2022 15:30:07 +0530
Ani Sinha  wrote:

> On Mon, May 16, 2022 at 8:56 PM Igor Mammedov  wrote:
> >
> > There is already ISADeviceClass::build_aml() callback which
> > builds device specific AML blob for some ISA devices.
> > To extend the same idea to other devices, add TYPE_ACPI_DEV_AML_IF
> > Interface that will provide a more generic callback which
> > will be used not only for ISA but other devices. It will
> > allow get rid of some data-mining and ad-hoc AML building,
> > by asking device(s) to generate its own AML blob like it's
> > done for ISA devices.
> >
> > Signed-off-by: Igor Mammedov 
> > ---
> >  include/hw/acpi/acpi_aml_interface.h | 40 
> >  hw/acpi/acpi_interface.c |  8 ++
> >  hw/acpi/meson.build  |  2 +-
> >  3 files changed, 49 insertions(+), 1 deletion(-)
> >  create mode 100644 include/hw/acpi/acpi_aml_interface.h
> >
> > diff --git a/include/hw/acpi/acpi_aml_interface.h 
> > b/include/hw/acpi/acpi_aml_interface.h
> > new file mode 100644
> > index 00..ab76f0e55d
> > --- /dev/null
> > +++ b/include/hw/acpi/acpi_aml_interface.h
> > @@ -0,0 +1,40 @@
> > +#ifndef ACPI_AML_INTERFACE_H
> > +#define ACPI_AML_INTERFACE_H
> > +
> > +#include "qom/object.h"
> > +#include "hw/acpi/aml-build.h"
> > +
> > +#define TYPE_ACPI_DEV_AML_IF "acpi-dev-aml-interface"
> > +typedef struct AcpiDevAmlIfClass AcpiDevAmlIfClass;
> > +DECLARE_CLASS_CHECKERS(AcpiDevAmlIfClass, ACPI_DEV_AML_IF, 
> > TYPE_ACPI_DEV_AML_IF)
> > +#define ACPI_DEV_AML_IF(obj) \
> > + INTERFACE_CHECK(AcpiDevAmlIf, (obj), TYPE_ACPI_DEV_AML_IF)
> > +
> > +typedef struct AcpiDevAmlIf AcpiDevAmlIf;  
> 
> I do not see where struct AcpiDevAmlIf is defined. I guess this is
> through the macro magic.

it's used for type checking only of opaque pointer
(Interfaces are not supposed to have any state)

> > +typedef void (*dev_aml_fn)(AcpiDevAmlIf *adev, Aml *scope);
> > +
> > +/**
> > + * AcpiDevAmlIfClass:
> > + *
> > + * build_dev_aml: adds device specific AML blob to provided scope
> > + *
> > + * Interface is designed for providing generic callback that builds device
> > + * specific AML blob.
> > + */
> > +struct AcpiDevAmlIfClass {
> > +/*  */
> > +InterfaceClass parent_class;
> > +
> > +/*  */
> > +dev_aml_fn build_dev_aml;
> > +};
> > +
> > +static inline void call_dev_aml_func(DeviceState *dev, Aml *scope)
> > +{
> > +if (object_dynamic_cast(OBJECT(dev), TYPE_ACPI_DEV_AML_IF)) {
> > +AcpiDevAmlIfClass *klass = ACPI_DEV_AML_IF_GET_CLASS(dev);
> > +klass->build_dev_aml(ACPI_DEV_AML_IF(dev), scope);
> > +}
> > +}
> > +
> > +#endif
> > diff --git a/hw/acpi/acpi_interface.c b/hw/acpi/acpi_interface.c
> > index 6583917b8e..c668d361f6 100644
> > --- a/hw/acpi/acpi_interface.c
> > +++ b/hw/acpi/acpi_interface.c
> > @@ -1,5 +1,6 @@
> >  #include "qemu/osdep.h"
> >  #include "hw/acpi/acpi_dev_interface.h"
> > +#include "hw/acpi/acpi_aml_interface.h"
> >  #include "qemu/module.h"
> >
> >  void acpi_send_event(DeviceState *dev, AcpiEventStatusBits event)
> > @@ -18,8 +19,15 @@ static void register_types(void)
> >  .parent= TYPE_INTERFACE,
> >  .class_size = sizeof(AcpiDeviceIfClass),
> >  };
> > +static const TypeInfo acpi_dev_aml_if_info = {
> > +.name  = TYPE_ACPI_DEV_AML_IF,
> > +.parent= TYPE_INTERFACE,
> > +.class_size = sizeof(AcpiDevAmlIfClass),
> > +};
> > +
> >
> >  type_register_static(_dev_if_info);
> > +type_register_static(_dev_aml_if_info);
> >  }
> >
> >  type_init(register_types)
> > diff --git a/hw/acpi/meson.build b/hw/acpi/meson.build
> > index 8bea2e6933..9504f5ce09 100644
> > --- a/hw/acpi/meson.build
> > +++ b/hw/acpi/meson.build
> > @@ -28,7 +28,7 @@ acpi_ss.add(when: 'CONFIG_PC', if_false: 
> > files('acpi-x86-stub.c'))
> >  if have_tpm
> >acpi_ss.add(files('tpm.c'))
> >  endif
> > -softmmu_ss.add(when: 'CONFIG_ACPI', if_false: files('acpi-stub.c', 
> > 'aml-build-stub.c', 'ghes-stub.c'))
> > +softmmu_ss.add(when: 'CONFIG_ACPI', if_false: files('acpi-stub.c', 
> > 'aml-build-stub.c', 'ghes-stub.c', 'acpi_interface.c'))  
> 
> This is wrong. It should be the stub file not the real thing.

I can put type definition into acpi-stub.c, but will be exact duplicate
(i.e. you can't stub QOM type definition), hence acpi_interface.c (which is
mostly QOM type definitions) is being included in non acpi build to avoid
duplication.

> 
> >  softmmu_ss.add_all(when: 'CONFIG_ACPI', if_true: acpi_ss)
> >  softmmu_ss.add(when: 'CONFIG_ALL', if_true: files('acpi-stub.c', 
> > 'aml-build-stub.c',
> >'acpi-x86-stub.c', 
> > 'ipmi-stub.c', 'ghes-stub.c',
> > --
> > 2.31.1
> >  
> 




Re: [PATCH] acpi/erst: fix fallthrough code upon validation failure

2022-05-19 Thread Igor Mammedov
On Fri, 13 May 2022 19:40:05 +0530
Ani Sinha  wrote:

> At any step when any validation fail in check_erst_backend_storage(), there is
> no need to continue further through other validation checks. Further, by
> continuing even when record_size is 0, we run the risk of triggering a divide
> by zero error if we continued with other validation checks. Hence, we should
> simply return from this function upon validation failure.
> 
> CC: Peter Maydell 
> CC: Eric DeVolder 
> Signed-off-by: Ani Sinha 

Reviewed-by: Igor Mammedov 

> ---
>  hw/acpi/erst.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/hw/acpi/erst.c b/hw/acpi/erst.c
> index de509c2b48..df856b2669 100644
> --- a/hw/acpi/erst.c
> +++ b/hw/acpi/erst.c
> @@ -440,6 +440,7 @@ static void check_erst_backend_storage(ERSTDeviceState 
> *s, Error **errp)
>  (record_size >= 4096) /* PAGE_SIZE */
>  )) {
>  error_setg(errp, "ERST record_size %u is invalid", record_size);
> +return;
>  }
>  
>  /* Validity check header */
> @@ -450,6 +451,7 @@ static void check_erst_backend_storage(ERSTDeviceState 
> *s, Error **errp)
>  (le16_to_cpu(header->reserved) == 0)
>  )) {
>  error_setg(errp, "ERST backend storage header is invalid");
> +return;
>  }
>  
>  /* Check storage_size against record_size */
> @@ -457,6 +459,7 @@ static void check_erst_backend_storage(ERSTDeviceState 
> *s, Error **errp)
>   (record_size > s->storage_size)) {
>  error_setg(errp, "ACPI ERST requires storage size be multiple of "
>  "record size (%uKiB)", record_size);
> +return;
>  }
>  
>  /* Compute offset of first and last record storage slot */




Re: [PATCH] pc: q35: Bump max_cpus to 512

2022-05-19 Thread Igor Mammedov
On Thu, 19 May 2022 13:53:49 +0700
Suravee Suthikulpanit  wrote:

> On 5/13/22 6:23 PM, Michael S. Tsirkin wrote:
> > On Mon, May 09, 2022 at 09:12:49AM +0200, Igor Mammedov wrote:  
> >> On Wed, 4 May 2022 08:16:39 -0500
> >> Suravee Suthikulpanit  wrote:
> >>  
> >>> This is the maximum number of vCPU supported by
> >>> the AMD x2APIC virtualization.
> >>>
> >>> Signed-off-by: Suravee Suthikulpanit
> >>> ---
> >>>   hw/i386/pc_q35.c | 2 +-
> >>>   1 file changed, 1 insertion(+), 1 deletion(-)
> >>>
> >>> diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
> >>> index 302288342a..e82b1c690d 100644
> >>> --- a/hw/i386/pc_q35.c
> >>> +++ b/hw/i386/pc_q35.c
> >>> @@ -357,7 +357,7 @@ static void pc_q35_machine_options(MachineClass *m)
> >>>   machine_class_allow_dynamic_sysbus_dev(m, TYPE_INTEL_IOMMU_DEVICE);
> >>>   machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE);
> >>>   machine_class_allow_dynamic_sysbus_dev(m, TYPE_VMBUS_BRIDGE);
> >>> -m->max_cpus = 288;
> >>> +m->max_cpus = 512;  
> >> Maybe we should bump it to KVM VCPU maximum,
> >> and make sure we error out if asked for combination of
> >> hardware/irqchip is not usable.  
> >
> > So what happens if one does 710 and then tries to use AMD x2APIC?
> > We'd like that to error out, right?
> >   
> 
> Since the AMD SVM x2AVIC can support only upto 512 vCPUs,
> KVM would return error when QEMU tries to create more than 512 vcpus
> in the following call-path:
> 
>kvm_vm_ioctl_create_vcpu
>  kvm_arch_vcpu_create
>svm_vcpu_create
>  avic_init_vcpu

what is actual error message that end user will get from that failure?

 
> Also, I tried to find a way to get the KVM VCPU max value via 
> KVM_CAP_MAX_VCPUS ioctl,
> but the accel/kvm/kvm-all.c:kvm_init() is called later than 
> hw/core/machine-smp.c:
> machine_parse_smp_config(), where it checks the specified QEMU -smp option.
> 
> So, if there is no objection, I will send out a patch to change m->max_cpus = 
> 1024
> to match current KVM limit.
> 
> Best Regards,
> Suravee
> 




Re: [PATCH 1/2] acpi/nvdimm: Create _LS{I,R,W} method for NVDIMM device

2022-05-19 Thread Igor Mammedov
On Wed, 18 May 2022 08:20:56 +0800
Robert Hoo  wrote:

> On Fri, 2022-05-06 at 11:23 +0200, Igor Mammedov wrote:
> >   
> > > 
> > > No, sorry, I didn't explain it clear.
> > > No extra interface/ABI but these 3 must _LS{I,R,W} nvdimm-sub-
> > > device
> > > methods. Of course, I'm going to extract 'SystemIO' and
> > > 'SystemMemory'
> > > operation regions out of NACL to be globally available.
> > > 
> > > The buffer (BUFF in above patch) will be gone. It is added by my
> > > this
> > > patch, its mere use is to covert param of _LS{I,R,W} into those of
> > > NACL. If I implemented each _LS{I,R,W} on their own, rather than
> > > wrap
> > > the multi-purpose NACL, no buffer needed, at least I now assume so.
> > > And, why declare the 4K buffer global to sub-nvdimm? I now recall
> > > that
> > > it is because if not each sub-nvdimm device would contain a 4K
> > > buff,
> > > which will make this SSDT enormously large.  
> > 
> > ok, lets see how it will look like when you are done.  
> 
> In ASL, can we define package with Arg in? e.g.
> 
> Name (PKG1, Package ()
> {
> Arg0,
> Arg1,
> Arg2
> })

Looking at the spec it doesn't seem to be a valid construct.
see "DefPackage :=" and "PackageElement :=" definitions.

However you can try to play with RefOf to turn ArgX into
reference (mind 'read' rules fro ArgTerm).

> But it cannot pass compilation. Any approach to achieve this? if so, we
> can still use simpler wrap scheme like v1 and save the 4K buffer.



> >   
> > > > 
> > > > So unless we have to add new host/guest ABI, I'd prefer reusing
> > > > existing one and complicate only new _LS{I,R,W} AML without
> > > > touching NACL or host side.
> > > 
> > > As mentioned above, I assume no new host/guest ABI, just extract
> > > 'SystemIO' and 'SystemMemory' operation regions to a higher level
> > > scope.  
> > > >
> 




Re: [PATCH 28/35] acpi: pvpanic-isa: use AcpiDevAmlIfClass:build_dev_aml to provide device's AML

2022-05-19 Thread Igor Mammedov
On Wed, 18 May 2022 12:29:25 -0400
"Michael S. Tsirkin"  wrote:

> On Tue, May 17, 2022 at 10:13:51AM +0200, Gerd Hoffmann wrote:
> > That problem isn't new and we already have a bunch of aml_* stubs
> > because of that.  I expect it'll work just fine, at worst we'll
> > have to add a stub or two in case some calls are not covered yet.  
> 
> Right but adding these stubs is a bother, we keep missing some.
> If possible I'd like the solution to be cleaner than the status quo.
> Is adding a wrapper instead of setting a method directly such
> a big problem really?

Stubs are the bother but not much compared to alternatives.
I can't recall missing stubs recently (it's hard to miss them
as it's build time failure that won't pass CI).

However wrapper would introduce ifdeffenry instead of a stub.
And my understanding was that it's not acceptable and stubs are
what consensus approach is/was to eliminate/minimize ifdefs
in the code.

Also adding wrapper won't help anything, we also need to
decouple AML code into separate source files to avoid
dependency on AML routines and that is a bigger crunch
that includes not only new source files but spreading
CONFIG_APCI all over the tree, so I'm not sure if end
result won't be worse compared to stubs. Stubs are not
the cleanest ways around the issue but they would be
simpler to maintain in the end.




Re: [PATCH] hostmem: default the amount of prealloc-threads to smp-cpus

2022-05-18 Thread Igor Mammedov
On Tue, 17 May 2022 20:46:50 +0200
Paolo Bonzini  wrote:

> On 5/17/22 14:38, dzej...@gmail.com wrote:
> > From: Jaroslav Jindrak 
> > 
> > Prior to the introduction of the prealloc-threads property, the amount
> > of threads used to preallocate memory was derived from the value of
> > smp-cpus passed to qemu, the amount of physical cpus of the host
> > and a hardcoded maximum value. When the prealloc-threads property
> > was introduced, it included a default of 1 in backends/hostmem.c and
> > a default of smp-cpus using the sugar API for the property itself. The
> > latter default is not used when the property is not specified on qemu's
> > command line, so guests that were not adjusted for this change suddenly
> > started to use the default of 1 thread to preallocate memory, which
> > resulted in observable slowdowns in guest boots for guests with large
> > memory (e.g. when using libvirt <8.2.0 or managing guests manually).
> > 
> > This commit restores the original behavior for these cases while not
> > impacting guests started with the prealloc-threads property in any way.
> > 
> > Fixes: 220c1fd864e9d ("hostmem: introduce "prealloc-threads" property")
> > Signed-off-by: Jaroslav Jindrak 
> > ---
> >   backends/hostmem.c | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/backends/hostmem.c b/backends/hostmem.c
> > index a7bae3d713..624bb7ecd3 100644
> > --- a/backends/hostmem.c
> > +++ b/backends/hostmem.c
> > @@ -274,7 +274,7 @@ static void host_memory_backend_init(Object *obj)
> >   backend->merge = machine_mem_merge(machine);
> >   backend->dump = machine_dump_guest_core(machine);
> >   backend->reserve = true;
> > -backend->prealloc_threads = 1;
> > +backend->prealloc_threads = machine->smp.cpus;
> >   }
> >   
> >   static void host_memory_backend_post_init(Object *obj)  
> 
> Queued, thanks.

could you drop this patch pls (there is an more acceptable alternative,
see my other replies in this thread if we decide to put management policy
decisions in QEMU code).

(well unless layer violation is acceptable practice now
and it's really discouraging to do cleanup work if gets discarded)

PS:
There is no good default in this case (whatever number is picked
it could be good or bad depending on usecase).

> Paolo
> 




Re: [PATCH] hostmem: default the amount of prealloc-threads to smp-cpus

2022-05-18 Thread Igor Mammedov
On Tue, 17 May 2022 17:33:54 +0100
Daniel P. Berrangé  wrote:

> On Tue, May 17, 2022 at 05:12:28PM +0200, Igor Mammedov wrote:
> > On Tue, 17 May 2022 14:38:58 +0200
> > dzej...@gmail.com wrote:
> >   
> > > From: Jaroslav Jindrak 
> > > 
> > > Prior to the introduction of the prealloc-threads property, the amount
> > > of threads used to preallocate memory was derived from the value of
> > > smp-cpus passed to qemu, the amount of physical cpus of the host
> > > and a hardcoded maximum value. When the prealloc-threads property
> > > was introduced, it included a default of 1 in backends/hostmem.c and
> > > a default of smp-cpus using the sugar API for the property itself. The
> > > latter default is not used when the property is not specified on qemu's
> > > command line, so guests that were not adjusted for this change suddenly
> > > started to use the default of 1 thread to preallocate memory, which
> > > resulted in observable slowdowns in guest boots for guests with large
> > > memory (e.g. when using libvirt <8.2.0 or managing guests manually).  
> > 
> > current behavior in QEMU is intentionally conservative. threads
> > number is subject to host configuration and limitations management
> > layer puts on it and it's not QEMU job to conjure magic numbers that
> > are host/workload depended.  
> 
> I think that's missing the point. QEMU *did* historically set the
> prealloc threads equal to num CPUs, so we have precedent here. The
> referenced commit lost that behaviour because it only wired up the
> defaults in one particular CLI scenario. That's a clear regression
> on QEMU's side.

commit preserved behavior with legacy options to reduce disturbance.
Considering that users will have update QEMU which most likely includes
newer libvirt as well which lets configure number of allocation threads [1].
Users should fix configuration rather then pulling back layer violation hacks
(precedent is not a good excuse wrt reluctance to adapt to new behavior)

1) https://libvirt.org/formatdomain.html#elementsMemoryAllocation

> 
> With regards,
> Daniel




Re: [PATCH 00/35] pc/q35: refactor ISA and SMBUS AML generation

2022-05-17 Thread Igor Mammedov
On Mon, 16 May 2022 16:47:20 -0400
"Michael S. Tsirkin"  wrote:

> On Mon, May 16, 2022 at 11:25:35AM -0400, Igor Mammedov wrote:
> > 
> > Series is excerpt form larger refactoring that does
> > the same for PCI devices, but it's too large at this
> > point, so I've split off a relatively self-contained
> > ISA/SMBUS patches into a smaller separate series, and
> > PCI refactoring will follow up on top of this series
> > using the same AcpiDevAmlIf interface.
> > 
> > Series consolidates and unifies how pc/q35 machine
> > generates AML for ISA and SMBUS devices. It adds
> > a new more generic interface 'AcpiDevAmlIf' that
> > replaces ISA specific ISADeviceClass::build_aml
> > hook and should allow to use the same approach
> > (i.e. ask a device to provide its own AML) but
> > not limited to ISA bus.
> > Series applies AcpiDevAmlIf interface to a few
> > ISA devices that were already using
> > ISADeviceClass::build_aml and to devices /tpm,
> > applesmc,pvpanic,ipmi/ that were generated in
> > custom way. The AML generation for the later
> > class is normalized to behave like any other
> > ISA device that were using ISADeviceClass::build_aml
> > and converted to interface 'AcpiDevAmlIf'.
> > It simplifies process of building DSDT and
> > eliminates custom probing/wiring for those devices
> > as AML for them is generated at the time ISA/SMBUS
> > is enumerated.
> > 
> > Changes to DSDT tables QEMU generates are mostly
> > contextual where devices scattered across DSDT
> > are consolidated under respective device that
> > hosts bus they are attached to.  
> 
> I like this. Have one further enhancement idea before
> applying this, sent on list.

I'd prefer to implement that enhancement on top of this
series (and may be on top of follow up PCI conversion)
if we have to do it (as the enhancement would be a bit
of off-topic churn, i.e. solving another issue that we
already have).

> > PS:
> >  + series adds several ACPI tests for devices
> >that were missing them.
> > 
> > Igor Mammedov (35):
> >   acpi: add interface to build device specific AML
> >   acpi: make isa_build_aml() support AcpiDevAmlIf interface
> >   acpi: fdc-isa: replace ISADeviceClass::build_aml with
> > AcpiDevAmlIfClass:build_dev_aml
> >   acpi: parallel port: replace ISADeviceClass::build_aml with
> > AcpiDevAmlIfClass:build_dev_aml
> >   acpi: serial-is: replace ISADeviceClass::build_aml with
> > AcpiDevAmlIfClass:build_dev_aml
> >   acpi: mc146818rtc: replace ISADeviceClass::build_aml with
> > AcpiDevAmlIfClass:build_dev_aml
> >   acpi: pckbd: replace ISADeviceClass::build_aml with
> > AcpiDevAmlIfClass:build_dev_aml
> >   isa-bus: drop no longer used ISADeviceClass::build_aml
> >   tests: acpi: add and whitelist DSDT.ipmismbus expected blob
> >   tests: acpi: q35: add test for smbus-ipmi device
> >   tests: acpi: update expected blob DSDT.ipmismbus
> >   tests: acpi: whitelist DSDT.ipmismbus expected blob
> >   ipmi: acpi: use relative path to resource source
> >   tests: acpi: update expected DSDT.ipmismbus blob
> >   acpi: ich9-smb: add support for AcpiDevAmlIf interface
> >   acpi: ipmi: use AcpiDevAmlIf interface to build IPMI device
> > descriptors
> >   q35: acpi: drop not needed PCMachineClass::do_not_add_smb_acpi
> >   tests: acpi: white-list to be re-factored pc/q35 DSDT
> >   acpi: pc: isa bridge: use AcpiDevAmlIf interface to build ISA device
> > descriptors
> >   acpi: q35: isa bridge: use AcpiDevAmlIf interface to build ISA device
> > descriptors
> >   tests: acpi: update expected blobs
> >   tests: acpi: add and white-list DSDT.applesmc expected blob
> >   tests: acpi: add applesmc testcase
> >   acpi: applesmc: use AcpiDevAmlIfClass:build_dev_aml to provide
> > device's AML
> >   tests: acpi: update expected blobs
> >   tests: acpi: white-lists expected DSDT.pvpanic-isa blob
> >   tests: acpi: add pvpanic-isa: testcase
> >   acpi: pvpanic-isa: use AcpiDevAmlIfClass:build_dev_aml to provide
> > device's AML
> >   tests: acpi: update expected DSDT.pvpanic-isa blob
> >   tests: acpi: white-list DSDT.tis.tpm2/DSDT.tis.tpm12 expected blobs
> >   acpi: pc/q35: tpm-tis: fix TPM device scope
> >   acpi: pc/q35: remove not needed 'if' condition on pci bus
> >   acpi: tpm-tis: use AcpiDevAmlIfClass:build_dev_aml to provide device's
> > AML
> >   tests: acpi: update expected DSDT.tis.tpm2/DSDT.tis.tpm12 blobs
> >   x86: acpi-build: do not include hw/isa/i

Re: [PATCH 28/35] acpi: pvpanic-isa: use AcpiDevAmlIfClass:build_dev_aml to provide device's AML

2022-05-17 Thread Igor Mammedov
On Mon, 16 May 2022 16:46:29 -0400
"Michael S. Tsirkin"  wrote:

> On Mon, May 16, 2022 at 11:26:03AM -0400, Igor Mammedov wrote:
> > .. and clean up not longer needed conditionals in DSTD build code
> > pvpanic-isa AML will be fetched and included when ISA bridge will
> > build its own AML code (including attached devices).
> > 
> > Expected AML change:
> >the device under separate _SB.PCI0.ISA scope is moved directly
> >    under Device(ISA) node.
> > 
> > Signed-off-by: Igor Mammedov 
> > ---
> >  include/hw/misc/pvpanic.h |  9 -
> >  hw/i386/acpi-build.c  | 37 --
> >  hw/misc/pvpanic-isa.c | 42 +++
> >  3 files changed, 42 insertions(+), 46 deletions(-)
> > 
> > diff --git a/include/hw/misc/pvpanic.h b/include/hw/misc/pvpanic.h
> > index 7f16cc9b16..e520566ab0 100644
> > --- a/include/hw/misc/pvpanic.h
> > +++ b/include/hw/misc/pvpanic.h
> > @@ -33,13 +33,4 @@ struct PVPanicState {
> >  
> >  void pvpanic_setup_io(PVPanicState *s, DeviceState *dev, unsigned size);
> >  
> > -static inline uint16_t pvpanic_port(void)
> > -{
> > -Object *o = object_resolve_path_type("", TYPE_PVPANIC_ISA_DEVICE, 
> > NULL);
> > -if (!o) {
> > -return 0;
> > -}
> > -return object_property_get_uint(o, PVPANIC_IOPORT_PROP, NULL);
> > -}
> > -
> >  #endif
> > diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
> > index 517818cd9f..a42f41f373 100644
> > --- a/hw/i386/acpi-build.c
> > +++ b/hw/i386/acpi-build.c
> > @@ -30,7 +30,6 @@
> >  #include "hw/pci/pci.h"
> >  #include "hw/core/cpu.h"
> >  #include "target/i386/cpu.h"
> > -#include "hw/misc/pvpanic.h"
> >  #include "hw/timer/hpet.h"
> >  #include "hw/acpi/acpi-defs.h"
> >  #include "hw/acpi/acpi.h"
> > @@ -117,7 +116,6 @@ typedef struct AcpiMiscInfo {
> >  #endif
> >  const unsigned char *dsdt_code;
> >  unsigned dsdt_size;
> > -uint16_t pvpanic_port;
> >  } AcpiMiscInfo;
> >  
> >  typedef struct AcpiBuildPciBusHotplugState {
> > @@ -302,7 +300,6 @@ static void acpi_get_misc_info(AcpiMiscInfo *info)
> >  #ifdef CONFIG_TPM
> >  info->tpm_version = tpm_get_version(tpm_find());
> >  #endif
> > -info->pvpanic_port = pvpanic_port();
> >  }
> >  
> >  /*
> > @@ -1749,40 +1746,6 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
> >  aml_append(dsdt, scope);
> >  }
> >  
> > -if (misc->pvpanic_port) {
> > -scope = aml_scope("\\_SB.PCI0.ISA");
> > -
> > -dev = aml_device("PEVT");
> > -aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
> > -
> > -crs = aml_resource_template();
> > -aml_append(crs,
> > -aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 
> > 1, 1)
> > -);
> > -aml_append(dev, aml_name_decl("_CRS", crs));
> > -
> > -aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
> > -  aml_int(misc->pvpanic_port), 
> > 1));
> > -field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
> > -aml_append(field, aml_named_field("PEPT", 8));
> > -aml_append(dev, field);
> > -
> > -/* device present, functioning, decoding, shown in UI */
> > -aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
> > -
> > -method = aml_method("RDPT", 0, AML_NOTSERIALIZED);
> > -aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
> > -aml_append(method, aml_return(aml_local(0)));
> > -aml_append(dev, method);
> > -
> > -method = aml_method("WRPT", 1, AML_NOTSERIALIZED);
> > -aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
> > -aml_append(dev, method);
> > -
> > -aml_append(scope, dev);
> > -aml_append(dsdt, scope);
> > -}
> > -
> >  sb_scope = aml_scope("\\_SB");
> >  {
> >  Object *pci_host;
> > diff --git a/hw/misc/pvpanic-isa.c b/hw/misc/pvpanic-isa.c
> > index b84d4d458d..ccec50f61b 100644
> > --- a/hw/misc/pvpanic-isa.c
> > +++ b/hw/misc/pvpa

Re: [PATCH] hostmem: default the amount of prealloc-threads to smp-cpus

2022-05-17 Thread Igor Mammedov
On Tue, 17 May 2022 14:38:58 +0200
dzej...@gmail.com wrote:

> From: Jaroslav Jindrak 
> 
> Prior to the introduction of the prealloc-threads property, the amount
> of threads used to preallocate memory was derived from the value of
> smp-cpus passed to qemu, the amount of physical cpus of the host
> and a hardcoded maximum value. When the prealloc-threads property
> was introduced, it included a default of 1 in backends/hostmem.c and
> a default of smp-cpus using the sugar API for the property itself. The
> latter default is not used when the property is not specified on qemu's
> command line, so guests that were not adjusted for this change suddenly
> started to use the default of 1 thread to preallocate memory, which
> resulted in observable slowdowns in guest boots for guests with large
> memory (e.g. when using libvirt <8.2.0 or managing guests manually).

current behavior in QEMU is intentionally conservative. threads
number is subject to host configuration and limitations management
layer puts on it and it's not QEMU job to conjure magic numbers that
are host/workload depended.
If user needs more prealloc threads they need to specify it explicitly
for each memory backend (i.e. convince management to do it or fix your
scripts to so).

CCing Michal, as he recently looked into similar topic.

To behave it the old way you need to use legacy -mem-prealloc option.


> This commit restores the original behavior for these cases while not
> impacting guests started with the prealloc-threads property in any way.
> 
> Fixes: 220c1fd864e9d ("hostmem: introduce "prealloc-threads" property")
> Signed-off-by: Jaroslav Jindrak 
> ---
>  backends/hostmem.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/backends/hostmem.c b/backends/hostmem.c
> index a7bae3d713..624bb7ecd3 100644
> --- a/backends/hostmem.c
> +++ b/backends/hostmem.c
> @@ -274,7 +274,7 @@ static void host_memory_backend_init(Object *obj)
>  backend->merge = machine_mem_merge(machine);
>  backend->dump = machine_dump_guest_core(machine);
>  backend->reserve = true;
> -backend->prealloc_threads = 1;
> +backend->prealloc_threads = machine->smp.cpus;
pls, do not add more dependencies to random external objects to memory backends.

If you have to do that, use machine compat properties instead, but then
the essence of the issue stays the same (user shall define optimal threads
number and provide it to qemu explicitly)

>  }
>  
>  static void host_memory_backend_post_init(Object *obj)




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