On Mon, Mar 6, 2023 at 7:26 PM LIU Zhiwei wrote:
>
>
> On 2023/3/5 17:42, Jim Shu wrote:
> > This patch also enables debugger to set current privilege mode to
> > VU/VS-mode.
> >
> > Extend previous commit 81d2929c41d32af138f3562f5a7b309f6eac7ca7 to
> >
Thanks for reviewing.
I'll fix this issue.
On Mon, Mar 6, 2023 at 7:26 PM LIU Zhiwei wrote:
>
>
> On 2023/3/5 17:42, Jim Shu wrote:
> > This patch also enables debugger to set current privilege mode to
> > VU/VS-mode.
> >
> > Extend previous commit 81d2929
This patch enables a debugger to read current virtualization mode via
virtual "virt" register. After it, we could get full current privilege
mode via both "priv" and "virt" register.
Extend previous commit ab9056ff9bdb3f95db6e7a666d10522d289f14ec to
support H-exte
This patch also enables debugger to set current privilege mode to
VU/VS-mode.
Extend previous commit 81d2929c41d32af138f3562f5a7b309f6eac7ca7 to
support H-extension.
Signed-off-by: Jim Shu
Reviewed-by: Frank Chang
---
target/riscv/gdbstub.c | 18 --
1 file changed, 16
If the number of interrupt is not multiple of 32, PLIC will have
out-of-bound access to source_priority array. Compute the number of
interrupt in the last word to avoid this out-of-bound access of array.
Signed-off-by: Jim Shu
---
hw/intc/sifive_plic.c | 12 +++-
1 file changed, 11
let tlb_fill() function also increments PMU counter when it is from
two-stage translation, so QEMU could also monitor these PMU events when
CPU runs in VS/VU mode (like running guest OS).
Signed-off-by: Jim Shu
---
target/riscv/cpu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion
Gentle ping.
It's a patch for fix and spec alignment of PLIC.
On Mon, Oct 3, 2022 at 12:14 PM Jim Shu wrote:
>
> This patchset fixes hard-coded maximum priority of interrupt priority
> register and also changes this register to WARL field to align the PLIC
> spec.
>
>
This patchset fixes hard-coded maximum priority of interrupt priority
register and also changes this register to WARL field to align the PLIC
spec.
Changelog:
v3:
* fix opposite of power-of-2 max priority checking expression.
v2:
* change interrupt priority register to WARL field.
Jim Shu
each bit of interrupt priority register to WARL field when the number of
supported priority is power-of-2.
[1]
https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc#interrupt-priorities
Signed-off-by: Jim Shu
---
hw/intc/sifive_plic.c | 21 +++--
1 file changed, 19
Property
in maximum priority level.
Signed-off-by: Emmanuel Blot
Signed-off-by: Jim Shu
Reviewed-by: Frank Chang
---
hw/intc/sifive_plic.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index af4ae3630e..f864efa761 100644
Hi Clément,
> > > @@ -180,7 +180,15 @@ static void sifive_plic_write(void *opaque, hwaddr
> > > addr, uint64_t value,
> > > if (addr_between(addr, plic->priority_base, plic->num_sources << 2))
> > > {
> > > uint32_t irq = ((addr - plic->priority_base) >> 2) + 1;
> > >
> > > -
hi Clément,
Thank you very much.
I'll fix it in the next version patch.
Thanks,
Jim Shu
On Fri, Sep 30, 2022 at 8:58 PM Clément Chigot wrote:
>
> Hi Jim,
>
> On Fri, Sep 30, 2022 at 2:32 PM Jim Shu wrote:
> >
> > PLIC spec [1] requires interrupt source priority regi
each bit of interrupt priority register to WARL field when the number of
supported priority is power-of-2.
[1]
https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc#interrupt-priorities
Signed-off-by: Jim Shu
---
hw/intc/sifive_plic.c | 21 +++--
1 file changed, 19
This patchset fixes hard-coded maximum priority of interrupt priority
register and also changes this register to WARL field to align the PLIC
spec.
Changelog:
v2:
* change interrupt priority register to WARL field.
Jim Shu (2):
hw/intc: sifive_plic: fix hard-coded max priority level
hw
Property
in maximum priority level.
Signed-off-by: Emmanuel Blot
Signed-off-by: Jim Shu
Reviewed-by: Frank Chang
---
hw/intc/sifive_plic.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index af4ae3630e..f864efa761 100644
;num_priorities + 1" should be power-of-2 and SW could
discover available bits of interrupt source priority.
I'll do this enhancement in the next version patch.
[1]
https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc#interrupt-priorities
Thanks,
Jim Shu
On Mon, Sep 26, 202
Hi Tyler,
Thanks for the explanation. I understand the issue here.
I think we should align the priority base in each RISC-V platform to
the same value (no matter 0x0 or 0x4) if they use PLIC in the same
way.
Thanks,
Jim Shu
On Tue, Sep 27, 2022 at 4:04 AM Tyler Ng wrote:
>
>
formula "irq = ((addr - plic->priority_base) >> 2) + 1" will
take offset 0x4 as IRQ source 1, which is correct.
Your fix will cause the bug in existing machines.
Thanks,
Jim Shu
On Tue, Sep 6, 2022 at 11:21 PM Tyler Ng wrote:
>
> Here's the patch SHA t
Property
in maximum priority level.
Signed-off-by: Emmanuel Blot
Signed-off-by: Jim Shu
Reviewed-by: Frank Chang
---
hw/intc/sifive_plic.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index af4ae3630e..f864efa761 100644
Reviewed-by: Jim Shu
On Fri, Aug 19, 2022 at 3:11 PM Tommy Wu wrote:
>
> Fix the type of parent_obj of SiFiveEState from 'SysBusDevice'
> to 'MachineState'. Because the parent of SiFiveEState is 'MachineState'.
>
> Signed-off-by: Tommy Wu
> ---
> include/hw/riscv/sifive
Hi Alistair,
Why do we want to support that? We can do either and we are
> implementing the much more usual scheme. I don't see a reason to
> bother implementing the other one. Is anyone ever going to use it?
>
Thanks for your response.
I got it.
Regards,
Jim Shu
in RISC-V priv spec,
so I think it's reasonable to implement them in QEMU. The only issue here is
to choose a proper CPU option name to turn on/off HW update of A/D bits.
Regards,
Jim Shu
On Mon, Jul 18, 2022 at 12:02 PM Anup Patel wrote:
> +Atish
>
> On Mon, Jul 18, 2022 at 9:23 A
spec v1.12:
"When a virtual page is accessed and the A bit is clear, or is written
and the D bit is clear, a page-fault exception (corresponding to the
original access type) is raised."
Signed-off-by: Jim Shu
Reviewed-by: Frank Chang
---
target/riscv/cpu.c| 2 ++
target/r
Tested-by: Jim Shu
On Fri, Mar 4, 2022 at 7:00 PM Damien Hedde
wrote:
>
>
>
> On 3/3/22 14:32, Philippe Mathieu-Daudé wrote:
> > On 23/2/22 10:12, Damien Hedde wrote:
> >> Hi Philippe,
> >>
> >> I suppose it is ok if I change your mail in the rev
Tested-by: Jim Shu
On Thu, Mar 3, 2022 at 10:46 PM Philippe Mathieu-Daudé <
philippe.mathieu.da...@gmail.com> wrote:
> On 23/2/22 10:07, Damien Hedde wrote:
> > Allow plugging any sysbus device on this machine (the sysbus
> > devices still need to be 'user-creatable')
Tested-by: Jim Shu
On Wed, Feb 23, 2022 at 5:14 PM Damien Hedde
wrote:
> This device can be used to create a memory wrapped into a
> sysbus device.
> This device has one property 'readonly' which allows
> to choose between a ram or a rom.
>
> The purpose for this device is to
Tested-by: Jim Shu
On Fri, Mar 4, 2022 at 11:23 PM Philippe Mathieu-Daudé <
philippe.mathieu.da...@gmail.com> wrote:
> On 23/2/22 10:07, Damien Hedde wrote:
> > The devices are:
> > + ibex-timer
> > + ibex-uart
> > + riscv.aclint.swi
> > + ris
Tested-by: Jim Shu
On Fri, Mar 4, 2022 at 12:36 AM Damien Hedde
wrote:
>
>
> On 3/3/22 15:41, Philippe Mathieu-Daudé wrote:
> > On 23/2/22 10:07, Damien Hedde wrote:
> >> Add the property to configure a the base address of the ram.
> >> The default value re
Tested-by: Jim Shu
On Wed, Feb 23, 2022 at 5:37 PM Damien Hedde
wrote:
> This command allows to map an mmio region of sysbus device onto
> the system memory. Its behavior mimics the sysbus_mmio_map()
> function apart from the automatic unmap (the C function unmaps
> the region if i
Tested-by: Jim Shu
On Wed, Feb 23, 2022 at 5:59 PM Damien Hedde
wrote:
> The none machine was using the parent state structure.
> We'll need a custom state to add a field in the following commit.
>
> Signed-off-by: Damien Hedde
> ---
> hw/core/n
Tested-by: Jim Shu
On Wed, Feb 23, 2022 at 5:18 PM Damien Hedde
wrote:
> rom_set_order_override() and rom_reset_order_override() were called
> in qemu_create_cli_devices() to set the rom_order_override value
> once and for all when creating the devices added on CLI.
>
>
Tested-by: Jim Shu
On Thu, May 19, 2022 at 11:36 PM Damien Hedde
wrote:
> phase_until() now supports the following transitions:
> + accel-created -> machine-initialized
> + machine-initialized -> machine-ready
>
> As a consequence we can now support the use of qmp_ex
Tested-by: Jim Shu
On Thu, May 19, 2022 at 11:41 PM Damien Hedde
wrote:
> phase_until() is implemented in vl.c and is meant to be used
> to make startup progress up to a specified phase being reached().
> At this point, no behavior change is introduced: phase_until()
> only suppo
Tested-by: Jim Shu
On Thu, May 19, 2022 at 11:37 PM Damien Hedde
wrote:
> Instead of checking the phase everytime, just store the result
> in a flag. We will use more of it in the following commit.
>
> Signed-off-by: Damien Hedde
> Reviewed-by: Philippe Mathieu-Daudé
> -
Tested-by: Jim Shu
On Thu, May 19, 2022 at 11:37 PM Damien Hedde
wrote:
> From: Mirela Grujic
>
> This commit allows to use the QMP command to add a cold-plugged
> device like we can do with the CLI option -device.
>
> Note: for device_add command in qdev.json adding th
Tested-by: Jim Shu
On Thu, May 19, 2022 at 11:41 PM Damien Hedde
wrote:
> phase_get() returns the current phase, we'll use it in next
> commit.
>
> Signed-off-by: Damien Hedde
> Reviewed-by: Philippe Mathieu-Daudé
> ---
> include/hw/qdev-core.h | 19
Hi all,
Thanks for the work!
I'm from SiFive and we are very interested in this feature.
QMP/QAPI configurable QEMU machine is a useful feature in our use case.
With this feature, we can both model our versatile FPGA-based platforms
more easily and model a new platform without modification of
.
Changelog:
v2:
* Fix high 32-bit write access of 64-bit RO registers
* Fix commit log
Jim Shu (2):
hw/dma: sifive_pdma: support high 32-bit access of 64-bit register
hw/dma: sifive_pdma: permit 4/8-byte access size of PDMA registers
hw/dma/sifive_pdma.c | 181
It's obvious that PDMA supports 64-bit access of 64-bit registers, and
in previous commit, we confirm that PDMA supports 32-bit access of
both 32/64-bit registers. Thus, we configure 32/64-bit memory access
of PDMA registers as valid in general.
Signed-off-by: Jim Shu
Reviewed-by: Frank Chang
2 80001000 0002
=> md.l 0x28000 1; md.l 0x280001000 1 <= Dump src/dst memory contents
280000000: 12345678 xV4.
280001000: 12345678 xV4.
Signed-off-by: Jim Shu
Reviewed
Hi Bin,
Thanks for the review.
I will fix the commit log and the behavior of writing high 32-bit of RO
registers in v2 patch.
Thanks,
Jim Shu
On Tue, Jan 4, 2022 at 10:55 AM Bin Meng wrote:
> Hi Jim,
>
> On Tue, Dec 28, 2021 at 8:53 AM Jim Shu wrote:
> >
> > Real PDM
It's obvious that PDMA support 64-bit access of 64-bit registers, and
in previous commit, we confirm that PDMA support 32-bit access of both
32/64-bit registers. Thus, we configure 32/64-bit memory access of
PDMA registers as valid in general.
Signed-off-by: Jim Shu
Reviewed-by: Frank Chang
2 80001000 0002
=> md.l 0x28000 1; md.l 0x280001000 1 <= Dump src/dst memory contents
280000000: 12345678 xV4.
280001000: 12345678 xV4.
Signed-off-by: Jim Shu
Reviewed-by: Frank Chang
---
hw/dma/sif
HiFive Unmatched PDMA supports high/low 32-bit access of 64-bit
register, but QEMU emulation support low part access now. Enhance QEMU
emulation to support high 32-bit access.
Also, permit 4/8-byte valid access in PDMA as we have verified 32/64-bit
accesses of PDMA registers are supported.
Jim
Currently, PMP permission checking of TLB page is bypassed if TLB hits
Fix it by propagating PMP permission to TLB page permission.
PMP permission checking also use MMU-style API to change TLB permission
and size.
Signed-off-by: Jim Shu
---
target/riscv/cpu_helper.c | 84
Currently, PMP permission checking of TLB page is bypassed if TLB hits
Fix it by propagating PMP permission to TLB page permission.
PMP permission checking also use MMU-style API to change TLB permission
and size.
Signed-off-by: Jim Shu
---
target/riscv/cpu_helper.c | 84
.
To fix this issue, this patch set addes the feature to propagate PMP
permission to the TLB page and flush TLB pages if PMP permission has
been changed.
The patch set is tested on Zephyr RTOS userspace testsuite on QEMU riscv32
virt machine.
Jim Shu (3):
target/riscv: propagate PMP permission
Like MMU translation, add qemu log of PMP permission checking for
debugging.
Signed-off-by: Jim Shu
---
target/riscv/cpu_helper.c | 12
1 file changed, 12 insertions(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index f6ac63bf0e..c1ecb8a710 100644
Like MMU translation, add qemu log of PMP permission checking for
debugging.
Signed-off-by: Jim Shu
---
target/riscv/cpu_helper.c | 12
1 file changed, 12 insertions(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index f6ac63bf0e..c1ecb8a710 100644
If PMP permission of any address has been changed by updating PMP entry,
flush all TLB pages to prevent from getting old permission.
Signed-off-by: Jim Shu
---
target/riscv/pmp.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index ebd874cde3
If PMP permission of any address has been changed by updating PMP entry,
flush all TLB pages to prevent from getting old permission.
Signed-off-by: Jim Shu
---
target/riscv/pmp.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index ebd874cde3
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