On Wed, 11 Oct 2023 at 07:28, Nicholas Piggin wrote:
>
> On Tue Oct 10, 2023 at 10:05 PM AEST, Joel Stanley wrote:
> > On Tue, 10 Oct 2023 at 18:24, Nicholas Piggin wrote:
> > >
> > > POWER10 is the latest IBM Power machine. Although it is not offered in
&g
On Fri, 6 Oct 2023 at 07:23, Glenn Miles wrote:
>
> Allow external devices to drive pca9552 input pins by adding
> input GPIO's to the model. This allows a device to connect
> its output GPIO's to the pca9552 input GPIO's.
>
> In order for an external device to set the state of a pca9552
> pin,
On Tue, 10 Oct 2023 at 18:25, Nicholas Piggin wrote:
>
> POWER10 is the latest pseries CPU.
>
> Signed-off-by: Nicholas Piggin
Reviewed-by: Joel Stanley
> ---
> hw/ppc/spapr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/ppc/spapr
; powernv10 at the moment.
>
> Signed-off-by: Nicholas Piggin
Reviewed-by: Joel Stanley
Do we need to update the docs?
We should consider updating the skiboot to the latest release too.
> ---
> hw/ppc/pnv.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
rn BookE images now.
>
> Signed-off-by: Nicholas Piggin
Reviewed-by: Joel Stanley
Should we get mpe to add a https://github.com/linuxppc/qemu-ci-images
for you to keep those kernel images? But perhaps you'd prefer to keep
them on gitlab. Just a suggestion.
> ---
> tests/avocado
Signed-off-by: Cédric Le Goater
Reviewed-by: Joel Stanley
messy.
> ---
> hw/i2c/aspeed_i2c.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
> index 7275d40749a9..1037c22b2f79 100644
> --- a/hw/i2c/aspeed_i2c.
On Fri, 22 Sept 2023 at 13:21, Cédric Le Goater wrote:
> > +t->start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
> > +return calculate_time(t, MAX(MAX(t->match[0], t->match[1]), 0));
>
> This MAX(MAX(x, y), 0) looks strange to me. Would you remember where it comes
> from ? Thanks,
That
noted that in this case, the ROM will not be installed and the
> initial boot sequence (U-Boot loading) will fetch instructions using
> SPI transactions which is significantly slower. That's exactly how HW
> operates though.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by:
On Thu, 31 Aug 2023 at 13:22, Cédric Le Goater wrote:
>
> On 8/31/23 15:00, Joel Stanley wrote:
> > On Thu, 31 Aug 2023 at 12:39, Cédric Le Goater wrote:
> >>
> >> When the -nodefaults option is set, flash devices should be created
> >> with :
> >>
the first foray for the aspeed machines into
nodefaults removing things that previously would have just worked. I
know we haven't had it in our recommended command lines for a long
time, so that's fine.
Reviewed-by: Joel Stanley
Should the content of your commit message go in the docs?
> ---
> hw
On Tue, 29 Aug 2023 at 14:45, Cédric Le Goater wrote:
>
> On 8/9/23 16:56, Frederic Barrat wrote:
> > Hello Joel,
> >
> > So we're re-using the same xscom ops as on P8. A quick look at the
> > definition of those 4 registers on P8 (0xb0020) and on P9/P10 (0x00090040)
> > seem to show they are
there any value in testing both the old and the new images?
Reviewed-by: Joel Stanley
>
> Signed-off-by: Cédric Le Goater
> ---
>
> Requires patches from Hang Yu [1]
>
> [1]
> https://lore.kernel.org/qemu-devel/20230812065230.8839-1-francis_...@stu.pku.edu.cn/
>
SoC due
> to tight integration of the FSI master IP with the OPB, mainly the
> existence of an MMIO-mapping of the CFAM address straight onto a
> sub-region of the OPB address space.
>
> Signed-off-by: Andrew Jeffery
> Signed-off-by: Cédric Le Goater
> Signed-off-by: Ni
M.
>
> Signed-off-by: Andrew Jeffery
> Signed-off-by: Cédric Le Goater
> Signed-off-by: Ninad Palsule
Reviewed-by: Joel Stanley
> ---
> hw/fsi/cfam.c | 1 +
> hw/fsi/fsi-master.c | 203
> hw/fsi/fsi.c
On Fri, 25 Aug 2023 at 20:31, Ninad Palsule wrote:
>
> This is a part of patchset where IBM's Flexible Service Interface is
> introduced.
>
> An APB-to-OPB bridge enabling access to the OPB from the ARM core in
> the AST2600. Hardware limitations prevent the OPB from being directly
> mapped into
On Fri, 25 Aug 2023 at 20:35, Ninad Palsule wrote:
>
> This patchset introduces IBM's Flexible Service Interface(FSI).
>
> Time for some fun with inter-processor buses. FSI allows a service
> processor access to the internal buses of a host POWER processor to
> perform configuration or debugging.
On Fri, 25 Aug 2023 at 20:31, Ninad Palsule wrote:
>
> This is a part of patchset where IBM's Flexible Service Interface is
> introduced.
>
> The LBUS is modelled to maintain the qdev bus hierarchy and to take
> advantage of the object model to automatically generate the CFAM
> configuration
Hi Ninad,
On Fri, 25 Aug 2023 at 20:51, Ninad Palsule wrote:
>
> Hello,
>
> Please review the patch-set.
>
> This is a first step towards introducing model for IBM's Flexible
> Service Interface. The full functionality will be implemented over the
> time.
You have a typo in the subject, I think
);
lpc->chip_id = gcid;
- lpc->mbase = (void *)addr;
+ lpc->xbase = dt_get_address(lpc_node, 0, NULL);
lpc->fw_idsel = 0xff;
lpc->fw_rdsz = 0xff;
lpc->node = lpc_node;
Signed-off-by: Joel Stanley
---
hw/ppc/pnv_lpc.c | 5 +
The P9 and P10 models re-used the xscom_regs memory region for the mmio
access, which is confusing.
Add a separate memory region in preparation for enabling both xscom and
mmio access.
Signed-off-by: Joel Stanley
---
include/hw/ppc/pnv_lpc.h | 3 ++-
hw/ppc/pnv.c | 4 ++--
hw/ppc
>From P9 on the LPC bus is memory mapped. However the xscom access still
is possible, so add it too.
Signed-off-by: Joel Stanley
---
include/hw/ppc/pnv_xscom.h | 6 ++
hw/ppc/pnv.c | 4
hw/ppc/pnv_lpc.c | 6 ++
3 files changed, 16 insertions(+)
diff --
not be applied.
Joel Stanley (3):
pnv/lpc: Place mmio regs in their own memory region
pnv/lpc: Hook up xscom region for P9/P10
HACK: pnv/lpc: Set up XSCOM dt for P9
include/hw/ppc/pnv_lpc.h | 3 ++-
include/hw/ppc/pnv_xscom.h | 6 ++
hw/ppc/pnv.c | 8 ++--
hw/ppc
Revert the changes in the recent "Fix linux-user host detection for
riscv64" patch as it broke ppc64le. Instead add riscv to the switch
statement that performs normalisation of the host cpu name.
Fixes: 89e5b7935e92 ("configure: Fix linux-user host detection for riscv64")
On Sat, 5 Aug 2023 at 18:02, Richard Henderson
wrote:
>
> Mirror the host_arch variable from meson.build, so that we
> probe for the correct linux-user/include/host/ directory.
This broke all of the linux-user targets for me on a ppc64le host.
None show up when running configure --help, and
On Thu, 3 Aug 2023 at 13:55, Helge Deller wrote:
> > 143551 brk(NULL) = 0x0009b000
> > 143551 brk(0x0009b8fc) = 0x0009b000
>
> I think the problem is the brk with 9b000 here.
> It's not 64k aligned (=pages size of your ppc64le).
>
> Please try with this patch on top of Richard's series:
>
> > @@
Hi Richard,
On Thu, 3 Aug 2023 at 01:53, Richard Henderson
wrote:
>
> Builds on Helge's v6, incorporating my feedback plus
> some other minor cleanup.
This succeeds for the armhf static binary on ppc64le host that was
previously segfaulting.
However, the arm static binary on ppc64le host now
On Tue, 1 Aug 2023 at 23:28, Helge Deller wrote:
>
> This patch series is a fix-up for some current problems
> regarding heap memory / brk handling in qemu which happens
> on some 32-bit platforms, e.g. problems loading static
> binaries.
>
> This series includes the 5 patches from Akihiko Odaki
On Mon, 31 Jul 2023 at 18:24, Helge Deller wrote:
> > I re-read the thread again. As it seems Joel already tried the latest
> > version from me? Sadly I can't test myself on ppc64le (static binary
> > needs klibc-PupSAGgtpafMlSLXOLgje1kXFo8.so in /usr/lib which I can't
> > install on a debian
ge Deller, have you seen it?
> ("linux-user: Fix and optimize target memory layout", a v5 already).
Applying this series fixes the qemu-arm running the static armhf
binary on my ppc64le host that I reported here[1].
Tested-by: Joel Stanley
The changes conflict with Helge's patches,
On Fri, 28 Jul 2023 at 18:58, Helge Deller wrote:
>
> While trying to fix a bug which prevents running a static
> armhf binary with linux-user, I noticed a whole bunch of
> memory layout issues on various platforms. Most noteably
> the free heap space was very limited in the current setup.
> A
On Sun, 30 Jul 2023 at 09:43, Nicholas Piggin wrote:
>
> On Wed Jul 26, 2023 at 4:35 PM AEST, Joel Stanley wrote:
> > On Wed, 12 Jul 2023 at 02:12, Nicholas Piggin wrote:
> > >
> > > On Tue Jul 11, 2023 at 9:03 PM AEST, Matheus Tavares Bernardino wrote:
&g
On Wed, 12 Jul 2023 at 02:12, Nicholas Piggin wrote:
>
> On Tue Jul 11, 2023 at 9:03 PM AEST, Matheus Tavares Bernardino wrote:
> > > Nicholas Piggin wrote:
> > >
> > > diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c
> > > index 6911b73c07..ce8b42eb15 100644
> > > --- a/gdbstub/gdbstub.c
> >
Linux sets these to control cache flush behaviour on Power9. Supervisor
and hypervisor are allowed to write, and reads are noops.
Add implementations to avoid noisy messages when booting Linux under the
pseries machine with guest_errors enabled.
Reviewed-by: Nicholas Piggin
Signed-off-by: Joel
On Sat, 8 Jul 2023 at 01:17, Nicholas Piggin wrote:
> > --- a/include/hw/ppc/pnv_xscom.h
> > +++ b/include/hw/ppc/pnv_xscom.h
> > @@ -127,6 +127,17 @@ struct PnvXScomInterfaceClass {
> > #define PNV10_XSCOM_EC(proc)\
> > ((0x2 << 16) | ((1 << (3 - (proc))) << 12))
> >
>
On Fri, 7 Jul 2023 at 07:30, Cédric Le Goater wrote:
>
> On 7/7/23 09:12, Joel Stanley wrote:
> > The Quad Management Engine (QME) manages power related settings for its
> > quad. The xscom region is separate from the quad xscoms, therefore a new
> > region is added. Th
) and special
wakeup (SPWU) registers. This quietens some sxcom errors when skiboot
boots on p10.
Power9 does not have a QME.
Signed-off-by: Joel Stanley
---
v2:
Clean up extra whitespace
Make realize quad specific so power9 doesn't end up with the qme region
---
include/hw/ppc/pnv_core.h | 4
On Fri, 7 Jul 2023 at 05:04, Cédric Le Goater wrote:
> pnv_quad_realize realizes power9 and power10 quad objects but ...
>
> > }
> >
> > static Property pnv_quad_properties[] = {
> > @@ -528,6 +581,9 @@ static void pnv_quad_power10_class_init(ObjectClass
> > *oc, void *data)
> >
> >
) and special
wakeup (SPWU) registers. This quietens some sxcom errors when skiboot
boots on p10.
Signed-off-by: Joel Stanley
---
include/hw/ppc/pnv_core.h | 4 +++
include/hw/ppc/pnv_xscom.h | 11
hw/ppc/pnv.c | 5
hw/ppc/pnv_core.c | 56
Add the function name so there's an indication as to where the message
is coming from. Change all prints to use the offset instead of the
address.
Signed-off-by: Joel Stanley
---
Happy to use the address instead of the offset (or print both), but I
like the idea of being consistent.
---
hw/ppc
On Wed, 5 Jul 2023 at 10:02, Cédric Le Goater wrote:
>
> On 7/5/23 04:05, Joel Stanley wrote:
> > On Wed, 5 Jul 2023 at 01:27, Nicholas Piggin wrote:
> >>
> >> The P10 core xscom memory regions overlap because the size is wrong.
> >> The P10 core+L2 x
0108108000-00010810 (prio 0, i/o): xscom-core.7: 0x8000
00010811-000108117fff (prio 0, i/o): xscom-core.6: 0x8000
00010812-000108127fff (prio 0, i/o): xscom-core.5: 0x8000
00010814-000108147fff (prio 0, i/o): xscom-core.4: 0x8000
Reviewed-by
Make the existing pnv_quad_xscom_read/write be P9 specific, in
preparation for a different P10 callback.
Reviewed-by: Cédric Le Goater
Signed-off-by: Joel Stanley
---
v2: Add scom region size to class
---
include/hw/ppc/pnv_core.h | 13 -
hw/ppc/pnv.c | 11
Rename the functions to include P9 in the name in preparation for adding
P10 versions.
Correct the unimp read message while we're changing the function.
Reviewed-by: Cédric Le Goater
Signed-off-by: Joel Stanley
---
v2: Fix unimp print, and grammar in the commit message
---
hw/ppc/pnv_core.c
the s/write/read/ mistakes, and is
checkpatch clean.
v1: https://lore.kernel.org/qemu-devel/20230630035547.80329-1-j...@jms.id.au/
Joel Stanley (5):
ppc/pnv: quad xscom callbacks are P9 specific
ppc/pnv: Subclass quad xscom callbacks
ppc/pnv: Add P10 quad xscom model
ppc/pnv: Add P10 core
Like the quad xscoms, add a core model for P10 to allow future
differentiation from P9.
Signed-off-by: Joel Stanley
---
hw/ppc/pnv_core.c | 44 ++--
1 file changed, 42 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index
Firmware now warns if booting in LPAR per core mode (PPC bit 62). So
this warning doesn't trigger, report the core thread state is 0.
Reviewed-by: Cédric Le Goater
Signed-off-by: Joel Stanley
---
hw/ppc/pnv_core.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/hw/ppc
(prio 0, i/o): xscom-core.0
Signed-off-by: Joel Stanley
---
v2: Fix unimp read message
Wrap lines at 80 col
Set size
---
include/hw/ppc/pnv_xscom.h | 2 +-
hw/ppc/pnv.c | 2 +-
hw/ppc/pnv_core.c | 54 ++
3 files changed, 56
owernv
> machine, it is preferable to emulate OPAL LPAR-per-thread, so to
> account for this difference a flag is added and SPRs may become either
> per-thread, per-core shared, or per-LPAR shared. Per-LPAR registers
> become either per-thread or per-core shared depending on the mode.
>
&g
On Fri, 30 Jun 2023 at 07:30, Frederic Barrat wrote:
>
>
>
> On 30/06/2023 05:55, Joel Stanley wrote:
> > diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
> > index b9a57463aec4..7fff2fd9e298 100644
> > --- a/hw/ppc/pnv_core.c
> > +++ b/hw/p
Make the existing pnv_quad_xscom_read/write be P9 specific, in
preparation for a different P10 callback.
Signed-off-by: Joel Stanley
---
include/hw/ppc/pnv_core.h | 12 +++-
hw/ppc/pnv.c | 11 +++
hw/ppc/pnv_core.c | 36
instead wired so one is created for
each chiplet? Or should we report the value for all possible cores, like
the P9 code does for P9X_EX_NCU_SPEC_BAR?
switch (offset) {
case P9X_EX_NCU_SPEC_BAR:
case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */
Joel Stanley (4):
ppc/pnv: quad xscom
Firmware now warns if booting in LPAR per core mode (PPC bit 62). So
this warning doesn't trigger report the core thread state is 0.
Signed-off-by: Joel Stanley
---
hw/ppc/pnv_core.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index
Rename the to include P9 in the name in preparation for adding P10
versions.
Signed-off-by: Joel Stanley
---
hw/ppc/pnv_core.c | 17 +
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index 0bc3ad41c81c..0b1c3cccfebc 100644
Add a PnvQuad class for the P10 powernv machine. No xscoms are
implemented yet, but this allows them to be added.
Signed-off-by: Joel Stanley
---
hw/ppc/pnv.c | 2 +-
hw/ppc/pnv_core.c | 53 +++
2 files changed, 54 insertions(+), 1 deletion
f-by: Nicholas Piggin
Reviewed-by: Joel Stanley
> ---
> This fixes the failed MMIO error in the Linux sungem driver reset
> when it clears the WOL CSR.
>
> Thanks,
> Nick
>
> hw/net/sungem.c | 52 +
> hw/net/trace-events | 2
The phb error macros add a newline for you, so remove the second one to
avoid double whitespace.
Signed-off-by: Joel Stanley
---
hw/pci-host/pnv_phb4.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
index
On Thu, 15 Jun 2023 at 03:02, Nicholas Piggin wrote:
>
> On Wed Jun 14, 2023 at 11:09 AM AEST, Joel Stanley wrote:
> > On Thu, 8 Jun 2023 at 07:58, Nicholas Piggin wrote:
> > >
> > > Posting again, a couple of patches were merged and accounted for review
> >
heir investigation into
> https://github.com/zephyrproject-rtos/zephyr/issues/57512
Did you get an image to test with?
Reviewed-by: Joel Stanley
>
> hw/timer/nrf51_timer.c | 7 ++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/hw/timer/nrf51_timer.
e of this property is for the Cortex A7 of the
> Aspeed AST2600 SoC.
>
> Signed-off-by: Cédric Le Goater
You saw a crash with a buildroot image without this change, as I recall?
The logic is a bit hard to follow but it is good to see a fix.
Reviewed-by: Joel Stanley
> ---
> target/a
3 (mapped on
> /dev/ttyS2 under Linux) instead of the default UART5, one would use :
>
> -M ast2500-evb,bmc-console=uart3
>
> Cc: Abhishek Singh Dagur
> Signed-off-by: Cédric Le Goater
Reviewed-by: Joel Stanley
> ---
> docs/system/arm/aspeed.rst | 11 +++
On Wed, 7 Jun 2023 at 04:40, Cédric Le Goater wrote:
>
> and get rid of an unnecessary drive_get(IF_MTD) call.
>
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Cédric Le Goater
Reviewed-by: Joel Stanley
> ---
> hw/arm/aspeed.c | 8 +---
> 1 file cha
édric Le Goater
One suggestion below after reading patch 10.
Reviewed-by: Joel Stanley
> ---
> include/hw/block/flash.h | 4
> hw/block/m25p80.c| 6 ++
> 2 files changed, 10 insertions(+)
>
> diff --git a/include/hw/block/flash.h b/include/hw/block/flash.h
&g
ppe Mathieu-Daudé
> Signed-off-by: Cédric Le Goater
One small suggestion below that we could do as a follow up.
Reviewed-by: Joel Stanley
> ---
> hw/arm/stellaris.c | 4 +++-
> hw/arm/xilinx_zynq.c| 1 +
> hw/arm/xlnx-versal-virt.c | 1
used by the machine. Fix
> that and wire the CS lines of all available devices when the SSI bus
> is reset.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Joel Stanley
> ---
> hw/arm/aspeed.c | 5 +
> hw/ssi/aspeed_smc.c | 8
> 2 files changed, 9 inse
-by: Cédric Le Goater
Reviewed-by: Joel Stanley
> ---
> include/hw/ssi/ssi.h | 2 ++
> hw/ssi/ssi.c | 15 +++
> 2 files changed, 17 insertions(+)
>
> diff --git a/include/hw/ssi/ssi.h b/include/hw/ssi/ssi.h
> index 9e0706a5248c..01662521b09a 100644
>
On Wed, 7 Jun 2023 at 04:40, Cédric Le Goater wrote:
>
> Boards will use this new property to identify the device CS line and
> wire the SPI controllers accordingly.
"addr" and not "cs" or even "chip-select"?
Reviewed-by: Joel Stanley
>
> Cc: Alis
Delevoryas
> Signed-off-by: Cédric Le Goater
Reviewed-by: Joel Stanley
> ---
> hw/arm/fby35.c | 29 +++--
> 1 file changed, 15 insertions(+), 14 deletions(-)
>
> diff --git a/hw/arm/fby35.c b/hw/arm/fby35.c
> index f4600c290b62..f2ff6c1abfd9 100644
0-07ff
Reviewed-by: Joel Stanley
>
> Reviewed-by: Francisco Iglesias
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Cédric Le Goater
> ---
> hw/arm/aspeed.c | 12 ++--
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git
t; This avoids QEMU to coredump when running the "hash test" command
> under Zephyr.
Reviewed-by: Joel Stanley
Was never a fan of using this magic :)
>
> Cc: Steven Lee
> Cc: Joel Stanley
> Cc: qemu-sta...@nongnu.org
> Fixes: c5475b3f9a ("hw: Model ASPEED'
On Tue, 6 Jun 2023 at 19:28, Thomas Huth wrote:
>
> The ppc64 tuxrun tests are currently failing if "slirp" has been
> disabled in the binary since they are using "-netdev user" now.
> We have to skip the test if this network backend is missing.
Do the boot tests require networking? I doubt they
On Wed, 24 May 2023 at 06:38, Cédric Le Goater wrote:
>
> On 5/23/23 23:45, Ninad Palsule wrote:
> > The current modeling of Rainier machine creates zero filled VPDs(EEPROMs).
> > This makes some services and applications unhappy and causing them to fail.
> > Hence this drop adds some fabricated
On Wed, 5 Apr 2023 at 02:07, Jeremy Kerr wrote:
>
> Hi Joe,
>
> > > > Jeremy, how different is it ? Could we introduce properties or sub
> > > > classes, to support both.
> > >
> > > The differences (at least from the view of the current Linux driver
> > > implementation) are very minor; unless
On Tue, 28 Mar 2023 at 22:59, Richard Henderson
wrote:
>
> The following changes since commit d37158bb2425e7ebffb167d611be01f1e9e6c86f:
>
> Update version for v8.0.0-rc2 release (2023-03-28 20:43:21 +0100)
>
> are available in the Git repository at:
>
> https://gitlab.com/rth7680/qemu.git
, but if the test errors before connection then the swtpm process
will still be around.
Signed-off-by: Joel Stanley
---
tests/avocado/machine_aspeed.py | 42 +++--
1 file changed, 40 insertions(+), 2 deletions(-)
diff --git a/tests/avocado/machine_aspeed.py b/tests
On Mon, 27 Mar 2023 at 11:11, Stefan Berger wrote:
>
>
>
> On 3/26/23 21:05, Joel Stanley wrote:
> > Hi Ninad,
> >
> > On Sun, 26 Mar 2023 at 22:44, Ninad Palsule wrote:
> >>
> >> Hello,
> >>
> >> I have incorporated review com
On Mon, 27 Mar 2023 at 08:21, Cédric Le Goater wrote:
>
> >>> However on a clean boot into the TPM, the u-boot tpm commands fail:
> >>>
> >>> ast# tpm info
> >>> tpm@2e v2.0: VendorID 0x1014, DeviceID 0x0001, RevisionID 0x01 [closed]
> >>> ast# tpINTERRUPT>
> >>> ast# tpm init
> >>> ast# tpm info
On Mon, 27 Mar 2023 at 03:52, Ninad Palsule wrote:
>
> Hi Joel,
>
> On 3/26/23 8:05 PM, Joel Stanley wrote:
> > Hi Ninad,
> >
> > On Sun, 26 Mar 2023 at 22:44, Ninad Palsule wrote:
> >> Hello,
> >>
> >> I have incorporated review comm
On Sun, 26 Mar 2023 at 22:44, Ninad Palsule wrote:
>
> This is a documentation change for I2C TPM device support.
>
> Qemu already supports devices attached to ISA and sysbus.
> This drop adds support for the I2C bus attached TPM devices.
>
> Signed-off-by: Ninad Palsule
>
> ---
> V2:
>
>
Hi Ninad,
On Sun, 26 Mar 2023 at 22:44, Ninad Palsule wrote:
>
> Hello,
>
> I have incorporated review comments from Stefan. Please review.
>
> This drop adds support for the TPM devices attached to the I2C bus. It
> only supports the TPM2 protocol. You need to run it with the external
> TPM
goes at 0x,
> which violated that last host page problem above.
>
> The issue is resolved in patch 4, but the rest clean up other interfaces
> with the same issue. I'm not touching any interfaces that use start+len
> instead of start+end.
Thanks for looking at this Richard. I gave it a spin on a ppc64le host
and it resolved the assert.
Tested-by: Joel Stanley
Cheers,
Joel
On Mon, 6 Feb 2023 at 19:51, Titus Rwantare wrote:
>
> This is a simple i2c device that allows i2c capable devices to have
> GPIOs.
Nice.
In Linux this is supported by a driver called pca953x. Would it make
sense to name your model similarly (both the file and the prefixes you
use)?
If we do
n the calculation.
Does this affect the error counters observed under Linux?
>
> Signed-off-by: Stephen Longfield
> Reviewed-by: Hao Wu
> Message-Id: <20221220221437.3303721-1-slongfi...@google.com>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Joel Stanley
> ---
> hw
On Thu, 19 Jan 2023 at 12:37, Cédric Le Goater wrote:
>
> AST2600 Aspeed machines have an home made boot loader for secondaries.
> To improve support, export the internal ARM boot loader and use it
> instead.
I didn't quite follow why we're doing this. Is it just a cleanup?
>
> Signed-off-by:
rovided by OpenBMC for better support.
> - defconfigs includes more target tools for dev.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Joel Stanley
> ---
> tests/avocado/machine_aspeed.py | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git
On Thu, 19 Jan 2023 at 12:39, Cédric Le Goater wrote:
>
> Signed-off-by: Cédric Le Goater
NIce!
Reviewed-by: Joel Stanley
> ---
> tests/avocado/machine_aspeed.py | 11 +--
> 1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/tests/avocado/mach
On Thu, 19 Jan 2023 at 12:36, Cédric Le Goater wrote:
>
> From: Guenter Roeck
>
> supermicrox11-bmc is configured with ast2400-a1 SoC. This does not match
> the Supermicro documentation for X11 BMCs, and it does not match the
> devicetree file in the Linux kernel.
I found this sentence
On Thu, 19 Jan 2023 at 12:35, Cédric Le Goater wrote:
>
> From: Joel Stanley
>
> Update the test_arm_ast2600_debian test to
>
> - the latest Debian kernel
Would you like a newer version of this patch that uses the latest kernel?
> - use the Rainier machine instead of Tac
wed-by: Alex Bennée
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Cédric Le Goater
Reviewed-by: Joel Stanley
> ---
> include/hw/loader.h | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/include/hw/loader.h b/include/hw/loader.h
> index 70248e0da7
2]
> https://github.com/AspeedTech-BMC/zephyr/blob/v00.01.08/dts/arm/aspeed/ast10x0.dtsi
>
> Signed-off-by: Philippe Mathieu-Daudé
> Reviewed-by: Peter Delevoryas
> Reviewed-by: Cédric Le Goater
> Signed-off-by: Cédric Le Goater
Reviewed-by: Joel Stanley
> ---
> in
lle
> Cc: Tudor Ambarus
> Signed-off-by: Guenter Roeck
> Reviewed-by: Cédric Le Goater
> Message-Id: <20221221122213.1458540-1-li...@roeck-us.net>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Joel Stanley
I wonder if we could update the code so the padding is assumed.
> -
The model includes aspeed_scu.h but doesn't appear to require it.
Signed-off-by: Joel Stanley
---
hw/misc/aspeed_sdmc.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
index d2a3931033b3..abb272793393 100644
--- a/hw/misc/aspeed_sdmc.c
+++ b/hw
Enough model to capture the pinmux writes to enable correct operation of
the parts of pinmux that depend on GFX registers.
Signed-off-by: Joel Stanley
---
include/hw/arm/aspeed_soc.h | 3 +
include/hw/misc/aspeed_gfx.h | 31 +
hw/arm/aspeed_ast2600.c | 11
hw/arm
On Fri, 30 Dec 2022 at 11:35, Philippe Mathieu-Daudé wrote:
>
> IEC binary prefixes ease code review: the unit is explicit.
I strongly prefer the existing code; it tells you the size without
having to do maths.
>
> Signed-off-by: Philippe Mathieu-Daudé
> Reviewed-by: Peter Delevoryas
> ---
>
ard, they would expect the EEPROM
> to
> retain that information. It's very useful to be able to test things like this
> in QEMU as well, to verify software instrumentation like determining the cause
> of a reboot.
>
> Fixes: 5d8424dbd3e8 ("nvram: add AT24Cx i2c eeprom")
FRU Ver 0.02
> Product Manufacturer :
> Product Name : Mellanox ConnectX-6 DX OCP3.0
> Product Part Number : X
> Product Version : A9
> Product Serial:
> Product Custom Data 3 : ConnectX-6 DX
>
> Signed-of
your new function?
>
> - Added init_rom and init_rom_size attributes to TYPE_AT24C_EE
> - Added at24c_eeprom_init_rom helper function to initialize attributes
> - If -drive property is provided, it overrides init_rom data
>
> Signed-off-by: Peter Delevoryas
Reviewed-by: Joel
On Tue, 17 Jan 2023 at 23:24, Peter Delevoryas wrote:
>
> This helper is useful in board initialization because lets users initialize
> and
> realize an EEPROM on an I2C bus with a single function call.
>
> Signed-off-by: Peter Delevoryas
> Reviewed-by: Cédric Le Goate
On Tue, 17 Jan 2023 at 23:24, Peter Delevoryas wrote:
>
> aspeed_eeprom_init is an exact copy of at24c_eeprom_init, not needed.
>
> Signed-off-by: Peter Delevoryas
> Reviewed-by: Cédric Le Goater
> Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Joel Stanley
> ---
&g
Hi Nick,
On Thu, 24 Nov 2022 at 05:53, Nicholas Miehlbradt
wrote:
>
> Implements the Dynamic Execution Control Register (DEXCR) and the
> Hypervisor Dynamic Execution Control Register (HDEXCR) in TCG as
> defined in Power ISA 3.1B. Only aspects 5 (Non-privileged hash instruction
> enable) and 6
Linux has been added some time ago and the spi-nor driver is using it
> more often to detect the flash settings and even flash models.
Reviewed-by: Joel Stanley
Tested-by: Joel Stanley
Thanks Cédric!
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