Re: wiki.qemu.org account access request
On Thu, Apr 11, 2024 at 5:06 PM Zack Buhman wrote: > > I noticed the recent SH4 patches are included in the 9.0.0-rc3 release. > > Is it appropriate that I request a wiki.qemu.org account so that I may > document these changes in https://wiki.qemu.org/ChangeLog/9.0 in a manner > that is consistent with how the changes to other CPUs have been documented so > far? > > If so, I indeed desire such an account. I've created an account ZackBuhman for you and sent the password off-list. -- Thanks. -- Max
[PATCH v2] linux-user/syscall: fix target_msqid_ds time fields order
target_msqid_ds::msg_*time field pairs are reversed on 32-bit TARGET_PPC
and TARGET_SPARC and on big-endian TARGET_MIPS and TARGET_XTENSA.
Fix the order to match the kernel definitions.
The issue is spotted by the libc-test http://nsz.repo.hu/git/?p=libc-test
on big-endian xtensa core.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Max Filippov
---
Changes v1->v2:
- split into a separate patch
- add PPC, SPARC and big-endian MIPS
linux-user/syscall.c | 20 +++-
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index d9bfd31c1cad..781ed14bc613 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -4113,17 +4113,27 @@ static inline abi_long do_semtimedop(int semid,
struct target_msqid_ds
{
struct target_ipc_perm msg_perm;
-abi_ulong msg_stime;
#if TARGET_ABI_BITS == 32
+#if defined(TARGET_PPC) || defined(TARGET_SPARC) || \
+(TARGET_BIG_ENDIAN && (defined(TARGET_MIPS) || defined(TARGET_XTENSA)))
+abi_ulong __unused1;
+abi_ulong msg_stime;
+abi_ulong __unused2;
+abi_ulong msg_rtime;
+abi_ulong __unused3;
+abi_ulong msg_ctime;
+#else
+abi_ulong msg_stime;
abi_ulong __unused1;
-#endif
abi_ulong msg_rtime;
-#if TARGET_ABI_BITS == 32
abi_ulong __unused2;
-#endif
abi_ulong msg_ctime;
-#if TARGET_ABI_BITS == 32
abi_ulong __unused3;
+#endif
+#else
+abi_ulong msg_stime;
+abi_ulong msg_rtime;
+abi_ulong msg_ctime;
#endif
abi_ulong __msg_cbytes;
abi_ulong msg_qnum;
--
2.39.2
[PATCH v2] linux-user/syscall: xtensa: fix ipc_perm conversion
target_ipc_perm::mode and target_ipc_perm::__seq fields are 32-bit wide
on xtensa and thus need to use tswap32.
The issue is spotted by the libc-test http://nsz.repo.hu/git/?p=libc-test
on big-endian xtensa core.
Cc: qemu-sta...@nongnu.org
Fixes: a3da8be5126b ("target/xtensa: linux-user: fix sysv IPC structures")
Signed-off-by: Max Filippov
---
Changes v1->v2:
- split into a separate patch
linux-user/syscall.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index e384e1424890..d9bfd31c1cad 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -3758,12 +3758,13 @@ static inline abi_long target_to_host_ipc_perm(struct
ipc_perm *host_ip,
host_ip->gid = tswap32(target_ip->gid);
host_ip->cuid = tswap32(target_ip->cuid);
host_ip->cgid = tswap32(target_ip->cgid);
-#if defined(TARGET_ALPHA) || defined(TARGET_MIPS) || defined(TARGET_PPC)
+#if defined(TARGET_ALPHA) || defined(TARGET_MIPS) || defined(TARGET_PPC) || \
+defined(TARGET_XTENSA)
host_ip->mode = tswap32(target_ip->mode);
#else
host_ip->mode = tswap16(target_ip->mode);
#endif
-#if defined(TARGET_PPC)
+#if defined(TARGET_PPC) || defined(TARGET_XTENSA)
host_ip->__seq = tswap32(target_ip->__seq);
#else
host_ip->__seq = tswap16(target_ip->__seq);
@@ -3786,12 +3787,13 @@ static inline abi_long
host_to_target_ipc_perm(abi_ulong target_addr,
target_ip->gid = tswap32(host_ip->gid);
target_ip->cuid = tswap32(host_ip->cuid);
target_ip->cgid = tswap32(host_ip->cgid);
-#if defined(TARGET_ALPHA) || defined(TARGET_MIPS) || defined(TARGET_PPC)
+#if defined(TARGET_ALPHA) || defined(TARGET_MIPS) || defined(TARGET_PPC) || \
+defined(TARGET_XTENSA)
target_ip->mode = tswap32(host_ip->mode);
#else
target_ip->mode = tswap16(host_ip->mode);
#endif
-#if defined(TARGET_PPC)
+#if defined(TARGET_PPC) || defined(TARGET_XTENSA)
target_ip->__seq = tswap32(host_ip->__seq);
#else
target_ip->__seq = tswap16(host_ip->__seq);
--
2.39.2
Re: [PATCH] linux-user/syscall: xtensa: fix target_msqid_ds and ipc_perm conversion
On Fri, Mar 29, 2024 at 5:48 AM Philippe Mathieu-Daudé
wrote:
>
> Hi Max,
>
> On 29/3/24 07:31, Max Filippov wrote:
> > - target_ipc_perm::mode and target_ipc_perm::__seq fields are 32-bit wide
> >on xtensa and thus need to use tswap32
> > - target_msqid_ds::msg_*time field pairs are reversed on big-endian
> >xtensa
>
> Please split in 2 distinct patches.
Ok.
> > struct target_msqid_ds
> > {
> > struct target_ipc_perm msg_perm;
> > +#if defined(TARGET_XTENSA) && TARGET_BIG_ENDIAN
>
> Why restrict to only Xtensa here?
I have detected and tested it on xtensa.
I see other architectures (mips, parisc, ppc, sparc) that may need
that, but AFAICS it's not that it's applicable for all big endians.
> > +abi_ulong __unused1;
> > +abi_ulong msg_stime;
> > +abi_ulong __unused2;
> > +abi_ulong msg_rtime;
> > +abi_ulong __unused3;
> > +abi_ulong msg_ctime;
> > +#else
--
Thanks.
-- Max
[PATCH] linux-user/syscall: xtensa: fix target_msqid_ds and ipc_perm conversion
- target_ipc_perm::mode and target_ipc_perm::__seq fields are 32-bit wide
on xtensa and thus need to use tswap32
- target_msqid_ds::msg_*time field pairs are reversed on big-endian
xtensa
Both issues result in incorrect conversion results on big-endian xtensa
targets, spotted by the libc-test http://nsz.repo.hu/git/?p=libc-test
Cc: qemu-sta...@nongnu.org
Fixes: a3da8be5126b ("target/xtensa: linux-user: fix sysv IPC structures")
Signed-off-by: Max Filippov
---
linux-user/syscall.c | 19 +++
1 file changed, 15 insertions(+), 4 deletions(-)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index e384e1424890..cb334e90d6f0 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -3758,12 +3758,13 @@ static inline abi_long target_to_host_ipc_perm(struct
ipc_perm *host_ip,
host_ip->gid = tswap32(target_ip->gid);
host_ip->cuid = tswap32(target_ip->cuid);
host_ip->cgid = tswap32(target_ip->cgid);
-#if defined(TARGET_ALPHA) || defined(TARGET_MIPS) || defined(TARGET_PPC)
+#if defined(TARGET_ALPHA) || defined(TARGET_MIPS) || defined(TARGET_PPC) || \
+defined(TARGET_XTENSA)
host_ip->mode = tswap32(target_ip->mode);
#else
host_ip->mode = tswap16(target_ip->mode);
#endif
-#if defined(TARGET_PPC)
+#if defined(TARGET_PPC) || defined(TARGET_XTENSA)
host_ip->__seq = tswap32(target_ip->__seq);
#else
host_ip->__seq = tswap16(target_ip->__seq);
@@ -3786,12 +3787,13 @@ static inline abi_long
host_to_target_ipc_perm(abi_ulong target_addr,
target_ip->gid = tswap32(host_ip->gid);
target_ip->cuid = tswap32(host_ip->cuid);
target_ip->cgid = tswap32(host_ip->cgid);
-#if defined(TARGET_ALPHA) || defined(TARGET_MIPS) || defined(TARGET_PPC)
+#if defined(TARGET_ALPHA) || defined(TARGET_MIPS) || defined(TARGET_PPC) || \
+defined(TARGET_XTENSA)
target_ip->mode = tswap32(host_ip->mode);
#else
target_ip->mode = tswap16(host_ip->mode);
#endif
-#if defined(TARGET_PPC)
+#if defined(TARGET_PPC) || defined(TARGET_XTENSA)
target_ip->__seq = tswap32(host_ip->__seq);
#else
target_ip->__seq = tswap16(host_ip->__seq);
@@ -4111,6 +4113,14 @@ static inline abi_long do_semtimedop(int semid,
struct target_msqid_ds
{
struct target_ipc_perm msg_perm;
+#if defined(TARGET_XTENSA) && TARGET_BIG_ENDIAN
+abi_ulong __unused1;
+abi_ulong msg_stime;
+abi_ulong __unused2;
+abi_ulong msg_rtime;
+abi_ulong __unused3;
+abi_ulong msg_ctime;
+#else
abi_ulong msg_stime;
#if TARGET_ABI_BITS == 32
abi_ulong __unused1;
@@ -4122,6 +4132,7 @@ struct target_msqid_ds
abi_ulong msg_ctime;
#if TARGET_ABI_BITS == 32
abi_ulong __unused3;
+#endif
#endif
abi_ulong __msg_cbytes;
abi_ulong msg_qnum;
--
2.39.2
Re: [PATCH-for-9.1 18/21] target/xtensa: Extract MMU API to new mmu.c/mmu.h files
On Thu, Mar 21, 2024 at 8:50 AM Philippe Mathieu-Daudé wrote: > > Extract the MMU API and expose it via "mmu.h" so we can > reuse the methods in target/xtensa/ files. The MMU/MPU are replaceable configuration blocks in the xtensa architecture, their internals don't have architecture-wide significance and I believe their exposure should be kept to a minimum. I have a half-done xtensa MMU rework which I'd like to complete, it only exposes the interface for address translation, opcode translation and dumping. > Signed-off-by: Philippe Mathieu-Daudé > --- > target/xtensa/cpu.h| 32 +- > target/xtensa/mmu.h| 95 > target/xtensa/mmu.c| 889 > target/xtensa/mmu_helper.c | 892 + > target/xtensa/meson.build | 1 + > 5 files changed, 991 insertions(+), 918 deletions(-) > create mode 100644 target/xtensa/mmu.h > create mode 100644 target/xtensa/mmu.c -- Thanks. -- Max
Re: [PATCH 2/2] target/xtensa: tidy TLB way variability logic
On Mon, Jan 22, 2024 at 10:42 AM Peter Maydell wrote:
>
> On Fri, 19 Jan 2024 at 20:47, Max Filippov wrote:
> >
> > Whether TLB ways 5 and 6 are variable is not a property of the TLB
> > instance or a TLB entry instance, it's a property of the xtensa core
> > configuration.
> > Remove 'varway56' field from the xtensa_tlb structure and remove
> > 'variable' field from the xtensa_tlb_entry structure. Add
> > 'tlb_variable_way' array to the XtensaConfig and use it instead of
> > removed fields.
> >
> > Signed-off-by: Max Filippov
> > ---
> > target/xtensa/cpu.h | 3 +--
> > target/xtensa/mmu_helper.c | 38 ++--
> > target/xtensa/overlay_tool.h | 15 --
> > 3 files changed, 24 insertions(+), 32 deletions(-)
> >
> > diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
> > index 497325466397..24d3f15ea1bf 100644
> > --- a/target/xtensa/cpu.h
> > +++ b/target/xtensa/cpu.h
> > @@ -316,13 +316,11 @@ typedef struct xtensa_tlb_entry {
> > uint32_t paddr;
> > uint8_t asid;
> > uint8_t attr;
> > -bool variable;
> > } xtensa_tlb_entry;
> >
> > typedef struct xtensa_tlb {
> > unsigned nways;
> > const unsigned way_size[10];
> > -bool varway56;
> > unsigned nrefillentries;
> > } xtensa_tlb;
> >
> > @@ -493,6 +491,7 @@ typedef struct XtensaConfig {
> >
> > xtensa_tlb itlb;
> > xtensa_tlb dtlb;
> > +bool tlb_variable_way[16];
> >
> > uint32_t mpu_align;
> > unsigned n_mpu_fg_segments;
> > diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c
> > index d9f845e7fb6f..414c2f5ef669 100644
> > --- a/target/xtensa/mmu_helper.c
> > +++ b/target/xtensa/mmu_helper.c
> > @@ -105,23 +105,19 @@ static uint32_t xtensa_tlb_get_addr_mask(const
> > CPUXtensaState *env,
> > bool dtlb, uint32_t way)
> > {
> > if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
> > -bool varway56 = dtlb ?
> > -env->config->dtlb.varway56 :
> > -env->config->itlb.varway56;
> > -
> > switch (way) {
> > case 4:
> > return 0xfff0 << get_page_size(env, dtlb, way) * 2;
> >
> > case 5:
> > -if (varway56) {
> > +if (env->config->tlb_variable_way[5]) {
> > return 0xf800 << get_page_size(env, dtlb, way);
> > } else {
> > return 0xf800;
> > }
> >
> > case 6:
> > -if (varway56) {
> > +if (env->config->tlb_variable_way[6]) {
> > return 0xf000 << (1 - get_page_size(env, dtlb, way));
> > } else {
> > return 0xf000;
>
> So we now have a tlb_variable_way bool for all 16 possible
> ways, but the code actually only checks it for ways 5 and 6.
xtensa_tlb_set_entry checks this for all possible ways.
I would say that this is an unfortunate definition of MMU in the
xtensa ISA book that uses the variability of the ways 5/6 as a
discriminator between MMUv2 and MMUv3.
> Should we have an assertion somewhere that the config
> doesn't try to set it on ways where it has no effect ?
> Or is there actually a generic behaviour that would make
> sense for eg "way 3 is variable-way" that we just don't
> currently implement?
We currently use the TLB structure to implement the following
xtensa memory management options: cacheattr, region protection,
region translation, MMUv2 and MMUv3. First three only have
one variable way, in MMUv2 all ways except 5 and 6 are variable
and in MMUv3 all ways are variable. QEMU supports all of it
and tlb_variable_way is set properly in all of these cases.
> > @@ -150,11 +146,8 @@ static uint32_t get_vpn_mask(const CPUXtensaState
> > *env, bool dtlb, uint32_t way)
> > return xtensa_tlb_get_addr_mask(env, dtlb, way) << 2;
> > } else if (way <= 6) {
> > uint32_t mask = xtensa_tlb_get_addr_mask(env, dtlb, way);
> > -bool varway56 = dtlb ?
> > -env->config->dtlb.varway56 :
> > -env->config->itlb.varway56;
> >
> > -if (varway56) {
> > +if (env->config->tlb_variable_way[5]) {
> > return mask << (way == 5 ? 2 : 3);
> > } else {
> > return mask << 1;
>
> This doesn't look
Re: [PATCH 1/2] target/xtensa: wrap MMU and MPU state into structures
On Mon, Jan 22, 2024 at 10:29 AM Peter Maydell wrote:
>
> On Fri, 19 Jan 2024 at 20:47, Max Filippov wrote:
> >
> > Make separation of alternative xtensa memory management options state
> > explicit.
> >
> > Signed-off-by: Max Filippov
> > ---
> > target/xtensa/cpu.h| 18 +
> > target/xtensa/mmu_helper.c | 40 +++---
> > 2 files changed, 34 insertions(+), 24 deletions(-)
> >
> > diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
> > index 8a423706d8c0..497325466397 100644
> > --- a/target/xtensa/cpu.h
> > +++ b/target/xtensa/cpu.h
> > @@ -326,11 +326,21 @@ typedef struct xtensa_tlb {
> > unsigned nrefillentries;
> > } xtensa_tlb;
> >
> > +typedef struct XtensaMMU {
> > +xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE];
> > +xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE];
> > +unsigned autorefill_idx;
> > +} XtensaMMU;
> > +
> > typedef struct xtensa_mpu_entry {
> > uint32_t vaddr;
> > uint32_t attr;
> > } xtensa_mpu_entry;
> >
> > +typedef struct XtensaMPU {
> > +xtensa_mpu_entry fg[MAX_MPU_FOREGROUND_SEGMENTS];
> > +} XtensaMPU;
> > +
> > typedef struct XtensaGdbReg {
> > int targno;
> > unsigned flags;
> > @@ -526,10 +536,10 @@ struct CPUArchState {
> > uint32_t exclusive_val;
> >
> > #ifndef CONFIG_USER_ONLY
> > -xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE];
> > -xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE];
> > -xtensa_mpu_entry mpu_fg[MAX_MPU_FOREGROUND_SEGMENTS];
> > -unsigned autorefill_idx;
> > +union {
> > +XtensaMMU mmu;
> > +XtensaMPU mpu;
> > +};
>
> Is it really worth having this be a union ? I suspect it will
> make adding migration/savevm support later more awkward.
I have a draft implementation of savevm for xtensa and I did this part
using subsections with the .needed callback checking whether the
MMU or MPU option is enabled in the config. I wonder where the
awkwardness is expected.
> Otherwise
> Reviewed-by: Peter Maydell
Thanks!
-- Max
[PATCH 2/2] target/xtensa: tidy TLB way variability logic
Whether TLB ways 5 and 6 are variable is not a property of the TLB
instance or a TLB entry instance, it's a property of the xtensa core
configuration.
Remove 'varway56' field from the xtensa_tlb structure and remove
'variable' field from the xtensa_tlb_entry structure. Add
'tlb_variable_way' array to the XtensaConfig and use it instead of
removed fields.
Signed-off-by: Max Filippov
---
target/xtensa/cpu.h | 3 +--
target/xtensa/mmu_helper.c | 38 ++--
target/xtensa/overlay_tool.h | 15 --
3 files changed, 24 insertions(+), 32 deletions(-)
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 497325466397..24d3f15ea1bf 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -316,13 +316,11 @@ typedef struct xtensa_tlb_entry {
uint32_t paddr;
uint8_t asid;
uint8_t attr;
-bool variable;
} xtensa_tlb_entry;
typedef struct xtensa_tlb {
unsigned nways;
const unsigned way_size[10];
-bool varway56;
unsigned nrefillentries;
} xtensa_tlb;
@@ -493,6 +491,7 @@ typedef struct XtensaConfig {
xtensa_tlb itlb;
xtensa_tlb dtlb;
+bool tlb_variable_way[16];
uint32_t mpu_align;
unsigned n_mpu_fg_segments;
diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c
index d9f845e7fb6f..414c2f5ef669 100644
--- a/target/xtensa/mmu_helper.c
+++ b/target/xtensa/mmu_helper.c
@@ -105,23 +105,19 @@ static uint32_t xtensa_tlb_get_addr_mask(const
CPUXtensaState *env,
bool dtlb, uint32_t way)
{
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
-bool varway56 = dtlb ?
-env->config->dtlb.varway56 :
-env->config->itlb.varway56;
-
switch (way) {
case 4:
return 0xfff0 << get_page_size(env, dtlb, way) * 2;
case 5:
-if (varway56) {
+if (env->config->tlb_variable_way[5]) {
return 0xf800 << get_page_size(env, dtlb, way);
} else {
return 0xf800;
}
case 6:
-if (varway56) {
+if (env->config->tlb_variable_way[6]) {
return 0xf000 << (1 - get_page_size(env, dtlb, way));
} else {
return 0xf000;
@@ -150,11 +146,8 @@ static uint32_t get_vpn_mask(const CPUXtensaState *env,
bool dtlb, uint32_t way)
return xtensa_tlb_get_addr_mask(env, dtlb, way) << 2;
} else if (way <= 6) {
uint32_t mask = xtensa_tlb_get_addr_mask(env, dtlb, way);
-bool varway56 = dtlb ?
-env->config->dtlb.varway56 :
-env->config->itlb.varway56;
-if (varway56) {
+if (env->config->tlb_variable_way[5]) {
return mask << (way == 5 ? 2 : 3);
} else {
return mask << 1;
@@ -172,10 +165,6 @@ static void split_tlb_entry_spec_way(const CPUXtensaState
*env, uint32_t v,
bool dtlb, uint32_t *vpn,
uint32_t wi, uint32_t *ei)
{
-bool varway56 = dtlb ?
-env->config->dtlb.varway56 :
-env->config->itlb.varway56;
-
if (!dtlb) {
wi &= 7;
}
@@ -195,7 +184,7 @@ static void split_tlb_entry_spec_way(const CPUXtensaState
*env, uint32_t v,
break;
case 5:
-if (varway56) {
+if (env->config->tlb_variable_way[5]) {
uint32_t eibase = 27 + get_page_size(env, dtlb, wi);
*ei = (v >> eibase) & 0x3;
} else {
@@ -204,7 +193,7 @@ static void split_tlb_entry_spec_way(const CPUXtensaState
*env, uint32_t v,
break;
case 6:
-if (varway56) {
+if (env->config->tlb_variable_way[6]) {
uint32_t eibase = 29 - get_page_size(env, dtlb, wi);
*ei = (v >> eibase) & 0x7;
} else {
@@ -290,7 +279,7 @@ static void xtensa_tlb_set_entry(CPUXtensaState *env, bool
dtlb,
xtensa_tlb_entry *entry = xtensa_tlb_get_entry(env, dtlb, wi, ei);
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
-if (entry->variable) {
+if (env->config->tlb_variable_way[wi]) {
if (entry->asid) {
tlb_flush_page(cs, entry->vaddr);
}
@@ -338,29 +327,25 @@ static void reset_tlb_mmu_all_ways(CPUXtensaState *env,
for (wi = 0; wi < tlb->nways; ++wi) {
for (ei = 0; ei < tlb->way_size[wi]; ++ei) {
entry[wi][ei].asid = 0;
-entry[wi][ei].variable = true;
}
}
}
static void reset_tlb_mmu_ways56(CPUXtensaState *env,
- const xtensa_tlb *tlb,
x
[PATCH 0/2] target/xtensa: tidy xtensa memory management
Hello, this series separates xtensa MMU and MPU states and improves variable TLB way logic. Max Filippov (2): target/xtensa: wrap MMU and MPU state into structures target/xtensa: tidy TLB way variability logic target/xtensa/cpu.h | 21 +++--- target/xtensa/mmu_helper.c | 74 ++-- target/xtensa/overlay_tool.h | 15 +++- 3 files changed, 56 insertions(+), 54 deletions(-) -- 2.39.2
[PATCH 1/2] target/xtensa: wrap MMU and MPU state into structures
Make separation of alternative xtensa memory management options state
explicit.
Signed-off-by: Max Filippov
---
target/xtensa/cpu.h| 18 +
target/xtensa/mmu_helper.c | 40 +++---
2 files changed, 34 insertions(+), 24 deletions(-)
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 8a423706d8c0..497325466397 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -326,11 +326,21 @@ typedef struct xtensa_tlb {
unsigned nrefillentries;
} xtensa_tlb;
+typedef struct XtensaMMU {
+xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE];
+xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE];
+unsigned autorefill_idx;
+} XtensaMMU;
+
typedef struct xtensa_mpu_entry {
uint32_t vaddr;
uint32_t attr;
} xtensa_mpu_entry;
+typedef struct XtensaMPU {
+xtensa_mpu_entry fg[MAX_MPU_FOREGROUND_SEGMENTS];
+} XtensaMPU;
+
typedef struct XtensaGdbReg {
int targno;
unsigned flags;
@@ -526,10 +536,10 @@ struct CPUArchState {
uint32_t exclusive_val;
#ifndef CONFIG_USER_ONLY
-xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE];
-xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE];
-xtensa_mpu_entry mpu_fg[MAX_MPU_FOREGROUND_SEGMENTS];
-unsigned autorefill_idx;
+union {
+XtensaMMU mmu;
+XtensaMPU mpu;
+};
bool runstall;
AddressSpace *address_space_er;
MemoryRegion *system_er;
diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c
index 2fda4e887cce..d9f845e7fb6f 100644
--- a/target/xtensa/mmu_helper.c
+++ b/target/xtensa/mmu_helper.c
@@ -250,8 +250,8 @@ static xtensa_tlb_entry
*xtensa_tlb_get_entry(CPUXtensaState *env, bool dtlb,
assert(wi < tlb->nways && ei < tlb->way_size[wi]);
return dtlb ?
-env->dtlb[wi] + ei :
-env->itlb[wi] + ei;
+env->mmu.dtlb[wi] + ei :
+env->mmu.itlb[wi] + ei;
}
static xtensa_tlb_entry *get_tlb_entry(CPUXtensaState *env,
@@ -411,11 +411,11 @@ void reset_mmu(CPUXtensaState *env)
env->sregs[RASID] = 0x04030201;
env->sregs[ITLBCFG] = 0;
env->sregs[DTLBCFG] = 0;
-env->autorefill_idx = 0;
-reset_tlb_mmu_all_ways(env, >config->itlb, env->itlb);
-reset_tlb_mmu_all_ways(env, >config->dtlb, env->dtlb);
-reset_tlb_mmu_ways56(env, >config->itlb, env->itlb);
-reset_tlb_mmu_ways56(env, >config->dtlb, env->dtlb);
+env->mmu.autorefill_idx = 0;
+reset_tlb_mmu_all_ways(env, >config->itlb, env->mmu.itlb);
+reset_tlb_mmu_all_ways(env, >config->dtlb, env->mmu.dtlb);
+reset_tlb_mmu_ways56(env, >config->itlb, env->mmu.itlb);
+reset_tlb_mmu_ways56(env, >config->dtlb, env->mmu.dtlb);
} else if (xtensa_option_enabled(env->config, XTENSA_OPTION_MPU)) {
unsigned i;
@@ -430,8 +430,8 @@ void reset_mmu(CPUXtensaState *env)
}
} else {
env->sregs[CACHEATTR] = 0x;
-reset_tlb_region_way0(env, env->itlb);
-reset_tlb_region_way0(env, env->dtlb);
+reset_tlb_region_way0(env, env->mmu.itlb);
+reset_tlb_region_way0(env, env->mmu.dtlb);
}
}
@@ -462,7 +462,7 @@ static int xtensa_tlb_lookup(const CPUXtensaState *env,
const xtensa_tlb *tlb = dtlb ?
>config->dtlb : >config->itlb;
const xtensa_tlb_entry (*entry)[MAX_TLB_WAY_SIZE] = dtlb ?
-env->dtlb : env->itlb;
+env->mmu.dtlb : env->mmu.itlb;
int nhits = 0;
unsigned wi;
@@ -821,7 +821,7 @@ static int get_physical_addr_mmu(CPUXtensaState *env, bool
update_tlb,
split_tlb_entry_spec_way(env, vaddr, dtlb, , wi, );
if (update_tlb) {
-wi = ++env->autorefill_idx & 0x3;
+wi = ++env->mmu.autorefill_idx & 0x3;
xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, pte);
env->sregs[EXCVADDR] = vaddr;
qemu_log_mask(CPU_LOG_MMU, "%s: autorefill(%08x): %08x -> %08x\n",
@@ -957,8 +957,8 @@ void HELPER(wptlb)(CPUXtensaState *env, uint32_t p,
uint32_t v)
unsigned segment = p & XTENSA_MPU_SEGMENT_MASK;
if (segment < env->config->n_mpu_fg_segments) {
-env->mpu_fg[segment].vaddr = v & -env->config->mpu_align;
-env->mpu_fg[segment].attr = p & XTENSA_MPU_ATTR_MASK;
+env->mpu.fg[segment].vaddr = v & -env->config->mpu_align;
+env->mpu.fg[segment].attr = p & XTENSA_MPU_ATTR_MASK;
env->sregs[MPUENB] = deposit32(env->sregs[MPUENB], segment, 1, v);
tlb_flush(env_cpu(env));
}
@@ -969,7 +969,7 @@ uint32_t HELPER(rptlb0)(CPUXtensaState *env, uint32_t s)
unsigned segment = s & XTENSA_MPU_SEGMENT_MASK;
if (segment < env->config->n_mpu_fg_segments) {
-return en
[PATCH 0/4] target/xtensa: provide configuration with MPU
Hello, this series adds xtensa core 'sample_controller32' with 32 foreground entry MPU, adds missing translation for the 'wsr.mpucfg' opcode and makes xtensa/tcg/tests work with the new core. Max Filippov (4): target/xtensa: add translation for wsr.mpucfg target/xtensa: import sample_controller32 core tests/tcg/xtensa: tidy test linker script tests/tcg/xtensa: fix SR test for configs with MPU target/xtensa/core-sample_controller32.c |52 + .../core-sample_controller32/core-isa.h | 739 + .../core-sample_controller32/core-matmap.h| 106 + .../core-sample_controller32/gdb-config.c.inc | 144 + .../xtensa-modules.c.inc | 11845 target/xtensa/cores.list | 1 + target/xtensa/translate.c | 9 + tests/tcg/xtensa/linker.ld.S |34 +- tests/tcg/xtensa/test_sr.S|16 +- 9 files changed, 12921 insertions(+), 25 deletions(-) create mode 100644 target/xtensa/core-sample_controller32.c create mode 100644 target/xtensa/core-sample_controller32/core-isa.h create mode 100644 target/xtensa/core-sample_controller32/core-matmap.h create mode 100644 target/xtensa/core-sample_controller32/gdb-config.c.inc create mode 100644 target/xtensa/core-sample_controller32/xtensa-modules.c.inc -- 2.39.2
[PATCH 4/4] tests/tcg/xtensa: fix SR test for configs with MPU
- atomctl is available not only in the presence of s32c1i, but also with the exclusive access option - cacheadrdis SR has the same number as cacheattr, mpuenb SR has the same number as rasid and mpucfg SR has the same number as dtlbcfg, add MPU case to the tests of these SR numbers Signed-off-by: Max Filippov --- tests/tcg/xtensa/test_sr.S | 16 ++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/tests/tcg/xtensa/test_sr.S b/tests/tcg/xtensa/test_sr.S index 34441c7afff7..661ef6c66ed1 100644 --- a/tests/tcg/xtensa/test_sr.S +++ b/tests/tcg/xtensa/test_sr.S @@ -62,7 +62,7 @@ test_sr_mask /*acchi*/17, 0, 0 test_sr_mask /*acclo*/16, 0, 0 #endif -#if XCHAL_HAVE_S32C1I && XCHAL_HW_VERSION >= 23 +#if XCHAL_HAVE_S32C1I && XCHAL_HW_VERSION >= 23 || XCHAL_HAVE_EXCLUSIVE test_sr atomctl, 1 #else test_sr_mask /*atomctl*/99, 0, 0 @@ -74,7 +74,11 @@ test_sr br, 1 test_sr_mask /*br*/4, 0, 0 #endif +#if XCHAL_HAVE_MPU +test_sr cacheadrdis, 1 +#else test_sr_mask /*cacheattr*/98, 0, 0 +#endif #if XCHAL_HAVE_CCOUNT test_sr ccompare0, 1 @@ -106,6 +110,8 @@ test_sr depc, 1 #if XCHAL_HAVE_PTP_MMU test_sr dtlbcfg, 1 +#elif XCHAL_HAVE_MPU +test_sr_mask /*mpucfg*/92, 0, 3 #else test_sr_mask /*dtlbcfg*/92, 0, 0 #endif @@ -205,9 +211,15 @@ test_sr ps, 1 #if XCHAL_HAVE_PTP_MMU test_sr ptevaddr, 1 -test_sr rasid, 1 #else test_sr_mask /*ptevaddr*/83, 0, 0 +#endif + +#if XCHAL_HAVE_PTP_MMU +test_sr rasid, 1 +#elif XCHAL_HAVE_MPU +test_sr mpuenb, 1 +#else test_sr_mask /*rasid*/90, 0, 0 #endif -- 2.39.2
[PATCH 3/4] tests/tcg/xtensa: tidy test linker script
Drop MEMORY clause and related size definitions and output section
region specifications. Drop .rodata output section as the tests don't
use it. Add DATA_SEGMENT_ALIGN/DATA_SEGMENT_END around .data and .bss to
let the linker make an RW segment for data. Reserve 1M for stack instead
of almost 128M.
Signed-off-by: Max Filippov
---
tests/tcg/xtensa/linker.ld.S | 34 +++---
1 file changed, 11 insertions(+), 23 deletions(-)
diff --git a/tests/tcg/xtensa/linker.ld.S b/tests/tcg/xtensa/linker.ld.S
index ac89b0054ee4..0e21eee31ccc 100644
--- a/tests/tcg/xtensa/linker.ld.S
+++ b/tests/tcg/xtensa/linker.ld.S
@@ -10,9 +10,8 @@
#define XCHAL_WINDOW_UF12_VECOFS 0x0140
#endif
-#define RAM_SIZE 0x0800 /* 128M */
-#define ROM_SIZE 0x1000 /* 4k */
#define VECTORS_RESERVED_SIZE 0x1000
+#define STACK_SIZE 0x0010
#if XCHAL_HAVE_BE
OUTPUT_FORMAT("elf32-xtensa-be")
@@ -21,18 +20,13 @@ OUTPUT_FORMAT("elf32-xtensa-le")
#endif
ENTRY(_start)
-MEMORY {
-ram : ORIGIN = XCHAL_VECBASE_RESET_VADDR, LENGTH = RAM_SIZE
-rom : ORIGIN = XCHAL_RESET_VECTOR_VADDR, LENGTH = ROM_SIZE
-}
-
SECTIONS
{
-.init :
+.init XCHAL_RESET_VECTOR_VADDR :
{
*(.init)
*(.init.*)
-} > rom
+}
#if XCHAL_HAVE_WINDOWED
.vector.window XCHAL_WINDOW_VECTORS_VADDR :
@@ -119,23 +113,16 @@ SECTIONS
*(.vector.kernel.*)
*(.vector.user.*)
*(.vector.double.*)
-} > ram
+}
.text :
{
_ftext = .;
*(.text .stub .text.* .gnu.linkonce.t.* .literal .literal.*)
_etext = .;
-} > ram
+}
-.rodata :
-{
-. = ALIGN(4);
-_frodata = .;
-*(.rodata .rodata.* .gnu.linkonce.r.*)
-*(.rodata1)
-_erodata = .;
-} > ram
+. = DATA_SEGMENT_ALIGN(0x1000, 0x1000);
.data :
{
@@ -146,7 +133,7 @@ SECTIONS
_gp = ALIGN(16);
*(.sdata .sdata.* .gnu.linkonce.s.*)
_edata = .;
-} > ram
+}
.bss :
{
@@ -160,7 +147,8 @@ SECTIONS
*(COMMON)
_ebss = .;
_end = .;
-} > ram
-}
+}
-PROVIDE(_fstack = (ORIGIN(ram) & 0xf000) + LENGTH(ram) - 16);
+. = DATA_SEGMENT_END(.);
+_fstack = ALIGN(. + STACK_SIZE, 16);
+}
--
2.39.2
[PATCH 1/4] target/xtensa: add translation for wsr.mpucfg
Although MPUCFG is not writable, the opcode wsr.mpucfg is defined and it
just does nothing. Define wsr.mpucfg as nop.
Signed-off-by: Max Filippov
---
target/xtensa/translate.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index de899405994e..6a2f5d308e6a 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -5332,6 +5332,15 @@ static const XtensaOpcodeOps core_ops[] = {
XTENSA_OPTION_TRACE_PORT,
},
.op_flags = XTENSA_OP_PRIVILEGED,
+}, {
+.name = "wsr.mpucfg",
+.translate = translate_nop,
+.test_exceptions = test_exceptions_sr,
+.par = (const uint32_t[]){
+MPUCFG,
+XTENSA_OPTION_MPU,
+},
+.op_flags = XTENSA_OP_PRIVILEGED,
}, {
.name = "wsr.mpuenb",
.translate = translate_wsr_mpuenb,
--
2.39.2
[PATCH] tests/tcg/xtensa: add test for OOB TLB reads
Add a test reading *TLB ways 0..15. Signed-off-by: Max Filippov --- tests/tcg/xtensa/test_mmu.S | 11 +++ 1 file changed, 11 insertions(+) diff --git a/tests/tcg/xtensa/test_mmu.S b/tests/tcg/xtensa/test_mmu.S index 1006c8cf77b2..94cd09563c7a 100644 --- a/tests/tcg/xtensa/test_mmu.S +++ b/tests/tcg/xtensa/test_mmu.S @@ -43,6 +43,17 @@ test_suite mmu #endif .endm +test tlb_read_ways +movia2, 0 +1: +ritlb0 a3, a2 +ritlb1 a3, a2 +rdtlb0 a3, a2 +rdtlb1 a3, a2 +addia2, a2, 1 +bltui a2, 16, 1b +test_end + test tlb_group movia2, 0x0402 /* PPN */ movia3, BASE + 0x0124 /* VPN */ -- 2.39.2
[PATCH] target/xtensa: fix OOB TLB entry access
r[id]tlb[01], [iw][id]tlb opcodes use TLB way index passed in a register
by the guest. The host uses 3 bits of the index for ITLB indexing and 4
bits for DTLB, but there's only 7 entries in the ITLB array and 10 in
the DTLB array, so a malicious guest may trigger out-of-bound access to
these arrays.
Change split_tlb_entry_spec return type to bool to indicate whether TLB
way passed to it is valid. Change get_tlb_entry to return NULL in case
invalid TLB way is requested. Add assertion to xtensa_tlb_get_entry that
requested TLB way and entry indices are valid. Add checks to the
[rwi]tlb helpers that requested TLB way is valid and return 0 or do
nothing when it's not.
Cc: qemu-sta...@nongnu.org
Fixes: b67ea0cd7441 ("target-xtensa: implement memory protection options")
Signed-off-by: Max Filippov
---
target/xtensa/mmu_helper.c | 47 --
1 file changed, 35 insertions(+), 12 deletions(-)
diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c
index 12552a33470e..2fda4e887cce 100644
--- a/target/xtensa/mmu_helper.c
+++ b/target/xtensa/mmu_helper.c
@@ -224,22 +224,31 @@ static void split_tlb_entry_spec_way(const CPUXtensaState
*env, uint32_t v,
* Split TLB address into TLB way, entry index and VPN (with index).
* See ISA, 4.6.5.5 - 4.6.5.8 for the TLB addressing format
*/
-static void split_tlb_entry_spec(CPUXtensaState *env, uint32_t v, bool dtlb,
-uint32_t *vpn, uint32_t *wi, uint32_t *ei)
+static bool split_tlb_entry_spec(CPUXtensaState *env, uint32_t v, bool dtlb,
+ uint32_t *vpn, uint32_t *wi, uint32_t *ei)
{
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
*wi = v & (dtlb ? 0xf : 0x7);
-split_tlb_entry_spec_way(env, v, dtlb, vpn, *wi, ei);
+if (*wi < (dtlb ? env->config->dtlb.nways : env->config->itlb.nways)) {
+split_tlb_entry_spec_way(env, v, dtlb, vpn, *wi, ei);
+return true;
+} else {
+return false;
+}
} else {
*vpn = v & REGION_PAGE_MASK;
*wi = 0;
*ei = (v >> 29) & 0x7;
+return true;
}
}
static xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env, bool dtlb,
unsigned wi, unsigned ei)
{
+const xtensa_tlb *tlb = dtlb ? >config->dtlb : >config->itlb;
+
+assert(wi < tlb->nways && ei < tlb->way_size[wi]);
return dtlb ?
env->dtlb[wi] + ei :
env->itlb[wi] + ei;
@@ -252,11 +261,14 @@ static xtensa_tlb_entry *get_tlb_entry(CPUXtensaState
*env,
uint32_t wi;
uint32_t ei;
-split_tlb_entry_spec(env, v, dtlb, , , );
-if (pwi) {
-*pwi = wi;
+if (split_tlb_entry_spec(env, v, dtlb, , , )) {
+if (pwi) {
+*pwi = wi;
+}
+return xtensa_tlb_get_entry(env, dtlb, wi, ei);
+} else {
+return NULL;
}
-return xtensa_tlb_get_entry(env, dtlb, wi, ei);
}
static void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
@@ -482,7 +494,12 @@ uint32_t HELPER(rtlb0)(CPUXtensaState *env, uint32_t v,
uint32_t dtlb)
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
uint32_t wi;
const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, );
-return (entry->vaddr & get_vpn_mask(env, dtlb, wi)) | entry->asid;
+
+if (entry) {
+return (entry->vaddr & get_vpn_mask(env, dtlb, wi)) | entry->asid;
+} else {
+return 0;
+}
} else {
return v & REGION_PAGE_MASK;
}
@@ -491,7 +508,12 @@ uint32_t HELPER(rtlb0)(CPUXtensaState *env, uint32_t v,
uint32_t dtlb)
uint32_t HELPER(rtlb1)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
{
const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, NULL);
-return entry->paddr | entry->attr;
+
+if (entry) {
+return entry->paddr | entry->attr;
+} else {
+return 0;
+}
}
void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
@@ -499,7 +521,7 @@ void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint32_t
dtlb)
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
uint32_t wi;
xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, );
-if (entry->variable && entry->asid) {
+if (entry && entry->variable && entry->asid) {
tlb_flush_page(env_cpu(env), entry->vaddr);
entry->asid = 0;
}
@@ -537,8 +559,9 @@ void HELPER(wtlb)(CPUXtensaState *env, uint32_t p, uint32_t
v, uint32_t dtlb)
uint32_t vpn;
uint32_t wi;
uint32_t ei;
-split_tlb_entry_spec(env, v, dtlb, , , );
-xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, p);
+if (split_tlb_entry_spec(env, v, dtlb, , , )) {
+xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, p);
+}
}
/*!
--
2.39.2
[PATCH 1/2] target/xtensa: use generic instruction breakpoint infrastructure
Don't embed ibreak exception generation into TB and don't invalidate TB
on ibreak address change. Add CPUBreakpoint pointers to xtensa
CPUArchState, use cpu_breakpoint_insert/cpu_breakpoint_remove_by_ref to
manage ibreak breakpoints and provide TCGCPUOps::debug_check_breakpoint
callback that recognizes valid instruction breakpoints.
Signed-off-by: Max Filippov
---
target/xtensa/cpu.c| 1 +
target/xtensa/cpu.h| 4
target/xtensa/dbg_helper.c | 46 +-
target/xtensa/helper.c | 12 ++
target/xtensa/translate.c | 17 --
5 files changed, 47 insertions(+), 33 deletions(-)
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index e20fe87bf255..b74ee8917065 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -235,6 +235,7 @@ static const struct TCGCPUOps xtensa_tcg_ops = {
.do_interrupt = xtensa_cpu_do_interrupt,
.do_transaction_failed = xtensa_cpu_do_transaction_failed,
.do_unaligned_access = xtensa_cpu_do_unaligned_access,
+.debug_check_breakpoint = xtensa_debug_check_breakpoint,
#endif /* !CONFIG_USER_ONLY */
};
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index dd8172930653..8a423706d8c0 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -229,6 +229,7 @@ enum {
#define MAX_NCCOMPARE 3
#define MAX_TLB_WAY_SIZE 8
#define MAX_NDBREAK 2
+#define MAX_NIBREAK 2
#define MAX_NMEMORY 4
#define MAX_MPU_FOREGROUND_SEGMENTS 32
@@ -547,6 +548,8 @@ struct CPUArchState {
/* Watchpoints for DBREAK registers */
struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK];
+/* Breakpoints for IBREAK registers */
+struct CPUBreakpoint *cpu_breakpoint[MAX_NIBREAK];
};
/**
@@ -590,6 +593,7 @@ void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr
physaddr, vaddr addr,
int mmu_idx, MemTxAttrs attrs,
MemTxResult response, uintptr_t retaddr);
hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
+bool xtensa_debug_check_breakpoint(CPUState *cs);
#endif
void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
void xtensa_count_regs(const XtensaConfig *config,
diff --git a/target/xtensa/dbg_helper.c b/target/xtensa/dbg_helper.c
index 3e0c9e8e8be0..497dafca719c 100644
--- a/target/xtensa/dbg_helper.c
+++ b/target/xtensa/dbg_helper.c
@@ -33,27 +33,21 @@
#include "exec/exec-all.h"
#include "exec/address-spaces.h"
-static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr)
-{
-uint32_t paddr;
-uint32_t page_size;
-unsigned access;
-int ret = xtensa_get_physical_addr(env, false, vaddr, 2, 0,
- , _size, );
-if (ret == 0) {
-tb_invalidate_phys_addr(_space_memory, paddr,
-MEMTXATTRS_UNSPECIFIED);
-}
-}
-
void HELPER(wsr_ibreakenable)(CPUXtensaState *env, uint32_t v)
{
+CPUState *cs = env_cpu(env);
uint32_t change = v ^ env->sregs[IBREAKENABLE];
unsigned i;
for (i = 0; i < env->config->nibreak; ++i) {
if (change & (1 << i)) {
-tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]);
+if (v & (1 << i)) {
+cpu_breakpoint_insert(cs, env->sregs[IBREAKA + i],
+ BP_CPU, >cpu_breakpoint[i]);
+} else {
+cpu_breakpoint_remove_by_ref(cs, env->cpu_breakpoint[i]);
+env->cpu_breakpoint[i] = NULL;
+}
}
}
env->sregs[IBREAKENABLE] = v & ((1 << env->config->nibreak) - 1);
@@ -62,12 +56,32 @@ void HELPER(wsr_ibreakenable)(CPUXtensaState *env, uint32_t
v)
void HELPER(wsr_ibreaka)(CPUXtensaState *env, uint32_t i, uint32_t v)
{
if (env->sregs[IBREAKENABLE] & (1 << i) && env->sregs[IBREAKA + i] != v) {
-tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]);
-tb_invalidate_virtual_addr(env, v);
+CPUState *cs = env_cpu(env);
+
+cpu_breakpoint_remove_by_ref(cs, env->cpu_breakpoint[i]);
+cpu_breakpoint_insert(cs, v, BP_CPU, >cpu_breakpoint[i]);
}
env->sregs[IBREAKA + i] = v;
}
+bool xtensa_debug_check_breakpoint(CPUState *cs)
+{
+XtensaCPU *cpu = XTENSA_CPU(cs);
+CPUXtensaState *env = >env;
+unsigned int i;
+
+if (xtensa_get_cintlevel(env) >= env->config->debug_level) {
+return false;
+}
+for (i = 0; i < env->config->nibreak; ++i) {
+if (env->sregs[IBREAKENABLE] & (1 << i) &&
+env->sregs[IBREAKA + i] == env->pc) {
+return true;
+}
+}
+return false;
+}
+
static void set_dbreak(CPUXtensaState *env, unsigned i, uint32_t dbreaka,
uint32_t dbreakc)
{
diff --git a/target/xtensa/helper.c b/ta
[PATCH 2/2] tests/tcg/xtensa: add icount/ibreak priority test
When icount and ibreak exceptions are due to happen on the same address icount has higher precedence. Signed-off-by: Max Filippov --- tests/tcg/xtensa/test_break.S | 25 - 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/tests/tcg/xtensa/test_break.S b/tests/tcg/xtensa/test_break.S index 3aa18b5cec3f..4c618feb5b10 100644 --- a/tests/tcg/xtensa/test_break.S +++ b/tests/tcg/xtensa/test_break.S @@ -129,7 +129,7 @@ test ibreak_remove 4: test_end -test ibreak_priority +test ibreak_break_priority set_vector debug_vector, 2f rsila2, debug_level - 1 movia2, 1f @@ -145,6 +145,29 @@ test ibreak_priority movia3, 0x2 assert eq, a2, a3 test_end + +test ibreak_icount_priority +set_vector debug_vector, 2f +rsila2, debug_level - 1 +movia2, 1f +wsr a2, ibreaka0 +movia2, 1 +wsr a2, ibreakenable +movia2, -2 +wsr a2, icount +movia2, 1 +wsr a2, icountlevel +isync +rsila2, 0 +nop +1: +break 0, 0 +test_fail +2: +rsr a2, debugcause +movia3, 0x1 +assert eq, a2, a3 +test_end #endif test icount -- 2.39.2
[PATCH 0/2] target/xtensa: use generic instruction breakpoint infrastructure
Hello, this series makes target/xtensa use generic instruction breakpoint infrastructure removing its use of tb_invalidate_phys_addr. It also adds a new TCG test checking relative priority of icount and ibreak exceptions for target/xtensa. Max Filippov (2): target/xtensa: use generic instruction breakpoint infrastructure tests/tcg/xtensa: add icount/ibreak priority test target/xtensa/cpu.c | 1 + target/xtensa/cpu.h | 4 +++ target/xtensa/dbg_helper.c| 46 +++ target/xtensa/helper.c| 12 + target/xtensa/translate.c | 17 - tests/tcg/xtensa/test_break.S | 25 ++- 6 files changed, 71 insertions(+), 34 deletions(-) -- 2.39.2
Re: [PATCH for-6.1 v6 14/17] accel/tcg: Move breakpoint recognition outside translation
On Tue, Nov 28, 2023 at 10:06 AM Richard Henderson wrote: > On 11/28/23 05:08, Philippe Mathieu-Daudé wrote: > > (In sysemu there is a single use in Xtensa tb_invalidate_virtual_addr). > > I suspect that should be migrated to use the common HW breakpoint support. I'm taking a look. -- Thanks. -- Max
[PULL 0/1] target/xtensa fixes for v8.2
The following changes since commit 9c673a41eefc50f1cb2fe3c083e7de842c7d276a: Update version for v8.2.0-rc0 release (2023-11-14 12:35:47 -0500) are available in the Git repository at: https://github.com/OSLL/qemu-xtensa.git tags/20231119-xtensa-1 for you to fetch changes up to 1b173d06068c4a4e93fad88205399232925967a4: linux-user: xtensa: fix signal delivery in FDPIC (2023-11-19 10:56:26 -0800) target/xtensa fixes for v8.2: - fix signal delivery in FDPIC Max Filippov (1): linux-user: xtensa: fix signal delivery in FDPIC linux-user/xtensa/signal.c | 28 ++-- 1 file changed, 26 insertions(+), 2 deletions(-)
Re: [PULL] target/xtensa fixes for v8.2
On Sun, Nov 19, 2023 at 10:52 AM Max Filippov wrote: > > The following changes since commit b411438aa4ecaf4bbde90e20283e5899fec10f58: > > target/xtensa: Use tcg_gen_sextract_i32 (2023-10-21 19:17:28 -0700) > > are available in the Git repository at: > > https://github.com/OSLL/qemu-xtensa.git tags/20231119-xtensa > > for you to fetch changes up to 79cc6538fba73b3c071d76d912486e96540df98f: > > linux-user: xtensa: fix signal delivery in FDPIC (2023-11-19 10:38:07 -0800) > > > target/xtensa updates for v8.2: > > - fix signal delivery in FDPIC > > -------- > Max Filippov (1): > linux-user: xtensa: fix signal delivery in FDPIC > > linux-user/xtensa/signal.c | 28 ++-- > 1 file changed, 26 insertions(+), 2 deletions(-) Sorry, wrong tag, please ignore. -- Thanks. -- Max
[PULL] target/xtensa fixes for v8.2
The following changes since commit b411438aa4ecaf4bbde90e20283e5899fec10f58: target/xtensa: Use tcg_gen_sextract_i32 (2023-10-21 19:17:28 -0700) are available in the Git repository at: https://github.com/OSLL/qemu-xtensa.git tags/20231119-xtensa for you to fetch changes up to 79cc6538fba73b3c071d76d912486e96540df98f: linux-user: xtensa: fix signal delivery in FDPIC (2023-11-19 10:38:07 -0800) target/xtensa updates for v8.2: - fix signal delivery in FDPIC Max Filippov (1): linux-user: xtensa: fix signal delivery in FDPIC linux-user/xtensa/signal.c | 28 ++-- 1 file changed, 26 insertions(+), 2 deletions(-)
Re: [PATCH] linux-user: xtensa: fix signal delivery in FDPIC
On Sun, Nov 12, 2023 at 8:51 AM Richard Henderson
wrote:
>
> On 11/11/23 03:22, Max Filippov wrote:
> > In FDPIC signal handlers are passed around as FD pointers. Actual code
> > address and GOT pointer must be fetched from memory by the QEMU code
> > that implements kernel signal delivery functionality. This change is
> > equivalent to the following kernel change:
> > 9c2cc74fb31e ("xtensa: fix signal delivery to FDPIC process")
> >
> > Cc: qemu-sta...@nongnu.org
> > Fixes: d2796be69d7c ("linux-user: add support for xtensa FDPIC")
> > Signed-off-by: Max Filippov
> > ---
> > linux-user/xtensa/signal.c | 28 ++--
> > 1 file changed, 26 insertions(+), 2 deletions(-)
> >
> > diff --git a/linux-user/xtensa/signal.c b/linux-user/xtensa/signal.c
> > index f5fb8b5cbebe..32dcfa522919 100644
> > --- a/linux-user/xtensa/signal.c
> > +++ b/linux-user/xtensa/signal.c
> > @@ -157,6 +157,9 @@ void setup_rt_frame(int sig, struct target_sigaction
> > *ka,
> > {
> > abi_ulong frame_addr;
> > struct target_rt_sigframe *frame;
> > +int is_fdpic = info_is_fdpic(((TaskState *)thread_cpu->opaque)->info);
> > +abi_ulong handler = 0;
> > +abi_ulong handler_fdpic_GOT = 0;
> > uint32_t ra;
> > bool abi_call0;
> > unsigned base;
> > @@ -165,6 +168,17 @@ void setup_rt_frame(int sig, struct target_sigaction
> > *ka,
> > frame_addr = get_sigframe(ka, env, sizeof(*frame));
> > trace_user_setup_rt_frame(env, frame_addr);
> >
> > +if (is_fdpic) {
> > +abi_ulong funcdesc_ptr = ka->_sa_handler;
> > +
> > +if (get_user_ual(handler, funcdesc_ptr)
> > +|| get_user_ual(handler_fdpic_GOT, funcdesc_ptr + 4)) {
> > +goto give_sigsegv;
> > +}
> > +} else {
> > +handler = ka->_sa_handler;
> > +}
>
> This part is ok, with the last hunk, because it's taking care of the fd for
> the handler.
>
> > @@ -185,14 +199,21 @@ void setup_rt_frame(int sig, struct target_sigaction
> > *ka,
> > }
> >
> > if (ka->sa_flags & TARGET_SA_RESTORER) {
> > -ra = ka->sa_restorer;
> > +if (is_fdpic) {
> > +if (get_user_ual(ra, ka->sa_restorer)) {
> > +unlock_user_struct(frame, frame_addr, 0);
> > +goto give_sigsegv;
> > +}
> > +} else {
> > +ra = ka->sa_restorer;
> > +}
>
> This part is questionable. It does match the kernel, so as far as that goes,
>
> Reviewed-by: Richard Henderson
>
> However, it does not handle the GOT register for the restorer, like we do on
> ARM. That
> said, I can't find any libc sources for xtensa, or at least that aren't out
> of date by a
It's WIP, available at https://github.com/jcmvbkbc/uclibc-ng-xtensa
branch xtensa-1.0.44-fdpic
> decade, so I can't tell if libc *knows* the got register won't be loaded, and
> it doesn't
> matter because it only uses the sigreturn syscall.
That's the case. AFAU the restorer field is not for public use and the function
used as a restorer by the uclibc does not care about the GOT pointer.
--
Thanks.
-- Max
[PATCH] linux-user: xtensa: fix signal delivery in FDPIC
In FDPIC signal handlers are passed around as FD pointers. Actual code
address and GOT pointer must be fetched from memory by the QEMU code
that implements kernel signal delivery functionality. This change is
equivalent to the following kernel change:
9c2cc74fb31e ("xtensa: fix signal delivery to FDPIC process")
Cc: qemu-sta...@nongnu.org
Fixes: d2796be69d7c ("linux-user: add support for xtensa FDPIC")
Signed-off-by: Max Filippov
---
linux-user/xtensa/signal.c | 28 ++--
1 file changed, 26 insertions(+), 2 deletions(-)
diff --git a/linux-user/xtensa/signal.c b/linux-user/xtensa/signal.c
index f5fb8b5cbebe..32dcfa522919 100644
--- a/linux-user/xtensa/signal.c
+++ b/linux-user/xtensa/signal.c
@@ -157,6 +157,9 @@ void setup_rt_frame(int sig, struct target_sigaction *ka,
{
abi_ulong frame_addr;
struct target_rt_sigframe *frame;
+int is_fdpic = info_is_fdpic(((TaskState *)thread_cpu->opaque)->info);
+abi_ulong handler = 0;
+abi_ulong handler_fdpic_GOT = 0;
uint32_t ra;
bool abi_call0;
unsigned base;
@@ -165,6 +168,17 @@ void setup_rt_frame(int sig, struct target_sigaction *ka,
frame_addr = get_sigframe(ka, env, sizeof(*frame));
trace_user_setup_rt_frame(env, frame_addr);
+if (is_fdpic) {
+abi_ulong funcdesc_ptr = ka->_sa_handler;
+
+if (get_user_ual(handler, funcdesc_ptr)
+|| get_user_ual(handler_fdpic_GOT, funcdesc_ptr + 4)) {
+goto give_sigsegv;
+}
+} else {
+handler = ka->_sa_handler;
+}
+
if (!lock_user_struct(VERIFY_WRITE, frame, frame_addr, 0)) {
goto give_sigsegv;
}
@@ -185,14 +199,21 @@ void setup_rt_frame(int sig, struct target_sigaction *ka,
}
if (ka->sa_flags & TARGET_SA_RESTORER) {
-ra = ka->sa_restorer;
+if (is_fdpic) {
+if (get_user_ual(ra, ka->sa_restorer)) {
+unlock_user_struct(frame, frame_addr, 0);
+goto give_sigsegv;
+}
+} else {
+ra = ka->sa_restorer;
+}
} else {
/* Not used, but retain for ABI compatibility. */
install_sigtramp(frame->retcode);
ra = default_rt_sigreturn;
}
memset(env->regs, 0, sizeof(env->regs));
-env->pc = ka->_sa_handler;
+env->pc = handler;
env->regs[1] = frame_addr;
env->sregs[WINDOW_BASE] = 0;
env->sregs[WINDOW_START] = 1;
@@ -212,6 +233,9 @@ void setup_rt_frame(int sig, struct target_sigaction *ka,
env->regs[base + 3] = frame_addr + offsetof(struct target_rt_sigframe,
info);
env->regs[base + 4] = frame_addr + offsetof(struct target_rt_sigframe, uc);
+if (is_fdpic) {
+env->regs[base + 11] = handler_fdpic_GOT;
+}
unlock_user_struct(frame, frame_addr, 1);
return;
--
2.39.2
Re: [PATCH] MAINTAINERS: Add include/hw/xtensa/mx_pic.h to the XTFPAG machine section
On Tue, Nov 7, 2023 at 2:21 AM Thomas Huth wrote: > > These machines are the only user of the mx_pic code, so the > header (which is currently "unmaintained" according to the > MAINTAINERS file) should be added to this section. > > Signed-off-by: Thomas Huth > --- > MAINTAINERS | 1 + > 1 file changed, 1 insertion(+) Typo in subject: s/XTFPAG/XTFPGA/ Otherwise: Acked-by: Max Filippov -- Thanks. -- Max
Re: [PATCH 6/9] target/xtensa: Use tcg_gen_extract_i32
On Mon, Oct 23, 2023 at 9:10 AM Philippe Mathieu-Daudé wrote: > > Inspired-by: Richard Henderson > Signed-off-by: Philippe Mathieu-Daudé > --- > target/xtensa/translate.c | 6 +- > 1 file changed, 1 insertion(+), 5 deletions(-) Reviewed-by: Max Filippov -- Thanks. -- Max
Re: [PATCH 7/7] target/xtensa: Use tcg_gen_sextract_i32
On Thu, Oct 19, 2023 at 11:29 AM Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/xtensa/translate.c | 12 +--- > 1 file changed, 1 insertion(+), 11 deletions(-) Reviewed-by: Max Filippov -- Thanks. -- Max
Re: [RFC PATCH v2 31/78] target/xtensa: add fallthrough pseudo-keyword
On Fri, Oct 13, 2023 at 12:58 AM Emmanouil Pitsidianakis wrote: > > In preparation of raising -Wimplicit-fallthrough to 5, replace all > fall-through comments with the fallthrough attribute pseudo-keyword. > > Signed-off-by: Emmanouil Pitsidianakis > --- > target/xtensa/op_helper.c | 8 > target/xtensa/translate.c | 2 +- > 2 files changed, 5 insertions(+), 5 deletions(-) Reviewed-by: Max Filippov -- Thanks. -- Max
Re: [PATCH] target/xtensa: Assert that interrupt level is within bounds
On Tue, Jul 4, 2023 at 6:27 AM Peter Maydell wrote: > > On Sat, 24 Jun 2023 at 01:20, Max Filippov wrote: > > > > On Fri, Jun 23, 2023 at 8:41 AM Peter Maydell > > wrote: > > > > > > In handle_interrupt() we use level as an index into the interrupt_vector[] > > > array. This is safe because we have checked it against > > > env->config->nlevel, > > > but Coverity can't see that (and it is only true because each CPU config > > > sets its XCHAL_NUM_INTLEVELS to something less than MAX_NLEVELS), so it > > > complains about a possible array overrun (CID 1507131) > > > > > > Add an assert() which will make Coverity happy and catch the unlikely > > > case of a mis-set XCHAL_NUM_INTLEVELS in future. > > > > > > Signed-off-by: Peter Maydell > > > --- > > > NB: only tested with 'make check-avocado'. You could argue that we > > > should mark the coverity issue as false-positive instead if you like. > > > --- > > > target/xtensa/exc_helper.c | 3 +++ > > > 1 file changed, 3 insertions(+) > > > > Acked-by: Max Filippov > > Thanks. I'll take it via target-arm since I'm doing a pullreq > anyway, unless you'd prefer otherwise. It's good, please go ahead. -- Thanks. -- Max
Re: [PATCH] target/xtensa: Assert that interrupt level is within bounds
On Fri, Jun 23, 2023 at 8:41 AM Peter Maydell wrote: > > In handle_interrupt() we use level as an index into the interrupt_vector[] > array. This is safe because we have checked it against env->config->nlevel, > but Coverity can't see that (and it is only true because each CPU config > sets its XCHAL_NUM_INTLEVELS to something less than MAX_NLEVELS), so it > complains about a possible array overrun (CID 1507131) > > Add an assert() which will make Coverity happy and catch the unlikely > case of a mis-set XCHAL_NUM_INTLEVELS in future. > > Signed-off-by: Peter Maydell > --- > NB: only tested with 'make check-avocado'. You could argue that we > should mark the coverity issue as false-positive instead if you like. > --- > target/xtensa/exc_helper.c | 3 +++ > 1 file changed, 3 insertions(+) Acked-by: Max Filippov -- Thanks. -- Max
Re: [PATCH 17/22] hw/xtensa: add VIRTIO as dependencies for XTENSA_VIRT
On Wed, May 3, 2023 at 2:12 AM Alex Bennée wrote: > > These are needed for board creation so fail under "make check" with a > --without-default-devices build. > > Signed-off-by: Alex Bennée > --- > hw/xtensa/Kconfig | 2 ++ > 1 file changed, 2 insertions(+) Reviewed-by: Max Filippov -- Thanks. -- Max
Re: [PATCH 8/9] target/xtensa: Finish conversion to tcg_gen_qemu_{ld, st}_*
On Tue, May 2, 2023 at 6:57 AM Richard Henderson wrote: > > Convert away from the old interface with the implicit > MemOp argument. > > Signed-off-by: Richard Henderson > --- > target/xtensa/translate.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Reviewed-by: Max Filippov -- Thanks. -- Max
[PULL 0/2] target/xtensa TCG test updates
Hi Peter, please pull the following updates for the target/xtensa TCG tests. The following changes since commit 27a03171d02ee0de8de4e2d3bed241795d672859: Merge tag 'pull-tcg-20230313' of https://gitlab.com/rth7680/qemu into staging (2023-03-14 10:09:15 +) are available in the Git repository at: https://github.com/OSLL/qemu-xtensa.git tags/20230316-xtensa for you to fetch changes up to 51139fb3e7b05dd7daeca8f00748678ce9e087e5: tests/tcg/xtensa: allow testing big-endian cores (2023-03-15 05:08:04 -0700) target/xtensa updates for v8.0: - enable testing big-endian xtensa cores Max Filippov (2): tests/tcg/xtensa: add linker.ld to CLEANFILES tests/tcg/xtensa: allow testing big-endian cores MAINTAINERS| 1 + tests/tcg/xtensa/Makefile.softmmu-target | 5 +++-- tests/tcg/xtensaeb/Makefile.softmmu-target | 5 + 3 files changed, 9 insertions(+), 2 deletions(-) create mode 100644 tests/tcg/xtensaeb/Makefile.softmmu-target -- Thanks. -- Max
[PATCH] tests/tcg/xtensa: allow testing big-endian cores
Don't disable all big-endian tests, instead check whether $(CORE) is supported by the configured $(QEMU) and enable tests if it is. Signed-off-by: Max Filippov Reviewed-by: Philippe Mathieu-Daudé --- MAINTAINERS| 1 + tests/tcg/xtensa/Makefile.softmmu-target | 4 ++-- tests/tcg/xtensaeb/Makefile.softmmu-target | 5 + 3 files changed, 8 insertions(+), 2 deletions(-) create mode 100644 tests/tcg/xtensaeb/Makefile.softmmu-target diff --git a/MAINTAINERS b/MAINTAINERS index d51ddee0b94b..94faa804610e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -371,6 +371,7 @@ S: Maintained F: target/xtensa/ F: hw/xtensa/ F: tests/tcg/xtensa/ +F: tests/tcg/xtensaeb/ F: disas/xtensa.c F: include/hw/xtensa/xtensa-isa.h F: configs/devices/xtensa*/default.mak diff --git a/tests/tcg/xtensa/Makefile.softmmu-target b/tests/tcg/xtensa/Makefile.softmmu-target index 948c0e6506bd..ba6cd9fde3fe 100644 --- a/tests/tcg/xtensa/Makefile.softmmu-target +++ b/tests/tcg/xtensa/Makefile.softmmu-target @@ -2,7 +2,8 @@ # Xtensa softmmu tests # -ifneq ($(TARGET_BIG_ENDIAN),y) +CORE=dc232b +ifneq ($(shell $(QEMU) -cpu help | grep -w $(CORE)),) XTENSA_SRC = $(SRC_PATH)/tests/tcg/xtensa XTENSA_ALL = $(filter-out $(XTENSA_SRC)/linker.ld.S,$(wildcard $(XTENSA_SRC)/*.S)) @@ -15,7 +16,6 @@ XTENSA_USABLE_TESTS = $(filter-out $(XTENSA_BROKEN_TESTS), $(XTENSA_TESTS)) TESTS += $(XTENSA_USABLE_TESTS) VPATH += $(XTENSA_SRC) -CORE=dc232b QEMU_OPTS+=-M sim -cpu $(CORE) -nographic -semihosting -icount 6 $(EXTFLAGS) -kernel INCLUDE_DIRS = $(SRC_PATH)/target/xtensa/core-$(CORE) diff --git a/tests/tcg/xtensaeb/Makefile.softmmu-target b/tests/tcg/xtensaeb/Makefile.softmmu-target new file mode 100644 index ..4204a96d53c0 --- /dev/null +++ b/tests/tcg/xtensaeb/Makefile.softmmu-target @@ -0,0 +1,5 @@ +# +# Xtensa softmmu tests +# + +include $(SRC_PATH)/tests/tcg/xtensa/Makefile.softmmu-target -- 2.30.2
Re: [PATCH] tests/tcg/xtensa: add linker.ld to CLEANFILES
On Tue, Mar 14, 2023 at 4:41 PM Wilfred Mallawa wrote: > > On Tue, 2023-03-14 at 15:08 -0700, Max Filippov wrote: > > Linker script for xtensa tests must be preprocessed for a specific > > target, remove it as a part of make clean. > > > > Signed-off-by: Max Filippov > > --- > > tests/tcg/xtensa/Makefile.softmmu-target | 1 + > > 1 file changed, 1 insertion(+) > Wilfred Mallawa The tag is missing, I assume you meant Reviewed-by. -- Thanks. -- Max
[PATCH] tests/tcg/xtensa: add linker.ld to CLEANFILES
Linker script for xtensa tests must be preprocessed for a specific target, remove it as a part of make clean. Signed-off-by: Max Filippov --- tests/tcg/xtensa/Makefile.softmmu-target | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/tcg/xtensa/Makefile.softmmu-target b/tests/tcg/xtensa/Makefile.softmmu-target index 973e55298ee4..948c0e6506bd 100644 --- a/tests/tcg/xtensa/Makefile.softmmu-target +++ b/tests/tcg/xtensa/Makefile.softmmu-target @@ -26,6 +26,7 @@ ASFLAGS = -Wa,--no-absolute-literals LDFLAGS = -Tlinker.ld -nostartfiles -nostdlib CRT= crt.o vectors.o +CLEANFILES += linker.ld linker.ld: linker.ld.S $(CC) $(XTENSA_INC) -E -P $< -o $@ -- 2.30.2
Re: [PATCH 67/70] target/xtensa: Avoid tcg_const_i32
On Sun, Feb 26, 2023 at 9:48 PM Richard Henderson wrote: > > All remaining uses are strictly read-only. > > Signed-off-by: Richard Henderson > --- > target/xtensa/translate.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) Reviewed-by: Max Filippov -- Thanks. -- Max
Re: [PATCH 66/70] target/xtensa: Split constant in bit shift
On Sun, Feb 26, 2023 at 9:48 PM Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/xtensa/translate.c | 8 > 1 file changed, 4 insertions(+), 4 deletions(-) Reviewed-by: Max Filippov -- Thanks. -- Max
Re: [PATCH 65/70] target/xtensa: Use tcg_gen_subfi_i32 in translate_sll
On Sun, Feb 26, 2023 at 9:48 PM Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/xtensa/translate.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Reviewed-by: Max Filippov -- Thanks. -- Max
Re: [PATCH 64/70] target/xtensa: Avoid tcg_const_i32 in translate_l32r
On Sun, Feb 26, 2023 at 9:48 PM Richard Henderson wrote: > > Use addi on the addition side and tcg_constant_i32 on the other. > > Signed-off-by: Richard Henderson > --- > target/xtensa/translate.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) Reviewed-by: Max Filippov -- Thanks. -- Max
Re: [PATCH 63/70] target/xtensa: Tidy translate_clamps
On Sun, Feb 26, 2023 at 9:48 PM Richard Henderson wrote: > > All writes to arg[0].out; use tcg_constant_i32. > > Signed-off-by: Richard Henderson > --- > target/xtensa/translate.c | 8 > 1 file changed, 4 insertions(+), 4 deletions(-) Reviewed-by: Max Filippov -- Thanks. -- Max
Re: [PATCH 62/70] target/xtensa: Tidy translate_bb
On Sun, Feb 26, 2023 at 9:48 PM Richard Henderson wrote: > > Replace ifdefs with C, tcg_const_i32 with tcg_constant_i32. > We only need a single temporary for this. > > Signed-off-by: Richard Henderson > --- > target/xtensa/translate.c | 18 +++--- > 1 file changed, 7 insertions(+), 11 deletions(-) Reviewed-by: Max Filippov -- Thanks. -- Max
Re: [PATCH qemu] timer/i8254: Fix one shot PIT mode
On Sun, Feb 26, 2023 at 1:18 AM Damien Zammit wrote: > > Hi Michael, > > Thanks for reviewing this on a weekend! > > On 26/2/23 19:51, Michael S. Tsirkin wrote: > > On Sun, Feb 26, 2023 at 01:58:10AM +, Damien Zammit wrote: > >> case 0: > >> -out = (d >= s->count); > >> -break; > > > > > > I think you need something like > > /* FALLTHRU */ > > here otherwise some gcc versions will warn. > > > >> case 1: > >> -out = (d < s->count); > >> +out = (d >= s->count); > > It seems that there are quite a number of these consecutive fallthrough cases > without /* FALLTHRU */ in i8254_common.c > > Can these be fixed in a separate patch? I believe that the comment is only needed when there's code between the labels and is not needed between the labels that follow each other. -- Thanks. -- Max
Re: [PATCH 72/76] target/xtensa: Drop tcg_temp_free
On Sat, Feb 25, 2023 at 1:20 AM Richard Henderson wrote: > > Translators are no longer required to free tcg temporaries. > > Signed-off-by: Richard Henderson > --- > target/xtensa/translate.c | 107 -- > 1 file changed, 107 deletions(-) Reviewed-by: Max Filippov -- Thanks. -- Max
Re: [PATCH 71/76] target/sparc: Drop reset_sar_tracker
On Sat, Feb 25, 2023 at 1:20 AM Richard Henderson wrote: > > Translators are no longer required to free tcg temporaries. > Remove sar_m32_allocated, as sar_m32 non-null is equivalent. > > Signed-off-by: Richard Henderson > --- > target/xtensa/translate.c | 14 ++ > 1 file changed, 2 insertions(+), 12 deletions(-) There should be 'target/xtensa' in the subject. Reviewed-by: Max Filippov -- Thanks. -- Max
[PATCH] linux-user: add support for xtensa FDPIC
Define xtensa-specific info_is_fdpic and fill in FDPIC-specific
registers in the xtensa version of init_thread.
Signed-off-by: Max Filippov
---
include/elf.h| 1 +
linux-user/elfload.c | 16 +++-
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/include/elf.h b/include/elf.h
index 8bf1e72720d5..e8bfe38a9fbd 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -1619,6 +1619,7 @@ typedef struct elf64_shdr {
#define ELFOSABI_MODESTO11 /* Novell Modesto. */
#define ELFOSABI_OPENBSD12 /* OpenBSD. */
#define ELFOSABI_ARM_FDPIC 65 /* ARM FDPIC */
+#define ELFOSABI_XTENSA_FDPIC 65 /* Xtensa FDPIC */
#define ELFOSABI_ARM97 /* ARM */
#define ELFOSABI_STANDALONE 255 /* Standalone (embedded) application */
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 5928c14dfc97..150d1d450396 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -1748,6 +1748,15 @@ static inline void init_thread(struct target_pt_regs
*regs,
regs->windowstart = 1;
regs->areg[1] = infop->start_stack;
regs->pc = infop->entry;
+if (info_is_fdpic(infop)) {
+regs->areg[4] = infop->loadmap_addr;
+regs->areg[5] = infop->interpreter_loadmap_addr;
+if (infop->interpreter_loadmap_addr) {
+regs->areg[6] = infop->interpreter_pt_dynamic_addr;
+} else {
+regs->areg[6] = infop->pt_dynamic_addr;
+}
+}
}
/* See linux kernel: arch/xtensa/include/asm/elf.h. */
@@ -2207,11 +2216,16 @@ static void zero_bss(abi_ulong elf_bss, abi_ulong
last_bss, int prot)
}
}
-#ifdef TARGET_ARM
+#if defined(TARGET_ARM)
static int elf_is_fdpic(struct elfhdr *exec)
{
return exec->e_ident[EI_OSABI] == ELFOSABI_ARM_FDPIC;
}
+#elif defined(TARGET_XTENSA)
+static int elf_is_fdpic(struct elfhdr *exec)
+{
+return exec->e_ident[EI_OSABI] == ELFOSABI_XTENSA_FDPIC;
+}
#else
/* Default implementation, always false. */
static int elf_is_fdpic(struct elfhdr *exec)
--
2.30.2
Re: [PATCH 1/1] Fix some typos
On Tue, Nov 29, 2022 at 6:08 PM Dongdong Zhang wrote: > diff --git a/python/qemu/machine/qtest.py b/python/qemu/machine/qtest.py > index 1a1fc6c9b0..906bd13298 100644 > --- a/python/qemu/machine/qtest.py > +++ b/python/qemu/machine/qtest.py > @@ -42,7 +42,7 @@ class QEMUQtestProtocol: > :raise socket.error: on socket connection errors > > .. note:: > - No conection is estabalished by __init__(), this is done > + No connection is estabalished by __init__(), this is done There are two typos in this line, the other one is 'estabalished'. -- Thanks. -- Max
Re: [PATCH v2 19/21] gdbstub: move register helpers into standalone include
On Thu, Jan 5, 2023 at 8:51 AM Alex Bennée wrote: > > These inline helpers are all used by target specific code so move them > out of the general header so we don't needlessly pollute the rest of > the API with target specific stuff. > > Note we have to include cpu.h in semihosting as it was relying on a > side effect before. > > Signed-off-by: Alex Bennée > --- > target/xtensa/core-dc232b.c| 2 +- > target/xtensa/core-dc233c.c| 2 +- > target/xtensa/core-de212.c | 2 +- > target/xtensa/core-de233_fpu.c | 2 +- > target/xtensa/core-dsp3400.c | 2 +- > target/xtensa/core-fsf.c | 2 +- > target/xtensa/core-lx106.c | 2 +- > target/xtensa/core-sample_controller.c | 2 +- > target/xtensa/core-test_kc705_be.c | 2 +- > target/xtensa/core-test_mmuhifi_c3.c | 2 +- > target/xtensa/gdbstub.c| 2 +- > target/xtensa/helper.c | 2 +- Please update the target/xtensa/import_core.sh as well. -- Thanks. -- Max
Re: [PATCH] cleanup: Tweak and re-run return_directly.cocci
On Mon, Nov 21, 2022 at 6:01 AM Markus Armbruster wrote: > .../xtensa/core-dsp3400/xtensa-modules.c.inc | 136 +- > target/xtensa/core-lx106/xtensa-modules.c.inc | 16 +-- These files are generated and were imported from xtensa configuration overlays, they're not supposed to be changed. -- Thanks. -- Max
Re: [PATCH 6/7] target/xtensa: Honour -semihosting-config userspace=on
On Mon, Aug 15, 2022 at 12:03 PM Peter Maydell wrote: > > Honour the commandline -semihosting-config userspace=on option, > instead of always permitting userspace semihosting calls in system > emulation mode, by passing the correct value to the is_userspace > argument of semihosting_enabled(). > > Note that this is a behaviour change: if the user wants to > do semihosting calls from userspace they must now specifically > enable them on the command line. > > xtensa semihosting is not implemented for linux-user builds. > > Signed-off-by: Peter Maydell > --- > target/xtensa/translate.c | 7 --- > 1 file changed, 4 insertions(+), 3 deletions(-) Acked-by: Max Filippov -- Thanks. -- Max
Re: [PATCH v5 2/2] target/xtensa: Use semihosting/syscalls.h
On Wed, Jun 29, 2022 at 3:14 AM Alex Bennée wrote: > Max Filippov writes: > > There's no notion of 'serial hardware' for the xtensa-sim, all it has is > > the three standard stdio file descriptors. > > Which are accessed via semihosting calls? Yes. > Are they implicitly mapped to > 3 chardev devices for stdin, stdout and stderr? In the absence of -serial option they are not mapped. In the presence of that option they are mapped to the single chardev that was passed as the parameter of that option. > > But it was convenient thinking > > of them as a serial port. I agree that no magic is needed here, but > > the change shouldn't be quiet eiter, so xtensa-sim should warn (or > > maybe even quit with an error code) when it sees the -serial option. > > If the default chardevs already map to the 3 FDs then perhaps -serial > should be invalid because it is more explicit to use -chardev to > redirect the stream you want somewhere else. However I don't see them at > the moment: > > ➜ ./qemu-system-xtensa -M sim -semihosting -S -display none -monitor stdio > QEMU 7.0.50 monitor - type 'help' for more information > (qemu) info chardev > compat_monitor0: filename=stdio > parallel0: filename=vc Well, that mapping was done by me, manually (grep for sim_console in the target/xtensa/xtensa-semi.c), so no wonder that parts like this don't work. -- Thanks. -- Max
Re: [PATCH v5 2/2] target/xtensa: Use semihosting/syscalls.h
On Wed, Jun 29, 2022 at 1:09 AM Alex Bennée wrote:
> Richard Henderson writes:
> > On 6/28/22 19:08, Max Filippov wrote:
> >> On Tue, Jun 28, 2022 at 4:43 AM Richard Henderson
> >> wrote:
> >>> }
> >>> -if (serial_hd(0)) {
> >>> -xtensa_sim_open_console(serial_hd(0));
> >>> -}
> >> I've noticed that with this change '-serial stdio' and its variants
> >> are still
> >> accepted in the command line, but now they do nothing.
> >
> > Pardon? They certainly will do something, via writes to the serial
> > hardware.
> >
> >
> >> This quiet
> >> change of behavior is unfortunate. I wonder if it would be acceptable
> >> to map the '-serial stdio' option in the presence of '-semihosting' to
> >> something like '-chardev stdio,id=id1 -semihosting-config chardev=id1'?
> >
> > I dunno. I'm wary of having xtensa be unique here. Alex, thoughts?
>
> Is semihosting *the* serial hardware for xtensa-sim or is it overriding
> another serial interface? I'm wary of adding more magical behaviour for
> -serial as it can be confusing enough already what actually gets routed
> to it if not doing everything explicitly.
There's no notion of 'serial hardware' for the xtensa-sim, all it has is
the three standard stdio file descriptors. But it was convenient thinking
of them as a serial port. I agree that no magic is needed here, but
the change shouldn't be quiet eiter, so xtensa-sim should warn (or
maybe even quit with an error code) when it sees the -serial option.
--
Thanks.
-- Max
Re: [PATCH v5 2/2] target/xtensa: Use semihosting/syscalls.h
On Tue, Jun 28, 2022 at 5:36 PM Richard Henderson
wrote:
> On 6/28/22 19:08, Max Filippov wrote:
> > On Tue, Jun 28, 2022 at 4:43 AM Richard Henderson
> > wrote:
...
> >> diff --git a/hw/xtensa/sim.c b/hw/xtensa/sim.c
> >> index 946c71cb5b..5cca6a170e 100644
> >> --- a/hw/xtensa/sim.c
> >> +++ b/hw/xtensa/sim.c
> >> @@ -87,9 +87,6 @@ XtensaCPU *xtensa_sim_common_init(MachineState *machine)
> >> xtensa_create_memory_regions(, "xtensa.sysram",
> >>get_system_memory());
> >> }
> >> -if (serial_hd(0)) {
> >> -xtensa_sim_open_console(serial_hd(0));
> >> -}
> >
> > I've noticed that with this change '-serial stdio' and its variants are
> > still
> > accepted in the command line, but now they do nothing.
>
> Pardon? They certainly will do something, via writes to the serial hardware.
What I meant was that with '-serial' option prior to this change it was
possible to redirect the standard streams of the sim machine, to stdio,
or socket or wherever, but after this change the option will be accepted,
but the machine will always have its first three file descriptors connected
to the QEMU's first three file descriptors.
I'd print a warning here, saying that the behavior has changed and
the '-semihosting-config chardev' must be used now.
> > This quiet
> > change of behavior is unfortunate. I wonder if it would be acceptable
> > to map the '-serial stdio' option in the presence of '-semihosting' to
> > something like '-chardev stdio,id=id1 -semihosting-config chardev=id1'?
>
> I dunno. I'm wary of having xtensa be unique here. Alex, thoughts?
Yeah, I thought about it some more and now it doesn't look like a good
idea to me either.
> >> +switch (regs[4]) {
> >> +case SELECT_ONE_READ:
> >> +events = G_IO_IN;
> >> +break;
> >> +case SELECT_ONE_WRITE:
> >> +events = G_IO_OUT;
> >> +break;
> >> +case SELECT_ONE_EXCEPT:
> >> +events = G_IO_PRI;
> >> +break;
> >> +default:
> >> +xtensa_cb(cs, -1, EINVAL);
> >
> > This doesn't match what there used to be: it was possible to call
> > select_one with rq other than SELECT_ONE_* and that would've
> > passed NULL for all fd sets in the select invocation turning it into
> > a sleep. It would return 0 after the timeout.
>
> Hmm. Is there any documentation of what it was *supposed* to do? Passing rq
> ==
> 0xdeadbeef and expecting a specific behaviour seems odd.
I haven't found any documentation for that simcall.
All I can say is that the logic in the code that used to be here is matching
exactly the logic in the code of the xtensa ISS from Cadence/Tensilica.
--
Thanks.
-- Max
running softmmu tcg target tests locally
Hello,
there used to be an option to run tcg tests for a softmmu target with
make check-tcg
but since the commit 5377a1000192 ("tests/tcg: list test targets in
Makefile.prereqs")
it is no longer working for me.
Is it supposed to be working and was broken by accident? Or what is the correct
way to run these tests now?
--
Thanks.
-- Max
Re: [PATCH v5 0/2] target/xtensa: semihosting cleanup
On Tue, Jun 28, 2022 at 4:43 AM Richard Henderson wrote: > > Changes for v5: > * Rebase on master. > > r~ > > > Richard Henderson (2): > target/xtensa: Use an exception for semihosting > target/xtensa: Use semihosting/syscalls.h > > target/xtensa/cpu.h | 3 +- > target/xtensa/helper.h | 3 - > hw/xtensa/sim.c | 3 - > target/xtensa/exc_helper.c | 4 + > target/xtensa/translate.c | 3 +- > target/xtensa/xtensa-semi.c | 229 > 6 files changed, 59 insertions(+), 186 deletions(-) Tested-by: Max Filippov -- Thanks. -- Max
Re: [PATCH v5 2/2] target/xtensa: Use semihosting/syscalls.h
On Tue, Jun 28, 2022 at 4:43 AM Richard Henderson
wrote:
>
> This separates guest file descriptors from host file descriptors,
> and utilizes shared infrastructure for integration with gdbstub.
> Remove the xtensa custom console handing and rely on the
> generic -semihosting-config handling of chardevs.
>
> Signed-off-by: Richard Henderson
> ---
> target/xtensa/cpu.h | 1 -
> hw/xtensa/sim.c | 3 -
> target/xtensa/xtensa-semi.c | 226
> 3 files changed, 50 insertions(+), 180 deletions(-)
>
> diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
> index ea66895e7f..99ac3efd71 100644
> --- a/target/xtensa/cpu.h
> +++ b/target/xtensa/cpu.h
> @@ -612,7 +612,6 @@ void xtensa_translate_init(void);
> void **xtensa_get_regfile_by_name(const char *name, int entries, int bits);
> void xtensa_breakpoint_handler(CPUState *cs);
> void xtensa_register_core(XtensaConfigList *node);
> -void xtensa_sim_open_console(Chardev *chr);
> void check_interrupts(CPUXtensaState *s);
> void xtensa_irq_init(CPUXtensaState *env);
> qemu_irq *xtensa_get_extints(CPUXtensaState *env);
> diff --git a/hw/xtensa/sim.c b/hw/xtensa/sim.c
> index 946c71cb5b..5cca6a170e 100644
> --- a/hw/xtensa/sim.c
> +++ b/hw/xtensa/sim.c
> @@ -87,9 +87,6 @@ XtensaCPU *xtensa_sim_common_init(MachineState *machine)
> xtensa_create_memory_regions(, "xtensa.sysram",
> get_system_memory());
> }
> -if (serial_hd(0)) {
> -xtensa_sim_open_console(serial_hd(0));
> -}
I've noticed that with this change '-serial stdio' and its variants are still
accepted in the command line, but now they do nothing. This quiet
change of behavior is unfortunate. I wonder if it would be acceptable
to map the '-serial stdio' option in the presence of '-semihosting' to
something like '-chardev stdio,id=id1 -semihosting-config chardev=id1'?
> @@ -194,165 +169,64 @@ void xtensa_semihosting(CPUXtensaState *env)
...
> case TARGET_SYS_select_one:
> {
> -uint32_t fd = regs[3];
> -uint32_t rq = regs[4];
> -uint32_t target_tv = regs[5];
> -uint32_t target_tvv[2];
> +int timeout, events;
>
> -struct timeval tv = {0};
> +if (regs[5]) {
> +uint32_t tv_sec, tv_usec;
> +uint64_t msec;
>
> -if (target_tv) {
> -cpu_memory_rw_debug(cs, target_tv,
> -(uint8_t *)target_tvv, sizeof(target_tvv), 0);
> -tv.tv_sec = (int32_t)tswap32(target_tvv[0]);
> -tv.tv_usec = (int32_t)tswap32(target_tvv[1]);
> -}
> -if (fd < 3 && sim_console) {
> -if ((fd == 1 || fd == 2) && rq == SELECT_ONE_WRITE) {
> -regs[2] = 1;
> -} else if (fd == 0 && rq == SELECT_ONE_READ) {
> -regs[2] = sim_console->input.offset > 0;
> -} else {
> -regs[2] = 0;
> +if (get_user_u32(tv_sec, regs[5]) ||
> +get_user_u32(tv_usec, regs[5])) {
get_user_u32(tv_usec, regs[5] + 4)?
> +xtensa_cb(cs, -1, EFAULT);
> +return;
> }
> -regs[3] = 0;
> -} else {
> -fd_set fdset;
>
> -FD_ZERO();
> -FD_SET(fd, );
> -regs[2] = select(fd + 1,
> - rq == SELECT_ONE_READ ? : NULL,
> - rq == SELECT_ONE_WRITE ? : NULL,
> - rq == SELECT_ONE_EXCEPT ? : NULL,
> - target_tv ? : NULL);
> -regs[3] = errno_h2g(errno);
> +/* Poll timeout is in milliseconds; overflow to infinity. */
> +msec = tv_sec * 1000ull + DIV_ROUND_UP(tv_usec, 1000ull);
> +timeout = msec <= INT32_MAX ? msec : -1;
> +} else {
> +timeout = -1;
> }
> +
> +switch (regs[4]) {
> +case SELECT_ONE_READ:
> +events = G_IO_IN;
> +break;
> +case SELECT_ONE_WRITE:
> +events = G_IO_OUT;
> +break;
> +case SELECT_ONE_EXCEPT:
> +events = G_IO_PRI;
> +break;
> +default:
> +xtensa_cb(cs, -1, EINVAL);
This doesn't match what there used to be: it was possible to call
select_one with rq other than SELECT_ONE_* and that would've
passed NULL for all fd sets in the select invocation turning it into
a sleep. It would return 0 after the timeout.
--
Thanks.
-- Max
Re: [PATCH v4 2/2] target/xtensa: Use semihosting/syscalls.h
On Tue, Jun 7, 2022 at 10:36 PM Richard Henderson
wrote:
>
> This separates guest file descriptors from host file descriptors,
> and utilizes shared infrastructure for integration with gdbstub.
> Remove the xtensa custom console handing and rely on the
> generic -semihosting-config handling of chardevs.
>
> Signed-off-by: Richard Henderson
> ---
> target/xtensa/cpu.h | 1 -
> hw/xtensa/sim.c | 3 -
> target/xtensa/xtensa-semi.c | 323 +++-
> 3 files changed, 97 insertions(+), 230 deletions(-)
>
> diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
> index ea66895e7f..99ac3efd71 100644
> --- a/target/xtensa/cpu.h
> +++ b/target/xtensa/cpu.h
> @@ -612,7 +612,6 @@ void xtensa_translate_init(void);
> void **xtensa_get_regfile_by_name(const char *name, int entries, int bits);
> void xtensa_breakpoint_handler(CPUState *cs);
> void xtensa_register_core(XtensaConfigList *node);
> -void xtensa_sim_open_console(Chardev *chr);
> void check_interrupts(CPUXtensaState *s);
> void xtensa_irq_init(CPUXtensaState *env);
> qemu_irq *xtensa_get_extints(CPUXtensaState *env);
> diff --git a/hw/xtensa/sim.c b/hw/xtensa/sim.c
> index 946c71cb5b..5cca6a170e 100644
> --- a/hw/xtensa/sim.c
> +++ b/hw/xtensa/sim.c
> @@ -87,9 +87,6 @@ XtensaCPU *xtensa_sim_common_init(MachineState *machine)
> xtensa_create_memory_regions(, "xtensa.sysram",
> get_system_memory());
> }
> -if (serial_hd(0)) {
> -xtensa_sim_open_console(serial_hd(0));
> -}
Do I understand correctly that the sim machine will no longer
support the -serial option with this change?
> return cpu;
> }
>
> diff --git a/target/xtensa/xtensa-semi.c b/target/xtensa/xtensa-semi.c
> index 5375f106fc..7ef4be353e 100644
> --- a/target/xtensa/xtensa-semi.c
> +++ b/target/xtensa/xtensa-semi.c
> @@ -27,8 +27,10 @@
>
> #include "qemu/osdep.h"
> #include "cpu.h"
> -#include "chardev/char-fe.h"
> +#include "exec/gdbstub.h"
> #include "semihosting/semihost.h"
> +#include "semihosting/syscalls.h"
This does not build on top of the current master, is there a branch where
it's buildable?
...
> -switch (host_errno) {
> -case 0: return 0;
> -case EPERM: return TARGET_EPERM;
> -case ENOENT:return TARGET_ENOENT;
> -case ESRCH: return TARGET_ESRCH;
> -case EINTR: return TARGET_EINTR;
> -case EIO: return TARGET_EIO;
> -case ENXIO: return TARGET_ENXIO;
> -case E2BIG: return TARGET_E2BIG;
> -case ENOEXEC: return TARGET_ENOEXEC;
> -case EBADF: return TARGET_EBADF;
> -case ECHILD:return TARGET_ECHILD;
> -case EAGAIN:return TARGET_EAGAIN;
> -case ENOMEM:return TARGET_ENOMEM;
> -case EACCES:return TARGET_EACCES;
> -case EFAULT:return TARGET_EFAULT;
> -#ifdef ENOTBLK
> -case ENOTBLK: return TARGET_ENOTBLK;
> -#endif
AFAIR there were reports that qemu doesn't build on some
systems because they were missing ENOTBLK and other
error codes that were made conditional here.
...
> +#define E(N) case E##N: err = TARGET_E##N; break
...
> +E(PERM);
> +E(NOENT);
> +E(SRCH);
> +E(INTR);
> +E(IO);
> +E(NXIO);
> +E(2BIG);
> +E(NOEXEC);
> +E(BADF);
> +E(CHILD);
> +E(AGAIN);
> +E(NOMEM);
> +E(ACCES);
> +E(FAULT);
> +E(NOTBLK);
> +E(BUSY);
> +E(EXIST);
> +E(XDEV);
> +E(NODEV);
> +E(NOTDIR);
> +E(ISDIR);
> +E(INVAL);
> +E(NFILE);
> +E(MFILE);
> +E(NOTTY);
> +E(TXTBSY);
> +E(FBIG);
> +E(NOSPC);
> +E(SPIPE);
> +E(ROFS);
> +E(MLINK);
> +E(PIPE);
> +E(DOM);
> +E(RANGE);
> +E(NOSYS);
> +E(LOOP);
I'm not sure mangling error code names is a good idea.
--
Thanks.
-- Max
[PULL v2 00/18] target/xtensa updates for v7.1
Hello, please pull the following updates for the target/xtensa. Changes since v1: - rebase series to the current master - drop big-endian tests enabling patch (cannot test it because of the test infrastructure change) - add cache testing opcodes patch The following changes since commit 31abf61c4929a91275fe32f1fafe6e6b3e840b2a: Merge tag 'pull-ppc-20220505' of https://gitlab.com/danielhb/qemu into staging (2022-05-05 13:52:22 -0500) are available in the Git repository at: https://github.com/OSLL/qemu-xtensa.git tags/20220506-xtensa-1 for you to fetch changes up to 59491e97f89eaeee275f57fb6bb40f0152429fb3: target/xtensa: implement cache test option opcodes (2022-05-06 15:37:10 -0700) target/xtensa updates for v7.1: - expand test coverage to MMUv3, cores without windowed registers or loop option; - import lx106 core (used in the esp8266 IoT chips); - use tcg_constant_* in the front end; - add clock input to the xtensa CPU; - fix reset state of the xtensa MX PIC; - implement cache testing opcodes. Max Filippov (17): target/xtensa: fix missing tcg_temp_free in gen_window_check target/xtensa: use tcg_contatnt_* for numeric literals target/xtensa: use tcg_constant_* for exceptions target/xtensa: use tcg_constant_* for TLB opcodes target/xtensa: use tcg_constant_* for numbered special registers target/xtensa: use tcg_constant_* for FPU conversion opcodes target/xtensa: use tcg_constant_* for remaining opcodes target/xtensa: add clock input to xtensa CPU hw/xtensa: fix reset value of MIROUT register of MX PIC tests/tcg/xtensa: fix build for cores without windowed registers tests/tcg/xtensa: restore vecbase SR after test tests/tcg/xtensa: fix watchpoint test tests/tcg/xtensa: remove dependency on the loop option tests/tcg/xtensa: enable autorefill phys_mem tests for MMUv3 tests/tcg/xtensa: enable mmu tests for MMUv3 tests/tcg/xtensa: fix vectors and checks in timer test target/xtensa: implement cache test option opcodes Simon Safar (1): target/xtensa: import core lx106 hw/xtensa/mx_pic.c|2 +- target/xtensa/core-lx106.c| 51 + target/xtensa/core-lx106/core-isa.h | 470 ++ target/xtensa/core-lx106/gdb-config.c.inc | 83 + target/xtensa/core-lx106/xtensa-modules.c.inc | 7668 + target/xtensa/cores.list |1 + target/xtensa/cpu.c | 15 + target/xtensa/cpu.h |5 + target/xtensa/op_helper.c |7 +- target/xtensa/translate.c | 211 +- tests/tcg/xtensa/crt.S|2 + tests/tcg/xtensa/test_break.S | 86 +- tests/tcg/xtensa/test_mmu.S | 182 +- tests/tcg/xtensa/test_phys_mem.S | 10 +- tests/tcg/xtensa/test_sr.S|2 + tests/tcg/xtensa/test_timer.S | 68 +- 16 files changed, 8604 insertions(+), 259 deletions(-) create mode 100644 target/xtensa/core-lx106.c create mode 100644 target/xtensa/core-lx106/core-isa.h create mode 100644 target/xtensa/core-lx106/gdb-config.c.inc create mode 100644 target/xtensa/core-lx106/xtensa-modules.c.inc -- Thanks. -- Max
[PULL 00/18] target/xtensa updates for v7.1
Hello, please pull the following updates for the target/xtensa. The following changes since commit 823a3f11fb8f04c3c3cc0f95f968fef1bfc6534f: Update version for v7.0.0 release (2022-04-19 18:44:36 +0100) are available in the Git repository at: https://github.com/OSLL/qemu-xtensa.git tags/20220506-xtensa for you to fetch changes up to 5e1d80a3fc16d5dbe7d677af6ba4df94d68c75d2: tests/tcg/xtensa: fix vectors and checks in timer test (2022-04-27 10:15:23 -0700) target/xtensa updates for v7.1: - expand test coverage to big-endian, MMUv3, cores without windowed registers or loop option; - import lx106 core (used in the esp8266 IoT chips); - use tcg_constant_* in the front end; - add clock input to the xtensa CPU; - fix reset state of the xtensa MX PIC. Max Filippov (17): tests/tcg/xtensa: allow testing big-endian cores target/xtensa: fix missing tcg_temp_free in gen_window_check target/xtensa: use tcg_contatnt_* for numeric literals target/xtensa: use tcg_constant_* for exceptions target/xtensa: use tcg_constant_* for TLB opcodes target/xtensa: use tcg_constant_* for numbered special registers target/xtensa: use tcg_constant_* for FPU conversion opcodes target/xtensa: use tcg_constant_* for remaining opcodes target/xtensa: add clock input to xtensa CPU hw/xtensa: fix reset value of MIROUT register of MX PIC tests/tcg/xtensa: fix build for cores without windowed registers tests/tcg/xtensa: restore vecbase SR after test tests/tcg/xtensa: fix watchpoint test tests/tcg/xtensa: remove dependency on the loop option tests/tcg/xtensa: enable autorefill phys_mem tests for MMUv3 tests/tcg/xtensa: enable mmu tests for MMUv3 tests/tcg/xtensa: fix vectors and checks in timer test Simon Safar (1): target/xtensa: import core lx106 MAINTAINERS |1 + hw/xtensa/mx_pic.c|2 +- target/xtensa/core-lx106.c| 52 + target/xtensa/core-lx106/core-isa.h | 470 ++ target/xtensa/core-lx106/gdb-config.c.inc | 83 + target/xtensa/core-lx106/xtensa-modules.c.inc | 7668 + target/xtensa/cores.list |1 + target/xtensa/cpu.c | 15 + target/xtensa/cpu.h |5 + target/xtensa/op_helper.c |7 +- target/xtensa/translate.c | 173 +- tests/tcg/xtensa/Makefile.softmmu-target |4 +- tests/tcg/xtensa/crt.S|2 + tests/tcg/xtensa/test_break.S | 86 +- tests/tcg/xtensa/test_mmu.S | 182 +- tests/tcg/xtensa/test_phys_mem.S | 10 +- tests/tcg/xtensa/test_sr.S|2 + tests/tcg/xtensa/test_timer.S | 68 +- tests/tcg/xtensaeb/Makefile.softmmu-target|5 + 19 files changed, 8575 insertions(+), 261 deletions(-) create mode 100644 target/xtensa/core-lx106.c create mode 100644 target/xtensa/core-lx106/core-isa.h create mode 100644 target/xtensa/core-lx106/gdb-config.c.inc create mode 100644 target/xtensa/core-lx106/xtensa-modules.c.inc create mode 100644 tests/tcg/xtensaeb/Makefile.softmmu-target -- Thanks. -- Max
[PATCH] target/xtensa: implement cache test option opcodes
We don't model caches, so for l*ct opcodes return tags with all bits
(including Valid) set to 0. For all other opcodes don't do anything.
Signed-off-by: Max Filippov
---
target/xtensa/translate.c | 38 ++
1 file changed, 38 insertions(+)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 0cc44e9b3aba..3ade428a1bd3 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -1765,6 +1765,12 @@ static void translate_ldst(DisasContext *dc, const
OpcodeArg arg[],
tcg_temp_free(addr);
}
+static void translate_lct(DisasContext *dc, const OpcodeArg arg[],
+ const uint32_t par[])
+{
+tcg_gen_movi_i32(arg[0].out, 0);
+}
+
static void translate_l32r(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
@@ -3318,6 +3324,14 @@ static const XtensaOpcodeOps core_ops[] = {
.translate = translate_ldst,
.par = (const uint32_t[]){MO_UB, false, false},
.op_flags = XTENSA_OP_LOAD,
+}, {
+.name = "ldct",
+.translate = translate_lct,
+.op_flags = XTENSA_OP_PRIVILEGED,
+}, {
+.name = "ldcw",
+.translate = translate_nop,
+.op_flags = XTENSA_OP_PRIVILEGED,
}, {
.name = "lddec",
.translate = translate_mac16,
@@ -3331,6 +3345,14 @@ static const XtensaOpcodeOps core_ops[] = {
}, {
.name = "ldpte",
.op_flags = XTENSA_OP_ILL,
+}, {
+.name = "lict",
+.translate = translate_lct,
+.op_flags = XTENSA_OP_PRIVILEGED,
+}, {
+.name = "licw",
+.translate = translate_nop,
+.op_flags = XTENSA_OP_PRIVILEGED,
}, {
.name = (const char * const[]) {
"loop", "loop.w15", NULL,
@@ -4634,12 +4656,28 @@ static const XtensaOpcodeOps core_ops[] = {
.name = "saltu",
.translate = translate_salt,
.par = (const uint32_t[]){TCG_COND_LTU},
+}, {
+.name = "sdct",
+.translate = translate_nop,
+.op_flags = XTENSA_OP_PRIVILEGED,
+}, {
+.name = "sdcw",
+.translate = translate_nop,
+.op_flags = XTENSA_OP_PRIVILEGED,
}, {
.name = "setb_expstate",
.translate = translate_setb_expstate,
}, {
.name = "sext",
.translate = translate_sext,
+}, {
+.name = "sict",
+.translate = translate_nop,
+.op_flags = XTENSA_OP_PRIVILEGED,
+}, {
+.name = "sicw",
+.translate = translate_nop,
+.op_flags = XTENSA_OP_PRIVILEGED,
}, {
.name = "simcall",
.translate = translate_simcall,
--
2.30.2
[PATCH 6/7] tests/tcg/xtensa: enable mmu tests for MMUv3
MMU test suite is disabled for cores that have spanning TLB way, i.e. for all MMUv3 cores. Instead of disabling it make testing region virtual addresses explicit and invalidate TLB mappings for entries that conflict with the test. Signed-off-by: Max Filippov --- tests/tcg/xtensa/test_mmu.S | 182 1 file changed, 103 insertions(+), 79 deletions(-) diff --git a/tests/tcg/xtensa/test_mmu.S b/tests/tcg/xtensa/test_mmu.S index 4cbd6ef4f9d8..1006c8cf77b2 100644 --- a/tests/tcg/xtensa/test_mmu.S +++ b/tests/tcg/xtensa/test_mmu.S @@ -2,7 +2,9 @@ test_suite mmu -#if XCHAL_HAVE_PTP_MMU && !XCHAL_HAVE_SPANNING_WAY +#if XCHAL_HAVE_PTP_MMU +#define BASE 0x2000 +#define TLB_BASE 0x8000 .purgem test_init @@ -29,17 +31,27 @@ test_suite mmu idtlb a2 movia2, 0x0009 idtlb a2 +#if XCHAL_HAVE_SPANNING_WAY +movia2, BASE | XCHAL_SPANNING_WAY +idtlb a2 +iitlb a2 +movia2, TLB_BASE | XCHAL_SPANNING_WAY +idtlb a2 +iitlb a2 +movia2, TLB_BASE +wsr a2, ptevaddr +#endif .endm test tlb_group movia2, 0x0402 /* PPN */ -movia3, 0x0124 /* VPN */ +movia3, BASE + 0x0124 /* VPN */ wdtlb a2, a3 witlb a2, a3 movia3, 0x0024 rdtlb0 a1, a3 ritlb0 a2, a3 -movia3, 0x0101 +movia3, BASE + 0x0101 assert eq, a1, a3 assert eq, a2, a3 movia3, 0x0024 @@ -48,17 +60,17 @@ test tlb_group movia3, 0x0402 assert eq, a1, a3 assert eq, a2, a3 -movia3, 0x01234567 +movia3, BASE + 0x01234567 pdtlb a1, a3 pitlb a2, a3 -movia3, 0x01234014 +movia3, BASE + 0x01234014 assert eq, a1, a3 -movia3, 0x0123400c +movia3, BASE + 0x0123400c assert eq, a2, a3 movia3, 0x0024 idtlb a3 iitlb a3 -movia3, 0x01234567 +movia3, BASE + 0x01234567 pdtlb a1, a3 pitlb a2, a3 movia3, 0x0010 @@ -72,7 +84,7 @@ test_end test itlb_miss set_vector kernel, 1f -movia3, 0x0010 +movia3, BASE + 0x0010 jx a3 test_fail 1: @@ -86,7 +98,7 @@ test_end test dtlb_miss set_vector kernel, 1f -movia3, 0x0010 +movia3, BASE + 0x0010 l8uia2, a3, 0 test_fail 1: @@ -116,11 +128,11 @@ test dtlb_multi_hit set_vector kernel, 1f movia2, 0x0402 /* PPN */ -movia3, 0x0124 /* VPN */ +movia3, BASE + 0x0124 /* VPN */ wdtlb a2, a3 -movia3, 0x0127 /* VPN */ +movia3, BASE + 0x0127 /* VPN */ wdtlb a2, a3 -movia3, 0x0120 +movia3, BASE + 0x0120 pdtlb a2, a3 test_fail 1: @@ -168,15 +180,18 @@ test load_store_privilege and a3, a3, a1 movia1, 4 or a3, a3, a1 +movia5, BASE +add a3, a3, a5 witlb a2, a3 movia3, 10f movia1, 0x000f and a1, a3, a1 +add a1, a1, a5 movia2, 0x0403 /* PPN */ -movia3, 0x0124 /* VPN */ +movia3, BASE + 0x0124 /* VPN */ wdtlb a2, a3 -movia3, 0x0121 +movia3, BASE + 0x0121 movia2, 0x4004f jx a1 10: @@ -192,6 +207,7 @@ test load_store_privilege movia3, 1b movia1, 0x000f and a3, a3, a1 +add a3, a3, a5 assert eq, a2, a3 rsr a2, exccause movia3, 26 @@ -206,9 +222,9 @@ test cring_load_store_privilege set_vector double, 2f movia2, 0x0403 /* PPN */ -movia3, 0x0124 /* VPN */ +movia3, BASE + 0x0124 /* VPN */ wdtlb a2, a3 -movia3, 0x0124 +movia3, BASE + 0x0124 movia2, 0x4005f/* ring 1 + excm => cring == 0 */ wsr a2, ps isync @@ -245,10 +261,13 @@ test inst_fetch_prohibited and a3, a3, a1 movia1, 4 or a3, a3, a1 +movia5, BASE +add a3, a3, a5 witlb a2, a3 movia3, 10f movia1, 0x000f and a1, a3, a1 +add a1, a1, a5 jx a1 .align 4 10: @@ -268,9 +287,9 @@ test load_prohibited set_vector kernel, 2f movia2, 0x040c /* PPN */ -movia3, 0x0124 /* VPN */ +movia3, BASE + 0x0124 /* VPN */ wdtlb a2, a3 -movia3, 0x0122 +movia3, BASE + 0x0122 1: l8uia2, a3, 0 test_fail @@ -289,9 +308,9 @@ test store_prohibited set_vector kernel, 2f movia2, 0x0401 /* PPN */ -movia3, 0x0124 /* VPN */ +movia3, BASE + 0x0124 /* VPN */ wdtlb a2, a3 -movia3, 0x0123 +movia3, BASE + 0x0123 l8uia2, a3, 0 1: s8i a2, a3, 0 @@ -311,10 +330,10 @@ test_end * and DTLB way 7 to cover this PTE, ring=pt
[PATCH 2/7] tests/tcg/xtensa: restore vecbase SR after test
Writing garbage into the vecbase SR results in hang in the subsequent tests that expect to raise an exception. Restore vecbase SR to its reset value after the test. Signed-off-by: Max Filippov --- tests/tcg/xtensa/test_sr.S | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/tcg/xtensa/test_sr.S b/tests/tcg/xtensa/test_sr.S index b1a91a0637ee..34441c7afff7 100644 --- a/tests/tcg/xtensa/test_sr.S +++ b/tests/tcg/xtensa/test_sr.S @@ -221,6 +221,8 @@ test_sr_mask /*scompare1*/12, 0, 0 #if XCHAL_HAVE_VECBASE test_sr vecbase, 1 +movi a2, XCHAL_VECBASE_RESET_VADDR +wsra2, vecbase #else test_sr_mask /*vecbase*/231, 0, 0 #endif -- 2.30.2
[PATCH 7/7] tests/tcg/xtensa: fix vectors and checks in timer test
Timer test assumes that timer 0 IRQ has level 1 and other timers have higher level IRQs. This assumption is not correct and the levels may be arbitrary. Fix that assumption by providing TIMER*_VECTOR macro and using it for vector selection and by making the check for the timer exception cause conditional. Signed-off-by: Max Filippov --- tests/tcg/xtensa/test_timer.S | 48 ++- 1 file changed, 41 insertions(+), 7 deletions(-) diff --git a/tests/tcg/xtensa/test_timer.S b/tests/tcg/xtensa/test_timer.S index 2a383e77190e..2a06eebad883 100644 --- a/tests/tcg/xtensa/test_timer.S +++ b/tests/tcg/xtensa/test_timer.S @@ -38,6 +38,28 @@ test_end #if XCHAL_NUM_TIMERS +#if INTERRUPT_LEVEL(XCHAL_TIMER0_INTERRUPT) == 1 +#define TIMER0_VECTOR kernel +#else +#define TIMER0_VECTOR glue(level, INTERRUPT_LEVEL(XCHAL_TIMER0_INTERRUPT)) +#endif + +#if XCHAL_NUM_TIMERS > 1 +#if INTERRUPT_LEVEL(XCHAL_TIMER1_INTERRUPT) == 1 +#define TIMER1_VECTOR kernel +#else +#define TIMER1_VECTOR glue(level, INTERRUPT_LEVEL(XCHAL_TIMER1_INTERRUPT)) +#endif +#endif + +#if XCHAL_NUM_TIMERS > 2 +#if INTERRUPT_LEVEL(XCHAL_TIMER2_INTERRUPT) == 1 +#define TIMER2_VECTOR kernel +#else +#define TIMER2_VECTOR glue(level, INTERRUPT_LEVEL(XCHAL_TIMER2_INTERRUPT)) +#endif +#endif + test ccount_update_deadline movia2, 0 wsr a2, intenable @@ -90,9 +112,8 @@ test ccompare assert nei, a5, 0 test_end -#if INTERRUPT_LEVEL(XCHAL_TIMER0_INTERRUPT) == 1 test ccompare0_interrupt -set_vector kernel, 2f +set_vector TIMER0_VECTOR, 2f movia2, 0 wsr a2, intenable rsr a2, interrupt @@ -120,15 +141,16 @@ test ccompare0_interrupt bneza3, 1b test_fail 2: +#if INTERRUPT_LEVEL(XCHAL_TIMER0_INTERRUPT) == 1 rsr a2, exccause assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */ -test_end #endif +test_end #if XCHAL_NUM_TIMERS > 1 test ccompare1_interrupt -set_vector glue(level, INTERRUPT_LEVEL(XCHAL_TIMER1_INTERRUPT)), 2f +set_vector TIMER1_VECTOR, 2f movia2, 0 wsr a2, intenable rsr a2, interrupt @@ -153,13 +175,17 @@ test ccompare1_interrupt bneza3, 1b test_fail 2: +#if INTERRUPT_LEVEL(XCHAL_TIMER1_INTERRUPT) == 1 +rsr a2, exccause +assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */ +#endif test_end #endif #if XCHAL_NUM_TIMERS > 2 test ccompare2_interrupt -set_vector glue(level, INTERRUPT_LEVEL(XCHAL_TIMER2_INTERRUPT)), 2f +set_vector TIMER2_VECTOR, 2f movia2, 0 wsr a2, intenable rsr a2, interrupt @@ -182,12 +208,16 @@ test ccompare2_interrupt bneza3, 1b test_fail 2: +#if INTERRUPT_LEVEL(XCHAL_TIMER2_INTERRUPT) == 1 +rsr a2, exccause +assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */ +#endif test_end #endif test ccompare_interrupt_masked -set_vector kernel, 2f +set_vector TIMER0_VECTOR, 2f movia2, 0 wsr a2, intenable rsr a2, interrupt @@ -217,12 +247,14 @@ test ccompare_interrupt_masked test_fail 2: +#if INTERRUPT_LEVEL(XCHAL_TIMER0_INTERRUPT) == 1 rsr a2, exccause assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */ +#endif test_end test ccompare_interrupt_masked_waiti -set_vector kernel, 2f +set_vector TIMER0_VECTOR, 2f movia2, 0 wsr a2, intenable rsr a2, interrupt @@ -247,8 +279,10 @@ test ccompare_interrupt_masked_waiti waiti 0 test_fail 2: +#if INTERRUPT_LEVEL(XCHAL_TIMER0_INTERRUPT) == 1 rsr a2, exccause assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */ +#endif test_end #endif -- 2.30.2
[PATCH 5/7] tests/tcg/xtensa: enable autorefill phys_mem tests for MMUv3
Autorefill tests in the phys_mem test suite are disabled for cores that have spanning TLB way, i.e. for all MMUv3 cores. Instead of disabling it invalidate TLB mappings for entries that conflict with the test. Signed-off-by: Max Filippov --- tests/tcg/xtensa/test_phys_mem.S | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/tests/tcg/xtensa/test_phys_mem.S b/tests/tcg/xtensa/test_phys_mem.S index 9bb3ee3866ed..f935a702945c 100644 --- a/tests/tcg/xtensa/test_phys_mem.S +++ b/tests/tcg/xtensa/test_phys_mem.S @@ -2,7 +2,7 @@ test_suite phys_mem -#if XCHAL_HAVE_PTP_MMU && !XCHAL_HAVE_SPANNING_WAY +#if XCHAL_HAVE_PTP_MMU .purgem test_init @@ -13,6 +13,14 @@ test_suite phys_mem witlb a2, a3 movia2, 0xc000 wsr a2, ptevaddr +#if XCHAL_HAVE_SPANNING_WAY +movia2, 0xc000 | XCHAL_SPANNING_WAY +idtlb a2 +iitlb a2 +movia2, 0x2000 | XCHAL_SPANNING_WAY +idtlb a2 +iitlb a2 +#endif .endm test inst_fetch_get_pte_no_phys -- 2.30.2
[PATCH 1/7] tests/tcg/xtensa: fix build for cores without windowed registers
Don't try to initialize windowbase/windowstart in crt.S if they don't exist. Signed-off-by: Max Filippov --- tests/tcg/xtensa/crt.S | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/tcg/xtensa/crt.S b/tests/tcg/xtensa/crt.S index d9846acace90..909872cd3853 100644 --- a/tests/tcg/xtensa/crt.S +++ b/tests/tcg/xtensa/crt.S @@ -8,10 +8,12 @@ .text .global _start _start: +#if XCHAL_HAVE_WINDOWED movia2, 1 wsr a2, windowstart movia2, 0 wsr a2, windowbase +#endif movia1, _fstack movia2, 0x4000f wsr a2, ps -- 2.30.2
[PATCH 3/7] tests/tcg/xtensa: fix watchpoint test
xtensa core may have only one set of DBREAKA/DBREAKC registers. Don't hardcode register numbers in the test as 0 and 1, use macros that only index valid DBREAK* registers. Signed-off-by: Max Filippov --- tests/tcg/xtensa/test_break.S | 86 +++ 1 file changed, 46 insertions(+), 40 deletions(-) diff --git a/tests/tcg/xtensa/test_break.S b/tests/tcg/xtensa/test_break.S index 3379a3f9f06e..3aa18b5cec3f 100644 --- a/tests/tcg/xtensa/test_break.S +++ b/tests/tcg/xtensa/test_break.S @@ -200,64 +200,70 @@ test_end .endm #if XCHAL_NUM_DBREAK +#define DB0 0 +#if XCHAL_NUM_DBREAK > 1 +#define DB1 1 +#else +#define DB1 0 +#endif test dbreak_exact -dbreak_test 0, 0x403f, 0xd07f, 0xd07f, l8ui -dbreak_test 1, 0x403e, 0xd07e, 0xd07e, l16ui -dbreak_test 0, 0x403c, 0xd07c, 0xd07c, l32i +dbreak_test DB0, 0x403f, 0xd07f, 0xd07f, l8ui +dbreak_test DB1, 0x403e, 0xd07e, 0xd07e, l16ui +dbreak_test DB0, 0x403c, 0xd07c, 0xd07c, l32i -dbreak_test 1, 0x803f, 0xd07f, 0xd07f, s8i -dbreak_test 0, 0x803e, 0xd07e, 0xd07e, s16i -dbreak_test 1, 0x803c, 0xd07c, 0xd07c, s32i +dbreak_test DB1, 0x803f, 0xd07f, 0xd07f, s8i +dbreak_test DB0, 0x803e, 0xd07e, 0xd07e, s16i +dbreak_test DB1, 0x803c, 0xd07c, 0xd07c, s32i test_end -test dbreak_overlap -dbreak_test 0, 0x403f, 0xd07d, 0xd07c, l16ui -dbreak_test 1, 0x403f, 0xd07d, 0xd07c, l32i +test DBdbreak_overlap +dbreak_test DB0, 0x403f, 0xd07d, 0xd07c, l16ui +dbreak_test DB1, 0x403f, 0xd07d, 0xd07c, l32i -dbreak_test 0, 0x403e, 0xd07e, 0xd07f, l8ui -dbreak_test 1, 0x403e, 0xd07e, 0xd07c, l32i +dbreak_test DB0, 0x403e, 0xd07e, 0xd07f, l8ui +dbreak_test DB1, 0x403e, 0xd07e, 0xd07c, l32i -dbreak_test 0, 0x403c, 0xd07c, 0xd07d, l8ui -dbreak_test 1, 0x403c, 0xd07c, 0xd07c, l16ui +dbreak_test DB0, 0x403c, 0xd07c, 0xd07d, l8ui +dbreak_test DB1, 0x403c, 0xd07c, 0xd07c, l16ui -dbreak_test 0, 0x4038, 0xd078, 0xd07b, l8ui -dbreak_test 1, 0x4038, 0xd078, 0xd07a, l16ui -dbreak_test 0, 0x4038, 0xd078, 0xd07c, l32i +dbreak_test DB0, 0x4038, 0xd078, 0xd07b, l8ui +dbreak_test DB1, 0x4038, 0xd078, 0xd07a, l16ui +dbreak_test DB0, 0x4038, 0xd078, 0xd07c, l32i -dbreak_test 1, 0x4030, 0xd070, 0xd075, l8ui -dbreak_test 0, 0x4030, 0xd070, 0xd076, l16ui -dbreak_test 1, 0x4030, 0xd070, 0xd078, l32i +dbreak_test DB1, 0x4030, 0xd070, 0xd075, l8ui +dbreak_test DB0, 0x4030, 0xd070, 0xd076, l16ui +dbreak_test DB1, 0x4030, 0xd070, 0xd078, l32i -dbreak_test 0, 0x4020, 0xd060, 0xd06f, l8ui -dbreak_test 1, 0x4020, 0xd060, 0xd070, l16ui -dbreak_test 0, 0x4020, 0xd060, 0xd074, l32i +dbreak_test DB0, 0x4020, 0xd060, 0xd06f, l8ui +dbreak_test DB1, 0x4020, 0xd060, 0xd070, l16ui +dbreak_test DB0, 0x4020, 0xd060, 0xd074, l32i -dbreak_test 0, 0x803f, 0xd07d, 0xd07c, s16i -dbreak_test 1, 0x803f, 0xd07d, 0xd07c, s32i +dbreak_test DB0, 0x803f, 0xd07d, 0xd07c, s16i +dbreak_test DB1, 0x803f, 0xd07d, 0xd07c, s32i -dbreak_test 0, 0x803e, 0xd07e, 0xd07f, s8i -dbreak_test 1, 0x803e, 0xd07e, 0xd07c, s32i +dbreak_test DB0, 0x803e, 0xd07e, 0xd07f, s8i +dbreak_test DB1, 0x803e, 0xd07e, 0xd07c, s32i -dbreak_test 0, 0x803c, 0xd07c, 0xd07d, s8i -dbreak_test 1, 0x803c, 0xd07c, 0xd07c, s16i +dbreak_test DB0, 0x803c, 0xd07c, 0xd07d, s8i +dbreak_test DB1, 0x803c, 0xd07c, 0xd07c, s16i -dbreak_test 0, 0x8038, 0xd078, 0xd07b, s8i -dbreak_test 1, 0x8038, 0xd078, 0xd07a, s16i -dbreak_test 0, 0x8038, 0xd078, 0xd07c, s32i +dbreak_test DB0, 0x8038, 0xd078, 0xd07b, s8i +dbreak_test DB1, 0x8038, 0xd078, 0xd07a, s16i +dbreak_test DB0, 0x8038, 0xd078, 0xd07c, s32i -dbreak_test 1, 0x8030, 0xd070, 0xd075, s8i -dbreak_test 0, 0x8030, 0xd070, 0xd076, s16i -dbreak_test 1, 0x8030, 0xd070, 0xd078, s32i +dbreak_test DB1, 0x8030, 0xd070, 0xd075, s8i +dbreak_test DB0, 0x8030, 0xd070, 0xd076, s16i +dbreak_test DB1, 0x8030, 0xd070, 0xd078, s32i -dbreak_test 0, 0x8020, 0xd060, 0xd06f, s8i -dbreak_test 1, 0x8020, 0xd060, 0xd070, s16i -dbreak_t
[PATCH 4/7] tests/tcg/xtensa: remove dependency on the loop option
xtensa core may not have the loop option, but still have timers. Don't use loop opcode in the timer test. Signed-off-by: Max Filippov --- tests/tcg/xtensa/test_timer.S | 20 ++-- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/tests/tcg/xtensa/test_timer.S b/tests/tcg/xtensa/test_timer.S index 1ec8e20883ff..2a383e77190e 100644 --- a/tests/tcg/xtensa/test_timer.S +++ b/tests/tcg/xtensa/test_timer.S @@ -115,9 +115,9 @@ test ccompare0_interrupt movia2, 1 << XCHAL_TIMER0_INTERRUPT wsr a2, intenable rsila2, 0 -loopa3, 1f -nop 1: +addia3, a3, -1 +bneza3, 1b test_fail 2: rsr a2, exccause @@ -148,9 +148,9 @@ test ccompare1_interrupt movia2, 1 << XCHAL_TIMER1_INTERRUPT wsr a2, intenable rsila2, INTERRUPT_LEVEL(XCHAL_TIMER1_INTERRUPT) - 1 -loopa3, 1f -nop 1: +addia3, a3, -1 +bneza3, 1b test_fail 2: test_end @@ -177,9 +177,9 @@ test ccompare2_interrupt movia2, 1 << XCHAL_TIMER2_INTERRUPT wsr a2, intenable rsila2, INTERRUPT_LEVEL(XCHAL_TIMER2_INTERRUPT) - 1 -loopa3, 1f -nop 1: +addia3, a3, -1 +bneza3, 1b test_fail 2: test_end @@ -197,7 +197,7 @@ test ccompare_interrupt_masked wsr a2, ccompare2 #endif -movia3, 2 * WAIT_LOOPS +movia3, WAIT_LOOPS make_ccount_delta a2, a15 #if XCHAL_NUM_TIMERS > 1 wsr a2, ccompare1 @@ -211,9 +211,10 @@ test ccompare_interrupt_masked movia2, 1 << XCHAL_TIMER0_INTERRUPT wsr a2, intenable rsila2, 0 -loopa3, 1f -nop 1: +addia3, a3, -1 +bneza3, 1b + test_fail 2: rsr a2, exccause @@ -231,7 +232,6 @@ test ccompare_interrupt_masked_waiti wsr a2, ccompare2 #endif -movia3, 2 * WAIT_LOOPS make_ccount_delta a2, a15 #if XCHAL_NUM_TIMERS > 1 wsr a2, ccompare1 -- 2.30.2
[PATCH 0/7] tests/tcg/xtensa: test fixes and improvements
Hello, this series fixes xtensa TCG tests so that they could be built on cores with reduced configurations (e.g. missing windowed registers, no loop option, single data watchpoint register) and expands test coverage to configurations not supported earlier (e.g. MMUv3, timers at high IRQ levels). Max Filippov (7): tests/tcg/xtensa: fix build for cores without windowed registers tests/tcg/xtensa: restore vecbase SR after test tests/tcg/xtensa: fix watchpoint test tests/tcg/xtensa: remove dependency on the loop option tests/tcg/xtensa: enable autorefill phys_mem tests for MMUv3 tests/tcg/xtensa: enable mmu tests for MMUv3 tests/tcg/xtensa: fix vectors and checks in timer test tests/tcg/xtensa/crt.S | 2 + tests/tcg/xtensa/test_break.S| 86 --- tests/tcg/xtensa/test_mmu.S | 182 +-- tests/tcg/xtensa/test_phys_mem.S | 10 +- tests/tcg/xtensa/test_sr.S | 2 + tests/tcg/xtensa/test_timer.S| 68 +--- 6 files changed, 213 insertions(+), 137 deletions(-) -- 2.30.2
[PATCH] hw/xtensa: fix reset value of MIROUT register of MX PIC
MX PIC comes out of reset with IRQ routing registers set to 0, thus
not delivering any external IRQ to any connected CPU by default.
Fix the model to match the hardware.
Signed-off-by: Max Filippov
---
hw/xtensa/mx_pic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/xtensa/mx_pic.c b/hw/xtensa/mx_pic.c
index d889f953d17e..8211c993eb74 100644
--- a/hw/xtensa/mx_pic.c
+++ b/hw/xtensa/mx_pic.c
@@ -334,7 +334,7 @@ void xtensa_mx_pic_reset(void *opaque)
mx->miasg = 0;
mx->mipipart = 0;
for (i = 0; i < mx->n_irq; ++i) {
-mx->mirout[i] = 1;
+mx->mirout[i] = 0;
}
for (i = 0; i < mx->n_cpu; ++i) {
mx->cpu[i].mipicause = 0;
--
2.30.2
Re: [PATCH] target/xtensa: import core lx106
On Sun, Apr 24, 2022 at 10:40 PM Simon Safar wrote: > On Sat, Apr 23, 2022, at 2:26 PM, Max Filippov wrote: > > It's for a (future...) Lisp compiler! Somewhat in the style of MicroPython; > > the idea > > is to make code editable on the fly, without reflashing (... or restarting, > > even). > > Interesting. Do you use libisa or do you do instruction encoding on your own? > > It's my own; it's generating opcodes from the tree of tables in the Xtensa > reference. > A large part of the actual code looks a lot like those tables themselves; > there are still > some missing parts for some (e.g. overriding some defaults on which > instruction is > taking what kinds of parameters), which I'm just filling in on the go. I see. I once did something like that for QEMU TCG: https://github.com/OSLL/qemu-xtensa/commit/53604287d6fdad1ce9659135a8ecbb569be90380 > It's fairly hacky, but it might fit together well with the eventual purpose > of maybe > running some of this in that 40k RAM onboard & keeping it all Lisp. 40k of RAM is a reasonable concern (: I would guess though that libisa + xtensa core description are purely code and constant data, and as such they may be put into FLASH and not consume any RAM. > (I'll put it up somewhere eventually once it's not a complete mess & starts > doing > something interesting! assuming this ever happens, of course.) Have fun and good luck! -- Thanks. -- Max
Re: [PATCH v2] target/xtensa: import core lx106
On Sun, Apr 24, 2022 at 10:24 PM Simon Safar wrote: > On Sat, Apr 23, 2022, at 2:41 PM, Max Filippov wrote: > > I've noticed that this file is not from the original overlay (which I happen > > to have here: > > https://github.com/jcmvbkbc/xtensa-toolchain-build/blob/master/overlays/original/lx106.tar.gz), > > but has been changed (by adding '& ~1' to the 7th column), probably > > to make some older gdb version work. > > This change is not needed for the modern gdb versions. > > I've reverted this change and checked that the mainline gdb-11.1 > > built with the original overlay for the xtensa-elf target correctly > > interacts with the QEMU. Can you please confirm that? > > for simplicity, I just tried re-importing everything with your overlay (vs. > the one from xtensa); both actual code execution & gdb seems to be working > nicely. Yours is also nicer since there is about zero mismatch between what > import-core.sh expects & what it has access to (... while I had to tweak it a > bit, e.g. to skip core-matmap.inc, for it to be satisfied with the xtensa > version). > > Should I send a v3 with the results from importing your variant of the > overlay? (although at this point my "contribution" is really just reordering > cores.list after running the script :)) I've fixed it up on my side, so there's no need for the v3 if everything is working for you. I've applied it to my xtensa tree. Thanks! -- Max
Re: [PATCH v2] target/xtensa: import core lx106
Hi Simon, On Fri, Apr 22, 2022 at 9:09 PM Simon Safar wrote: > > This is the core used in e.g. ESP8266 chips. Importing them > using import_core.sh, with the required files sourced from > > https://github.com/espressif/xtensa-overlays > > core-lx106.c was generated by the script; the only change is removing > the reference to core-matmap.h which doesn't seem to be available. > > Signed-off-by: Simon Safar > Reviewed-by: Max Filippov > --- > target/xtensa/core-lx106.c| 52 + > target/xtensa/core-lx106/core-isa.h | 470 + > target/xtensa/core-lx106/gdb-config.c.inc | 83 + > target/xtensa/core-lx106/xtensa-modules.c.inc | 7668 + > target/xtensa/cores.list |1 + > 5 files changed, 8274 insertions(+) > create mode 100644 target/xtensa/core-lx106.c > create mode 100644 target/xtensa/core-lx106/core-isa.h > create mode 100644 target/xtensa/core-lx106/gdb-config.c.inc > create mode 100644 target/xtensa/core-lx106/xtensa-modules.c.inc [...] > diff --git a/target/xtensa/core-lx106/gdb-config.c.inc > b/target/xtensa/core-lx106/gdb-config.c.inc > new file mode 100644 > index 00..9a2233b811 > --- /dev/null > +++ b/target/xtensa/core-lx106/gdb-config.c.inc [...] I've noticed that this file is not from the original overlay (which I happen to have here: https://github.com/jcmvbkbc/xtensa-toolchain-build/blob/master/overlays/original/lx106.tar.gz), but has been changed (by adding '& ~1' to the 7th column), probably to make some older gdb version work. This change is not needed for the modern gdb versions. I've reverted this change and checked that the mainline gdb-11.1 built with the original overlay for the xtensa-elf target correctly interacts with the QEMU. Can you please confirm that? > + XTREG( 0, 0,32, 4, 4,0x,0x0006 & ~1,-2, 8,0x0100,a0, > 0,0,0,0,0,0) > + XTREG( 1, 4,32, 4, 4,0x0001,0x0006 & ~1,-2, 8,0x0100,a1, > 0,0,0,0,0,0) > + XTREG( 2, 8,32, 4, 4,0x0002,0x0006 & ~1,-2, 8,0x0100,a2, > 0,0,0,0,0,0) > + XTREG( 3, 12,32, 4, 4,0x0003,0x0006 & ~1,-2, 8,0x0100,a3, > 0,0,0,0,0,0) > + XTREG( 4, 16,32, 4, 4,0x0004,0x0006 & ~1,-2, 8,0x0100,a4, > 0,0,0,0,0,0) > + XTREG( 5, 20,32, 4, 4,0x0005,0x0006 & ~1,-2, 8,0x0100,a5, > 0,0,0,0,0,0) > + XTREG( 6, 24,32, 4, 4,0x0006,0x0006 & ~1,-2, 8,0x0100,a6, > 0,0,0,0,0,0) > + XTREG( 7, 28,32, 4, 4,0x0007,0x0006 & ~1,-2, 8,0x0100,a7, > 0,0,0,0,0,0) > + XTREG( 8, 32,32, 4, 4,0x0008,0x0006 & ~1,-2, 8,0x0100,a8, > 0,0,0,0,0,0) > + XTREG( 9, 36,32, 4, 4,0x0009,0x0006 & ~1,-2, 8,0x0100,a9, > 0,0,0,0,0,0) > + XTREG( 10, 40,32, 4, 4,0x000a,0x0006 & ~1,-2, 8,0x0100,a10, > 0,0,0,0,0,0) > + XTREG( 11, 44,32, 4, 4,0x000b,0x0006 & ~1,-2, 8,0x0100,a11, > 0,0,0,0,0,0) > + XTREG( 12, 48,32, 4, 4,0x000c,0x0006 & ~1,-2, 8,0x0100,a12, > 0,0,0,0,0,0) > + XTREG( 13, 52,32, 4, 4,0x000d,0x0006 & ~1,-2, 8,0x0100,a13, > 0,0,0,0,0,0) > + XTREG( 14, 56,32, 4, 4,0x000e,0x0006 & ~1,-2, 8,0x0100,a14, > 0,0,0,0,0,0) > + XTREG( 15, 60,32, 4, 4,0x000f,0x0006 & ~1,-2, 8,0x0100,a15, > 0,0,0,0,0,0) > + XTREG( 16, 64,32, 4, 4,0x0020,0x0006 & ~1,-2, 9,0x0100,pc, > 0,0,0,0,0,0) > + XTREG( 17, 68, 6, 4, 4,0x0203,0x0006 & ~1,-2, 2,0x1100,sar, > 0,0,0,0,0,0) > + XTREG( 18, 72,32, 4, 4,0x0205,0x0006 & ~1,-2, 2,0x1100,litbase, > 0,0,0,0,0,0) > + XTREG( 19, 76,32, 4, 4,0x02b0,0x0002 & ~1,-2, 2,0x1000,sr176, > 0,0,0,0,0,0) > + XTREG( 20, 80,32, 4, 4,0x02d0,0x0002 & ~1,-2, 2,0x1000,sr208, > 0,0,0,0,0,0) > + XTREG( 21, 84, 6, 4, 4,0x02e6,0x0006 & ~1,-2, 2,0x1100,ps, > 0,0,0,0,0,0) > + XTREG( 22, 88,32, 4, 4,0x0259,0x000d & ~1,-2, 2,0x1000,mmid, > 0,0,0,0,0,0) > + XTREG( 23, 92, 1, 4, 4,0x0260,0x0007 & ~1,-2, > 2,0x1000,ibreakenable,0,0,0,0,0,0) > + XTREG( 24, 96,32, 4, 4,0x0268,0x0007 & ~1,-2, 2,0x1000,ddr, > 0,0,0,0,0,0) > + XTREG( 25,100,32, 4, 4,0x0280,0x0007 & ~1,-2, 2,0x1000,ibreaka0, > 0,0,0,0,0,0) > + XTREG( 26,104,32, 4, 4,0x0290,0x0007 & ~1,-2, 2,0x1000,dbreaka0, > 0,0,0,0,0,0) > + XTREG( 27,108,32, 4, 4,0x02a0,0x0007 & ~1,-2, 2,0x1000,dbreakc0, > 0,0,0,0,0,0) > + XTREG( 28,112,32, 4, 4,0x02b1,0x0007 & ~1,-2, 2,0x1000,epc1, > 0,0,0,0,0,0) > + XTREG( 29,116,32, 4, 4,0x02b2,0x0007 & ~1,-2, 2,0x1000,epc2, > 0,0,0,0,0,0) > + XTREG( 30,120,32, 4, 4,0x02b3,0x0007 & ~1,-2, 2,0x1000,epc3, > 0,0,0,0,0,0) > + XTREG( 31,124,32,
Re: [PATCH] target/xtensa: import core lx106
On Fri, Apr 22, 2022 at 8:16 PM Simon Safar wrote: > It's for a (future...) Lisp compiler! Somewhat in the style of MicroPython; > the idea > is to make code editable on the fly, without reflashing (... or restarting, > even). Interesting. Do you use libisa or do you do instruction encoding on your own? -- Thanks. -- Max
[PATCH] target/xtensa: add clock input to xtensa CPU
Create clock input for the xtensa CPU device and initialize its
frequency to the default core frequency specified in the config.
Signed-off-by: Max Filippov
---
target/xtensa/cpu.c | 15 +++
target/xtensa/cpu.h | 5 +
target/xtensa/op_helper.c | 7 ---
3 files changed, 24 insertions(+), 3 deletions(-)
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 224f72323693..fd553fdfb5e6 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -34,6 +34,7 @@
#include "fpu/softfloat.h"
#include "qemu/module.h"
#include "migration/vmstate.h"
+#include "hw/qdev-clock.h"
static void xtensa_cpu_set_pc(CPUState *cs, vaddr value)
@@ -172,9 +173,23 @@ static void xtensa_cpu_initfn(Object *obj)
memory_region_init_io(env->system_er, obj, NULL, env, "er",
UINT64_C(0x1));
address_space_init(env->address_space_er, env->system_er, "ER");
+
+cpu->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, cpu, 0);
+clock_set_hz(cpu->clock, env->config->clock_freq_khz * 1000);
#endif
}
+XtensaCPU *xtensa_cpu_create_with_clock(const char *cpu_type, Clock
*cpu_refclk)
+{
+DeviceState *cpu;
+
+cpu = DEVICE(object_new(cpu_type));
+qdev_connect_clock_in(cpu, "clk-in", cpu_refclk);
+qdev_realize(cpu, NULL, _abort);
+
+return XTENSA_CPU(cpu);
+}
+
#ifndef CONFIG_USER_ONLY
static const VMStateDescription vmstate_xtensa_cpu = {
.name = "cpu",
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 4515f682aa26..6f773e681384 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -30,6 +30,7 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#include "hw/clock.h"
#include "xtensa-isa.h"
/* Xtensa processors have a weak memory model */
@@ -558,6 +559,7 @@ struct ArchCPU {
CPUState parent_obj;
/*< public >*/
+Clock *clock;
CPUNegativeOffsetState neg;
CPUXtensaState env;
};
@@ -792,4 +794,7 @@ static inline void cpu_get_tb_cpu_state(CPUXtensaState
*env, target_ulong *pc,
}
}
+XtensaCPU *xtensa_cpu_create_with_clock(const char *cpu_type,
+Clock *cpu_refclk);
+
#endif
diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c
index d85d3516d6a5..1af7becc54b1 100644
--- a/target/xtensa/op_helper.c
+++ b/target/xtensa/op_helper.c
@@ -38,12 +38,12 @@
void HELPER(update_ccount)(CPUXtensaState *env)
{
+XtensaCPU *cpu = XTENSA_CPU(env_cpu(env));
uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
env->ccount_time = now;
env->sregs[CCOUNT] = env->ccount_base +
-(uint32_t)((now - env->time_base) *
- env->config->clock_freq_khz / 100);
+(uint32_t)clock_ns_to_ticks(cpu->clock, now - env->time_base);
}
void HELPER(wsr_ccount)(CPUXtensaState *env, uint32_t v)
@@ -59,6 +59,7 @@ void HELPER(wsr_ccount)(CPUXtensaState *env, uint32_t v)
void HELPER(update_ccompare)(CPUXtensaState *env, uint32_t i)
{
+XtensaCPU *cpu = XTENSA_CPU(env_cpu(env));
uint64_t dcc;
qatomic_and(>sregs[INTSET],
@@ -66,7 +67,7 @@ void HELPER(update_ccompare)(CPUXtensaState *env, uint32_t i)
HELPER(update_ccount)(env);
dcc = (uint64_t)(env->sregs[CCOMPARE + i] - env->sregs[CCOUNT] - 1) + 1;
timer_mod(env->ccompare[i].timer,
- env->ccount_time + (dcc * 100) /
env->config->clock_freq_khz);
+ env->ccount_time + clock_ticks_to_ns(cpu->clock, dcc));
env->yield_needed = 1;
}
--
2.30.2
[PATCH v2 6/7] target/xtensa: use tcg_constant_* for FPU conversion opcodes
FPU conversion opcodes pass scale (range 0..15) and rounding mode to
their helpers. Use tcg_constant_* for them.
Reviewed-by: Richard Henderson
Signed-off-by: Max Filippov
---
target/xtensa/translate.c | 18 ++
1 file changed, 6 insertions(+), 12 deletions(-)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index c51aea460160..09fb3df40934 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -6512,20 +6512,19 @@ static void translate_const_s(DisasContext *dc, const
OpcodeArg arg[],
static void translate_float_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
-TCGv_i32 scale = tcg_const_i32(-arg[2].imm);
+TCGv_i32 scale = tcg_constant_i32(-arg[2].imm);
if (par[0]) {
gen_helper_uitof_d(arg[0].out, cpu_env, arg[1].in, scale);
} else {
gen_helper_itof_d(arg[0].out, cpu_env, arg[1].in, scale);
}
-tcg_temp_free(scale);
}
static void translate_float_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
-TCGv_i32 scale = tcg_const_i32(-arg[2].imm);
+TCGv_i32 scale = tcg_constant_i32(-arg[2].imm);
OpcodeArg arg32[1];
get_f32_o1(arg, arg32, 0);
@@ -6535,14 +6534,13 @@ static void translate_float_s(DisasContext *dc, const
OpcodeArg arg[],
gen_helper_itof_s(arg32[0].out, cpu_env, arg[1].in, scale);
}
put_f32_o1(arg, arg32, 0);
-tcg_temp_free(scale);
}
static void translate_ftoi_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
-TCGv_i32 rounding_mode = tcg_const_i32(par[0]);
-TCGv_i32 scale = tcg_const_i32(arg[2].imm);
+TCGv_i32 rounding_mode = tcg_constant_i32(par[0]);
+TCGv_i32 scale = tcg_constant_i32(arg[2].imm);
if (par[1]) {
gen_helper_ftoui_d(arg[0].out, cpu_env, arg[1].in,
@@ -6551,15 +6549,13 @@ static void translate_ftoi_d(DisasContext *dc, const
OpcodeArg arg[],
gen_helper_ftoi_d(arg[0].out, cpu_env, arg[1].in,
rounding_mode, scale);
}
-tcg_temp_free(rounding_mode);
-tcg_temp_free(scale);
}
static void translate_ftoi_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
-TCGv_i32 rounding_mode = tcg_const_i32(par[0]);
-TCGv_i32 scale = tcg_const_i32(arg[2].imm);
+TCGv_i32 rounding_mode = tcg_constant_i32(par[0]);
+TCGv_i32 scale = tcg_constant_i32(arg[2].imm);
OpcodeArg arg32[2];
get_f32_i1(arg, arg32, 1);
@@ -6571,8 +6567,6 @@ static void translate_ftoi_s(DisasContext *dc, const
OpcodeArg arg[],
rounding_mode, scale);
}
put_f32_i1(arg, arg32, 1);
-tcg_temp_free(rounding_mode);
-tcg_temp_free(scale);
}
static void translate_ldsti(DisasContext *dc, const OpcodeArg arg[],
--
2.30.2
[PATCH v3 7/7] target/xtensa: use tcg_constant_* for remaining opcodes
- gen_jumpi passes target PC to the helper;
- gen_callw_slot uses callinc (1..3);
- gen_brcondi passes immediate field (less than 32 different possible
values) to the helper;
- disas_xtensa_insn passes PC to the helpers;
- translate_entry passes PC, stack register number (0..15) and stack
frame size to the helper;
- gen_check_exclusive passes PC and boolean flag to the helper;
- test_exceptions_retw passes PC to the helper;
- gen_check_atomctl passes PC to the helper;
- translate_ssai passes immediate shift amount (0..31) to the helper;
- gen_waiti passes next PC and an immediate (0..15) to the helper;
use tcg_constant_* for the constants listed above. Fold gen_waiti body
into the translate_waiti as it's the only user.
Signed-off-by: Max Filippov
---
Changes v2->v3:
- use 'pc' consistently in gen_check_atomctl
Changes v1->v2:
- convert gen_jumpi, disas_xtensa_insn, test_exceptions_retw and
gen_check_atomctl
- use tcg_constant_* for PC
target/xtensa/translate.c | 77 +--
1 file changed, 25 insertions(+), 52 deletions(-)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 09fb3df40934..0cc44e9b3aba 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -396,19 +396,15 @@ static int adjust_jump_slot(DisasContext *dc, uint32_t
dest, int slot)
static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot)
{
-TCGv_i32 tmp = tcg_const_i32(dest);
-gen_jump_slot(dc, tmp, adjust_jump_slot(dc, dest, slot));
-tcg_temp_free(tmp);
+gen_jump_slot(dc, tcg_constant_i32(dest),
+ adjust_jump_slot(dc, dest, slot));
}
static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest,
int slot)
{
-TCGv_i32 tcallinc = tcg_const_i32(callinc);
-
tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS],
-tcallinc, PS_CALLINC_SHIFT, PS_CALLINC_LEN);
-tcg_temp_free(tcallinc);
+tcg_constant_i32(callinc), PS_CALLINC_SHIFT, PS_CALLINC_LEN);
tcg_gen_movi_i32(cpu_R[callinc << 2],
(callinc << 30) | (dc->base.pc_next & 0x3fff));
gen_jump_slot(dc, dest, slot);
@@ -454,9 +450,7 @@ static void gen_brcond(DisasContext *dc, TCGCond cond,
static void gen_brcondi(DisasContext *dc, TCGCond cond,
TCGv_i32 t0, uint32_t t1, uint32_t addr)
{
-TCGv_i32 tmp = tcg_const_i32(t1);
-gen_brcond(dc, cond, t0, tmp, addr);
-tcg_temp_free(tmp);
+gen_brcond(dc, cond, t0, tcg_constant_i32(t1), addr);
}
static uint32_t test_exceptions_sr(DisasContext *dc, const OpcodeArg arg[],
@@ -541,21 +535,6 @@ static MemOp gen_load_store_alignment(DisasContext *dc,
MemOp mop,
return mop;
}
-#ifndef CONFIG_USER_ONLY
-static void gen_waiti(DisasContext *dc, uint32_t imm4)
-{
-TCGv_i32 pc = tcg_const_i32(dc->base.pc_next);
-TCGv_i32 intlevel = tcg_const_i32(imm4);
-
-if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
-gen_io_start();
-}
-gen_helper_waiti(cpu_env, pc, intlevel);
-tcg_temp_free(pc);
-tcg_temp_free(intlevel);
-}
-#endif
-
static bool gen_window_check(DisasContext *dc, uint32_t mask)
{
unsigned r = 31 - clz32(mask);
@@ -1070,17 +1049,15 @@ static void disas_xtensa_insn(CPUXtensaState *env,
DisasContext *dc)
}
if (op_flags & XTENSA_OP_UNDERFLOW) {
-TCGv_i32 tmp = tcg_const_i32(dc->pc);
+TCGv_i32 pc = tcg_constant_i32(dc->pc);
-gen_helper_test_underflow_retw(cpu_env, tmp);
-tcg_temp_free(tmp);
+gen_helper_test_underflow_retw(cpu_env, pc);
}
if (op_flags & XTENSA_OP_ALLOCA) {
-TCGv_i32 tmp = tcg_const_i32(dc->pc);
+TCGv_i32 pc = tcg_constant_i32(dc->pc);
-gen_helper_movsp(cpu_env, tmp);
-tcg_temp_free(tmp);
+gen_helper_movsp(cpu_env, pc);
}
if (coprocessor && !gen_check_cpenable(dc, coprocessor)) {
@@ -1659,13 +1636,10 @@ static uint32_t test_overflow_entry(DisasContext *dc,
const OpcodeArg arg[],
static void translate_entry(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
-TCGv_i32 pc = tcg_const_i32(dc->pc);
-TCGv_i32 s = tcg_const_i32(arg[0].imm);
-TCGv_i32 imm = tcg_const_i32(arg[1].imm);
+TCGv_i32 pc = tcg_constant_i32(dc->pc);
+TCGv_i32 s = tcg_constant_i32(arg[0].imm);
+TCGv_i32 imm = tcg_constant_i32(arg[1].imm);
gen_helper_entry(cpu_env, pc, s, imm);
-tcg_temp_free(imm);
-tcg_temp_free(s);
-tcg_temp_free(pc);
}
static void translate_extui(DisasContext *dc, const OpcodeArg arg[],
@@ -1745,12 +1719,10 @@ static void gen_check_exclusive(DisasContext *dc,
TCGv_i32 addr, bool is_write)
static void gen_check_exclusive(DisasContext *dc, TCGv_i32 addr, bool is_write)
{
if (!option_enabled(dc, XTENSA_OPTION_MPU)) {
-TCGv_i32 tpc = tcg_const_i32(dc->pc);
-TCGv_i32 write =
[PATCH v2 4/7] target/xtensa: use tcg_constant_* for TLB opcodes
dtlb is a boolean flag, use tcg_constant_* for it.
Reviewed-by: Richard Henderson
Signed-off-by: Max Filippov
---
target/xtensa/translate.c | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index e92cc6fbf8c6..245c5968bd5d 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -1707,10 +1707,9 @@ static void translate_itlb(DisasContext *dc, const
OpcodeArg arg[],
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
-TCGv_i32 dtlb = tcg_const_i32(par[0]);
+TCGv_i32 dtlb = tcg_constant_i32(par[0]);
gen_helper_itlb(cpu_env, arg[0].in, dtlb);
-tcg_temp_free(dtlb);
#endif
}
@@ -2047,11 +2046,10 @@ static void translate_ptlb(DisasContext *dc, const
OpcodeArg arg[],
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
-TCGv_i32 dtlb = tcg_const_i32(par[0]);
+TCGv_i32 dtlb = tcg_constant_i32(par[0]);
tcg_gen_movi_i32(cpu_pc, dc->pc);
gen_helper_ptlb(arg[0].out, cpu_env, arg[1].in, dtlb);
-tcg_temp_free(dtlb);
#endif
}
@@ -2250,10 +2248,9 @@ static void translate_rtlb(DisasContext *dc, const
OpcodeArg arg[],
gen_helper_rtlb0,
gen_helper_rtlb1,
};
-TCGv_i32 dtlb = tcg_const_i32(par[0]);
+TCGv_i32 dtlb = tcg_constant_i32(par[0]);
helper[par[1]](arg[0].out, cpu_env, arg[1].in, dtlb);
-tcg_temp_free(dtlb);
#endif
}
@@ -2561,10 +2558,9 @@ static void translate_wtlb(DisasContext *dc, const
OpcodeArg arg[],
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
-TCGv_i32 dtlb = tcg_const_i32(par[0]);
+TCGv_i32 dtlb = tcg_constant_i32(par[0]);
gen_helper_wtlb(cpu_env, arg[0].in, arg[1].in, dtlb);
-tcg_temp_free(dtlb);
#endif
}
--
2.30.2
[PATCH v2 7/7] target/xtensa: use tcg_constant_* for remaining opcodes
- gen_jumpi passes target PC to the helper;
- gen_callw_slot uses callinc (1..3);
- gen_brcondi passes immediate field (less than 32 different possible
values) to the helper;
- disas_xtensa_insn passes PC to the helpers;
- translate_entry passes PC, stack register number (0..15) and stack
frame size to the helper;
- gen_check_exclusive passes PC and boolean flag to the helper;
- test_exceptions_retw passes PC to the helper;
- gen_check_atomctl passes PC to the helper;
- translate_ssai passes immediate shift amount (0..31) to the helper;
- gen_waiti passes next PC and an immediate (0..15) to the helper;
use tcg_constant_* for the constants listed above. Fold gen_waiti body
into the translate_waiti as it's the only user.
Signed-off-by: Max Filippov
---
Changes v1->v2:
- convert gen_jumpi, disas_xtensa_insn, test_exceptions_retw and
gen_check_atomctl
- use tcg_constant_* for PC
target/xtensa/translate.c | 75 +--
1 file changed, 24 insertions(+), 51 deletions(-)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 09fb3df40934..9b3c5c0ca45e 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -396,19 +396,15 @@ static int adjust_jump_slot(DisasContext *dc, uint32_t
dest, int slot)
static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot)
{
-TCGv_i32 tmp = tcg_const_i32(dest);
-gen_jump_slot(dc, tmp, adjust_jump_slot(dc, dest, slot));
-tcg_temp_free(tmp);
+gen_jump_slot(dc, tcg_constant_i32(dest),
+ adjust_jump_slot(dc, dest, slot));
}
static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest,
int slot)
{
-TCGv_i32 tcallinc = tcg_const_i32(callinc);
-
tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS],
-tcallinc, PS_CALLINC_SHIFT, PS_CALLINC_LEN);
-tcg_temp_free(tcallinc);
+tcg_constant_i32(callinc), PS_CALLINC_SHIFT, PS_CALLINC_LEN);
tcg_gen_movi_i32(cpu_R[callinc << 2],
(callinc << 30) | (dc->base.pc_next & 0x3fff));
gen_jump_slot(dc, dest, slot);
@@ -454,9 +450,7 @@ static void gen_brcond(DisasContext *dc, TCGCond cond,
static void gen_brcondi(DisasContext *dc, TCGCond cond,
TCGv_i32 t0, uint32_t t1, uint32_t addr)
{
-TCGv_i32 tmp = tcg_const_i32(t1);
-gen_brcond(dc, cond, t0, tmp, addr);
-tcg_temp_free(tmp);
+gen_brcond(dc, cond, t0, tcg_constant_i32(t1), addr);
}
static uint32_t test_exceptions_sr(DisasContext *dc, const OpcodeArg arg[],
@@ -541,21 +535,6 @@ static MemOp gen_load_store_alignment(DisasContext *dc,
MemOp mop,
return mop;
}
-#ifndef CONFIG_USER_ONLY
-static void gen_waiti(DisasContext *dc, uint32_t imm4)
-{
-TCGv_i32 pc = tcg_const_i32(dc->base.pc_next);
-TCGv_i32 intlevel = tcg_const_i32(imm4);
-
-if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
-gen_io_start();
-}
-gen_helper_waiti(cpu_env, pc, intlevel);
-tcg_temp_free(pc);
-tcg_temp_free(intlevel);
-}
-#endif
-
static bool gen_window_check(DisasContext *dc, uint32_t mask)
{
unsigned r = 31 - clz32(mask);
@@ -1070,17 +1049,15 @@ static void disas_xtensa_insn(CPUXtensaState *env,
DisasContext *dc)
}
if (op_flags & XTENSA_OP_UNDERFLOW) {
-TCGv_i32 tmp = tcg_const_i32(dc->pc);
+TCGv_i32 pc = tcg_constant_i32(dc->pc);
-gen_helper_test_underflow_retw(cpu_env, tmp);
-tcg_temp_free(tmp);
+gen_helper_test_underflow_retw(cpu_env, pc);
}
if (op_flags & XTENSA_OP_ALLOCA) {
-TCGv_i32 tmp = tcg_const_i32(dc->pc);
+TCGv_i32 pc = tcg_constant_i32(dc->pc);
-gen_helper_movsp(cpu_env, tmp);
-tcg_temp_free(tmp);
+gen_helper_movsp(cpu_env, pc);
}
if (coprocessor && !gen_check_cpenable(dc, coprocessor)) {
@@ -1659,13 +1636,10 @@ static uint32_t test_overflow_entry(DisasContext *dc,
const OpcodeArg arg[],
static void translate_entry(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
-TCGv_i32 pc = tcg_const_i32(dc->pc);
-TCGv_i32 s = tcg_const_i32(arg[0].imm);
-TCGv_i32 imm = tcg_const_i32(arg[1].imm);
+TCGv_i32 pc = tcg_constant_i32(dc->pc);
+TCGv_i32 s = tcg_constant_i32(arg[0].imm);
+TCGv_i32 imm = tcg_constant_i32(arg[1].imm);
gen_helper_entry(cpu_env, pc, s, imm);
-tcg_temp_free(imm);
-tcg_temp_free(s);
-tcg_temp_free(pc);
}
static void translate_extui(DisasContext *dc, const OpcodeArg arg[],
@@ -1745,12 +1719,10 @@ static void gen_check_exclusive(DisasContext *dc,
TCGv_i32 addr, bool is_write)
static void gen_check_exclusive(DisasContext *dc, TCGv_i32 addr, bool is_write)
{
if (!option_enabled(dc, XTENSA_OPTION_MPU)) {
-TCGv_i32 tpc = tcg_const_i32(dc->pc);
-TCGv_i32 write = tcg_const_i32(is_write);
+TCGv_i32 pc = tcg_constant_i32(dc-
[PATCH v2 2/7] target/xtensa: use tcg_contatnt_* for numeric literals
Replace tcg_const_* for numeric literals with tcg_constant_*.
Reviewed-by: Richard Henderson
Signed-off-by: Max Filippov
---
target/xtensa/translate.c | 28 +---
1 file changed, 9 insertions(+), 19 deletions(-)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 9ecbbf172114..53f75f7586b2 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -306,16 +306,14 @@ static void gen_right_shift_sar(DisasContext *dc,
TCGv_i32 sa)
static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa)
{
-TCGv_i32 tmp = tcg_const_i32(32);
if (!dc->sar_m32_allocated) {
dc->sar_m32 = tcg_temp_local_new_i32();
dc->sar_m32_allocated = true;
}
tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f);
-tcg_gen_sub_i32(cpu_SR[SAR], tmp, dc->sar_m32);
+tcg_gen_sub_i32(cpu_SR[SAR], tcg_constant_i32(32), dc->sar_m32);
dc->sar_5bit = false;
dc->sar_m32_5bit = true;
-tcg_temp_free(tmp);
}
static void gen_exception(DisasContext *dc, int excp)
@@ -1956,11 +1954,10 @@ static void translate_mov(DisasContext *dc, const
OpcodeArg arg[],
static void translate_movcond(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
-TCGv_i32 zero = tcg_const_i32(0);
+TCGv_i32 zero = tcg_constant_i32(0);
tcg_gen_movcond_i32(par[0], arg[0].out,
arg[2].in, zero, arg[1].in, arg[0].in);
-tcg_temp_free(zero);
}
static void translate_movi(DisasContext *dc, const OpcodeArg arg[],
@@ -1972,7 +1969,7 @@ static void translate_movi(DisasContext *dc, const
OpcodeArg arg[],
static void translate_movp(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
-TCGv_i32 zero = tcg_const_i32(0);
+TCGv_i32 zero = tcg_constant_i32(0);
TCGv_i32 tmp = tcg_temp_new_i32();
tcg_gen_andi_i32(tmp, arg[2].in, 1 << arg[2].imm);
@@ -1980,7 +1977,6 @@ static void translate_movp(DisasContext *dc, const
OpcodeArg arg[],
arg[0].out, tmp, zero,
arg[1].in, arg[0].in);
tcg_temp_free(tmp);
-tcg_temp_free(zero);
}
static void translate_movsp(DisasContext *dc, const OpcodeArg arg[],
@@ -6443,7 +6439,7 @@ static void translate_compare_d(DisasContext *dc, const
OpcodeArg arg[],
[COMPARE_OLE] = gen_helper_ole_d,
[COMPARE_ULE] = gen_helper_ule_d,
};
-TCGv_i32 zero = tcg_const_i32(0);
+TCGv_i32 zero = tcg_constant_i32(0);
TCGv_i32 res = tcg_temp_new_i32();
TCGv_i32 set_br = tcg_temp_new_i32();
TCGv_i32 clr_br = tcg_temp_new_i32();
@@ -6455,7 +6451,6 @@ static void translate_compare_d(DisasContext *dc, const
OpcodeArg arg[],
tcg_gen_movcond_i32(TCG_COND_NE,
arg[0].out, res, zero,
set_br, clr_br);
-tcg_temp_free(zero);
tcg_temp_free(res);
tcg_temp_free(set_br);
tcg_temp_free(clr_br);
@@ -6475,7 +6470,7 @@ static void translate_compare_s(DisasContext *dc, const
OpcodeArg arg[],
[COMPARE_ULE] = gen_helper_ule_s,
};
OpcodeArg arg32[3];
-TCGv_i32 zero = tcg_const_i32(0);
+TCGv_i32 zero = tcg_constant_i32(0);
TCGv_i32 res = tcg_temp_new_i32();
TCGv_i32 set_br = tcg_temp_new_i32();
TCGv_i32 clr_br = tcg_temp_new_i32();
@@ -6489,7 +6484,6 @@ static void translate_compare_s(DisasContext *dc, const
OpcodeArg arg[],
arg[0].out, res, zero,
set_br, clr_br);
put_f32_i2(arg, arg32, 1, 2);
-tcg_temp_free(zero);
tcg_temp_free(res);
tcg_temp_free(set_br);
tcg_temp_free(clr_br);
@@ -6665,14 +6659,13 @@ static void translate_mov_s(DisasContext *dc, const
OpcodeArg arg[],
static void translate_movcond_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
-TCGv_i64 zero = tcg_const_i64(0);
+TCGv_i64 zero = tcg_constant_i64(0);
TCGv_i64 arg2 = tcg_temp_new_i64();
tcg_gen_ext_i32_i64(arg2, arg[2].in);
tcg_gen_movcond_i64(par[0], arg[0].out,
arg2, zero,
arg[1].in, arg[0].in);
-tcg_temp_free_i64(zero);
tcg_temp_free_i64(arg2);
}
@@ -6680,12 +6673,11 @@ static void translate_movcond_s(DisasContext *dc, const
OpcodeArg arg[],
const uint32_t par[])
{
if (arg[0].num_bits == 32) {
-TCGv_i32 zero = tcg_const_i32(0);
+TCGv_i32 zero = tcg_constant_i32(0);
tcg_gen_movcond_i32(par[0], arg[0].out,
arg[2].in, zero,
arg[1].in, arg[0].in);
-tcg_temp_free(zero);
} else {
translate_movcond_d(dc, arg, par);
}
@@ -6694,7 +6686,7 @@ static void translate_movcond_s(DisasContext *dc, const
OpcodeArg arg[],
static void translate_movp_d(DisasCo
[PATCH v2 1/7] target/xtensa: fix missing tcg_temp_free in gen_window_check
pc and w are allocated with tcg_const_i32 but not freed in
gen_window_check. Use tcg_constant_i32 for them both.
Fixes: 2db59a76c421 ("target-xtensa: record available window in TB flags")
Signed-off-by: Max Filippov
---
Changes v1->v2:
- also use tcg_constant_* for PC
target/xtensa/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index b1491ed625e5..9ecbbf172114 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -571,8 +571,8 @@ static bool gen_window_check(DisasContext *dc, uint32_t
mask)
unsigned r = 31 - clz32(mask);
if (r / 4 > dc->window) {
-TCGv_i32 pc = tcg_const_i32(dc->pc);
-TCGv_i32 w = tcg_const_i32(r / 4);
+TCGv_i32 pc = tcg_constant_i32(dc->pc);
+TCGv_i32 w = tcg_constant_i32(r / 4);
gen_helper_window_check(cpu_env, pc, w);
dc->base.is_jmp = DISAS_NORETURN;
--
2.30.2
[PATCH v2 5/7] target/xtensa: use tcg_constant_* for numbered special registers
Numbered special registers are small arrays of consecutive SRs. Use
tcg_constant_* for the SR index.
Reviewed-by: Richard Henderson
Signed-off-by: Max Filippov
---
target/xtensa/translate.c | 16
1 file changed, 4 insertions(+), 12 deletions(-)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 245c5968bd5d..c51aea460160 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -2612,15 +2612,13 @@ static void translate_wsr_ccompare(DisasContext *dc,
const OpcodeArg arg[],
{
#ifndef CONFIG_USER_ONLY
uint32_t id = par[0] - CCOMPARE;
-TCGv_i32 tmp = tcg_const_i32(id);
assert(id < dc->config->nccompare);
if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
}
tcg_gen_mov_i32(cpu_SR[par[0]], arg[0].in);
-gen_helper_update_ccompare(cpu_env, tmp);
-tcg_temp_free(tmp);
+gen_helper_update_ccompare(cpu_env, tcg_constant_i32(id));
#endif
}
@@ -2640,11 +2638,9 @@ static void translate_wsr_dbreaka(DisasContext *dc,
const OpcodeArg arg[],
{
#ifndef CONFIG_USER_ONLY
unsigned id = par[0] - DBREAKA;
-TCGv_i32 tmp = tcg_const_i32(id);
assert(id < dc->config->ndbreak);
-gen_helper_wsr_dbreaka(cpu_env, tmp, arg[0].in);
-tcg_temp_free(tmp);
+gen_helper_wsr_dbreaka(cpu_env, tcg_constant_i32(id), arg[0].in);
#endif
}
@@ -2653,11 +2649,9 @@ static void translate_wsr_dbreakc(DisasContext *dc,
const OpcodeArg arg[],
{
#ifndef CONFIG_USER_ONLY
unsigned id = par[0] - DBREAKC;
-TCGv_i32 tmp = tcg_const_i32(id);
assert(id < dc->config->ndbreak);
-gen_helper_wsr_dbreakc(cpu_env, tmp, arg[0].in);
-tcg_temp_free(tmp);
+gen_helper_wsr_dbreakc(cpu_env, tcg_constant_i32(id), arg[0].in);
#endif
}
@@ -2666,11 +2660,9 @@ static void translate_wsr_ibreaka(DisasContext *dc,
const OpcodeArg arg[],
{
#ifndef CONFIG_USER_ONLY
unsigned id = par[0] - IBREAKA;
-TCGv_i32 tmp = tcg_const_i32(id);
assert(id < dc->config->nibreak);
-gen_helper_wsr_ibreaka(cpu_env, tmp, arg[0].in);
-tcg_temp_free(tmp);
+gen_helper_wsr_ibreaka(cpu_env, tcg_constant_i32(id), arg[0].in);
#endif
}
--
2.30.2
[PATCH v2 3/7] target/xtensa: use tcg_constant_* for exceptions
Use tcg_contant_* for exception number, exception cause, debug cause
code and exception PC.
Signed-off-by: Max Filippov
---
Changes v1->v2:
- also use tcg_constant_* for PC
target/xtensa/translate.c | 18 +-
1 file changed, 5 insertions(+), 13 deletions(-)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 53f75f7586b2..e92cc6fbf8c6 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -318,18 +318,13 @@ static void gen_left_shift_sar(DisasContext *dc, TCGv_i32
sa)
static void gen_exception(DisasContext *dc, int excp)
{
-TCGv_i32 tmp = tcg_const_i32(excp);
-gen_helper_exception(cpu_env, tmp);
-tcg_temp_free(tmp);
+gen_helper_exception(cpu_env, tcg_constant_i32(excp));
}
static void gen_exception_cause(DisasContext *dc, uint32_t cause)
{
-TCGv_i32 tpc = tcg_const_i32(dc->pc);
-TCGv_i32 tcause = tcg_const_i32(cause);
-gen_helper_exception_cause(cpu_env, tpc, tcause);
-tcg_temp_free(tpc);
-tcg_temp_free(tcause);
+TCGv_i32 pc = tcg_constant_i32(dc->pc);
+gen_helper_exception_cause(cpu_env, pc, tcg_constant_i32(cause));
if (cause == ILLEGAL_INSTRUCTION_CAUSE ||
cause == SYSCALL_CAUSE) {
dc->base.is_jmp = DISAS_NORETURN;
@@ -338,11 +333,8 @@ static void gen_exception_cause(DisasContext *dc, uint32_t
cause)
static void gen_debug_exception(DisasContext *dc, uint32_t cause)
{
-TCGv_i32 tpc = tcg_const_i32(dc->pc);
-TCGv_i32 tcause = tcg_const_i32(cause);
-gen_helper_debug_exception(cpu_env, tpc, tcause);
-tcg_temp_free(tpc);
-tcg_temp_free(tcause);
+TCGv_i32 pc = tcg_constant_i32(dc->pc);
+gen_helper_debug_exception(cpu_env, pc, tcg_constant_i32(cause));
if (cause & (DEBUGCAUSE_IB | DEBUGCAUSE_BI | DEBUGCAUSE_BN)) {
dc->base.is_jmp = DISAS_NORETURN;
}
--
2.30.2
[PATCH v2 0/7] target/xtensa: use tcg_constant_* where possible
this series replaces tcg_const_* with tcg_constant_* in the xtensa front end. Changes v1->v2: - also use tcg_constant_* for PC Max Filippov (7): target/xtensa: fix missing tcg_temp_free in gen_window_check target/xtensa: use tcg_contatnt_* for numeric literals target/xtensa: use tcg_constant_* for exceptions target/xtensa: use tcg_constant_* for TLB opcodes target/xtensa: use tcg_constant_* for numbered special registers target/xtensa: use tcg_constant_* for FPU conversion opcodes target/xtensa: use tcg_constant_* for remaining opcodes target/xtensa/translate.c | 171 -- 1 file changed, 54 insertions(+), 117 deletions(-) -- 2.30.2
[PATCH 6/6] target/xtensa: use tcg_constant_* for remaining opcodes
- gen_brcondi passes immediate field (less than 32 different possible
values) to the helper;
- gen_callw_slot uses callinc (1..3);
- translate_entry passes stack register number (0..15) to the helper;
- gen_check_exclusive passes boolean to the helper;
- translate_ssai passes immediate shift amount (0..31) to the helper;
- gen_waiti passes immediate (0..15) to the helper;
use tcg_constant_* for the constants listed above. Fold gen_waiti body
into the translate_waiti as it's the only user.
Signed-off-by: Max Filippov
---
target/xtensa/translate.c | 44 ---
1 file changed, 13 insertions(+), 31 deletions(-)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index fb4d80669c47..b3f8348dee26 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -406,11 +406,8 @@ static void gen_jumpi(DisasContext *dc, uint32_t dest, int
slot)
static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest,
int slot)
{
-TCGv_i32 tcallinc = tcg_const_i32(callinc);
-
tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS],
-tcallinc, PS_CALLINC_SHIFT, PS_CALLINC_LEN);
-tcg_temp_free(tcallinc);
+tcg_constant_i32(callinc), PS_CALLINC_SHIFT, PS_CALLINC_LEN);
tcg_gen_movi_i32(cpu_R[callinc << 2],
(callinc << 30) | (dc->base.pc_next & 0x3fff));
gen_jump_slot(dc, dest, slot);
@@ -456,9 +453,7 @@ static void gen_brcond(DisasContext *dc, TCGCond cond,
static void gen_brcondi(DisasContext *dc, TCGCond cond,
TCGv_i32 t0, uint32_t t1, uint32_t addr)
{
-TCGv_i32 tmp = tcg_const_i32(t1);
-gen_brcond(dc, cond, t0, tmp, addr);
-tcg_temp_free(tmp);
+gen_brcond(dc, cond, t0, tcg_constant_i32(t1), addr);
}
static uint32_t test_exceptions_sr(DisasContext *dc, const OpcodeArg arg[],
@@ -543,21 +538,6 @@ static MemOp gen_load_store_alignment(DisasContext *dc,
MemOp mop,
return mop;
}
-#ifndef CONFIG_USER_ONLY
-static void gen_waiti(DisasContext *dc, uint32_t imm4)
-{
-TCGv_i32 pc = tcg_const_i32(dc->base.pc_next);
-TCGv_i32 intlevel = tcg_const_i32(imm4);
-
-if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
-gen_io_start();
-}
-gen_helper_waiti(cpu_env, pc, intlevel);
-tcg_temp_free(pc);
-tcg_temp_free(intlevel);
-}
-#endif
-
static bool gen_window_check(DisasContext *dc, uint32_t mask)
{
unsigned r = 31 - clz32(mask);
@@ -1663,11 +1643,10 @@ static void translate_entry(DisasContext *dc, const
OpcodeArg arg[],
const uint32_t par[])
{
TCGv_i32 pc = tcg_const_i32(dc->pc);
-TCGv_i32 s = tcg_const_i32(arg[0].imm);
+TCGv_i32 s = tcg_constant_i32(arg[0].imm);
TCGv_i32 imm = tcg_const_i32(arg[1].imm);
gen_helper_entry(cpu_env, pc, s, imm);
tcg_temp_free(imm);
-tcg_temp_free(s);
tcg_temp_free(pc);
}
@@ -1749,11 +1728,10 @@ static void gen_check_exclusive(DisasContext *dc,
TCGv_i32 addr, bool is_write)
{
if (!option_enabled(dc, XTENSA_OPTION_MPU)) {
TCGv_i32 tpc = tcg_const_i32(dc->pc);
-TCGv_i32 write = tcg_const_i32(is_write);
-gen_helper_check_exclusive(cpu_env, tpc, addr, write);
+gen_helper_check_exclusive(cpu_env, tpc, addr,
+ tcg_constant_i32(is_write));
tcg_temp_free(tpc);
-tcg_temp_free(write);
}
}
#endif
@@ -2517,9 +2495,7 @@ static void translate_ssa8l(DisasContext *dc, const
OpcodeArg arg[],
static void translate_ssai(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
-TCGv_i32 tmp = tcg_const_i32(arg[0].imm);
-gen_right_shift_sar(dc, tmp);
-tcg_temp_free(tmp);
+gen_right_shift_sar(dc, tcg_constant_i32(arg[0].imm));
}
static void translate_ssl(DisasContext *dc, const OpcodeArg arg[],
@@ -2553,7 +2529,13 @@ static void translate_waiti(DisasContext *dc, const
OpcodeArg arg[],
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
-gen_waiti(dc, arg[0].imm);
+TCGv_i32 pc = tcg_const_i32(dc->base.pc_next);
+
+if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
+gen_io_start();
+}
+gen_helper_waiti(cpu_env, pc, tcg_constant_i32(arg[0].imm));
+tcg_temp_free(pc);
#endif
}
--
2.30.2
[PATCH 4/6] target/xtensa: use tcg_constant_* for numbered special registers
Numbered special registers are small arrays of consecutive SRs. Use
tcg_constant_* for the SR index.
Signed-off-by: Max Filippov
---
target/xtensa/translate.c | 16
1 file changed, 4 insertions(+), 12 deletions(-)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 82a0dbf46d7c..c4991735ead7 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -2615,15 +2615,13 @@ static void translate_wsr_ccompare(DisasContext *dc,
const OpcodeArg arg[],
{
#ifndef CONFIG_USER_ONLY
uint32_t id = par[0] - CCOMPARE;
-TCGv_i32 tmp = tcg_const_i32(id);
assert(id < dc->config->nccompare);
if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
}
tcg_gen_mov_i32(cpu_SR[par[0]], arg[0].in);
-gen_helper_update_ccompare(cpu_env, tmp);
-tcg_temp_free(tmp);
+gen_helper_update_ccompare(cpu_env, tcg_constant_i32(id));
#endif
}
@@ -2643,11 +2641,9 @@ static void translate_wsr_dbreaka(DisasContext *dc,
const OpcodeArg arg[],
{
#ifndef CONFIG_USER_ONLY
unsigned id = par[0] - DBREAKA;
-TCGv_i32 tmp = tcg_const_i32(id);
assert(id < dc->config->ndbreak);
-gen_helper_wsr_dbreaka(cpu_env, tmp, arg[0].in);
-tcg_temp_free(tmp);
+gen_helper_wsr_dbreaka(cpu_env, tcg_constant_i32(id), arg[0].in);
#endif
}
@@ -2656,11 +2652,9 @@ static void translate_wsr_dbreakc(DisasContext *dc,
const OpcodeArg arg[],
{
#ifndef CONFIG_USER_ONLY
unsigned id = par[0] - DBREAKC;
-TCGv_i32 tmp = tcg_const_i32(id);
assert(id < dc->config->ndbreak);
-gen_helper_wsr_dbreakc(cpu_env, tmp, arg[0].in);
-tcg_temp_free(tmp);
+gen_helper_wsr_dbreakc(cpu_env, tcg_constant_i32(id), arg[0].in);
#endif
}
@@ -2669,11 +2663,9 @@ static void translate_wsr_ibreaka(DisasContext *dc,
const OpcodeArg arg[],
{
#ifndef CONFIG_USER_ONLY
unsigned id = par[0] - IBREAKA;
-TCGv_i32 tmp = tcg_const_i32(id);
assert(id < dc->config->nibreak);
-gen_helper_wsr_ibreaka(cpu_env, tmp, arg[0].in);
-tcg_temp_free(tmp);
+gen_helper_wsr_ibreaka(cpu_env, tcg_constant_i32(id), arg[0].in);
#endif
}
--
2.30.2
[PATCH 5/6] target/xtensa: use tcg_constant_* for FPU conversion opcodes
FPU conversion opcodes pass scale (range 0..15) and rounding mode to
their helpers. Use tcg_constant_* for them.
Signed-off-by: Max Filippov
---
target/xtensa/translate.c | 18 ++
1 file changed, 6 insertions(+), 12 deletions(-)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index c4991735ead7..fb4d80669c47 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -6515,20 +6515,19 @@ static void translate_const_s(DisasContext *dc, const
OpcodeArg arg[],
static void translate_float_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
-TCGv_i32 scale = tcg_const_i32(-arg[2].imm);
+TCGv_i32 scale = tcg_constant_i32(-arg[2].imm);
if (par[0]) {
gen_helper_uitof_d(arg[0].out, cpu_env, arg[1].in, scale);
} else {
gen_helper_itof_d(arg[0].out, cpu_env, arg[1].in, scale);
}
-tcg_temp_free(scale);
}
static void translate_float_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
-TCGv_i32 scale = tcg_const_i32(-arg[2].imm);
+TCGv_i32 scale = tcg_constant_i32(-arg[2].imm);
OpcodeArg arg32[1];
get_f32_o1(arg, arg32, 0);
@@ -6538,14 +6537,13 @@ static void translate_float_s(DisasContext *dc, const
OpcodeArg arg[],
gen_helper_itof_s(arg32[0].out, cpu_env, arg[1].in, scale);
}
put_f32_o1(arg, arg32, 0);
-tcg_temp_free(scale);
}
static void translate_ftoi_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
-TCGv_i32 rounding_mode = tcg_const_i32(par[0]);
-TCGv_i32 scale = tcg_const_i32(arg[2].imm);
+TCGv_i32 rounding_mode = tcg_constant_i32(par[0]);
+TCGv_i32 scale = tcg_constant_i32(arg[2].imm);
if (par[1]) {
gen_helper_ftoui_d(arg[0].out, cpu_env, arg[1].in,
@@ -6554,15 +6552,13 @@ static void translate_ftoi_d(DisasContext *dc, const
OpcodeArg arg[],
gen_helper_ftoi_d(arg[0].out, cpu_env, arg[1].in,
rounding_mode, scale);
}
-tcg_temp_free(rounding_mode);
-tcg_temp_free(scale);
}
static void translate_ftoi_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
-TCGv_i32 rounding_mode = tcg_const_i32(par[0]);
-TCGv_i32 scale = tcg_const_i32(arg[2].imm);
+TCGv_i32 rounding_mode = tcg_constant_i32(par[0]);
+TCGv_i32 scale = tcg_constant_i32(arg[2].imm);
OpcodeArg arg32[2];
get_f32_i1(arg, arg32, 1);
@@ -6574,8 +6570,6 @@ static void translate_ftoi_s(DisasContext *dc, const
OpcodeArg arg[],
rounding_mode, scale);
}
put_f32_i1(arg, arg32, 1);
-tcg_temp_free(rounding_mode);
-tcg_temp_free(scale);
}
static void translate_ldsti(DisasContext *dc, const OpcodeArg arg[],
--
2.30.2
[PATCH 1/6] target/xtensa: use tcg_contatnt_* for numeric literals
Replace tcg_const_* for numeric literals with tcg_constant_*.
Signed-off-by: Max Filippov
---
target/xtensa/translate.c | 28 +---
1 file changed, 9 insertions(+), 19 deletions(-)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index f4dac27507fd..3379fc1fc774 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -306,16 +306,14 @@ static void gen_right_shift_sar(DisasContext *dc,
TCGv_i32 sa)
static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa)
{
-TCGv_i32 tmp = tcg_const_i32(32);
if (!dc->sar_m32_allocated) {
dc->sar_m32 = tcg_temp_local_new_i32();
dc->sar_m32_allocated = true;
}
tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f);
-tcg_gen_sub_i32(cpu_SR[SAR], tmp, dc->sar_m32);
+tcg_gen_sub_i32(cpu_SR[SAR], tcg_constant_i32(32), dc->sar_m32);
dc->sar_5bit = false;
dc->sar_m32_5bit = true;
-tcg_temp_free(tmp);
}
static void gen_exception(DisasContext *dc, int excp)
@@ -1957,11 +1955,10 @@ static void translate_mov(DisasContext *dc, const
OpcodeArg arg[],
static void translate_movcond(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
-TCGv_i32 zero = tcg_const_i32(0);
+TCGv_i32 zero = tcg_constant_i32(0);
tcg_gen_movcond_i32(par[0], arg[0].out,
arg[2].in, zero, arg[1].in, arg[0].in);
-tcg_temp_free(zero);
}
static void translate_movi(DisasContext *dc, const OpcodeArg arg[],
@@ -1973,7 +1970,7 @@ static void translate_movi(DisasContext *dc, const
OpcodeArg arg[],
static void translate_movp(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
-TCGv_i32 zero = tcg_const_i32(0);
+TCGv_i32 zero = tcg_constant_i32(0);
TCGv_i32 tmp = tcg_temp_new_i32();
tcg_gen_andi_i32(tmp, arg[2].in, 1 << arg[2].imm);
@@ -1981,7 +1978,6 @@ static void translate_movp(DisasContext *dc, const
OpcodeArg arg[],
arg[0].out, tmp, zero,
arg[1].in, arg[0].in);
tcg_temp_free(tmp);
-tcg_temp_free(zero);
}
static void translate_movsp(DisasContext *dc, const OpcodeArg arg[],
@@ -6444,7 +6440,7 @@ static void translate_compare_d(DisasContext *dc, const
OpcodeArg arg[],
[COMPARE_OLE] = gen_helper_ole_d,
[COMPARE_ULE] = gen_helper_ule_d,
};
-TCGv_i32 zero = tcg_const_i32(0);
+TCGv_i32 zero = tcg_constant_i32(0);
TCGv_i32 res = tcg_temp_new_i32();
TCGv_i32 set_br = tcg_temp_new_i32();
TCGv_i32 clr_br = tcg_temp_new_i32();
@@ -6456,7 +6452,6 @@ static void translate_compare_d(DisasContext *dc, const
OpcodeArg arg[],
tcg_gen_movcond_i32(TCG_COND_NE,
arg[0].out, res, zero,
set_br, clr_br);
-tcg_temp_free(zero);
tcg_temp_free(res);
tcg_temp_free(set_br);
tcg_temp_free(clr_br);
@@ -6476,7 +6471,7 @@ static void translate_compare_s(DisasContext *dc, const
OpcodeArg arg[],
[COMPARE_ULE] = gen_helper_ule_s,
};
OpcodeArg arg32[3];
-TCGv_i32 zero = tcg_const_i32(0);
+TCGv_i32 zero = tcg_constant_i32(0);
TCGv_i32 res = tcg_temp_new_i32();
TCGv_i32 set_br = tcg_temp_new_i32();
TCGv_i32 clr_br = tcg_temp_new_i32();
@@ -6490,7 +6485,6 @@ static void translate_compare_s(DisasContext *dc, const
OpcodeArg arg[],
arg[0].out, res, zero,
set_br, clr_br);
put_f32_i2(arg, arg32, 1, 2);
-tcg_temp_free(zero);
tcg_temp_free(res);
tcg_temp_free(set_br);
tcg_temp_free(clr_br);
@@ -,14 +6660,13 @@ static void translate_mov_s(DisasContext *dc, const
OpcodeArg arg[],
static void translate_movcond_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
-TCGv_i64 zero = tcg_const_i64(0);
+TCGv_i64 zero = tcg_constant_i64(0);
TCGv_i64 arg2 = tcg_temp_new_i64();
tcg_gen_ext_i32_i64(arg2, arg[2].in);
tcg_gen_movcond_i64(par[0], arg[0].out,
arg2, zero,
arg[1].in, arg[0].in);
-tcg_temp_free_i64(zero);
tcg_temp_free_i64(arg2);
}
@@ -6681,12 +6674,11 @@ static void translate_movcond_s(DisasContext *dc, const
OpcodeArg arg[],
const uint32_t par[])
{
if (arg[0].num_bits == 32) {
-TCGv_i32 zero = tcg_const_i32(0);
+TCGv_i32 zero = tcg_constant_i32(0);
tcg_gen_movcond_i32(par[0], arg[0].out,
arg[2].in, zero,
arg[1].in, arg[0].in);
-tcg_temp_free(zero);
} else {
translate_movcond_d(dc, arg, par);
}
@@ -6695,7 +6687,7 @@ static void translate_movcond_s(DisasContext *dc, const
OpcodeArg arg[],
static void translate_movp_d(DisasContext *dc, const OpcodeArg arg[],
[PATCH 2/6] target/xtensa: use tcg_constant_* for exceptions
Exception number, exception cause and debug cause codes are small
numbers, use tcg_contant_* for them.
Signed-off-by: Max Filippov
---
target/xtensa/translate.c | 12 +++-
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 3379fc1fc774..77d2e1303746 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -318,18 +318,14 @@ static void gen_left_shift_sar(DisasContext *dc, TCGv_i32
sa)
static void gen_exception(DisasContext *dc, int excp)
{
-TCGv_i32 tmp = tcg_const_i32(excp);
-gen_helper_exception(cpu_env, tmp);
-tcg_temp_free(tmp);
+gen_helper_exception(cpu_env, tcg_constant_i32(excp));
}
static void gen_exception_cause(DisasContext *dc, uint32_t cause)
{
TCGv_i32 tpc = tcg_const_i32(dc->pc);
-TCGv_i32 tcause = tcg_const_i32(cause);
-gen_helper_exception_cause(cpu_env, tpc, tcause);
+gen_helper_exception_cause(cpu_env, tpc, tcg_constant_i32(cause));
tcg_temp_free(tpc);
-tcg_temp_free(tcause);
if (cause == ILLEGAL_INSTRUCTION_CAUSE ||
cause == SYSCALL_CAUSE) {
dc->base.is_jmp = DISAS_NORETURN;
@@ -339,10 +335,8 @@ static void gen_exception_cause(DisasContext *dc, uint32_t
cause)
static void gen_debug_exception(DisasContext *dc, uint32_t cause)
{
TCGv_i32 tpc = tcg_const_i32(dc->pc);
-TCGv_i32 tcause = tcg_const_i32(cause);
-gen_helper_debug_exception(cpu_env, tpc, tcause);
+gen_helper_debug_exception(cpu_env, tpc, tcg_constant_i32(cause));
tcg_temp_free(tpc);
-tcg_temp_free(tcause);
if (cause & (DEBUGCAUSE_IB | DEBUGCAUSE_BI | DEBUGCAUSE_BN)) {
dc->base.is_jmp = DISAS_NORETURN;
}
--
2.30.2
[PATCH 3/6] target/xtensa: use tcg_constant_* for TLB opcodes
dtlb is a boolean flag, use tcg_constant_* for it.
Signed-off-by: Max Filippov
---
target/xtensa/translate.c | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 77d2e1303746..82a0dbf46d7c 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -1710,10 +1710,9 @@ static void translate_itlb(DisasContext *dc, const
OpcodeArg arg[],
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
-TCGv_i32 dtlb = tcg_const_i32(par[0]);
+TCGv_i32 dtlb = tcg_constant_i32(par[0]);
gen_helper_itlb(cpu_env, arg[0].in, dtlb);
-tcg_temp_free(dtlb);
#endif
}
@@ -2050,11 +2049,10 @@ static void translate_ptlb(DisasContext *dc, const
OpcodeArg arg[],
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
-TCGv_i32 dtlb = tcg_const_i32(par[0]);
+TCGv_i32 dtlb = tcg_constant_i32(par[0]);
tcg_gen_movi_i32(cpu_pc, dc->pc);
gen_helper_ptlb(arg[0].out, cpu_env, arg[1].in, dtlb);
-tcg_temp_free(dtlb);
#endif
}
@@ -2253,10 +2251,9 @@ static void translate_rtlb(DisasContext *dc, const
OpcodeArg arg[],
gen_helper_rtlb0,
gen_helper_rtlb1,
};
-TCGv_i32 dtlb = tcg_const_i32(par[0]);
+TCGv_i32 dtlb = tcg_constant_i32(par[0]);
helper[par[1]](arg[0].out, cpu_env, arg[1].in, dtlb);
-tcg_temp_free(dtlb);
#endif
}
@@ -2564,10 +2561,9 @@ static void translate_wtlb(DisasContext *dc, const
OpcodeArg arg[],
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
-TCGv_i32 dtlb = tcg_const_i32(par[0]);
+TCGv_i32 dtlb = tcg_constant_i32(par[0]);
gen_helper_wtlb(cpu_env, arg[0].in, arg[1].in, dtlb);
-tcg_temp_free(dtlb);
#endif
}
--
2.30.2
[PATCH 0/6] target/xtensa: use tcg_constant_* where possible
Hello, this series replaces tcg_const_* with tcg_constant_* in the xtensa front end. Max Filippov (6): target/xtensa: use tcg_contatnt_* for numeric literals target/xtensa: use tcg_constant_* for exceptions target/xtensa: use tcg_constant_* for TLB opcodes target/xtensa: use tcg_constant_* for numbered special registers target/xtensa: use tcg_constant_* for FPU conversion opcodes target/xtensa: use tcg_constant_* for remaining opcodes target/xtensa/translate.c | 130 -- 1 file changed, 39 insertions(+), 91 deletions(-) -- 2.30.2
Re: [PATCH] target/xtensa: import core lx106
Hi Simon, On Thu, Apr 21, 2022 at 1:04 PM Simon Safar via wrote: > > This is the core used in e.g. ESP8266 chips. Importing them > using import_core.sh, with the required files sourced from > > https://github.com/espressif/xtensa-overlays > > core-lx106.c was generated by the script; the only change is removing > the reference to core-matmap.h which doesn't seem to be available. > > Signed-off-by: Simon Safar > --- > target/xtensa/core-lx106.c| 52 + > target/xtensa/core-lx106/core-isa.h | 470 + > target/xtensa/core-lx106/gdb-config.c.inc | 83 + > target/xtensa/core-lx106/xtensa-modules.c.inc | 7668 + > 4 files changed, 8273 insertions(+) > create mode 100644 target/xtensa/core-lx106.c > create mode 100644 target/xtensa/core-lx106/core-isa.h > create mode 100644 target/xtensa/core-lx106/gdb-config.c.inc > create mode 100644 target/xtensa/core-lx106/xtensa-modules.c.inc An update to target/xtensa/cores.list is needed for this core to be built in qemu-6.2+. Please keep that file alphabetically sorted. With that addressed: Reviewed-by: Max Filippov I'm curious how is it supposed to be used? -- Thanks. -- Max
[PATCH] target/xtensa: add missing tcg_temp_free to gen_window_check
pc and w are allocated with tcg_const_i32 but not freed in
gen_window_check. Add missing tcg_temp_free for pc, use tcg_constant_i32
for w.
Fixes: 2db59a76c421 ("target-xtensa: record available window in TB flags")
Signed-off-by: Max Filippov
---
target/xtensa/translate.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index b1491ed625e5..f4dac27507fd 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -572,9 +572,10 @@ static bool gen_window_check(DisasContext *dc, uint32_t
mask)
if (r / 4 > dc->window) {
TCGv_i32 pc = tcg_const_i32(dc->pc);
-TCGv_i32 w = tcg_const_i32(r / 4);
+TCGv_i32 w = tcg_constant_i32(r / 4);
gen_helper_window_check(cpu_env, pc, w);
+tcg_temp_free(pc);
dc->base.is_jmp = DISAS_NORETURN;
return false;
}
--
2.30.2
[PATCH] tests/tcg/xtensa: allow testing big-endian cores
Don't disable all big-endian tests, instead check whether $(CORE) is supported by the configured $(QEMU) and enable tests if it is. Signed-off-by: Max Filippov --- MAINTAINERS| 1 + tests/tcg/xtensa/Makefile.softmmu-target | 4 ++-- tests/tcg/xtensaeb/Makefile.softmmu-target | 5 + 3 files changed, 8 insertions(+), 2 deletions(-) create mode 100644 tests/tcg/xtensaeb/Makefile.softmmu-target diff --git a/MAINTAINERS b/MAINTAINERS index 9aed5f3e04e4..e16585b073a3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -347,6 +347,7 @@ S: Maintained F: target/xtensa/ F: hw/xtensa/ F: tests/tcg/xtensa/ +F: tests/tcg/xtensaeb/ F: disas/xtensa.c F: include/hw/xtensa/xtensa-isa.h F: configs/devices/xtensa*/default.mak diff --git a/tests/tcg/xtensa/Makefile.softmmu-target b/tests/tcg/xtensa/Makefile.softmmu-target index 9530cac2ad95..f1cf2a6496d2 100644 --- a/tests/tcg/xtensa/Makefile.softmmu-target +++ b/tests/tcg/xtensa/Makefile.softmmu-target @@ -2,7 +2,8 @@ # Xtensa softmmu tests # -ifneq ($(TARGET_WORDS_BIGENDIAN),y) +CORE=dc232b +ifneq ($(shell $(QEMU) -cpu help | grep -w $(CORE)),) XTENSA_SRC = $(SRC_PATH)/tests/tcg/xtensa XTENSA_ALL = $(filter-out $(XTENSA_SRC)/linker.ld.S,$(wildcard $(XTENSA_SRC)/*.S)) @@ -15,7 +16,6 @@ XTENSA_USABLE_TESTS = $(filter-out $(XTENSA_BROKEN_TESTS), $(XTENSA_TESTS)) TESTS += $(XTENSA_USABLE_TESTS) VPATH += $(XTENSA_SRC) -CORE=dc232b QEMU_OPTS+=-M sim -cpu $(CORE) -nographic -semihosting -icount 6 $(EXTFLAGS) -kernel INCLUDE_DIRS = $(SRC_PATH)/target/xtensa/core-$(CORE) diff --git a/tests/tcg/xtensaeb/Makefile.softmmu-target b/tests/tcg/xtensaeb/Makefile.softmmu-target new file mode 100644 index ..4204a96d53c0 --- /dev/null +++ b/tests/tcg/xtensaeb/Makefile.softmmu-target @@ -0,0 +1,5 @@ +# +# Xtensa softmmu tests +# + +include $(SRC_PATH)/tests/tcg/xtensa/Makefile.softmmu-target -- 2.30.2
Re: [PATCH-for-7.0] softmmu: List CPU types again
On Thu, Mar 10, 2022 at 3:55 AM Philippe Mathieu-Daudé
wrote:
>
> From: Philippe Mathieu-Daudé
>
> Commit e0220bb5b2 made cpus.c target-agnostic but didn't notice
> the cpu_list() function is only defined in target-specific code
> in "cpu.h". Extract list_cpus() from the generic cpus.c into a
> new target-specific unit.
>
> Fixes: e0220bb5b2 ("softmmu: Build target-agnostic objects once")
> Reported-by: Max Filippov
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> softmmu/cpus.c | 8
> softmmu/cpus_list.c | 36
> softmmu/meson.build | 1 +
> 3 files changed, 37 insertions(+), 8 deletions(-)
> create mode 100644 softmmu/cpus_list.c
Tested-by: Max Filippov
--
Thanks.
-- Max
qemu-softmmu -cpu help broken
Hello,
I've noticed that the command
qemu-system-xtensa -cpu help
no longer prints anything. Apparently because cpu_list is no longer defined
in list_cpus inside softmmu/cpus.c
Bisection points to the following commit:
e0220bb5b200 ("softmmu: Build target-agnostic objects once")
Reverting the change for the cpus.c fixes it for me:
diff --git a/softmmu/meson.build b/softmmu/meson.build
index 8138248661a2..adede5e604db 100644
--- a/softmmu/meson.build
+++ b/softmmu/meson.build
@@ -1,5 +1,6 @@
specific_ss.add(when: 'CONFIG_SOFTMMU', if_true: [files(
'arch_init.c',
+ 'cpus.c',
'ioport.c',
'memory.c',
'physmem.c',
@@ -13,7 +14,6 @@ specific_ss.add(when: ['CONFIG_SOFTMMU',
'CONFIG_TCG'], if_true: [files(
softmmu_ss.add(files(
'balloon.c',
'bootdevice.c',
- 'cpus.c',
'cpu-throttle.c',
'cpu-timers.c',
'datadir.c',
I can send a proper patch if this is the right fix, please
let me know.
--
Thanks.
-- Max
[PATCH] tests/tcg/xtensa: allow testing big-endian cores
Don't disable all big-endian tests, instead check whether $(CORE) is supported by the configured $(QEMU) and enable tests if it is. Signed-off-by: Max Filippov --- MAINTAINERS| 1 + tests/tcg/xtensa/Makefile.softmmu-target | 4 ++-- tests/tcg/xtensaeb/Makefile.softmmu-target | 5 + 3 files changed, 8 insertions(+), 2 deletions(-) create mode 100644 tests/tcg/xtensaeb/Makefile.softmmu-target diff --git a/MAINTAINERS b/MAINTAINERS index 50435b8d2f50..8b5ed46a5f1c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -343,6 +343,7 @@ S: Maintained F: target/xtensa/ F: hw/xtensa/ F: tests/tcg/xtensa/ +F: tests/tcg/xtensaeb/ F: disas/xtensa.c F: include/hw/xtensa/xtensa-isa.h F: configs/devices/xtensa*/default.mak diff --git a/tests/tcg/xtensa/Makefile.softmmu-target b/tests/tcg/xtensa/Makefile.softmmu-target index 9530cac2ad95..f1cf2a6496d2 100644 --- a/tests/tcg/xtensa/Makefile.softmmu-target +++ b/tests/tcg/xtensa/Makefile.softmmu-target @@ -2,7 +2,8 @@ # Xtensa softmmu tests # -ifneq ($(TARGET_WORDS_BIGENDIAN),y) +CORE=dc232b +ifneq ($(shell $(QEMU) -cpu help | grep -w $(CORE)),) XTENSA_SRC = $(SRC_PATH)/tests/tcg/xtensa XTENSA_ALL = $(filter-out $(XTENSA_SRC)/linker.ld.S,$(wildcard $(XTENSA_SRC)/*.S)) @@ -15,7 +16,6 @@ XTENSA_USABLE_TESTS = $(filter-out $(XTENSA_BROKEN_TESTS), $(XTENSA_TESTS)) TESTS += $(XTENSA_USABLE_TESTS) VPATH += $(XTENSA_SRC) -CORE=dc232b QEMU_OPTS+=-M sim -cpu $(CORE) -nographic -semihosting -icount 6 $(EXTFLAGS) -kernel INCLUDE_DIRS = $(SRC_PATH)/target/xtensa/core-$(CORE) diff --git a/tests/tcg/xtensaeb/Makefile.softmmu-target b/tests/tcg/xtensaeb/Makefile.softmmu-target new file mode 100644 index ..4204a96d53c0 --- /dev/null +++ b/tests/tcg/xtensaeb/Makefile.softmmu-target @@ -0,0 +1,5 @@ +# +# Xtensa softmmu tests +# + +include $(SRC_PATH)/tests/tcg/xtensa/Makefile.softmmu-target -- 2.20.1
Re: [PATCH] Trim some trailing space from human-readable output
On Sat, Oct 9, 2021 at 8:24 AM Markus Armbruster wrote:
>
> I noticed -cpu help printing enough trailing spaces to make the output
> at least 84 characters wide. Looks ugly unless the terminal is wider.
> Ugly or not, trailing spaces are stupid.
>
> The culprit is this line in x86_cpu_list_entry():
>
> qemu_printf("x86 %-20s %-58s\n", name, desc);
>
> This prints a string with minimum field left-justified right before a
> newline. Change it to
>
> qemu_printf("x86 %-20s %s\n", name, desc);
>
> which avoids the trailing spaces and is simpler to boot.
>
> A search for the pattern with "git-grep -E '%-[0-9]+s\\n'" found a few
> more instances. Change them similarly.
>
> Signed-off-by: Markus Armbruster
> ---
> monitor/hmp-cmds.c | 2 +-
> target/i386/cpu-dump.c | 4 ++--
> target/i386/cpu.c | 2 +-
> target/ppc/cpu_init.c | 2 +-
> target/s390x/cpu_models.c | 4 ++--
> target/xtensa/mmu_helper.c | 2 +-
> 6 files changed, 8 insertions(+), 8 deletions(-)
For target/xtensa:
Acked-by: Max Filippov
--
Thanks.
-- Max
running TCG tests for xtensaeb
Hi Alex, I've tried to use make check-tcg CORE=test_kc705_be CROSS_CC_GUEST=xtensa-test_kc705_be-elf-gcc to run TCG tests for a big-endian xtensa core. I thought the following change would be sufficient to do it: ---8<--- diff --git a/tests/tcg/xtensa/Makefile.softmmu-target b/tests/tcg/xtensa/Makefile.softmmu-target index 9530cac2ad95..6588388967d9 100644 --- a/tests/tcg/xtensa/Makefile.softmmu-target +++ b/tests/tcg/xtensa/Makefile.softmmu-target @@ -2,7 +2,7 @@ # Xtensa softmmu tests # -ifneq ($(TARGET_WORDS_BIGENDIAN),y) +ifneq ($(shell $(QEMU) -cpu help | grep -w $(CORE)),) XTENSA_SRC = $(SRC_PATH)/tests/tcg/xtensa XTENSA_ALL = $(filter-out $(XTENSA_SRC)/linker.ld.S,$(wildcard $(XTENSA_SRC)/*.S)) ---8<--- but it turns out that tests/tcg/Makefile.target uses the following code to load target-specific bits: -include $(SRC_PATH)/tests/tcg/$(TARGET_NAME)/Makefile.softmmu-target and for big-endian xtensa TARGET_NAME is xtensaeb. However all xtensa tests are under tests/tcg/xtensa, so Makefile.softmmu-target isn't getting loaded at all. If I replace '$(TARGET_NAME)' with 'xtensa' in the above line everything works as expected. What do you think would be the best way to fix it? -- Thanks. -- Max
