Re: [Qemu-devel] [PULL] First RISC-V Patch Set for the 3.1 Soft Freeze

2018-10-18 Thread Michael Clark
o 7c28f4da20e5585dce7d575691dac5392b7c6f78: > >> > >>RISC-V: Don't add NULL bootargs to device-tree (2018-10-17 13:02:30 > -0700) > >> > >> -------- > >> First RISC-V Patch Set for

Re: [Qemu-devel] [PATCH v1 0/5] Misc RISC-V patches

2018-10-11 Thread Michael Clark
Hi All, On Thu, Oct 11, 2018 at 7:22 AM Palmer Dabbelt wrote: > On Wed, 10 Oct 2018 11:10:07 PDT (-0700), peter.mayd...@linaro.org wrote: > > On 10 October 2018 at 18:49, Palmer Dabbelt wrote: > >> we should really > >> get the ball rolling on our big patch backlog. > > > > Yes, please do.

Re: [Qemu-devel] qemu-riscv64 seg fault

2018-09-03 Thread Michael Clark
On Mon, Sep 3, 2018 at 8:16 PM, Pranith Kumar wrote: > On Mon, Sep 3, 2018 at 1:07 AM Michael Clark wrote: > > > > Thanks. I was just about to log an issue in the riscv-qemu issue tracker > on GitHub. > > > > I reproduced it on my side. The fact that it

Re: [Qemu-devel] qemu-riscv64 seg fault

2018-09-03 Thread Michael Clark
Thanks. I was just about to log an issue in the riscv-qemu issue tracker on GitHub. I reproduced it on my side. The fact that it is causes QEMU user to crash in translate.c is interesting. I ran your program with -d in_asm and it appears to crash in thread::join On Mon, Sep 3, 2018 at 7:58 PM,

Re: [Qemu-devel] microblaze build failure due to definition clash on riscv

2018-08-01 Thread Michael Clark
On Thu, Aug 2, 2018 at 3:57 PM, Philippe Mathieu-Daudé wrote: > Oops I just realized I forgot to Cc the QEMU list, doing it now. > > On 07/31/2018 07:40 AM, Edgar E. Iglesias wrote: > > On Mon, Jul 30, 2018 at 03:22:46PM -0300, Philippe Mathieu-Daudé wrote: > >> Hi, I'm getting this error while

Re: [Qemu-devel] [PATCH] RISC-V: Correct typo in RV32 perf counters

2018-07-30 Thread Michael Clark
On Mon, 30 Jul 2018 at 10:46 PM, Peter Maydell wrote: > On 25 May 2018 at 14:17, Richard Henderson wrote: > > On 05/24/2018 11:24 PM, Michael Clark wrote: > >> This patch enables mhpmcounter3h through mhpmcounter31h on RV32. > >> Previously the RV32 h versions (high

Re: [Qemu-devel] [PATCH v1 1/1] configure: Add RISC-V host support

2018-07-27 Thread Michael Clark
On Sat, Jul 28, 2018 at 11:49 AM, Alistair Francis wrote: > Allow QEMU to be built to run on a RISC-V host. > > QEMU does not yet have a RISC-V TCG or user mode target port, but > running other architectures on RISC-V using TCI does work. > There is this RISC-V TCG backend here:

Re: [Qemu-devel] [PATCH v2] riscv: remove define cpu_init()

2018-07-25 Thread Michael Clark
On Fri, May 18, 2018 at 8:02 PM, Igor Mammedov wrote: > On Fri, 18 May 2018 14:10:24 +1200 > Michael Clark wrote: > > > On Wed, May 16, 2018 at 4:00 AM, Igor Mammedov > wrote: > > > > > cpu_init() was removed since 2.12, so drop the define that is now > unu

Re: [Qemu-devel] [PATCH v1 2/5] sifive_u: Fix crash when introspecting the device

2018-07-17 Thread Michael Clark
On Wed, Jul 18, 2018 at 8:28 AM, Alistair Francis wrote: > Use the new object_initialize_child() and sysbus_init_child_obj() to > fix the issue. > > Signed-off-by: Alistair Francis > Reviewed-by: Michael Clark > --- > hw/riscv/sifive_u.c | 15 +++ > 1 fi

Re: [Qemu-devel] [PATCH v1 5/5] spike: Fix crash when introspecting the device

2018-07-17 Thread Michael Clark
On Wed, Jul 18, 2018 at 8:28 AM, Alistair Francis wrote: > Use the new object_initialize_child() and sysbus_init_child_obj() to > fix the issue. > > Signed-off-by: Alistair Francis > Reviewed-by: Michael Clark > --- > hw/riscv/spike.c | 10 -- > 1 file cha

Re: [Qemu-devel] [PATCH v1 4/5] riscv_hart: Fix crash when introspecting the device

2018-07-17 Thread Michael Clark
On Wed, Jul 18, 2018 at 8:28 AM, Alistair Francis wrote: > Use the new object_initialize_child() and sysbus_init_child_obj() to > fix the issue. > > Signed-off-by: Alistair Francis > Reviewed-by: Michael Clark > --- > hw/riscv/riscv_hart.c | 7 +++ > 1 file cha

Re: [Qemu-devel] [PATCH v1 3/5] virt: Fix crash when introspecting the device

2018-07-17 Thread Michael Clark
On Wed, Jul 18, 2018 at 8:28 AM, Alistair Francis wrote: > Use the new object_initialize_child() and sysbus_init_child_obj() to > fix the issue. > > Signed-off-by: Alistair Francis > Reviewed-by: Michael Clark > --- > hw/riscv/virt.c | 5 ++--- > 1 file cha

Re: [Qemu-devel] [PATCH v1 1/5] sifive_e: Fix crash when introspecting the device

2018-07-17 Thread Michael Clark
On Wed, Jul 18, 2018 at 8:27 AM, Alistair Francis wrote: > Use the new object_initialize_child() and sysbus_init_child_obj() to > fix the issue. > > Signed-off-by: Alistair Francis > Reviewed-by: Michael Clark > --- > hw/riscv/sifive_e.c | 12 ++-- > 1 fi

Re: [Qemu-devel] [PATCH v2 6/6] riscv64-softmmu.mak: Build Virtio Block support

2018-07-09 Thread Michael Clark
On Tue, 10 Jul 2018 at 12:29 PM, Alistair Francis wrote: > Add build time support for the VirtIO block device. This allows us to > attach a drive using the virtio-blk-device. I’m not sure what has changed in master, but VirtIO block and net for both softmmu-riscv32 and softmmu-riscv64 were

Re: [Qemu-devel] [PULL v4 0/7] riscv-pull queue

2018-07-09 Thread Michael Clark
On Tue, Jul 10, 2018 at 9:52 AM, Alistair Francis wrote: > On Mon, Jul 9, 2018 at 3:00 AM, Andreas Schwab wrote: > > What is the state of the sifive_u emulation? When I tried to boot a bbl > > with an included kernel I get these errors: > > > > qemu-system-riscv64: plic: invalid register

Re: [Qemu-devel] [PATCH v1 3/5] hw/riscv/virt: Connect the Xilinx PCIe

2018-06-23 Thread Michael Clark
> On 23/06/2018, at 1:07 PM, Peter Maydell wrote: > > On 22 June 2018 at 20:30, Alistair Francis wrote: >> Connect the Xilinx PCIe device based on the device tree included in the >> HiFive Unleashed ROM. > > Did you consider using the 'gpex' generic PCIe controller here? Yes. Alastair and

Re: [Qemu-devel] [PATCH v4 16/40] hw/riscv: Use the IEC binary prefix definitions

2018-06-10 Thread Michael Clark
ff-by: Philippe Mathieu-Daudé > Reviewed-by: Michael Clark > --- > hw/riscv/virt.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index ad03113e0f..34d48993a2 100644 > --- a/hw/riscv/virt.c > +++ b/h

Re: [Qemu-devel] [PATCH v2] elf: Add RISC-V PSABI ELF header defines

2018-05-25 Thread Michael Clark
On Fri, May 25, 2018 at 7:53 PM, Laurent Vivier <laur...@vivier.eu> wrote: > Le 25/05/2018 à 09:22, Michael Clark a écrit : > > Refer to the RISC-V PSABI specification for details: > > > > - https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md >

[Qemu-devel] [PATCH v2] elf: Add RISC-V PSABI ELF header defines

2018-05-25 Thread Michael Clark
cis <alistair.fran...@wdc.com> Signed-off-by: Michael Clark <m...@sifive.com> --- include/elf.h | 8 1 file changed, 8 insertions(+) diff --git a/include/elf.h b/include/elf.h index 934dbbd6b3ae..bd0493f43d19 100644 --- a/include/elf.h +++ b/include/elf.h @@ -1285,6 +1285,1

Re: [Qemu-devel] [PATCH v1 27/30] elf: Add RISC-V PSABI ELF header defines

2018-05-25 Thread Michael Clark
On Wed, May 23, 2018 at 6:44 PM, Laurent Vivier <laur...@vivier.eu> wrote: > Le 23/05/2018 à 02:15, Michael Clark a écrit : > > Refer to the RISC-V PSABI specification for details: > > > > - https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md >

[Qemu-devel] [PATCH] RISC-V: Correct typo in RV32 perf counters

2018-05-25 Thread Michael Clark
This patch enables mhpmcounter3h through mhpmcounter31h on RV32. Previously the RV32 h versions (high 32-bits of 64-bit counters) of these counters would trap with an illegal instruction instead of returning 0 as intended. Reported-by: Richard Henderson <r...@twiddle.net> Signed-off-by: M

Re: [Qemu-devel] [RISC-V] Coverity 1390849, Logically dead code

2018-05-25 Thread Michael Clark
On Fri, May 25, 2018 at 9:54 AM, Richard Henderson wrote: > In the latest Coverity scan, it reports > > 405if (csrno >= CSR_MHPMCOUNTER3 && csrno <= CSR_MHPMCOUNTER31) { > 406return 0; > 407} > 408#if defined(TARGET_RISCV32) > 409if (csrno >=

Re: [Qemu-devel] [PATCH v1 02/30] RISC-V: Improve page table walker spec compliance

2018-05-23 Thread Michael Clark
, May 23, 2018 at 12:14 PM, Michael Clark <m...@sifive.com> wrote: > - Inline PTE_TABLE check for better readability > - Change access checks from ternary operator to if > - Improve readibility of User page U mode and SUM test > - Disallow non U mode from fetching from User pages &g

[Qemu-devel] [PATCH v1 30/30] RISC-V: Support separate firmware and kernel payload

2018-05-22 Thread Michael Clark
m> Cc: Alistair Francis <alistair.fran...@wdc.com> Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/Makefile.objs | 1 + hw/riscv/boot.c | 172 hw/riscv/virt.c | 67 +++ include/hw/riscv/b

[Qemu-devel] [PATCH v1 29/30] RISC-V: Don't add NULL bootargs to device-tree

2018-05-22 Thread Michael Clark
--- hw/riscv/sifive_u.c | 4 +++- hw/riscv/spike.c| 6 -- hw/riscv/virt.c | 4 +++- 3 files changed, 10 insertions(+), 4 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 326b0f434cff..02721d43c474 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@

[Qemu-devel] [PATCH v1 28/30] RISC-V: linux-user support for RVE ABI

2018-05-22 Thread Michael Clark
Palmer Dabbelt <pal...@sifive.com> Cc: Sagar Karandikar <sag...@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Cc: Alistair Francis <alistair.fran...@wdc.com> Co-authored-by: Kito Cheng <kito.ch...@gmail.com> Co-authored-by: Michael Clark <

[Qemu-devel] [PATCH v1 26/30] RISC-V: Remove unnecessary disassembler constraints

2018-05-22 Thread Michael Clark
an...@wdc.com> Signed-off-by: Michael Clark <m...@sifive.com> --- disas/riscv.c | 138 -- 1 file changed, 138 deletions(-) diff --git a/disas/riscv.c b/disas/riscv.c index 7fd1019623ee..27546dd7902c 100644 --- a/disas/riscv.c +++ b/

[Qemu-devel] [PATCH v1 22/30] RISC-V: Add misa runtime write support

2018-05-22 Thread Michael Clark
.@wdc.com> Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 4 +++- target/riscv/cpu_bits.h | 11 +++ target/riscv/csr.c | 52 - 4 files changed, 66 insertions(+), 3 del

[Qemu-devel] [PATCH v1 20/30] RISC-V: Add misa to DisasContext

2018-05-22 Thread Michael Clark
aderborn.de> Cc: Alistair Francis <alistair.fran...@wdc.com> Cc: Emilio G. Cota <c...@braap.org> Signed-off-by: Michael Clark <m...@sifive.com> Reviewed-by: Richard Henderson <richard.hender...@linaro.org> --- target/riscv/translate.c | 78 ++

[Qemu-devel] [PATCH v1 11/30] RISC-V: Split out mstatus_fs from tb_flags

2018-05-22 Thread Michael Clark
<richard.hender...@linaro.org> Signed-off-by: Michael Clark <m...@sifive.com> Reviewed-by: Michael Clark <m...@sifive.com> --- target/riscv/cpu.h | 6 +++--- target/riscv/translate.c | 10 +- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/target/ris

[Qemu-devel] [PATCH v1 24/30] RISC-V: Fix PLIC pending bitfield reads

2018-05-22 Thread Michael Clark
Dabbelt <pal...@sifive.com> Cc: Sagar Karandikar <sag...@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Cc: Alistair Francis <alistair.fran...@wdc.com> Reported-by: Vincent Siles <vincent.si...@ens-lyon.org> Signed-off-by: Michael Clark &

[Qemu-devel] [PATCH v1 27/30] elf: Add RISC-V PSABI ELF header defines

2018-05-22 Thread Michael Clark
cis <alistair.fran...@wdc.com> Signed-off-by: Michael Clark <m...@sifive.com> --- include/elf.h | 8 1 file changed, 8 insertions(+) diff --git a/include/elf.h b/include/elf.h index 934dbbd6b3ae..d363ba85a688 100644 --- a/include/elf.h +++ b/include/elf.h @@ -1285,6 +1285,1

[Qemu-devel] [PATCH v1 10/30] RISC-V: Implement existential predicates for CSRs

2018-05-22 Thread Michael Clark
Dabbelt <pal...@sifive.com> Cc: Alistair Francis <alistair.fran...@wdc.com> Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/cpu.c| 6 ++ target/riscv/cpu.h| 5 +- target/riscv/cpu_helper.c | 3 +- t

[Qemu-devel] [PATCH v1 23/30] RISC-V: Fix CLINT timecmp low 32-bit writes

2018-05-22 Thread Michael Clark
aderborn.de> Cc: Alistair Francis <alistair.fran...@wdc.com> Co-Authored-by: Johannes Haring <johannes.har...@gmx.net> Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/sifive_clint.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git

[Qemu-devel] [PATCH v1 25/30] RISC-V: Enable second UART on sifive_e and sifive_u

2018-05-22 Thread Michael Clark
gt; Cc: Sagar Karandikar <sag...@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Cc: Alistair Francis <alistair.fran...@wdc.com> Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/sifive_e.c | 4 ++-- hw/riscv/sifive_u.c | 4 ++-- 2 fil

[Qemu-devel] [PATCH v1 09/30] RISC-V: Implement atomic mip/sip CSR updates

2018-05-22 Thread Michael Clark
Use the new CSR read/modify/write interface to implement atomic updates to mip/sip. Cc: Sagar Karandikar <sag...@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Cc: Palmer Dabbelt <pal...@sifive.com> Cc: Alistair Francis <alistair.fran...@wdc.com>

[Qemu-devel] [PATCH v1 21/30] RISC-V: Add misa.MAFD checks to translate

2018-05-22 Thread Michael Clark
lmann <kbast...@mail.uni-paderborn.de> Cc: Alistair Francis <alistair.fran...@wdc.com> Cc: Emilio G. Cota <c...@braap.org> Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/translate.c | 158 +++ 1 file changed, 15

[Qemu-devel] [PATCH v1 18/30] RISC-V: Add missing free for plic_hart_config

2018-05-22 Thread Michael Clark
Cc: Palmer Dabbelt <pal...@sifive.com> Cc: Sagar Karandikar <sag...@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Cc: Alistair Francis <alistair.fran...@wdc.com> Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/virt.c | 2 ++

[Qemu-devel] [PATCH v1 15/30] RISC-V: Add hartid and \n to interrupt logging

2018-05-22 Thread Michael Clark
: Alistair Francis <alistair.fran...@wdc.com> Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/cpu_helper.c | 18 ++ 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index bc15e19022cc..69

[Qemu-devel] [PATCH v1 06/30] RISC-V: Move non-ops from op_helper to cpu_helper

2018-05-22 Thread Michael Clark
; Cc: Palmer Dabbelt <pal...@sifive.com> Cc: Alistair Francis <alistair.fran...@wdc.com> Signed-off-by: Michael Clark <m...@sifive.com> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> --- target/riscv/Makefile.objs | 2 +- target/r

[Qemu-devel] [PATCH v1 17/30] RISC-V: Replace __builtin_popcount with ctpop8 in PLIC

2018-05-22 Thread Michael Clark
cis <alistair.fran...@wdc.com> Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/sifive_plic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c index b267ff88902d..dc6f4924e282 100644 --- a/hw/risc

[Qemu-devel] [PATCH v1 14/30] RISC-V: Add public API for the CSR dispatch table

2018-05-22 Thread Michael Clark
.@wdc.com> Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/cpu.h | 18 ++ target/riscv/csr.c | 35 ++- 2 files changed, 36 insertions(+), 17 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 242

[Qemu-devel] [PATCH v1 05/30] RISC-V: Allow setting and clearing multiple irqs

2018-05-22 Thread Michael Clark
<kbast...@mail.uni-paderborn.de> Cc: Palmer Dabbelt <pal...@sifive.com> Cc: Alistair Francis <alistair.fran...@wdc.com> Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/sifive_clint.c | 8 hw/riscv/sifive_plic.c | 4 ++-- target/riscv/cpu.h | 22 ++

[Qemu-devel] [PATCH v1 16/30] RISC-V: Use riscv prefix consistently on cpu helpers

2018-05-22 Thread Michael Clark
riscv_set_mode to riscv_cpu_set_mode Cc: Sagar Karandikar <sag...@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Cc: Palmer Dabbelt <pal...@sifive.com> Cc: Alistair Francis <alistair.fran...@wdc.com> Signed-off-by: Michael Clark <m...@sifive.com> ---

[Qemu-devel] [PATCH v1 12/30] RISC-V: Mark mstatus.fs dirty

2018-05-22 Thread Michael Clark
t;alistair.fran...@wdc.com> Cc: Richard Henderson <richard.hender...@linaro.org> Signed-off-by: Michael Clark <m...@sifive.com> Reviewed-by: Michael Clark <m...@sifive.com> Co-authored-by: Richard Henderson <richard.hender...@linaro.org> Co-authored-by: Michael C

[Qemu-devel] [PATCH v1 03/30] RISC-V: Use atomic_cmpxchg to update PLIC bitmaps

2018-05-22 Thread Michael Clark
as the count of pending interrupts is not used. Cc: Sagar Karandikar <sag...@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Cc: Palmer Dabbelt <pal...@sifive.com> Cc: Alistair Francis <alistair.fran...@wdc.com> Signed-off-by: Michael Clark &l

[Qemu-devel] [PATCH v1 19/30] RISC-V: Allow interrupt controllers to claim interrupts

2018-05-22 Thread Michael Clark
and software interrupts by other interrupt controller models. Cc: Palmer Dabbelt <pal...@sifive.com> Cc: Sagar Karandikar <sag...@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Cc: Alistair Francis <alistair.fran...@wdc.com> Signed-off-by: Michae

[Qemu-devel] [PATCH v1 13/30] RISC-V: Implement mstatus.TSR/TW/TVM

2018-05-22 Thread Michael Clark
.com> Cc: Matthew Suozzo <msuo...@google.com> Signed-off-by: Michael Clark <m...@sifive.com> Co-authored-by: Matthew Suozzo <msuo...@google.com> Co-authored-by: Michael Clark <m...@sifive.com> --- target/riscv/csr.c | 17 + target/riscv/op_helper.c

[Qemu-devel] [PATCH v1 07/30] RISC-V: Update CSR and interrupt definitions

2018-05-22 Thread Michael Clark
.@wdc.com> Signed-off-by: Michael Clark <m...@sifive.com> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> --- target/riscv/cpu_bits.h | 692 +-- target/riscv/op_helper.c | 4 +- 2 files changed, 376 insertions(+), 320 del

[Qemu-devel] [PATCH v1 01/30] RISC-V: Update address bits to support sv39 and sv48

2018-05-22 Thread Michael Clark
Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: Palmer Dabbelt Cc: Alistair Francis Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.h | 8 1 file changed, 4

[Qemu-devel] [PATCH v1 08/30] RISC-V: Implement modular CSR helper interface

2018-05-22 Thread Michael Clark
<kbast...@mail.uni-paderborn.de> Cc: Palmer Dabbelt <pal...@sifive.com> Cc: Alistair Francis <alistair.fran...@wdc.com> Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/Makefile.objs | 2 +- target/riscv/cpu.h | 18 +- target/riscv/cpu_helper.c

[Qemu-devel] [PATCH v1 04/30] RISC-V: Simplify riscv_cpu_local_irqs_pending

2018-05-22 Thread Michael Clark
This commit is intended to improve readability. There is no change to the logic. Cc: Sagar Karandikar <sag...@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Cc: Palmer Dabbelt <pal...@sifive.com> Cc: Alistair Francis <alistair.fran...@wdc.com>

[Qemu-devel] [PATCH v1 02/30] RISC-V: Improve page table walker spec compliance

2018-05-22 Thread Michael Clark
for PTE X flag and mstatus.mxr - Use memory_region_is_ram in pte update Cc: Sagar Karandikar <sag...@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Cc: Palmer Dabbelt <pal...@sifive.com> Cc: Alistair Francis <alistair.fran...@wdc.com> Signed-

[Qemu-devel] [PATCH v1 00/30] QEMU 2.13 RISC-V updates

2018-05-22 Thread Michael Clark
board test (HiFive1 binaries): pass * sifive_u board test (HiFive Unleashed): pass * riscv-tests: pass * checkpatch: pass Kito Cheng (1): RISC-V: linux-user support for RVE ABI Michael Clark (27): RISC-V: Update address bits to support sv39 and sv48 RISC-V: Improve page table walker spec

Re: [Qemu-devel] [PATCH] RISC-V: make it possible to alter default reset vector

2018-05-17 Thread Michael Clark
rt in a SiFive tree. I'll leave the RFC proper for another email. This is just an abstract. BTW - there are plently of others you can get to accept this patch ;-) See the 'Cc. Signed-off-by: Antony Pavlov <antonynpav...@gmail.com> > Cc: Michael Clark <m...@sifive.com> > Cc: Palmer Dabbel

Re: [Qemu-devel] [PATCH 4/9] target/riscv: Introduce cpu_riscv_get_fcsr

2018-05-17 Thread Michael Clark
On Fri, May 11, 2018 at 3:52 PM, Richard Henderson < richard.hender...@linaro.org> wrote: > Cc: Michael Clark <m...@sifive.com> > Cc: Palmer Dabbelt <pal...@sifive.com> > Cc: Sagar Karandikar <sag...@eecs.berkeley.edu> > Cc: Bastian Koppelmann <kbast

Re: [Qemu-devel] [PATCH 5/9] target/riscv: Honor CPU_DUMP_FPU

2018-05-17 Thread Michael Clark
On Sun, May 13, 2018 at 12:52 PM, Philippe Mathieu-Daudé <f4...@amsat.org> wrote: > On 05/11/2018 12:52 AM, Richard Henderson wrote: > > Cc: Michael Clark <m...@sifive.com> > > Cc: Palmer Dabbelt <pal...@sifive.com> > > Cc: Sagar Karandikar <sag...@eec

Re: [Qemu-devel] [PATCH v3 4/7] hw/riscv/sifive_u: Set the soc device tree node as a simple-bus

2018-05-17 Thread Michael Clark
On Tue, May 15, 2018 at 12:07 PM, Alistair Francis <alistair.fran...@wdc.com > wrote: > To allow Linux to ennumerate devices on the /soc/ node set it as a > "simple-bus". > > Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> > Reviewed-by: Michael

Re: [Qemu-devel] [PATCH v3 2/7] hw/riscv/sifive_e: Create a SiFive E SoC object

2018-05-17 Thread Michael Clark
On Tue, May 15, 2018 at 12:07 PM, Alistair Francis <alistair.fran...@wdc.com > wrote: > Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> > Reviewed-by: Michael Clark <m...@sifive.com> > --- > hw/riscv/sifive_e.c | 97 +++

Re: [Qemu-devel] [PATCH v2] riscv: remove define cpu_init()

2018-05-17 Thread Michael Clark
On Wed, May 16, 2018 at 4:00 AM, Igor Mammedov <imamm...@redhat.com> wrote: > cpu_init() was removed since 2.12, so drop the define that is now unused. > > Signed-off-by: Igor Mammedov <imamm...@redhat.com> > Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org> &g

Re: [Qemu-devel] [PATCH v2 20/27] target/riscv: Remove floatX_maybe_silence_nan from conversions

2018-05-12 Thread Michael Clark
On Sat, May 12, 2018 at 12:43 PM, Richard Henderson < richard.hender...@linaro.org> wrote: > This is now handled properly by the generic softfloat code. > > Cc: Michael Clark <m...@sifive.com> > Cc: Palmer Dabbelt <pal...@sifive.com> > Cc: Sagar Karandikar <sag

Re: [Qemu-devel] [PATCH v2 5/7] hw/riscv/sifive_u: Set the interrupt controler number of interrupts

2018-05-12 Thread Michael Clark
iscv/virt.c we have removed hardcoding a few more constants using in the device tree. e.g. we allocate and resolve phandles vs hardcoding them. We can alwauys make a follow up commits to move some of these magic numbers into constants in the headers, preferably with enum vs #define. Re

Re: [Qemu-devel] [PATCH v2 7/7] hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device

2018-05-12 Thread Michael Clark
On Sat, May 12, 2018 at 11:28 AM, Alistair Francis <alistair.fran...@wdc.com > wrote: > Connect the Cadence GEM ethernet device. This also requires us to > expose the plic interrupt lines. > > Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> > Re

Re: [Qemu-devel] [PATCH v2 6/7] hw/riscv/sifive_u: Move the uart device tree node under /soc/

2018-05-12 Thread Michael Clark
On Sat, May 12, 2018 at 11:28 AM, Alistair Francis <alistair.fran...@wdc.com > wrote: > Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> > Reviewed-by: Michael Clark <m...@sifive.com> > --- > hw/riscv/sifive_u.c | 2 +- > 1 file changed, 1 insertion

Re: [Qemu-devel] [PATCH v2 1/7] hw/riscv/sifive_u: Create a U54 SoC object

2018-05-12 Thread Michael Clark
lace the prefix "riscv_sifive_u54" to "riscv_sifive_u_soc" - Rename TYPE_RISCV_U54_SOC to TYPE_RISCV_U_SOC - Rename SiFiveU54State SiFiveUSOC (I don't think we need the State suffix for the SOC) Assuming we can do the renames to keep the SiFive U Series machine/SOC general: Reviewed-by: Michae

Re: [Qemu-devel] [PULL 0/3] RISC-V: QEMU 2.13 Minor Fixes

2018-05-09 Thread Michael Clark
On Wed, 9 May 2018 at 11:14 PM, Peter Maydell <peter.mayd...@linaro.org> wrote: > On 8 May 2018 at 23:05, Michael Clark <m...@sifive.com> wrote: > > > > > > On Wed, May 9, 2018 at 8:49 AM, Peter Maydell <peter.mayd...@linaro.org> > > wrote: >

[Qemu-devel] [PULL 3/3] riscv: requires libfdt

2018-05-09 Thread Michael Clark
rned 1 exit status make[1]: *** [qemu-system-riscv64] Error 1 make: *** [subdir-riscv64-softmmu] Error 2 Cc: qemu-sta...@nongnu.org Reviewed-by: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org> Reviewed-by: Michael Clark <m...@s

[Qemu-devel] [PULL 0/3] RISC-V: QEMU 2.13 Minor Fixes

2018-05-09 Thread Michael Clark
The following changes since commit c8b7e627b4269a3bc3ae41d9f420547a47e6d9b9: Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2018-05-04' into staging (2018-05-04 14:42:46 +0100) are available in the git repository at: https://github.com/riscv/riscv-qemu.git

[Qemu-devel] [PULL 1/3] riscv: spike: allow base == 0

2018-05-09 Thread Michael Clark
From: KONRAD Frederic <frederic.kon...@adacore.com> The sanity check on base doesn't allow htif to be mapped @0. Check if the symbol exists instead so we can map it where we want. Reviewed-by: Michael Clark <m...@sifive.com> Signed-off-by: KONRAD Frederic <frederic.kon...@adacore.

[Qemu-devel] [PULL 2/3] riscv: htif: increase the priority of the htif subregion

2018-05-09 Thread Michael Clark
00-0200 (prio 0, i/o): riscv.sifive.clint 8000-87ff (prio 0, ram): riscv.spike.ram Reviewed-by: Michael Clark <m...@sifive.com> Signed-off-by: KONRAD Frederic <frederic.kon...@adacore.com> Signed-off-by: Michael Clark <m...@sifive.com> Message-Id:

[Qemu-devel] [PATCH v1 5/6] target/riscv: convert to TranslatorOps

2018-05-09 Thread Michael Clark
From: "Emilio G. Cota" <c...@braap.org> Reviewed-by: Richard Henderson <richard.hender...@linaro.org> Cc: Michael Clark <m...@sifive.com> Cc: Palmer Dabbelt <pal...@sifive.com> Cc: Sagar Karandikar <sag...@eecs.berkeley.edu> Cc: Bastian Koppelmann <

[Qemu-devel] [PATCH v1 6/6] target/riscv: add misa to DisasContext

2018-05-09 Thread Michael Clark
keley.edu> Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Cc: Alistair Francis <alistair.fran...@wdc.com> Cc: Emilio G. Cota <c...@braap.org> Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/translate.c | 77 ++-

[Qemu-devel] [PATCH v1 2/6] translator: merge max_insns into DisasContextBase

2018-05-09 Thread Michael Clark
From: "Emilio G. Cota" While at it, use int for both num_insns and max_insns to make sure we have same-type comparisons. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- accel/tcg/translator.c | 21

[Qemu-devel] [PATCH v1 4/6] target/riscv: convert to DisasContextBase

2018-05-09 Thread Michael Clark
>cflags readers to tb_cflags(). Reviewed-by: Richard Henderson <richard.hender...@linaro.org> Cc: Michael Clark <m...@sifive.com> Cc: Palmer Dabbelt <pal...@sifive.com> Cc: Sagar Karandikar <sag...@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbast...@mail.uni-p

[Qemu-devel] [PATCH v1 3/6] target/riscv: convert to DisasJumpType

2018-05-09 Thread Michael Clark
From: "Emilio G. Cota" <c...@braap.org> Reviewed-by: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <richard.hender...@linaro.org> Cc: Michael Clark <m...@sifive.com> Cc: Palmer Dabbelt <pal...@sifive.com> Cc: Sagar

[Qemu-devel] [PATCH v1 1/6] target/riscv: avoid integer overflow in next_page PC check

2018-05-09 Thread Michael Clark
viewed-by: Richard Henderson <richard.hender...@linaro.org> Reviewed-by: Michael Clark <m...@sifive.com> Acked-by: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Cc: Michael Clark <m...@sifive.com> Cc: Palmer Dabbelt <pal...@sifive.com> Cc: Sagar Karandikar <sag...

[Qemu-devel] [PATCH v1 0/6] Translation loop conversion for riscv

2018-05-09 Thread Michael Clark
Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Cc: Alistair Francis <alistair.fran...@wdc.com> Cc: Emilio G. Cota <c...@braap.org> Signed-off-by: Michael Clark <m...@sifive.com> Emilio G. Cota (5): target/riscv: avoid integer overflow in next_page PC

Re: [Qemu-devel] [PATCH 18/18] target/riscv: convert to TranslatorOps

2018-05-09 Thread Michael Clark
On Sat, Apr 21, 2018 at 6:55 AM, Emilio G. Cota <c...@braap.org> wrote: > Reviewed-by: Richard Henderson <richard.hender...@linaro.org> > Cc: Michael Clark <m...@sifive.com> > Cc: Palmer Dabbelt <pal...@sifive.com> > Cc: Sagar Karandikar <sag...@eecs.berkel

Re: [Qemu-devel] [PATCH 01/18] translator: merge max_insns into DisasContextBase

2018-05-09 Thread Michael Clark
lio G. Cota <c...@braap.org> > Reviewed-by: Michael Clark <m...@sifive.com> > --- > accel/tcg/translator.c | 21 ++--- > include/exec/translator.h | 8 > target/alpha/translate.c | 6 ++ > target/arm/translate-a64.c | 8 +++- &g

[Qemu-devel] [PATCH v1] RISC-V: Add misa to DisasContext

2018-05-09 Thread Michael Clark
aderborn.de> Cc: Alistair Francis <alistair.fran...@wdc.com> Cc: Emilio G. Cota <c...@braap.org> Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/translate.c | 74 ++-- 1 file changed, 40 insertions(+), 34 deletions(-) d

Re: [Qemu-devel] [PATCH 00/10] Avoid integer overflow in next_page_start

2018-05-08 Thread Michael Clark
On Thu, Apr 12, 2018 at 11:56 AM, Richard Henderson < richard.hender...@linaro.org> wrote: > On 04/12/2018 01:29 AM, Emilio G. Cota wrote: > > To ease an eventual merge I'll be updating the patches' R-b tags as > > they come in this branch: > >

Re: [Qemu-devel] [PULL 00/20] RISC-V: QEMU 2.13 Privileged ISA emulation updates

2018-05-08 Thread Michael Clark
On Wed, May 9, 2018 at 1:22 AM, Peter Maydell <peter.mayd...@linaro.org> wrote: > On 6 May 2018 at 00:35, Michael Clark <m...@sifive.com> wrote: > > The following changes since commit c8b7e627b4269a3bc3ae41d9f42054 > 7a47e6d9b9: > > > > Merge remote-tracking

Re: [Qemu-devel] [PATCH] RISC-V: Remove unnecessary header include

2018-05-08 Thread Michael Clark
On Wed, May 9, 2018 at 2:42 AM, Philippe Mathieu-Daudé <f4...@amsat.org> wrote: > Signed-off-by: Philippe Mathieu-Daudé <f4...@amsat.org> > Reviewed-by: Michael Clark <m...@sifive.com> --- > hw/riscv/riscv_htif.c | 1 - > hw/riscv/sifive_e.c | 1 - > hw/ris

Re: [Qemu-devel] [PULL 0/3] RISC-V: QEMU 2.13 Minor Fixes

2018-05-08 Thread Michael Clark
On Wed, May 9, 2018 at 8:49 AM, Peter Maydell <peter.mayd...@linaro.org> wrote: > On 8 May 2018 at 21:07, Michael Clark <m...@sifive.com> wrote: > > The following changes since commit c8b7e627b4269a3bc3ae41d9f42054 > 7a47e6d9b9: > > > > Merge remote-tracking

[Qemu-devel] [PULL 2/3] riscv: htif: increase the priority of the htif subregion

2018-05-08 Thread Michael Clark
00-0200 (prio 0, i/o): riscv.sifive.clint 8000-87ff (prio 0, ram): riscv.spike.ram Reviewed-by: Michael Clark <m...@sifive.com> Signed-off-by: KONRAD Frederic <frederic.kon...@adacore.com> Signed-off-by: Michael Clark <m...@sifive.com> Message-Id:

[Qemu-devel] [PULL 1/3] riscv: spike: allow base == 0

2018-05-08 Thread Michael Clark
From: KONRAD Frederic <frederic.kon...@adacore.com> The sanity check on base doesn't allow htif to be mapped @0. Check if the symbol exists instead so we can map it where we want. Reviewed-by: Michael Clark <m...@sifive.com> Signed-off-by: KONRAD Frederic <frederic.kon...@adacore.

[Qemu-devel] [PULL 3/3] riscv: requires libfdt

2018-05-08 Thread Michael Clark
rned 1 exit status make[1]: *** [qemu-system-riscv64] Error 1 make: *** [subdir-riscv64-softmmu] Error 2 Reviewed-by: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org> Reviewed-by: Michael Clark <m...@sifive.com> Signed

[Qemu-devel] [PULL 0/3] RISC-V: QEMU 2.13 Minor Fixes

2018-05-08 Thread Michael Clark
The following changes since commit c8b7e627b4269a3bc3ae41d9f420547a47e6d9b9: Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2018-05-04' into staging (2018-05-04 14:42:46 +0100) are available in the git repository at: https://github.com/riscv/riscv-qemu.git

Re: [Qemu-devel] [PULL 0/3] RISC-V: QEMU 2.13 Minor Fixes

2018-05-08 Thread Michael Clark
On Wed, May 9, 2018 at 4:05 AM, Peter Maydell <peter.mayd...@linaro.org> wrote: > On 8 May 2018 at 00:14, Michael Clark <m...@sifive.com> wrote: > > The following changes since commit c8b7e627b4269a3bc3ae41d9f42054 > 7a47e6d9b9: > > > > Merge remote-tracking

[Qemu-devel] [PULL 3/3] riscv: requires libfdt

2018-05-07 Thread Michael Clark
rned 1 exit status make[1]: *** [qemu-system-riscv64] Error 1 make: *** [subdir-riscv64-softmmu] Error 2 Reviewed-by: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org> Reviewed-by: Michael Clark <m...@sifive.com> Signed

[Qemu-devel] [PULL 2/3] riscv: htif: increase the priority of the htif subregion

2018-05-07 Thread Michael Clark
00-0200 (prio 0, i/o): riscv.sifive.clint 8000-87ff (prio 0, ram): riscv.spike.ram Reviewed-by: Michael Clark <m...@sifive.com> Signed-off-by: KONRAD Frederic <frederic.kon...@adacore.com> Message-Id: <1525360636-18229-3-git-send-email-frederic.kon...

[Qemu-devel] [PULL 1/3] riscv: spike: allow base == 0

2018-05-07 Thread Michael Clark
From: KONRAD Frederic <frederic.kon...@adacore.com> The sanity check on base doesn't allow htif to be mapped @0. Check if the symbol exists instead so we can map it where we want. Reviewed-by: Michael Clark <m...@sifive.com> Signed-off-by: KONRAD Frederic <frederic.kon...@adacor

[Qemu-devel] [PULL 0/3] RISC-V: QEMU 2.13 Minor Fixes

2018-05-07 Thread Michael Clark
The following changes since commit c8b7e627b4269a3bc3ae41d9f420547a47e6d9b9: Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2018-05-04' into staging (2018-05-04 14:42:46 +0100) are available in the git repository at: https://github.com/riscv/riscv-qemu.git

[Qemu-devel] [PULL 19/20] RISC-V: No traps on writes to misa, minstret, mcycle

2018-05-05 Thread Michael Clark
rn.de> Cc: Palmer Dabbelt <pal...@sifive.com> Cc: Alistair Francis <alistair.fran...@wdc.com> Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/op_helper.c | 25 + 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/target/ri

[Qemu-devel] [PULL 17/20] RISC-V: Add mcycle/minstret support for -icount auto

2018-05-05 Thread Michael Clark
instructions will return the instruction count. Cc: Sagar Karandikar <sag...@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Cc: Palmer Dabbelt <pal...@sifive.com> Cc: Alistair Francis <alistair.fran...@wdc.com> Signed-off-by: Michael Clark &l

[Qemu-devel] [PULL 10/20] RISC-V: Remove EM_RISCV ELF_MACHINE indirection

2018-05-05 Thread Michael Clark
Pointless indirection. Other ports use EM_ constants directly. Cc: Sagar Karandikar <sag...@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Signed-off-by: Michael Clark <m...@sifive.com> Signed-off-by: Palmer Dabbelt <pal...@sifive.com> Revie

[Qemu-devel] [PULL 13/20] RISC-V: Hardwire satp to 0 for no-mmu case

2018-05-05 Thread Michael Clark
and more complex trap handling code). Cc: Sagar Karandikar <sag...@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Cc: Palmer Dabbelt <pal...@sifive.com> Cc: Alistair Francis <alistair.fran...@wdc.com> Signed-off-by: Michael Clark <m...@sifive

[Qemu-devel] [PULL 18/20] RISC-V: Make mtvec/stvec ignore vectored traps

2018-05-05 Thread Michael Clark
) fields is to drop writes to unsupported bits. Cc: Sagar Karandikar <sag...@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Cc: Palmer Dabbelt <pal...@sifive.com> Cc: Alistair Francis <alistair.fran...@wdc.com> Signed-off-by: Michael Clark <m

[Qemu-devel] [PULL 09/20] RISC-V: Make virt header comment title consistent

2018-05-05 Thread Michael Clark
Cc: Sagar Karandikar <sag...@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Signed-off-by: Michael Clark <m...@sifive.com> Signed-off-by: Palmer Dabbelt <pal...@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>

[Qemu-devel] [PULL 12/20] RISC-V: Update E and I extension order

2018-05-05 Thread Michael Clark
.@wdc.com> Signed-off-by: Michael Clark <m...@sifive.com> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5a527fbba0

  1   2   3   4   5   6   7   >