Public bug reported:
qemu 0.15.1
Interrupts does not work anymore if system reseted from interrupt.
There is no reset function registered for armv7m_nvic, and as it is part
of the core there is also no any reset for gic/nvic in cpu_reset() for
arm.
possible solution is to add reset function to
Public bug reported:
I have this error.
qemu: fatal: Trying to execute code outside RAM or ROM at 0x1000
R00=e000ed04 R01=3f5e392e R02=00ff R03=007e
R04=20007038 R05=20003e30 R06= R07=0003
R08= R09=00012874 R10=10101010 R11=
R12= R13=200031d0
Changes where made in
static void do_interrupt_v7m(CPUARMState *env)
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https://bugs.launchpad.net/bugs/944645
Title:
ARM: CORTEX M, ICI/IT bits in XPSR were not cleared then entering
** Attachment added: qemu gcc 4.6.1 bug.pdf
https://bugs.launchpad.net/bugs/944753/+attachment/2800876/+files/qemu%20gcc%204.6.1%20bug.pdf
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https://bugs.launchpad.net/bugs/944753
Public bug reported:
Just want to warn anyone who hacks QEMU cortex M support under MinGW, it
seems there is a bug in gcc 4.6.1 that compiles this peace of code
wrong.
translate.c:
if (IS_M(env)) {
tmp = tcg_const_i32((insn (1 4)) != 0);
/* PRIMASK
Yes, thanks. I have mentioned that too.
About:
but really you need to report gcc bugs to the gcc folks, not us.
I sow in source code that there are workarounds for different compilers
bugs on different platforms.
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I had the same problem then was trying to run project based on uC OS2.
So there is no problem in freeRtos or in uCOS and it is better to do
change in helper.c in function:
static void do_v7m_exception_exit(CPUARMState *env)
replace line
env-regs[15] = v7m_pop(env);
with
env-regs[15] =
From the manual
DDI0403C_arm_architecture_v7m_reference_manual_errata_markup_2_0.pdf
A6.7.97 POP
Pop Multiple Registers loads a subset (or possibly all) of the general-purpose
registers R0-R12 and the PC
or the LR from the stack.
If the registers loaded include the PC, the word loaded for the PC
Thanks for clarification. Now I understood what you there talking about
PopStack pseudocode function.
(4) It is entirely possible that hardware implementations to date ignore
the lsbit in this situation. That doesn't mean that software which
relies on this UNPREDICTABLE behaviour is not buggy.
Public bug reported:
qemu version 0.15.1
but the same code is in qemu 1.0
CPSID I does not disable interrupts for CORTEX M3
if (interrupt_request CPU_INTERRUPT_HARD
((IS_M(env) env-regs[15] 0xfff0)
|| !(env-uncached_cpsr CPSR_I))) {
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