On Tue, 16 Aug 2022 at 14:34, Alex Bennée wrote:
> Peter Maydell writes:
> > Is there some place (in the superclass??) that we can put a
> > default timeout that applies to *all* avocado tests, so we
> > don't have the risk of forgetting it in a particular test?
>
> I
On Sat, 13 Aug 2022 at 14:32, Marc Zyngier wrote:
> But we probably need to handle EINTR when creating the mini VM.
It's easy enough to add a retry-on-EINTR loop to the KVM_CREATE_VM
ioctl in the target/arm/ code. But do we need to do that more
widely ? At the moment QEMU seems to assume that
On Tue, 16 Aug 2022 at 13:26, Alex Bennée wrote:
>
> On some systems the test can hang. At least defining a timeout stops
> it from hanging forever.
Aha. Yeah, I've seen this test hang forever sometimes.
Is there some place (in the superclass??) that we can put a
default timeout that applies to
Hi; we haven't had an in-person KVM Forum for a while. This seems
like a good opportunity for people who are or who expect to be
submitting pull requests to get their GPG key signed, if it's
not been signed by anybody else yet or it's a bit low on signatures.
If that's you, and you're planning to
On Tue, 16 Aug 2022 at 10:59, Alex Bennée wrote:
> Shiny Saana writes:
> > I personally don't need any of the GPIO interfaces, but if needed
> > by someone else, that could be a good second step to
> > work on once that part of the board is implemented.
>
> Handling GPIOs in QEMU is fine (we
On Tue, 16 Aug 2022 at 10:40, zhukeqian wrote:
>
> Hi Peter,
>
> Setup an ARM virtual machine of machine virt and execute qmp
> "query-acpi-ospm-status" can trigger this bug.
Thanks. That is worth stating in the commit message, I think.
-- PMm
On Tue, 16 Aug 2022 at 10:26, Keqian Zhu wrote:
>
> This fixes a bug that causes segmentation fault with following dumpstack:
> #1 0xab64235c in qmp_query_acpi_ospm_status
> (errp=errp@entry=0xf030) at ../monitor/qmp-cmds.c:312
> #2 0xabfc4e20 in
semihosting calls from userspace they must now specifically
enable them on the command line.
xtensa semihosting is not implemented for linux-user builds.
Signed-off-by: Peter Maydell
---
target/xtensa/translate.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/target
semihosting calls from userspace they must now specifically
enable them on the command line.
MIPS semihosting is not implemented for linux-user builds.
Signed-off-by: Peter Maydell
---
target/mips/tcg/translate.c | 9 +
target/mips/tcg/micromips_translate.c.inc | 6
to
semihosting being enabled, and now the user must pass
"-semihosting-config enable=on" if they want it.
Signed-off-by: Peter Maydell
---
target/riscv/cpu_helper.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_help
if the guest is in userspace and this
isn't the linux-user build.
Signed-off-by: Peter Maydell
---
target/arm/translate-a64.c | 12 +---
target/arm/translate.c | 16
2 files changed, 5 insertions(+), 23 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm
if the guest is in userspace.
(Note that target/m68k doesn't support semihosting at all
in the linux-user build.)
Signed-off-by: Peter Maydell
---
target/m68k/op_helper.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c
index
semihosting calls from userspace they must now specifically
enable them on the command line.
nios2 semihosting is not implemented for linux-user builds.
Signed-off-by: Peter Maydell
---
target/nios2/translate.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/nios2
hosting enabled in general". Subsequent
commits will make each target that implements semihosting honour the
userspace=on option by passing the correct value and removing
whatever "don't do this for userspace" checking they were doing by
hand.
Signed-off-by: Peter Maydell
---
inclu
eally tested this much, just 'make check'
and 'make check-avocado'; I wanted to get it out to the
mailing list for discussion, anyway.
thanks
-- PMM
Peter Maydell (7):
semihosting: Allow optional use of semihosting from userspace
target/arm: Honour -semihosting-config userspace=on
target/m6
On Mon, 15 Aug 2022 at 16:53, vaishu venkat wrote:
>
> Hi team,
> We are currently required to use QEMU for virtualization of
> customized application. The application requires Bluetooth and Wi-fi support,
> as observed below warning,
> qemu-system-aarch64: -bt hci,host: warning:
On Mon, 15 Aug 2022 at 15:55, Jonathan Cameron via wrote:
> In the interests of defensive / correct handling from QEMU I took a
> look into why it was crashing. Turns out that providing a NULL write
> callback for
> the memory device region (that the above overlarge write was spilling into)
>
On Sat, 13 Aug 2022 at 18:54, Shiny Saana wrote:
> I'd like to implement support for emulating the teensy 4.1 board (
> https://www.pjrc.com/store/teensy41.html) to QEMU.
>
> I'm honestly quite lost as to where to start at the moment, since
> I can't really find any emulated Cortex-M7 that would
On Mon, 15 Aug 2022 at 12:22, Gerd Hoffmann wrote:
>
> On Mon, Aug 01, 2022 at 02:23:55PM +0100, Peter Maydell wrote:
> > I've been debugging a segfault in the raspi3b display device, and I've
> > tracked it down to a race condition, but I'm not sure what the ri
On Sat, 13 Aug 2022 at 12:27, Anton Kochkov wrote:
>
> Cortex-M NVIC can be configured with different amount of
> the maximum available priority bits. FreeRTOS has asserts
> that checks if the all unavailable priority bits are unset
> after writing into this register in real hardware.
This
On Sat, 13 Aug 2022 at 00:23, Furquan Shaikh wrote:
>
> Unlike ARM, RISC-V does not define a separate breakpoint type for
> semihosting. Instead, it is entirely ABI. Thus, we need an option
> to allow users to configure what the ebreak behavior should be for
> different privilege levels - M, S,
On Sat, 13 Aug 2022 at 01:53, Furquan Shaikh wrote:
> I ran into a problem when I was testing a project (with a microkernel
> in M-mode and tasks in U-mode) that uses semihosting for debugging.
> The semihosting worked fine for M-mode but not in U-mode. As I started
> digging into this, I
-real-hardware CPU initfn, for a64fx. (This
ordering is partly historical and partly required because a64fx needs
the SVE properties.)
Reorder the file into:
* CPU property support functions
* initfns for real hardware CPUs
* initfns for host and max
* class boilerplate
Signed-off-by: Peter
On Sun, 3 Jul 2022 at 09:25, Richard Henderson
wrote:
>
> This is a major reorg to arm page table walking. While the result
> here is "merely" Hardware-assited Access Flag and Dirty Bit Setting
> (HAFDBS), the ultimate goal is the Realm Management Extension (RME).
> RME "recommends" that HAFDBS
On Fri, 10 Jun 2022 at 17:07, Peter Maydell wrote:
>
> From: Richard Henderson
>
> With ARMv8, this field is always RES0.
> With ARMv7, targeting EL2 and TA=0, it is always 0xA.
I was just looking at this change again because we still
have the loose end of syn_simd_access_trap()
On Fri, 12 Aug 2022 at 15:11, Philipp Tomsich wrote:
>
> On Fri, 12 Aug 2022 at 16:01, Andrew Jones wrote:
> >
> > > Update the decode pattern to reflect the specification.
> >
> > I got hung-up on this for a bit since there isn't any "must-be-0" fields,
>
> Please refer to '“Zifencei”
On Fri, 12 Aug 2022 at 14:17, Philipp Tomsich wrote:
>
> Our decoding of fence-instructions is problematic in respect to the
> RISC-V ISA specification:
> - rs and rd are ignored, but need to be 0
> - fm is ignored
>
> This change adjusts the decode pattern to enfore rs and rd being 0,
> and
(I've added your rwth-aachen.de address because the quicinc
one seems to be bouncing :-( )
On Mon, 18 Jul 2022 at 12:54, Tobias Roehmel wrote:
>
> From: Tobias Röhmel
>
> Signed-off-by: Tobias Röhmel
Having looked a bit more carefully at the architecture
manual, I think this is not complete.
On Mon, 18 Jul 2022 at 12:54, Tobias Roehmel wrote:
>
> From: Tobias Röhmel
>
> Cortex-R52 has the MPUIR register which has the same encoding
> has the MIDR alias with opc2=4. So we only add that alias
> when we are not realizing a Cortex-R.
>
> Signed-off-by: Tobias Röhmel
> ---
>
On Fri, 12 Aug 2022 at 12:44, wrote:
>
> From: Guoyi Tu
>
> qemu_socketpair() will create a pair of connected sockets
> with FD_CLOEXEC set
>
> Signed-off-by: Guoyi Tu
> ---
> include/qemu/sockets.h | 3 +++
> util/osdep.c | 24
> 2 files changed, 27
~~
Rather than trying to be clever, since this is called 3 times during
tests, let's simply use g_strdup_printf().
Signed-off-by: Marc-André Lureau
Reviewed-by: Markus Armbruster
Message-id: 20220810121513.1356081-1-marcandre.lur...@redhat.com
Reviewed-by: Peter Maydell
[PMM: fixed co
On Fri, 12 Aug 2022 at 12:44, wrote:
>
> From: Guoyi Tu
>
> set close-on-exec flag on the new opened file descriptors at default
What goes wrong if we don't do this? The commit message
is a good place to explain what bug the commit is fixing,
and its consequences.
thanks
-- PMM
truncation warning
Peter Maydell (1):
target/arm: Don't report Statistical Profiling Extension in ID registers
Philippe Mathieu-Daudé (1):
cutils: Add missing dyld(3) include on macOS
Stefan Weil (1):
Fix some typos in documentation (most of them found by codespell)
Zenghui Yu (1)
-by: Peter Maydell
Signed-off-by: Peter Maydell
---
util/cutils.c | 4
util/oslib-posix.c | 4
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/util/cutils.c b/util/cutils.c
index cb43dda213c..def9c746ced 100644
--- a/util/cutils.c
+++ b/util/cutils.c
@@ -3
=on).
Reported-by: Zenghui Yu
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Zenghui Yu
Message-id: 20220811131127.947334-1-peter.mayd...@linaro.org
---
target/arm/cpu.c | 11 +++
1 file changed, 11 insertions(+)
diff --git
From: Stefan Weil
Signed-off-by: Stefan Weil
Reviewed-by: Hongren (Zenithal) Zheng
Message-id: 20220812075642.1200578-1...@weilnetz.de
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
docs/about/deprecated.rst | 2 +-
docs/specs/acpi_erst.rst| 4 ++--
docs/system
with
ACPI enabled and '-machine gic-version=4'.
While at it, let's convert the remaining hard coded gic_version into
enumeration VIRT_GIC_VERSION_2 for consistency.
Signed-off-by: Zenghui Yu
Message-id: 20220812022018.1069-1-yuzeng...@huawei.com
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
On Thu, 11 Aug 2022 at 21:47, Furquan Shaikh wrote:
>
> Unlike ARM, RISC-V does not define a separate breakpoint type for
> semihosting. Instead, it is entirely ABI. Thus, we need an option
> to allow users to configure what the ebreak behavior should be for
> different privilege levels - M, S,
On Tue, 9 Aug 2022 at 23:22, Philippe Mathieu-Daudé via
wrote:
>
> Commit 06680b15b4 moved qemu_*_exec_dir() to cutils but forgot
> to move the macOS dyld(3) include, resulting in the following
> error (when building with Homebrew GCC on macOS Monterey 12.4):
>
> [313/1197] Compiling C object
On Tue, 9 Aug 2022 at 19:57, Ben Dooks wrote:
>
> Add a helper for qemu_fdt_setprop_strings() to take a set of strings
> to put into a device-tree, which removes several open-coded methods
> such as setting an char arr[] = {..} or setting char val[] = "str\0str2";
>
> This is for hw/arm, hw/mips
On Fri, 12 Aug 2022 at 03:20, Zenghui Yu wrote:
>
> With the introduction of the new TCG GICv4, build_madt() is badly broken
> as we do not present any GIC Redistributor structure in MADT for GICv4
> guests, so that they have no idea about where the Redistributor
> register frames are. This fixes
On Wed, 10 Aug 2022 at 13:20, wrote:
>
> From: Marc-André Lureau
>
> ../tests/test-qobject-input-visitor.c: In function ‘test_visitor_in_list’:
> ../tests/test-qobject-input-visitor.c:454:49: warning: ‘%d’ directive output
> may be truncated writing between 1 and 10 bytes into a region of size
On Fri, 12 Aug 2022 at 08:59, Stefan Weil via wrote:
>
> Signed-off-by: Stefan Weil
> ---
> docs/about/deprecated.rst | 2 +-
> docs/specs/acpi_erst.rst| 4 ++--
> docs/system/devices/canokey.rst | 8
> docs/system/devices/cxl.rst | 12 ++--
> 4 files
On Fri, 12 Aug 2022 at 08:59, Stefan Weil via wrote:
>
> Signed-off-by: Stefan Weil
> ---
Reviewed-by: Peter Maydell
thanks
-- PMM
I've added some more relevant mailing lists to the cc.
On Fri, 12 Aug 2022 at 09:45, Vitaly Chikunov wrote:
> On Fri, Aug 12, 2022 at 05:14:27AM +0300, Vitaly Chikunov wrote:
> > I noticed that we starting to get many errors like this:
> >
> > qemu-system-aarch64: Failed to retrieve host CPU
On Thu, 11 Aug 2022 at 22:26, Pierre Muller wrote:
>But as I use machines on which I am not admin,
> I needed to compile capstone locally, install it inside my home dir,
> and export PKG_CONFIG_PATH to allow the meson configuration
> to correctly detect this local installation...
Yes, like
On Thu, 11 Aug 2022 at 18:48, Richard Henderson
wrote:
> You can use |= for bool as well. You don't need the short-circuting of ||
> here.
That seems like the kind of thing that -Wbool-operation is likely to
warn about either now or in future, though...
-- PMM
On Thu, 11 Aug 2022 at 18:16, Peter Maydell wrote:
>
> Update the ID registers for TCG's '-cpu max' to report a FEAT_PMUv3p5
> compliant PMU.
>
> Signed-off-by: Peter Maydell
Oops, forgot the docs update:
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
() and
pmenvcntr_op_finish() bring their logic closer into line with that of
pmccntr_op_start() and pmccntr_op_finish(), which already had to cope
with the overflow being either at 32 or 64 bits.)
Signed-off-by: Peter Maydell
---
target/arm/cpu.h | 1 +
target/arm/internals.h | 3 +-
target
-i -e 's/pmu_8_/pmuv3p/g' target/arm/*.[ch]
Signed-off-by: Peter Maydell
---
target/arm/cpu.h| 16
target/arm/helper.c | 18 +-
2 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 5168e3d837e..122ec8a47ec
FEAT_PMUv3p5 introduces new bits MDCR_EL2.HCCD and MDCR_EL3.SCCD,
which disable the cycle counter from counting at EL2 and EL3.
Add the code to support these bits.
Signed-off-by: Peter Maydell
---
target/arm/cpu.h| 20
target/arm/helper.c | 20
2
.
Signed-off-by: Peter Maydell
---
target/arm/helper.c | 17 +
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 7a367371921..41def52cf7b 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1172,6 +1172,17
Update the ID registers for TCG's '-cpu max' to report a FEAT_PMUv3p5
compliant PMU.
Signed-off-by: Peter Maydell
---
target/arm/cpu64.c | 2 +-
target/arm/cpu_tcg.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index
was that a guest could write to the bits
in the high half of registers like PMCNTENSET_EL0 that are supposed
to be RES0.
Signed-off-by: Peter Maydell
---
target/arm/internals.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index
that updates to the various
registers which affect whether the PMU is counting are handled
correctly.
Signed-off-by: Peter Maydell
---
target/arm/helper.c | 45 +
1 file changed, 45 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
ur in this situation is simply to not
try to set the timer if it would be beyond that point. Detect the
overflow, and skip setting the timer in that case.
Signed-off-by: Peter Maydell
---
target/arm/helper.c | 22 ++
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a
When the cycle counter overflows, we are intended to set bit 31 in PMOVSR
to indicate this. However a missing ULL suffix means that we end up
setting all of bits 63-31. Fix the bug.
Signed-off-by: Peter Maydell
---
target/arm/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
, with the overflow detection
configurably at the 32 bit or 64 bit mark
It also fixes a set of bugs in the existing PMU emulation which I
discovered while trying to test my additions.
This is of course all intended for 7.2.
thanks
-- PMM
Peter Maydell (10):
target/arm: Don't corrupt high half of PMOVSR
bits MDCR_EL2.HCCD and MDCR_EL3.SCCD.
Signed-off-by: Peter Maydell
---
target/arm/helper.c | 17 +++--
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 41def52cf7b..434885d024a 100644
--- a/target/arm/helper.c
+++ b/target/arm
On Thu, 11 Aug 2022 at 14:35, Pierre Muller wrote:
>I don't know if this is the right place to submit this report,
> but I have a problem with my attempt to check the 7.1.0 release candidate
> for linux user powerpc CPU.
>
>I am testing a simple executable, compiled with Free Pacal
On Thu, 11 Aug 2022 at 16:24, Alex Bennée wrote:
>
> Hi,
>
> I've been collecting a number of small fixes since the tree was
> frozen. I've been mostly focusing on improving the reliability of the
> avocado tests and seeing if there are any low hanging fruit for
> improving the performance.
>
=on).
Reported-by: Zenghui Yu
Signed-off-by: Peter Maydell
---
I think we missed this earlier because it happens not to be hit if
you boot the kernel into EL1, only EL2.
---
target/arm/cpu.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index
s anyway.
> >> Richard, do you know a reason to consider this critical?
> >>
> >> On Wed, 10 Aug 2022 at 13:04, Peter Maydell >> <mailto:peter.mayd...@linaro.org>> wrote:
> >>
> >> On Wed, 10 Aug 2022 at 21:00, Vitaly Buka >
On Thu, 11 Aug 2022 at 11:09, Marc-André Lureau
wrote:
> On Thu, Aug 11, 2022 at 1:05 PM Markus Armbruster wrote:
>> Your moves tear closely related code apart. This is going to be a drag
>> for developers in general and maintainers in particular.
>>
>> Ergonomics suffer when related code is in
On Wed, 10 Aug 2022 at 21:00, Vitaly Buka wrote:
>
> How can we land this one?
Pinging it a week ago rather than now would have been a good start :-(
I think it got missed because you didn't cc the linux-user maintainer.
Is this a critical fix for 7.1 or can we let it slip to 7.2 ?
thanks
--
On Wed, 10 Aug 2022 at 14:14, Zenghui Yu wrote:
> The r4p1 TRM says that the Neoverse N1 core supports SPE (the value
> of ID_AA64DFR0.PMSVer is 0b0001) but do we really support SPE
> emulation in QEMU?
>
> The guest immediately received an unexpected exception (with EC==0,
> at EFI stage) when I
On Wed, 10 Aug 2022 at 06:59, Laurent Vivier wrote:
>
> Le 09/08/2022 à 11:51, Peter Maydell a écrit :
> > Laurent, ping ?
>
> Sorry, I didn't see your message. I'm going to apply it if it's ok to go into
> rc3?
Not sure about rc3; I'd have been OK with it in rc2 but I th
On Tue, 9 Aug 2022 at 19:50, Ben Dooks wrote:
>
> On Mon, Aug 01, 2022 at 12:30:22PM +0100, Peter Maydell wrote:
> > On Wed, 27 Jul 2022 at 23:39, Ben Dooks wrote:
> > >
> > > Change to using the qemu_fdt_setprop_strings() helper in
> > > hw/core cod
On Tue, 9 Aug 2022 at 19:48, Ben Dooks wrote:
>
> On Mon, Aug 01, 2022 at 12:37:33PM +0100, Peter Maydell wrote:
> > On Wed, 27 Jul 2022 at 23:44, Ben Dooks wrote:
> > > @@ -285,8 +280,6 @@ static void fdt_add_gem_nodes(VersalVirt *s)
> > >
> > > stati
on a single thread anyway,
not holding the lock is likely mostly not going to introduce
races, but it can cause us to trip over assertions that we
do hold the lock, such as the one reported in issue 1130.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1130
Signed-off-by: Peter Maydell
Reviewed
:
* icount: Take iothread lock when running QEMU timers
Peter Maydell (1):
icount: Take iothread lock when running QEMU timers
accel/tcg/tcg-accel-ops-icount.c | 6 ++
1 file changed, 6 insertions(+)
Laurent, ping ?
thanks
-- PMM
On Mon, 1 Aug 2022 at 12:43, Peter Maydell wrote:
>
> On Mon, 25 Jul 2022 at 12:13, Daniel P. Berrangé wrote:
> >
> > On Mon, Jul 25, 2022 at 12:00:35PM +0100, Peter Maydell wrote:
> > > For handling guest POSIX timers
On Mon, 8 Aug 2022 at 18:57, BB wrote:
> Am 8. August 2022 14:15:40 MESZ schrieb Igor Mammedov :
> >On Wed, 3 Aug 2022 19:26:30 +0200
> >While refactoring we should keep migration stream compatible with older
> >QEMU versions (we must not regress widely x86 code path). Which might be
> >tricky in
Hi; I just reduced QEMU's storage usage on gitlab by 130GB (no typo!)
using https://gitlab.com/eskultety/gitlab_cleaner, which Dan helpfully
pointed me at. This script removes old pipelines, which take up a
lot of storage space for QEMU because they include the stdout logs
for all the CI jobs in
On Mon, 8 Aug 2022 at 18:05, BALATON Zoltan wrote:
> But the handler we register here just calls cpu_reset which seems to just
> call the reset method of the CPU object. If we have nothing else to do
> here do we need to explicitly call cpi_reset like this? Wouldn't the CPU
> object be reset by
On Sat, 6 Aug 2022 at 12:24, BALATON Zoltan wrote:
> I may look at it later when Peter's second patch changing
> this code lands if there are any cleanups possible
You mean the 2nd patch I sent in that RFC series? I'm not
currently totally sure what I want to do with that. Looking
at the code
On Sat, 6 Aug 2022 at 12:17, Daniel Henrique Barboza
wrote:
>
> Balaton,
>
> I had a change of heart. The code is too clear that it won't overflow.
> It felt overkill changing var types just for that.
>
> Peter already marked it as Ignored - False Positive in Coverity as well.
> So this would be
On Fri, 5 Aug 2022 at 18:33, Ilya Leoshkevich wrote:
>
> After mprotect(addr, PROT_NONE), addr can still be executed if there
> are cached translations. Drop them.
>
> Signed-off-by: Ilya Leoshkevich
> ---
> accel/tcg/translate-all.c | 17 -
> 1 file changed, 12 insertions(+), 5
On Fri, 5 Aug 2022 at 17:50, BALATON Zoltan wrote:
> This also
> allows to get the cpu without a link with something like:
>
> PPC4XX_MACHINE(current_machine /* or qdev_get_machine() */)->soc.cpu
...and now you have device code that's making assumptions about
the machine and SoC it's in.
Just
Hi; I noticed today that Debian's libslirp-dev package doesn't ship
a static library version of libslirp. I was going to file a Debian
bug about that, but then looking at upstream 'libslirp' I found
that its README.md
https://gitlab.freedesktop.org/slirp/libslirp
only documents how to build a
On Fri, 5 Aug 2022 at 13:55, BALATON Zoltan wrote:
> I know this is a mess curently but QOM is full of boilerplate code which
> is confusing for new people and makes it hard to undestand the code. So
> cutting down the boilerplate and making things simpler would help people
> who want to get
On Fri, 5 Aug 2022 at 12:27, Marc-André Lureau
wrote:
> On Fri, Aug 5, 2022 at 3:11 PM Christian Schoenebeck
> wrote:
> > I was thinking the same as Marc-André before:
> >
> > commit 1dacd88ddcf33eb6ed044c4080e3ef5e3de4b6b6
> > Author: Marc-André Lureau
> > Date: Wed Mar 23 19:57:27 2022
On Fri, 5 Aug 2022 at 11:28, Ilya Leoshkevich wrote:
> On Fri, 2022-08-05 at 09:50 +0100, Peter Maydell wrote:
> > Which guests do you observe this on ? I think we should indeed
> > fix this in the translators. More specifically, I think we should
> > get this correct alread
On Fri, 5 Aug 2022 at 10:53, Zhang Chen wrote:
>
> When enable the virtio-net-pci, guest network packet will
> load the vnet_hdr. In COLO status, the primary VM's network
> packet maybe redirect to another VM, it need filter-redirect
> enable the vnet_hdr flag at the same time, COLO-proxy will
>
On Fri, 5 Aug 2022 at 06:56, Zhang, Chen wrote:
>
>
>
> > -Original Message-
> > From: Jason Wang
> > I wonder under which case we can see data == NULL?
> >
> > AFAIK, data is either dup via packet_new() or assigned to a pointer to the
> > buf
> > in packet_new_nocopy().
>
> Yes, you
On Thu, 4 Aug 2022 at 19:50, Ilya Leoshkevich wrote:
>
> When the first instruction of a translation block is located in a
> non-readable page, qemu-user fills siginfo_t correctly. For the other
> instructions the result is as if it were the first instruction, which
> is not correct.
>
> The
On Thu, 4 Aug 2022 at 19:03, BALATON Zoltan wrote:
> I was trying to find out how to do it but I don't understand QOM enough to
> answer the simple question of how to get the cpu object from QOM. My
> guesses are:
>
> object_resolve_path_type("/machine", TYPE_POWERPC_CPU, NULL)
>
> or maybe
>
>
On Thu, 4 Aug 2022 at 18:32, Qi Hu wrote:
>
More specifically, this is adding support for disassembling
on LoongArch hosts. The handling of disassembling LoongArch
guests is already connected up.
thanks
-- PMM
On Mon, 25 Jul 2022 at 21:24, Daniel Henrique Barboza
wrote:
>
> Coverity reports that commit fc34e81acd51 ("target/ppc: add macros to
> check privilege level") turned the following code unreachable:
>
> if (!prefixed && !(ctx->insns_flags2 & PPC2_LSQ_ISA207)) {
> /* lq and stq were
Ping?
thanks
-- PMM
On Fri, 29 Jul 2022 at 16:59, Peter Maydell wrote:
>
> In rocker_port_phys_link_status() and rocker_port_phys_enable_read()
> we construct a 64-bit value with one bit per front-panel port.
> However we accidentally do the shift as 32-bit arithmetic, w
On Thu, 4 Aug 2022 at 11:07, Thomas Huth wrote:
>
> On 04/08/2022 10.56, Peter Maydell wrote:
> > But the point of TRB_LINK_LIMIT is that regardless of what the
> > contents of the TRBs are, the loop is not supposed to
> > be able to continue for more than TRB_LINK_LIM
On Thu, 4 Aug 2022 at 09:00, Thomas Huth wrote:
>
> On 02/08/2022 16.09, Peter Maydell wrote:
> > On Tue, 2 Aug 2022 at 14:53, Thomas Huth wrote:
> >>
> >> The XHCI code could enter an endless loop in case the guest points
> >> QEMU to fetch TRBs from i
On Wed, 3 Aug 2022 at 18:26, Bernhard Beschow wrote:
>
> On Tue, Aug 2, 2022 at 8:37 AM Philippe Mathieu-Daudé via
> wrote:
>>
>> On 28/7/22 15:16, Igor Mammedov wrote:
>> > On Thu, 28 Jul 2022 13:29:07 +0100
>> > Peter Maydell wrote:
>> >
&
On Fri, 29 Jul 2022 at 14:09, Alberto Faria wrote:
>
> Make non-void static functions whose return values are ignored by
> all callers return void instead.
>
> These functions were found by static-analyzer.py.
>
> Not all occurrences of this problem were fixed.
>
> Signed-off-by: Alberto Faria
On Wed, 3 Aug 2022 at 12:44, Daniel P. Berrangé wrote:
> Inconsistent return value checking is designed-in behaviour for
> QEMU's current Error handling coding pattern with error_abort/fatal.
Yes; I habitually mark as false-positive Coverity reports about
missing error checks where it has not
On Tue, 2 Aug 2022 at 17:43, Daniel P. Berrangé wrote:
>
> The latest glibc 2.36 has extended sys/mount.h so that it
> defines the FSCONFIG_* enum constants. These are historically
> defined in linux/mount.h, and thus if you include both headers
> the compiler complains:
>
> In file included from
On Tue, 20 Aug 2019 at 08:12, Paolo Bonzini wrote:
>
> There is a race between TCG and accesses to the dirty log:
>
> vCPU thread reader thread
> --- ---
> TLB check -> slow path
> notdirty_mem_write
>
On Tue, 2 Aug 2022 at 15:20, Konrad, Frederic wrote:
>
> Hi Peter,
>
> CC'ing Philippe.
>
> > -Original Message-
> > From: Qemu-devel > bounces+fkonrad=amd@nongnu.org> On Behalf Of Peter Maydell
> > Sent: 02 August 2022 14:19
> > To:
On Tue, 2 Aug 2022 at 14:53, Thomas Huth wrote:
>
> The XHCI code could enter an endless loop in case the guest points
> QEMU to fetch TRBs from invalid memory areas. Fix it by properly
> checking the return value of dma_memory_read().
It certainly makes sense to check the return value from
continue to trap, as happens on
hardware.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1132
Signed-off-by: Peter Maydell
---
It would be nice if we could just set the .valid.min_access_size in
the MemoryRegionOps to 1 and have the memory system core synthesize
the 1 and 2 byte accesses
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