On Mon, 2022-05-02 at 01:08 -0700, Peter Delevoryas wrote:
> I was setting gpioV4-7 to "1110" using the QOM pin property handler
> and
> noticed that lowering gpioV7 was inadvertently lowering gpioV4-6 too.
>
> (qemu) qom-set /machine/soc/gpio gpioV4 true
> (qemu) qom-set /machine/soc/gpio
\
> @@ -2767,9 +2767,9 @@ VSX_CVT_FP_TO_FP_VECTOR(xscvdpqp, 1, float64,
> float128, VsrD(0), f128, 1)
> * ttp - target type
> * sfld - source vsr_t field
> * tfld - target vsr_t field
> - * sfprf - set FPRF
> + * sfifprf - set FPRF
set FI and FPRF?
otherwise, Reviewed-by: Rashmica Gupta
signature.asc
Description: This is a digitally signed message part
7.4.3 Floating-Point Overflow Exception' as instructions
that don't modify FR, FI and FPRF. It would be ideal if the ISA
mentioned that there were exceptions in the part that you quoted!
This patch makes sense to me.
Reviewed-by: Rashmica Gupta
>
> The root cause for this seems t
Hello,
cc'ing Paul and Nick for clarification on the behaviour of xsrsp (see below)
On Tue, 2022-05-10 at 17:46 -0300, Víctor Colombo wrote:
> The FI bit in FPSCR is said to be a non-sticky bit on Power ISA.
> One could think this means that, if an instruction is said to modify
> the FPSCR regis
> - GPIOU0..GPIOU7 should have been GPIU0..GPIU7.
> > > - GPIW0..GPIW7 should have been GPIOW0..GPIOW7.
> > > - GPIOY0..GPIOY7 and GPIOZ0...GPIOZ7 were disabled.
> > > Fixes: 4b7f956862dc2db4c5c ("hw/gpio: Add basic Aspeed GPIO model
> > > for AST2400 and AST2500"
On Tue, 2021-07-13 at 16:28 +0930, Joel Stanley wrote:
> There are two GPIO controllers in the ast2600; one is 3.3V and the
> other
> is 1.8V.
>
> Signed-off-by: Joel Stanley
Thanks for picking this up.
Reviewed-by: Rashmica Gupta
> ---
> hw/gp
remove the offset to save future confusion.
>
> Signed-off-by: Joel Stanley
Makes sense, and it is cleaner.
Reviewed-by: Rashmica Gupta
> ---
> hw/gpio/aspeed_gpio.c | 73 +
> --
> 1 file changed, 36 insertions(+), 37 deletions(-)
>
perianal, which happens to be the RTC.
>
> The mmio region used by each device is a maximum of 2KB, so avoid the
> calculations and hard code this as the maximum.
>
> Fixes: 36d737ee82b2 ("hw/gpio: Add in AST2600 specific
> implementation")
> Signed-off-by: Joel Stan
Signed-off-by: Rashmica Gupta
Reviewed-by: Cédric Le Goater
---
include/hw/arm/aspeed_soc.h | 3 +++
hw/arm/aspeed_soc.c | 17 +
2 files changed, 20 insertions(+)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index cef605ad6b..fa04abddd8 100644
source driving the GPIO pins in the model is the ARM
model (as there currently aren't models for the LPC or Coprocessor).
(2) None of the registers in the model are reset tolerant (needs
integration with the watchdog).
Signed-off-by: Rashmica Gupta
Tested-by: Andrew Jeffery
Reviewed-by: Cédri
The AST2600 has the same sets of 3.6v gpios as the AST2400 plus an
addtional two sets of 1.8V gpios.
Signed-off-by: Rashmica Gupta
Reviewed-by: Cédric Le Goater
---
hw/gpio/aspeed_gpio.c | 142 --
1 file changed, 137 insertions(+), 5 deletions(-)
diff
added debounce regs, renamed get/set to
read/write to minimise confusion with a 'set' of registers.
Rashmica Gupta (3):
hw/gpio: Add basic Aspeed GPIO model for AST2400 and AST2500
aspeed: add a GPIO controller to the SoC
hw/gpio: Add in AST2600 specific implementation
in
On Fri, 2019-08-16 at 18:21 +0200, Cédric Le Goater wrote:
> On 16/08/2019 09:32, Rashmica Gupta wrote:
> > v5:
> > - integrated AspeedGPIOController fields into AspeedGPIOClass
> > - separated ast2600_3_6v and ast2600_1_8v into two classes
>
> Rashmica,
>
> This
Cédric, this is how I thought changes to the SOC for your aspeed-4.1
branch would look
>From 13a07834476fa266c352d9a075b341c483b2edf9 Mon Sep 17 00:00:00 2001
From: Rashmica Gupta
Date: Fri, 16 Aug 2019 15:18:22 +1000
Subject: [PATCH] Aspeed SOC changes
---
include/hw/arm/aspeed_soc.h |
The AST2600 has the same sets of 3.6v gpios as the AST2400 plus an
addtional two sets of 1.8V gpios.
Signed-off-by: Rashmica Gupta
---
hw/gpio/aspeed_gpio.c | 142 --
1 file changed, 137 insertions(+), 5 deletions(-)
diff --git a/hw/gpio/aspeed_gpio.c b
source driving the GPIO pins in the model is the ARM
model (as there currently aren't models for the LPC or Coprocessor).
(2) None of the registers in the model are reset tolerant (needs
integration with the watchdog).
Signed-off-by: Rashmica Gupta
Tested-by: Andrew Jeffery
---
incl
with a 'set' of registers.
Rashmica Gupta (3):
hw/gpio: Add basic Aspeed GPIO model for AST2400 and AST2500
aspeed: add a GPIO controller to the SoC
hw/gpio: Add in AST2600 specific implementation
include/hw/arm/aspeed_soc.h |3 +
include/hw/gpio/aspeed_gpio.h | 100
Signed-off-by: Rashmica Gupta
---
include/hw/arm/aspeed_soc.h | 3 +++
hw/arm/aspeed_soc.c | 17 +
2 files changed, 20 insertions(+)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index cef605ad6b..fa04abddd8 100644
--- a/include/hw/arm
On Wed, 2019-08-14 at 14:37 +0200, Cédric Le Goater wrote:
> On 14/08/2019 09:14, Rashmica Gupta wrote:
...
> > +static void aspeed_2600_gpio_realize(DeviceState *dev, Error
> > **errp)
> > +{
> > +AspeedGPIOState *s = ASPEED_GPIO(dev);
> > +
Thanks for the feedback! I fixed up all the things you mentioned in v4.
On Tue, 2019-08-13 at 17:31 +1000, Alexey Kardashevskiy wrote:
>
> On 30/07/2019 15:45, Rashmica Gupta wrote:
> > The AST2600 has the same sets of 3.6v gpios as the AST2400 plus an
> > addtional two
On Tue, 2019-08-06 at 14:57 +0100, Peter Maydell wrote:
> On Tue, 30 Jul 2019 at 06:45, Rashmica Gupta
> wrote:
> > GPIO pins are arranged in groups of 8 pins labeled
> > A,B,..,Y,Z,AA,AB,AC.
> > (Note that the ast2400 controller only goes up to group AB).
> > A set
Signed-off-by: Rashmica Gupta
---
hw/arm/aspeed_soc.c | 17 +
include/hw/arm/aspeed_soc.h | 3 +++
2 files changed, 20 insertions(+)
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index c6fb3700f2..ff422c8ad1 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm
source driving the GPIO pins in the model is the ARM
model (as there currently aren't models for the LPC or Coprocessor).
(2) None of the registers in the model are reset tolerant (needs
integration with the watchdog).
Signed-off-by: Rashmica Gupta
Tested-by: Andrew Jeffery
---
hw/gpio/Ma
ementation (patch 3)
- renamed a couple of variables for clarity
v2: Addressed Andrew's feedback, added debounce regs, renamed get/set to
read/write to minimise confusion with a 'set' of registers.
Rashmica Gupta (3):
hw/gpio: Add basic Aspeed GPIO model for AST2400 and AST2500
aspe
The AST2600 has the same sets of 3.6v gpios as the AST2400 plus an
addtional two sets of 1.8V gpios.
Signed-off-by: Rashmica Gupta
---
hw/gpio/aspeed_gpio.c | 188 --
slirp | 2 +-
2 files changed, 184 insertions(+), 6 deletions(-)
diff
source driving the GPIO pins in the model is the ARM
model (as there currently aren't models for the LPC or Coprocessor).
(2) None of the registers in the model are reset tolerant (needs
integration with the watchdog).
Signed-off-by: Rashmica Gupta
---
hw/gpio/Makefile.objs | 1
The AST2600 has the same sets of 3.6v gpios as the AST2400 plus an
addtional two sets of 1.8V gpios.
Signed-off-by: Rashmica Gupta
---
hw/gpio/aspeed_gpio.c | 186 +-
include/hw/gpio/aspeed_gpio.h | 2 +-
2 files changed, 184 insertions(+), 4 deletions
(only exists on ast2500)
- added ast2600 implementation (patch 3)
- renamed a couple of variables for clarity
v2: Addressed Andrew's feedback, added debounce regs, renamed get/set to
read/write to minimise confusion with a 'set' of registers.
Rashmica Gupta (3):
hw/gpio: Add basic
Signed-off-by: Rashmica Gupta
---
hw/arm/aspeed_soc.c | 17 +
include/hw/arm/aspeed_soc.h | 3 +++
2 files changed, 20 insertions(+)
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index c6fb3700f2..ff422c8ad1 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm
Doh! Forgot the v2 tag!
On Mon, 2019-07-15 at 16:19 +1000, Rashmica Gupta wrote:
> Rebased on Peter's target-arm.next branch.
>
> v2: Addressed Andrew's feedback, added debounce regs, renamed get/set
> to
> read/write to minimise confusion with a 'set' o
source driving the GPIO pins in the model is the ARM
model (as there currently aren't models for the LPC or Coprocessor).
(2) None of the registers in the model are reset tolerant (needs
integration with the watchdog).
Signed-off-by: Rashmica Gupta
---
hw/gpio/Makefile.objs | 1
Rebased on Peter's target-arm.next branch.
v2: Addressed Andrew's feedback, added debounce regs, renamed get/set to
read/write to minimise confusion with a 'set' of registers.
Rashmica Gupta (2):
hw/gpio: Add basic Aspeed GPIO model for AST2400 and AST2500
aspeed: add
Signed-off-by: Rashmica Gupta
---
hw/arm/aspeed_soc.c | 17 +
include/hw/arm/aspeed_soc.h | 3 +++
2 files changed, 20 insertions(+)
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index c6fb3700f2..ff422c8ad1 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm
Sorry for the late reply! I agree with most of your feedback and will
send out
a v2 shortly with those changes. I have a few replies below
[snip]
> > +static const struct AspeedGPIO gpios[0x1f0] = {
> > +/* Set ABCD */
> > +[GPIO_ABCD_DATA_VALUE] = {0, read_data_value,
> > _write_data_val
On Tue, 2019-06-18 at 11:21 +0200, Cédric Le Goater wrote:
> On 18/06/2019 10:51, Rashmica Gupta wrote:
> > Signed-off-by: Rashmica Gupta
> > ---
> > hw/arm/aspeed_soc.c | 17 +
> > include/hw/arm/aspeed_soc.h | 3 +++
> > 2 files change
Add in details for GPIO controller for AST 2400 and 2500
Signed-off-by: Rashmica Gupta
---
hw/gpio/Makefile.objs | 1 +
hw/gpio/aspeed_gpio.c | 869 ++
include/hw/gpio/aspeed_gpio.h | 76 +++
3 files changed, 946 insertions(+)
create mode
would be great!
Rashmica Gupta (2):
hw/gpio: Add basic Aspeed GPIO model
aspeed: add a GPIO controller to the SoC
hw/arm/aspeed_soc.c | 17 +
hw/gpio/Makefile.objs | 1 +
hw/gpio/aspeed_gpio.c | 869 ++
include/hw/arm/aspeed_soc.h
Signed-off-by: Rashmica Gupta
---
hw/arm/aspeed_soc.c | 17 +
include/hw/arm/aspeed_soc.h | 3 +++
2 files changed, 20 insertions(+)
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index 1cc98b9f40..8583869acf 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm
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