I/O currently being synchronous, there is no reason to ever clear the
SR_TXE bit. However the SR_TC bit may be cleared by software writing
to the SR register, so set it on each write.
In addition, fix the reset value of the USART status register.
Signed-off-by: Richard Braun <rbr...@sceen.
On Fri, Feb 09, 2018 at 10:23:13AM +0100, Richard Braun wrote:
> On Thu, Feb 08, 2018 at 02:58:29PM +, Peter Maydell wrote:
> > The guest can clear the TC and TXE bits by writing to the USART_SR
> > directly, so this code should set both of them, I think ?
>
> Right,
device here, we only want to
emulate visible states. As mentioned above, software should always see
the TXE bit set, since writes are synchronous. TC should be set though,
because it may be cleared by an explicit write to SR setting it to 0.
I'll post a new version of the patch soon.
--
Richard Braun
On Thu, Feb 08, 2018 at 02:58:29PM +, Peter Maydell wrote:
> On 4 February 2018 at 20:41, Richard Braun <rbr...@sceen.net> wrote:
> > Consider that data is always immediately sent. As a result, keep
> > the SR_TXE and SR_TC bits always set. In addition, fix the reset v
Consider that data is always immediately sent. As a result, keep
the SR_TXE and SR_TC bits always set. In addition, fix the reset value
of the USART status register.
Signed-off-by: Richard Braun <rbr...@sceen.net>
---
hw/char/stm32f2xx_usart.c | 4
include/hw/char/stm32f2xx_u
