Since QEMU maintains TLB entries keyed by the device ID, there is no separate
device entry cache. This means we need to invalidate all translations keyed by
the device ID.
Signed-off-by: Roman Kapl
---
hw/i386/amd_iommu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/i386
Address was swapped with value when writing MMIO registers, so the user
saw garbage in lot of cases. The interrupt status was not correctly set.
Signed-off-by: Roman Kapl
---
hw/i386/amd_iommu.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
v1 -> v2: Change the amdvi_writeq_
On 4/27/21 1:24 AM, Michael S. Tsirkin wrote:
> On Mon, Apr 26, 2021 at 10:21:54AM +0200, Roman Kapl wrote:
>> Address was swapped with value when writing MMIO registers, so the user
>> saw garbage in lot of cases. The interrupt status was not correctly set.
>>
>>
Address was swapped with value when writing MMIO registers, so the user
saw garbage in lot of cases. The interrupt status was not correctly set.
Signed-off-by: Roman Kapl
---
hw/i386/amd_iommu.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/i386/amd_iommu.c b/hw
On 3/9/20 12:43 PM, Roman Kapl wrote:
On 3/5/20 11:37 PM, Alex Williamson wrote:
On Fri, 28 Feb 2020 13:08:00 +0100
Roman Kapl wrote:
For MSI-X interrupts, remember what the last used eventfd was (KVM
bypass vs QEMU) and only call vfio_set_irq_signaling if it has changed.
This not only
On 3/5/20 11:37 PM, Alex Williamson wrote:
On Fri, 28 Feb 2020 13:08:00 +0100
Roman Kapl wrote:
For MSI-X interrupts, remember what the last used eventfd was (KVM
bypass vs QEMU) and only call vfio_set_irq_signaling if it has changed.
This not only helps with performance, but it seems
and this patch, SET_ACTION_TRIGGER is not called during
mask/unmask. This really only affects guests that actively use MSI-X masking.
Signed-off-by: Roman Kapl
---
This patch scratches my particular itch. I am able to get our guest (which masks
MSI on each interrupt) running, without getting randomly stuck
On 2/11/20 6:57 PM, Peter Maydell wrote:
On Fri, 7 Feb 2020 at 09:55, Roman Kapl wrote:
Documentation says for WDA '0: Assert WDOG output.' and for SRS
'0: Assert system reset signal.'.
Signed-off-by: Roman Kapl
---
hw/misc/imx2_wdt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion
Documentation says for WDA '0: Assert WDOG output.' and for SRS
'0: Assert system reset signal.'.
Signed-off-by: Roman Kapl
---
hw/misc/imx2_wdt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/misc/imx2_wdt.c b/hw/misc/imx2_wdt.c
index e47e442592..c8944729c4 100644
Uses the i.MX2 rudimentary watchdog driver.
Signed-off-by: Roman Kapl
---
hw/arm/fsl-imx6.c | 21 +
include/hw/arm/fsl-imx6.h | 4
2 files changed, 25 insertions(+)
diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c
index 7b7b97f74c..f2adaca1c5 100644
--- a/hw
. The excp, argument is now removed,
since the type of exception can be inferred from the singlestep_enabled flags.
removed the guards around gen_exception, since they are unnecessary.
Fixes: 0e3bf48909 ("ppc: add DBCR based debugging").
Signed-off-by: Roman Kapl
---
target/ppc/transl
SPR_NOACCESS, SPR_NOACCESS,
--
2.20.1.3.gf17a2b179
Reviewed-by: Laurent Vivier
Tested-by: Laurent Vivier
Thanks Jon, I did not test with e6500. The patch fixes the issue &
debugging still works on e5500.
Roman Kapl
From: Rudolf Marek
Fix the SYSCALL instruction in 64-bit (long mode). The RF flag
should be cleared in R11 as well as in the RFLAGS. Intel
and AMD CPUs behave same. AMD has this documented in the
APM vol 3.
Signed-off-by: Roman Kapl
Signed-off-by: Rudolf Marek
---
target/i386/seg_helper.c
.
Following instructions are implemented: dcbfep dcbstep dcbtep dcbtstep dcbzep
dcbzlep icbiep lbepx ldepx lfdepx lhepx lwepx stbepx stdepx stfdepx sthepx
stwepx.
Following vector instructions are not: evlddepx evstddepx lvepx lvepxl stvepx
stvepxl.
Signed-off-by: Roman Kapl
---
Contains squashed changes
Hi,
On 09/20/2018 02:19 PM, Philippe Mathieu-Daudé wrote:
On 8/24/18 3:17 PM, Roman Kapl wrote:
The TCG backend uses LOWREGMASK to get the low 7 bits of register numbers. This
7 = 0b111: the low 3 bits?
Yes, low 3 bits, 8 registers, the commit message is wrong.
Thanks, Roman Kapl
ht -- I've referenced the wrong tree. At least this needs to
be fixed if it won't be squashed.
Thanks, Roman Kapl
are.
Thanks, Roman Kapl
ping http://patchwork.ozlabs.org/patch/961849/
On 08/24/2018 03:17 PM, Roman Kapl wrote:
The TCG backend uses LOWREGMASK to get the low 7 bits of register numbers. This
was defined as no-op for 32-bit x86, with the assumption that we have eight
registers anyway. This assumption is not true once
. The PPC_CACHE/PPC_INTEGER type mask was
changed to PPC_NONE.
Fixes: ea8073c10d ("target/ppc: add external PID support")
Signed-off-by: Roman Kapl
---
This fixes the sandalfoot image boot. And thanks to PMM for spotting the GETPC
issue.
target/ppc/mem_helper.c | 15 ++-
ted
to the problem with your image.
Thanks, Roman Kapl
I've just realised that because this bug is still dependent upon queued
patches, it
would make sense for me to push a slightly modified version of David's
ppc-for-3.1
branch to github to help reproduce the issue. Below are the instructi
Hi,
On 09/19/2018 08:57 AM, Mark Cave-Ayland wrote:
On 18/09/2018 22:12, Mark Cave-Ayland wrote:
Roman, can you reproduce this locally at all? My setup is nothing
special, just Debian Stretch on amd64.
I've just realised that because this bug is still dependent upon queued
patches, it
.
Following instructions are implemented: dcbfep dcbstep dcbtep dcbtstep dcbzep
dcbzlep icbiep lbepx ldepx lfdepx lhepx lwepx stbepx stdepx stfdepx sthepx
stwepx.
Following vector instructions are not: evlddepx evstddepx lvepx lvepxl stvepx
stvepxl.
Signed-off-by: Roman Kapl
---
v1 -> v2:
cha
.
Following instructions are implemented: dcbfep dcbstep dcbtep dcbtstep dcbzep
dcbzlep icbiep lbepx ldepx lfdepx lhepx lwepx stbepx stdepx stfdepx sthepx
stwepx.
Following vector instructions are not: evlddepx evstddepx lvepx lvepxl stvepx
stvepxl.
Signed-off-by: Roman Kapl
---
v1 -> v2:
cha
On 08/31/2018 05:35 AM, David Gibson wrote:
On Tue, Aug 14, 2018 at 06:59:54PM +0200, Roman Kapl wrote:
External PID is a mechanism present on BookE 2.06 that enables application to
store/load data from different address spaces. There are special version of some
instructions, which operate
message.
This could help debug or detect earlier errors like
c2d9644e6d ("target/arm: Fix crash on conditional instruction in an IT block")
Signed-off-by: Roman Kapl
---
tcg/tcg.c | 29 +
tcg/tcg.h | 3 ++-
2 files changed, 31 insertions(+), 1 deletion(-)
uot;.
Fixes: 770c2fc7bb ("Add vector operations")
Signed-off-by: Roman Kapl
---
Note: It could also be possible to add a dedicated VEC_LOWREGMASK, but I don't
think it is better or signigicantly faster.
tcg/i386/tcg-target.inc.c | 4
1 file changed, 4 deletions(-)
diff --git a/
, section
K1.1.7).
Fix the 'skip on condtion' code to create a new label only if it does not
already exist. Previously multiple labels were created, but only the last one of
them was set.
Signed-off-by: Roman Kapl
---
v1 -> v2
Split arm_conditional_skip into arm_gen_condlabel and arm_skip_unl
Hi and thanks for review,
On 08/14/2018 08:12 PM, Peter Maydell wrote:
On 14 August 2018 at 17:54, Roman Kapl wrote:
If an instruction is conditional (like CBZ) and it is executed conditionally
(using the ITx instruction), a jump to undefined label is generated.
Fix the 'skip on condtion
of
them was set.
Signed-off-by: Roman Kapl
---
target/arm/translate.c | 32 ++--
1 file changed, 18 insertions(+), 14 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index f845da7c63..f7c03a36e6 100644
--- a/target/arm/translate.c
+++ b
Add support for DBCR (debug control register) based debugging as used on
BookE ppc. So far supports only branch and single-step events, but these are
the important ones. GDB in Linux guest can now do single-stepping.
Signed-off-by: Roman Kapl
---
v1 -> v2
Only handle the xcept
of
them was set.
Signed-off-by: Roman Kapl
---
target/arm/translate.c | 32 ++--
1 file changed, 18 insertions(+), 14 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index f845da7c63..f7c03a36e6 100644
--- a/target/arm/translate.c
+++ b
.
Following instructions are implemented: dcbfep dcbstep dcbtep dcbtstep dcbzep
dcbzlep icbiep lbepx ldepx lfdepx lhepx lwepx stbepx stdepx stfdepx sthepx
stwepx.
Following vector instructions are not: evlddepx evstddepx lvepx lvepxl stvepx
stvepxl.
Signed-off-by: Roman Kapl
---
target/ppc/cpu.h
Add support for DBCR (debug control register) based debugging as used on
BookE ppc. So far supports only branch and single-step events, but these are
the important ones. GDB in Linux guest can now do single-stepping.
Signed-off-by: Roman Kapl
---
target/ppc/cpu.h| 5 ++
target
nux, but it is valid to set DECAR to zero
(and may make sense as part of decrementer initialization when interrupts are
disabled).
Signed-off-by: Roman Kapl <r...@sysgo.com>
---
hw/ppc/ppc_booke.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/ppc_booke.c b/hw/ppc/pp
nux, but it is valid to set DECAR to zero
(and may make sense as part of decrementer initialization when interrupts are
disabled).
Signed-off-by: Roman Kapl <r...@sysgo.com>
---
hw/ppc/ppc_booke.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/ppc_booke.c b/hw/ppc/pp
rcu_read_unlock was not called if the address_space_access_valid result is
negative.
This caused (at least) a problem when qemu on PPC/E500+TAP failed to terminate
properly and instead got stuck in a deadlock.
Signed-off-by: Roman Kapl <r...@sysgo.com>
---
exec.c | 1 +
1 file chan
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