not provide a definition of that struct.
>
> Signed-off-by: Peter Maydell
LGTM.
Reviewed-by: Sandipan Das
> ---
> I need this to be able to do the ppc64le cross-build on my
> Ubuntu Bionic x86-64 system.
>
> risu_ppc64.c | 2 ++
> risu_reginfo_ppc64.c | 1 +
> 2 f
This fixes the pattern for the Deliver A Random Number (darn)
instruction to ensure that the value of the L field, which is
used to determine the type and length of the generated random
number, is never 3 which is currently reserved for future use.
Signed-off-by: Sandipan Das
---
ppc64.risu | 2
$ qemu-ppc64le -cpu power9 test
0x8c00
After:
$ qemu-ppc64le -cpu power8 test
0x8c00
$ qemu-ppc64le -cpu power9 test
0x8c80
Signed-off-by: Sandipan Das
---
linux-user/elfload.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
Use 'f' instead of 'r' as the prefix when dumping the values
of floating-point registers.
Signed-off-by: Sandipan Das <sandi...@linux.vnet.ibm.com>
---
risu_reginfo_ppc64.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/risu_reginfo_ppc64.c b/risu_reginfo_ppc64.c
of the registers. This can cause
a mismatch as the addresses may vary across the master and
the apprentice instances. This is avoided by always adding
8 to the offset used for calculating the ea.
Signed-off-by: Sandipan Das <sandi...@linux.vnet.ibm.com>
---
ppc64.risu | 4 ++--
1 file chan
The patterns for the following instructions are added:
* Load Byte and Zero (lbz)
* Load Byte and Zero with Update (lbzu)
* Load Byte and Zero Indexed (lbzx)
* Load Byte and Zero with Update Indexed (lbzux)
* Load Doubleword (ld)
Signed-off-by: Sandipan Das <sandi...@linux.vnet.ibm.
.
Changelog:
v2 -> Added a cover letter as requested by Peter.
Sandipan Das (3):
ppc64.risu: Add missing byte and dword loads
ppc64.risu: Fix pattern for load qword
risu_reginfo_ppc64.c: Fix register name prefix
ppc64.risu | 29 +++--
risu_reginfo_ppc64.c |
On 03/06/2018 05:09 PM, Peter Maydell wrote:
> On 6 March 2018 at 06:42, Sandipan Das <sandi...@linux.vnet.ibm.com> wrote:
>> The patterns for the following instructions are added:
>> * Load Byte and Zero (lbz)
>> * Load Byte and Zero with Update (lbzu)
>> *
Use 'f' instead of 'r' as the prefix when dumping the values
of floating-point registers.
Signed-off-by: Sandipan Das <sandi...@linux.vnet.ibm.com>
---
risu_reginfo_ppc64.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/risu_reginfo_ppc64.c b/risu_reginfo_ppc64.c
of the registers. This can cause
a mismatch as the addresses may vary across the master and
the apprentice instances. This is avoided by always adding
8 to the offset used for calculating the ea.
Signed-off-by: Sandipan Das <sandi...@linux.vnet.ibm.com>
---
ppc64.risu | 4 ++--
1 file chan
The patterns for the following instructions are added:
* Load Byte and Zero (lbz)
* Load Byte and Zero with Update (lbzu)
* Load Byte and Zero Indexed (lbzx)
* Load Byte and Zero with Update Indexed (lbzux)
* Load Doubleword (ld)
Signed-off-by: Sandipan Das <sandi...@linux.vnet.ibm.
Doubleword (srad[.])
* Shift Right Algebraic Doubleword Immediate (sradi[.])
Signed-off-by: Sandipan Das <sandi...@linux.vnet.ibm.com>
---
v2: Add tcg_temp_free() required in gen_sraw() and gen_srad()
v3: Remove explicit checking for ISA v3.0 when setting CA32
v4: Set CA32 only when CA is
Doubleword (srad[.])
* Shift Right Algebraic Doubleword Immediate (sradi[.])
Signed-off-by: Sandipan Das <sandi...@linux.vnet.ibm.com>
---
v2: Add tcg_temp_free() required in gen_sraw() and gen_srad()
v3: Remove explicit checking for ISA v3.0 when setting CA32
---
target/ppc/int_helper
On Monday 22 May 2017 12:33 PM, Nikunj A Dadhania wrote:
> Sandipan Das <sandipandas1...@gmail.com> writes:
>
>> The patterns for the following instructions are fixed:
>> * Rotate Left Doubleword then Clear Right (rldcr[.])
>> * Rotate Left Doubleword Imme
The patterns for the following instructions are fixed:
* Rotate Left Doubleword then Clear Right (rldcr[.])
* Rotate Left Doubleword Immediate then Clear Right (rldicr[.])
* Rotate Left Doubleword Immediate then Mask Insert (rldimi[.])
Signed-off-by: Sandipan Das <sandipandas1...@gmail.
instructions,
the extended opcodes are incorrect and the shift field 'sha' is
absent. Also, the shift field 'sh' should be used in place of the
register field 'rb'.
Signed-off-by: Sandipan Das <sandipandas1...@gmail.com>
---
ppc64.risu | 10 +-
1 file changed, 5 insertions(+), 5 del
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