Hello Luc,
thanks for having a look at the patch.
On 25/07/2021 10:08, Luc Michel wrote:
Hi Sebastian,
On 11:49 Fri 09 Jul , Sebastian Huber wrote:
According to the GICv3 specification register GICD_ISPENDR0 is Banked for each
You're referring to GICv3 but actually modifying GICv2 model
On 09/07/2021 11:49, Sebastian Huber wrote:
According to the GICv3 specification register GICD_ISPENDR0 is Banked for each
connected PE with GICR_TYPER.Processor_Number < 8. For Qemu this is the case
since GIC_NCPU == 8.
For SPI, make the interrupt pending on all CPUs and not j
our is at least present on the i.MX7D which uses an Cortex-A7MPCore.
Signed-off-by: Sebastian Huber
---
hw/intc/arm_gic.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index a994b1f024..8e377bac59 100644
--- a/hw/intc/arm_gi
With this Qemu:
qemu-system-arm --version
QEMU emulator version 4.2.50 (v4.2.0-1276-g863d2ed582)
Copyright (c) 2003-2019 Fabrice Bellard and the QEMU Project developers
I still have the same issue:
(gdb) info registers
r0 0x0 0
r1 0x9010001
I can also build the latest Git master of Qemu if this helps.
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https://bugs.launchpad.net/bugs/1277433
Title:
GDB context is inconsistent after "monitor system_reset"
Status in QEMU:
Set initial MAC address to the one specified by the command line.
Signed-off-by: Sebastian Huber <sebastian.hu...@embedded-brains.de>
Reviewed-by: Jason Wang <jasow...@redhat.com>
Reviewed-by: Peter Crosthwaite <peter.crosthwa...@xilinx.com>
---
hw/net/cadence_gem.c | 6 ++
Ping.
Attached is a rebased version.
On 30/01/15 18:56, Peter Crosthwaite wrote:
On Thu, Jan 29, 2015 at 9:48 PM, Sebastian Huber
sebastian.hu...@embedded-brains.de wrote:
Set initial MAC address to the one specified by the command line.
Signed-off-by: Sebastian Huber sebastian.hu
Set initial MAC address to the one specified by the command line.
Signed-off-by: Sebastian Huber sebastian.hu...@embedded-brains.de
---
hw/net/cadence_gem.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index de26609
Set initial MAC address to the one specified by the command line.
Signed-off-by: Sebastian Huber sebastian.hu...@embedded-brains.de
Reviewed-by: Jason Wang jasow...@redhat.com
v2: Remove superfluous whitespace change.
---
hw/net/cadence_gem.c | 6 ++
1 file changed, 6 insertions(+)
diff
Hello,
On 2014-03-02 16:56, Sebastian Huber wrote:
On 03/02/2014 02:17 PM, Michael Tokarev wrote:
26.02.2014 11:53, Sebastian Huber wrote:
Ping.
There was another comment on this, about the first hunk,
see https://lists.gnu.org/archive/html/qemu-trivial/2014-02/msg00067.html
Note
Hello Fabien,
On 2014-03-12 11:17, Fabien Chouteau wrote:
Thanks Sebastian, I will try my first pull request :)
I think Mark already did this
http://lists.gnu.org/archive/html/qemu-devel/2014-03/msg02325.html
?
--
Sebastian Huber, embedded brains GmbH
Address : Dornierstr. 4, D-82178
Färber afaer...@suse.de
Tested-by: Mark Cave-Ayland mark.cave-ayl...@ilande.co.uk
Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Sebastian Huber sebastian.hu...@embedded-brains.de
---
target-sparc/cpu.c |3 +-
target-sparc/cpu.h |4 ++-
target-sparc/helper.h
v5: Fix two typos. Generate an IU instead of FPU exception in case CASA is not
supported by the CPU. Define CASA feature for all SPARC64 CPUs (due to the
#ifndef TARGET_SPARC64 it must go into the #else branch).
v6: Move CHECK_IU_FEATURE(dc, CASA); in #ifndef TARGET_SPARC64 block since
SPARC64
on qemu-system-sparc64 (see below for the output from current
git master with the v4 patch applied):
thanks for testing my patch. Can I download these ISO images somewhere
so that I can try to fix my patch?
--
Sebastian Huber, embedded brains GmbH
Address : Dornierstr. 4, D-82178 Puchheim
);
atomic_store(a, 3);
e = 4;
b = atomic_compare_exchange_strong(a, e, 5);
assert(!b);
assert(atomic_load(a) == 3);
}
Tested also on a NGMP board with a LEON4 processor.
Reviewed-by: Fabien Chouteau chout...@adacore.com
Reviewed-by: Andreas Färber afaer...@suse.de
Signed-off-by: Sebastian Huber
On 03/02/2014 02:17 PM, Michael Tokarev wrote:
26.02.2014 11:53, Sebastian Huber wrote:
Ping.
There was another comment on this, about the first hunk,
see https://lists.gnu.org/archive/html/qemu-trivial/2014-02/msg00067.html
Note that the comment below this line mentions the +1 which is
being
Ping.
--
Sebastian Huber, embedded brains GmbH
Address : Dornierstr. 4, D-82178 Puchheim, Germany
Phone : +49 89 189 47 41-16
Fax : +49 89 189 47 41-09
E-Mail : sebastian.hu...@embedded-brains.de
PGP : Public key available on request.
Diese Nachricht ist keine geschäftliche
Hello,
exists there someone who is able to commit this?
On 2014-02-14 17:22, Andreas Färber wrote:
Am 14.02.2014 17:06, schrieb Sebastian Huber:
The LEON3 processor has support for the CASA instruction which is
normally only available for SPARC V9 processors. Binutils 2.24
and GCC 4.9
-by: Fabien Chouteau chout...@adacore.com
Signed-off-by: Sebastian Huber sebastian.hu...@embedded-brains.de
---
hw/timer/grlib_gptimer.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/timer/grlib_gptimer.c b/hw/timer/grlib_gptimer.c
index 74c16d6..7672d3a 100644
--- a/hw
On 2014-02-13 16:50, Fabien Chouteau wrote:
On 02/13/2014 03:55 PM, Fabien Chouteau wrote:
On 02/13/2014 02:00 PM, Sebastian Huber wrote:
On 2014-02-13 13:01, Fabien Chouteau wrote:
On 02/13/2014 10:52 AM, Sebastian Huber wrote:
The LEON3 processor has support for the CASA instruction which
(b);
assert(atomic_load(a) == 2);
atomic_store(a, 3);
e = 4;
b = atomic_compare_exchange_strong(a, e, 5);
assert(!b);
assert(atomic_load(a) == 3);
}
Tested also on a NGMP board with a LEON4 processor.
Signed-off-by: Sebastian Huber sebastian.hu...@embedded-brains.de
, you may want to consider setting up tests/tcg/sparc/ for test
cases and/or use qtest with accel=tcg similar to what mst did for ACPI
regression testing.
Ok, I will have a look at this. Is this a required step to get the patch
committed?
--
Sebastian Huber, embedded brains GmbH
Address
(b);
assert(atomic_load(a) == 2);
atomic_store(a, 3);
e = 4;
b = atomic_compare_exchange_strong(a, e, 5);
assert(!b);
assert(atomic_load(a) == 3);
}
Tested also on a NGMP board with a LEON4 processor.
v4: Fix coding style.
Signed-off-by: Sebastian Huber sebastian.hu
The GPTIMER uses 32-bit registers. Use a 64-bit operation to get the
ptimer count, otherwise we end up with a count of 0 for GPTIMER counter
values of 0x.
---
hw/timer/grlib_gptimer.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/timer/grlib_gptimer.c
= atomic_compare_exchange_strong(a, e, 2);
assert(b);
assert(atomic_load(a) == 2);
atomic_store(a, 3);
e = 4;
b = atomic_compare_exchange_strong(a, e, 5);
assert(!b);
assert(atomic_load(a) == 3);
}
Signed-off-by: Sebastian Huber sebastian.hu...@embedded-brains.de
Reviewed
On 2014-02-13 13:01, Fabien Chouteau wrote:
On 02/13/2014 10:52 AM, Sebastian Huber wrote:
The LEON3 processor has support for the CASA instruction which is
normally only available for SPARC V9 processors. Binutils 2.24
and GCC 4.9 will support this instruction for LEON3. GCC uses
On 2014-02-06 09:57, Peter Maydell wrote:
On 6 February 2014 08:40, Michael Tokarevm...@tls.msk.ru wrote:
03.02.2014 13:18, Sebastian Huber wrote:
A lot of real world LEON3 systems are shipped with the GRMON boot
loader. This boot loader initializes the stack pointer with the end of
RAM
Public bug reported:
After a monitor system_reset the GDB view to the system state differs
from QEMUs processor state.
Breakpoint 8, _ARMV4_Exception_interrupt () at
/home/sh/rtems-4.11/c/src/../../cpukit/score/cpu/arm/arm_exc_interrupt.S:74
74 mov EXCHANGE_LR, lr
(gdb) info
On 2014-02-06 09:40, Michael Tokarev wrote:
03.02.2014 13:18, Sebastian Huber wrote:
A lot of real world LEON3 systems are shipped with the GRMON boot
loader. This boot loader initializes the stack pointer with the end of
RAM address. The application can use this to detect the RAM size
Signed-off-by: Sebastian Huber sebastian.hu...@embedded-brains.de
Reviewed-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
hw/misc/zynq_slcr.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c
index e42a5b0..d1cc233
?
--
Sebastian Huber, embedded brains GmbH
Address : Dornierstr. 4, D-82178 Puchheim, Germany
Phone : +49 89 189 47 41-16
Fax : +49 89 189 47 41-09
E-Mail : sebastian.hu...@embedded-brains.de
PGP : Public key available on request.
Diese Nachricht ist keine geschäftliche Mitteilung im
A lot of real world LEON3 systems are shipped with the GRMON boot
loader. This boot loader initializes the stack pointer with the end of
RAM address. The application can use this to detect the RAM size of a
particular board variant.
Signed-off-by: Sebastian Huber sebastian.hu...@embedded
Signed-off-by: Sebastian Huber sebastian.hu...@embedded-brains.de
---
hw/misc/zynq_slcr.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c
index e42a5b0..433d439 100644
--- a/hw/misc/zynq_slcr.c
+++ b/hw/misc/zynq_slcr.c
Hello,
maybe this patch can be qualified as trivial?
http://lists.nongnu.org/archive/html/qemu-devel/2013-11/msg03488.html
On 2014-01-07 19:07, Sebastian Huber wrote:
Hello,
would somebody mind committing this.
On 12/06/2013 06:48 PM, Richard Henderson wrote:
On 11/27/2013 08:50 PM
Hello,
would somebody mind committing this.
On 12/06/2013 06:48 PM, Richard Henderson wrote:
On 11/27/2013 08:50 PM, Sebastian Huber wrote:
Synchronize the program counter before the power down helper call
otherwise interrupts will return to the wrong context.
Signed-off-by: Sebastian Huber
Hello,
would someone please have a look at this.
On 2013-11-28 11:27, Sebastian Huber wrote:
The LEON3 processor has support for the CASA instruction which is
normally only available for SPARC V9 processors. Binutils 2.24
and GCC 4.9 will support this instruction for LEON3. GCC uses
Hello,
On 2013-11-26 15:04, Sebastian Huber wrote:
The LEON3 processor has support for the CASA instruction which is
normally only available for SPARC V9 processors. Binutils 2.24
and GCC 4.9 will support this instruction for LEON3. GCC uses it to
generate C11 atomic operations.
---
target
The LEON3 processor has support for the CASA instruction which is
normally only available for SPARC V9 processors. Binutils 2.24
and GCC 4.9 will support this instruction for LEON3. GCC uses it to
generate C11 atomic operations.
The CAS synthetic instruction uses an ASI of 0x80. If
The LEON3 processor has support for the CASA instruction which is
normally only available for SPARC V9 processors. Binutils 2.24
and GCC 4.9 will support this instruction for LEON3. GCC uses it to
generate C11 atomic operations.
---
target-sparc/cpu.c |3 +-
target-sparc/cpu.h
Synchronize the program counter before the power down helper call
otherwise interrupts will return to the wrong context.
Signed-off-by: Sebastian Huber sebastian.hu...@embedded-brains.de
---
target-sparc/translate.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/target
The env-pc is not necessarily up-to-date in the helper function. Use
the program counter of the disassembly context instead.
Signed-off-by: Sebastian Huber sebastian.hu...@embedded-brains.de
---
target-sparc/helper.c|6 +++---
target-sparc/helper.h|2 +-
target-sparc/translate.c
In case the smc91c111 interface signals that it cannot receive more
packets the packets are queued and further reception will be disabled.
In case the interface is again ready to receive packets notify the upper
layer.
Signed-off-by: Sebastian Huber sebastian.hu...@embedded-brains.de
---
hw/net
this be
{
env-cp15.c12_vbar = (uint32_t) (value ~0x1FUL);
return 0;
}
?
--
Sebastian Huber, embedded brains GmbH
Address : Dornierstr. 4, D-82178 Puchheim, Germany
Phone : +49 89 189 47 41-16
Fax : +49 89 189 47 41-09
E-Mail : sebastian.hu...@embedded-brains.de
PGP : Public key available
this Security Extensions is the VBAR. So
for me the only missing Qemu feature is the VBAR if I want to use nearly the
same binary on Qemu and the real hardware.
--
Sebastian Huber, embedded brains GmbH
Address : Dornierstr. 4, D-82178 Puchheim, Germany
Phone : +49 89 189 47 41-16
Fax : +49 89 189
? This may avoid adding
a new enum arm_features.
--
Sebastian Huber, embedded brains GmbH
Address : Dornierstr. 4, D-82178 Puchheim, Germany
Phone : +49 89 189 47 41-16
Fax : +49 89 189 47 41-09
E-Mail : sebastian.hu...@embedded-brains.de
PGP : Public key available on request.
Diese
On 06/07/2013 06:19 AM, Peter Crosthwaite wrote:
Hi Sebastian,
I'd like to get this merged with the fix I suggested. Are you able to
remake or ok if I ammend and resend your patch?
I am fine with your change. My version is to restrictive.
--
Sebastian Huber, embedded brains GmbH
Address
Hello Peter,
thanks for your suggestions. I will look at the WFI support and may send a
patch for the SEV/WFE, but this will take some weeks.
--
Sebastian Huber, embedded brains GmbH
Address : Dornierstr. 4, D-82178 Puchheim, Germany
Phone : +49 89 189 47 41-16
Fax : +49 89 189 47 41
executes the busy wait loop most of the time. Is it possible to trigger a
schedule event in Qemu which stops the simulation on one CPU and selects
another CPU instead?
--
Sebastian Huber, embedded brains GmbH
Address : Dornierstr. 4, D-82178 Puchheim, Germany
Phone : +49 89 189 47 41-16
Fax
If I replace the idle thread with this code
void *_CPU_Thread_Idle_body( uintptr_t ignored )
{
while ( true ) {
__asm__ volatile (wfi);
}
}
void foobarblub(void)
{
__asm__ volatile (nop; nop; nop; nop; nop);
bsp_reset();
}
then I get also an invalid execution sequence:
If I use this idle thread
volatile int sdlkfj = 0;
void *_CPU_Thread_Idle_body( uintptr_t ignored )
{
while ( true ) {
while ( sdlkfj == 0 ) {
__asm__ volatile (wfi; nop; nop; nop);
}
__asm__ volatile (wfi; nop; nop; nop);
}
}
then the test program seems to run forever
Thanks a lot for your help! It is not a Qemu problem.
I ported the code from a pre ARMv7 environment. In the assembler code I
have this:
msr spsr, r5
The GNU as translates this to:
msr SPSR_fc, r5
Correct is this:
msr SPSR_fsxc, r5
I fixed the assembler source and now all SPSR
Public bug reported:
I use Qemu (Git 1239b472bb0dba8060f1af29d40dafbc1b2860d4) to test a SMP
application on ARM. I use the following command line:
qemu-system-arm -S -s -net none -nographic -M realview-pbx-a9 -kernel
app.exe -m 256M -no-reboot -smp 2 -icount 8
The application crashes because
** Attachment added: ELF file of the application.
https://bugs.launchpad.net/qemu/+bug/1182344/+attachment/3682743/+files/app.exe
--
You received this bug notification because you are a member of qemu-
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https://bugs.launchpad.net/bugs/1182344
Title:
?
In case I start two CPUs and execute a while (1) loop in both of them with
interrupts disabled. Will Qemu ever switch from one CPU to the other?
--
Sebastian Huber, embedded brains GmbH
Address : Dornierstr. 4, D-82178 Puchheim, Germany
Phone : +49 89 189 47 41-16
Fax : +49 89 189 47 41
---
hw/misc/zynq_slcr.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c
index 8418327..e88702e 100644
--- a/hw/misc/zynq_slcr.c
+++ b/hw/misc/zynq_slcr.c
@@ -396,6 +396,9 @@ static void zynq_slcr_write(void *opaque, hwaddr
response
(gdb) Malformed response to offset query, timeout
Have a nice day!
--
Sebastian Huber, embedded brains GmbH
Address : Obere Lagerstr. 30, D-82178 Puchheim, Germany
Phone : +49 89 18 90 80 79-6
Fax : +49 89 18 90 80 79-9
E-Mail : sebastian.hu...@embedded-brains.de
PGP : Public key
On 17/12/11 01:50, Peter Maydell wrote:
On 16 December 2011 18:50, Sebastian Huber
sebastian.hu...@embedded-brains.de wrote:
According to ARMv7-M Architecture Reference Manual issue D section
B3.2.10 System Handler Prioriy Register 1, SHPR1, B3.2.11 System
Handler Prioriy Register 2, SHPR2
According to ARMv7-M Architecture Reference Manual issue D section
B3.2.10 System Handler Prioriy Register 1, SHPR1, B3.2.11 System
Handler Prioriy Register 2, SHPR2, and B3.2.12 System Handler Prioriy
Register 3, SHPR3.
Signed-off-by: Sebastian Huber sebastian.hu...@embedded-brains.de
---
hw
Hello,
I am able to run the RTEMS real time system on the TI Stellaris LM3S6965
with a working system tick. I used the attached local hacks and patches
with the Qemu development branch from today.
Have a nice day!
--
Sebastian Huber, embedded brains GmbH
Address : Obere Lagerstr. 30, D
This is unused for the ARMv7-M NVIC.
Signed-off-by: Sebastian Huber sebastian.hu...@embedded-brains.de
---
hw/arm_gic.c |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/hw/arm_gic.c b/hw/arm_gic.c
index 5139d95..cafcc81 100644
--- a/hw/arm_gic.c
+++ b/hw/arm_gic.c
Hello,
this may help to fix Bug 696094.
--
Sebastian Huber, embedded brains GmbH
Address : Obere Lagerstr. 30, D-82178 Puchheim, Germany
Phone : +49 89 18 90 80 79-6
Fax : +49 89 18 90 80 79-9
E-Mail : sebastian.hu...@embedded-brains.de
PGP : Public key available on request.
Diese
Hello,
how can I disable interrupts on the Cortex M3 based board LM3S6965EVB?
Even if I set PRIMASK, FAULTMASK and BASEPRI to 1 the SYSTICK interrupt
handler gets called.
Have a nice day!
On 05/06/11 12:31, Sebastian Huber wrote:
Hello,
how can I disable interrupts on the Cortex M3 based board LM3S6965EVB?
Even if I set PRIMASK, FAULTMASK and BASEPRI to 1 the SYSTICK interrupt
handler gets called.
Have a nice day!
I think the interrupt handling logic for ARMv7M is wrong
On 05/06/11 15:44, Peter Maydell wrote:
On 5 June 2011 14:06, Sebastian Huber
sebastian.hu...@embedded-brains.de wrote:
I think the interrupt handling logic for ARMv7M is wrong in cpu-exec.c
line 470. Please have a look at the attached patch.
--- a/cpu-exec.c
+++ b/cpu-exec.c
On 05/06/11 16:57, Peter Maydell wrote:
On 5 June 2011 15:17, Sebastian Huber
sebastian.hu...@embedded-brains.de wrote:
On 05/06/11 15:44, Peter Maydell wrote:
[...]
(It looks suspiciously as if most of the v7M priority handling
is simply missing from QEMU, ie you have bigger problems
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