Re: [PATCH] tests/qemu-iotests/testenv: Use the "r2d" machine for sh4/sh4eb

On Wed, 18 Sep 2024 04:43:50 +0900, Thomas Huth wrote: > > Commit 0ea0538fae516f9b4 removed the default machine of the sh4 > binaries, so a lot of iotests are failing now without such a default > machine. Teach the iotest harness to use the "r2d" machine instead > to fix this problem. > > Signed-

Re: [PATCH 0/3] hw/sh4: Remove the deprecated SHIX machine

/meson.build| 1 - > hw/sh4/Kconfig | 7 - > hw/sh4/meson.build | 1 - > 12 files changed, 7 insertions(+), 401 deletions(-) > delete mode 100644 hw/block/tc58128.c > delete mode 100644 hw/sh4/shix.c > > -- > 2.45.2 > for hw/sh4 Reviewed-by: Yoshinori Sato -- Yosinori Sato

Re: [RFC PATCH] tests/avocado: Re-enable gdbsim-r5f562n8 testing U-Boot

timeout = 30 > KERNEL_COMMON_COMMAND_LINE = 'printk.time=0 ' > > -@skipUnless(os.getenv('QEMU_TEST_FLAKY_TESTS'), 'Test is unstable on > GitLab') > - > def test_uboot(self): > """ > U-Boot and checks that the console is operational. > -- > 2.45.2 > Reviewed-by: Yoshinori Sato -- Yosinori Sato

Re: [PATCH] target/sh4: Avoid shift into sign bit in update_itlb_use()

o_interrupt(CPUState *cs) > > static void update_itlb_use(CPUSH4State * env, int itlbnb) > { > -uint8_t or_mask = 0, and_mask = (uint8_t) - 1; > +uint32_t or_mask = 0, and_mask = 0xff; > > switch (itlbnb) { > case 0: > -- > 2.34.1 > Reviewed-by: Yoshinori Sato -- Yosinori Sato

Re: [PATCH] target/sh4: Update DisasContextBase.insn_start

@@ static void decode_gusa(DisasContext *ctx, CPUSH4State > *env) > */ > for (i = 1; i < max_insns; ++i) { > tcg_gen_insn_start(pc + i * 2, ctx->envflags); > +ctx->base.insn_start = tcg_last_op(); > } > } > #endif > -- > 2.34.1 > Reviewed-by: Yoshinori Sato -- Yosinori Sato

Re: [PATCH for-9.0 v3 0/4] target/sh4: Fix mac.[lw]

On Sat, 04 May 2024 17:25:52 +0900, Michael Tokarev wrote: > > 06.04.2024 08:37, Richard Henderson wrote: > > Zack's recent patches, tidied a little bit, and with > > test cases added. > > These fixes ended up in stable-8.2, but not in stable-7.2. > This is because in 7.2, the context is a bit di

Re: [PATCH v4 4/4] target/sh4: Rename TCGv variables as manual for SUBV opcode

, Rn, Rm); > tcg_gen_and_i32(t1, t1, t2); > tcg_gen_shri_i32(cpu_sr_t, t1, 31); > -tcg_gen_mov_i32(REG(B11_8), t0); > + tcg_gen_mov_i32(Rn, result); > } > return; > case 0x2008: /* tst Rm,Rn */ > -- > 2.41.0 > Reviewed-by: Yoshinori Sato -- Yosinori Sato

Re: [PATCH v4 3/4] target/sh4: Rename TCGv variables as manual for ADDV opcode

tcg_gen_xor_i32(t2, Rm, Rn); > tcg_gen_andc_i32(cpu_sr_t, t1, t2); > tcg_gen_shri_i32(cpu_sr_t, cpu_sr_t, 31); > -tcg_gen_mov_i32(REG(B11_8), t0); > + tcg_gen_mov_i32(Rn, result); > } > return; > case 0x2009: /* and Rm,Rn */ > -- > 2.41.0 > Reviewed-by: Yoshinori Sato -- Yosinori Sato

Re: [PATCH v4 1/4] target/sh4: Fix ADDV opcode

; +{ > +addv(INT_MAX, 1, INT_MIN, 1); > +addv(INT_MAX - 1, 1, INT_MAX, 0); > + > +return 0; > +} > diff --git a/tests/tcg/sh4/Makefile.target b/tests/tcg/sh4/Makefile.target > index 4d09291c0c..521b8b0a76 100644 > --- a/tests/tcg/sh4/Makefile.target > +++ b/tests/tcg/sh4/Makefile.target > @@ -17,3 +17,6 @@ TESTS += test-macl > > test-macw: CFLAGS += -O -g > TESTS += test-macw > + > +test-addv: CFLAGS += -O -g > +TESTS += test-addv > -- > 2.41.0 > Reviewed-by: Yoshinori Sato -- Yosinori Sato

Re: [PATCH v4 2/4] target/sh4: Fix SUBV opcode

subv(INT_MAX, 1, INT_MAX - 1, 0); > +subv(0, 1, -1, 0); > +subv(-1, -1, 0, 0); > + > +return 0; > +} > diff --git a/tests/tcg/sh4/Makefile.target b/tests/tcg/sh4/Makefile.target > index 521b8b0a76..7852fa62d8 100644 > --- a/tests/tcg/sh4/Makefile.target > +++ b/tests/tcg/sh4/Makefile.target > @@ -20,3 +20,6 @@ TESTS += test-macw > > test-addv: CFLAGS += -O -g > TESTS += test-addv > + > +test-subv: CFLAGS += -O -g > +TESTS += test-subv > -- > 2.41.0 > Reviewed-by: Yoshinori Sato -- Yosinori Sato

Re: [PATCH] target/sh4: add missing CHECK_NOT_DELAY_SLOT

4 + B7_0 * 4) & ~3); > return; > -- > 2.41.0 > That's what the documentation said. > If a PC-relative load instruction is executed in a delay slot, > an illegal slot instruction exception will be generated. Reviewed-by: Yoshinori Sato -- Yosinori Sato

Re: [PATCH 30/32] target/rx: Use translator_ld*

On Fri, 05 Apr 2024 19:24:57 +0900, Richard Henderson wrote: > > Cc: Yoshinori Sato > Signed-off-by: Richard Henderson > --- > target/rx/translate.c | 27 ++- > 1 file changed, 14 insertions(+), 13 deletions(-) > > diff --git a/target/rx

Re: [PATCH v2] sh4: mac.w: implement saturation arithmetic logic

* If there is no overflow, the result is already inside > + * the saturation bounds. > + * > + * If there was no overflow, MACH is unchanged. > + */ > +env->macl = result; > } > +} else { > +/* In non-saturation arithmetic mode, the accumulator is 64-bit */ > +int64_t mac = (((uint64_t)env->mach) << 32) | env->macl; > + > +/* The carry bit of the 64-bit addition is discarded */ > +int64_t result = mac + (int64_t)mul; > +env->macl = result; > +env->mach = result >> 32; > } > } > > -- > 2.41.0 > Reviewd-by: Yoshinori Sato -- Yosinori Sato

Re: [PATCH] sh4: mac.w: memory accesses are 16-bit words

sas.com/us/en/document/mas/sh-4-software-manual > This instruction performs signed multiplication of the 16-bit operands > whose addresses are the contents of general registers Rm and Rn, > adds the 32-bit result to the MAC register contents, and stores the > result in the MAC register. Operands Rm and Rn are each incremented > by 2 each time they are read. Reviewed-by: Yoshinori Sato -- Yosinori Sato

Re: [PATCH v1 07/21] sh4: correct typos

ion-related registers > */ > > /* Immediate data for TRAPA instruction - TRA */ > -- > γαῖα πυρί μιχθήτω > Reviewed-by: Yoshinori Sato -- Yosinori Sato

Re: [PATCH v3 07/11] hw/sh4/r2d: Realize IDE controller before accessing it

sysbus_mmio_map(busdev, 1, 0x1400080c); > mmio_ide_init_drives(dev, dinfo, NULL); > -- > 2.41.0 > Reviewed-by: Yoshinori Sato -- Yosinori Sato

Re: [PATCH v3 03/11] hw/rx/rx62n: Only call qdev_get_gpio_in() when necessary

{ > - sysbus_connect_irq(sci, i, s->irq[irqbase + i]); > +sysbus_connect_irq(sci, i, > + qdev_get_gpio_in(DEVICE(&s->icu), irqbase + i)); > } > sysbus_mmio_map(sci, 0, RX62N_SCI_BASE + unit * 0x08); > } > -- > 2.41.0 > Reviewed-by: Yoshinori Sato -- Yosinori Sato

Re: [PATCH v3 02/11] hw/rx/rx62n: Reduce inclusion of 'qemu/units.h'

; +++ b/hw/rx/rx62n.c > @@ -23,6 +23,7 @@ > #include "qemu/osdep.h" > #include "qapi/error.h" > #include "qemu/error-report.h" > +#include "qemu/units.h" > #include "hw/rx/rx62n.h" > #include "hw/loader.h" > #include "hw/sysbus.h" > -- > 2.41.0 > Reviewed-by: Yoshinori Sato -- Yosinori Sato

Re: [PATCH 1/2] target/sh4: Deprecate the shix machine

YPE_SH7750R_CPU; > +mc->deprecation_reason = "old and unmaintained - use a newer machine > instead"; > } > > DEFINE_MACHINE("shix", shix_machine_init) > -- > 2.42.0 > I can't maintain this either. Reviewed-by: Yoshinori Sato -- Yosinori Sato

Re: [PATCH] MAINTAINERS: Add include/hw/timer/tmu012.h to the SH4 R2D section

On Thu, 26 Oct 2023 17:00:11 +0900, Thomas Huth wrote: > > tmu012.h is the header that belongs to hw/timer/sh_timer.c, so we > should list it in the same section as sh_timer.c. > > Signed-off-by: Thomas Huth Reviewed-by: Yoshinori Sato > --- > MAINTAINERS | 1 + > 1 f

Re: [PATCH 18/45] hw/sh4/r2d: use pci_init_nic_devices()

uld be dynamically assigned. > > Now, the first rtl8139 gets slot 2 and everything else is dynamic. > > Signed-off-by: David Woodhouse Reviewed-by: Yoshinori Sato > --- > hw/sh4/r2d.c | 6 ++ > 1 file changed, 2 insertions(+), 4 deletions(-) > > diff --git a/h

Re: [PATCH 5/7] target/rx: Use tcg_gen_ext_i32

On Fri, 20 Oct 2023 03:29:19 +0900, Richard Henderson wrote: > > Signed-off-by: Richard Henderson Reviewed-by: Yoshinori Sato > --- > target/rx/translate.c | 11 +++ > 1 file changed, 3 insertions(+), 8 deletions(-) > > diff --git a/target/rx/translate.c b/

Re: [PATCH RFC] hw/sh4/sh7750: Add STBCR/STBCR2 register support

On Wed, 18 Oct 2023 21:40:23 +0900, Geert Uytterhoeven wrote: > > The new Linux SH7750 clock driver uses the registers for power-down > mode control, causing a crash: > > byte read to SH7750_STBCR_A7 (0x1fc4) not supported > Aborted (core dumped) > > Fix this by adding suppor

Re: [PATCH 1/3] hw/pci-host/sh_pcic: Declare CPU QOM types using DEFINE_TYPES() macro

gned-off-by: Philippe Mathieu-Daudé Reviewed-by: Yoshinori Sato > --- > hw/pci-host/sh_pci.c | 40 +--- > 1 file changed, 17 insertions(+), 23 deletions(-) > > diff --git a/hw/pci-host/sh_pci.c b/hw/pci-host/sh_pci.c > index 77e7bbc65f..41aed48

Re: [PATCH 3/3] hw/pci-host/sh_pcic: Replace magic value by proper definition

On Thu, 12 Oct 2023 13:12:37 +0900, Philippe Mathieu-Daudé wrote: > > Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Yoshinori Sato > --- > hw/pci-host/sh_pci.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/hw/pci-host/sh_pci.c b

Re: [PATCH 2/3] hw/pci-host/sh_pcic: Correct PCI host / devfn#0 function names

On Thu, 12 Oct 2023 13:12:36 +0900, Philippe Mathieu-Daudé wrote: > > Host bridge device and PCI function #0 are inverted. > > Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Yoshinori Sato > --- > hw/pci-host/sh_pci.c | 16 > 1 file changed, 8 inser

Re: [PATCH] target/sh4: fix crashes on signal delivery

at the last instruction > in a gUSA region, we copy R1 to R15 to restore the correct stack pointer > and avoid crashing. > > There's another bug: if we are interrupted in a delay slot, we save the > address of the instruction in the delay slot. We must save the address of &g

Re: [PATCH 18/19] hw/rx: Set QDev properties using QDev API

kernel_filename != NULL, &error_abort); > +qdev_prop_set_link(DEVICE(&s->mcu), "main-bus", OBJECT(sysmem)); > +qdev_prop_set_uint32(DEVICE(&s->mcu), "xtal-frequency-hz", > + rxc->xtal_freq_hz); > +qdev_prop_set_bit(DEVICE(&s->mcu), "load-kernel", kernel_filename != > NULL); > > if (!kernel_filename) { > if (machine->firmware) { > -- > 2.38.1 > Reviewed-by: Yoshinori Sato -- Yosinori Sato

Re: [PATCH v2 5/8] rx: re-randomize rng-seed on reboot

added, so that we have a pointer to that copy of the FDT. > > Cc: Yoshinori Sato > Signed-off-by: Jason A. Donenfeld > --- > hw/rx/rx-gdbsim.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/hw/rx/rx-gdbsim.c b/hw/rx/rx-gdbsim.c > index 8ffe1b8035..1

Re: [PATCH v2] target/sh4: Fix TB_FLAG_UNALIGN

On Mon, 03 Oct 2022 02:23:51 +0900, Richard Henderson wrote: > > Ping, or should I create a PR myself? > > r~ Sorry. I can't work this week, so please submit a PR. > > On 9/1/22 07:15, Yoshinori Sato wrote: > > On Thu, 01 Sep 2022 19:15:09 +0900, > > Rich

Re: [PATCH 5/6] rx: re-randomize rng-seed on reboot

added, so that we have a pointer to that copy of the FDT. > > Cc: Yoshinori Sato > Signed-off-by: Jason A. Donenfeld > --- > hw/rx/rx-gdbsim.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/hw/rx/rx-gdbsim.c b/hw/rx/rx-gdbsim.c > index 8ffe1b8035..1

Re: [PATCH v2] target/sh4: Fix TB_FLAG_UNALIGN

textBase *dcbase, CPUState *cs) >(tbflags & (1 << SR_RB))) * 0x10; > ctx->fbank = tbflags & FPSCR_FR ? 0x10 : 0; > > -if (tbflags & GUSA_MASK) { > +#ifdef CONFIG_USER_ONLY > +if (tbflags & TB_FLAG_GUSA_MASK) { > +/* In gUSA exclusive region. */ > uint32_t pc = ctx->base.pc_next; > uint32_t pc_end = ctx->base.tb->cs_base; > -int backup = sextract32(ctx->tbflags, GUSA_SHIFT, 8); > +int backup = sextract32(ctx->tbflags, TB_FLAG_GUSA_SHIFT, 8); > int max_insns = (pc_end - pc) / 2; > > if (pc != pc_end + backup || max_insns < 2) { > /* This is a malformed gUSA region. Don't do anything special, > since the interpreter is likely to get confused. */ > -ctx->envflags &= ~GUSA_MASK; > -} else if (tbflags & GUSA_EXCLUSIVE) { > +ctx->envflags &= ~TB_FLAG_GUSA_MASK; > +} else if (tbflags & TB_FLAG_GUSA_EXCLUSIVE) { > /* Regardless of single-stepping or the end of the page, > we must complete execution of the gUSA region while > holding the exclusive lock. */ > @@ -2285,6 +2290,7 @@ static void sh4_tr_init_disas_context(DisasContextBase > *dcbase, CPUState *cs) > return; > } > } > +#endif > > /* Since the ISA is fixed-width, we can bound by the number > of instructions remaining on the page. */ > @@ -2309,8 +2315,8 @@ static void sh4_tr_translate_insn(DisasContextBase > *dcbase, CPUState *cs) > DisasContext *ctx = container_of(dcbase, DisasContext, base); > > #ifdef CONFIG_USER_ONLY > -if (unlikely(ctx->envflags & GUSA_MASK) > -&& !(ctx->envflags & GUSA_EXCLUSIVE)) { > +if (unlikely(ctx->envflags & TB_FLAG_GUSA_MASK) > +&& !(ctx->envflags & TB_FLAG_GUSA_EXCLUSIVE)) { > /* We're in an gUSA region, and we have not already fallen > back on using an exclusive region. Attempt to parse the > region into a single supported atomic operation. Failure > @@ -2330,9 +2336,9 @@ static void sh4_tr_tb_stop(DisasContextBase *dcbase, > CPUState *cs) > { > DisasContext *ctx = container_of(dcbase, DisasContext, base); > > -if (ctx->tbflags & GUSA_EXCLUSIVE) { > +if (ctx->tbflags & TB_FLAG_GUSA_EXCLUSIVE) { > /* Ending the region of exclusivity. Clear the bits. */ > -ctx->envflags &= ~GUSA_MASK; > +ctx->envflags &= ~TB_FLAG_GUSA_MASK; > } > > switch (ctx->base.is_jmp) { > -- > 2.34.1 > Reviewed-by: Yoshinori Sato -- Yosinori Sato

Re: [PATCH] target/sh4: Fix TB_FLAG_UNALIGN

gt; problem if another flag is added in the future? > > Hmm, or perhaps move it down below, so that we see bit 3 used, then bits > 4-12, then bit 13. > > > r~ How about this fix? From 69fc46c0e439026cabedc8ddfa0a880d0df09a6b Mon Sep 17 00:00:00 2001 From: Yoshinori Sato Date

Re: [PATCH] target/sh4: Fix TB_FLAG_UNALIGN

On Tue, 30 Aug 2022 01:10:29 +0900, Richard Henderson wrote: > > On 8/29/22 02:05, BALATON Zoltan wrote: > > On Sun, 28 Aug 2022, Richard Henderson wrote: > >> The value previously chosen overlaps GUSA_MASK. > >> > >> Cc: qemu-sta...@nongnu.org > >> Fixes: 4da06fb3062 ("target/sh4: Implement prct

Re: [PATCH] target/sh4: Honor QEMU_LOG_FILENAME with QEMU_LOG=cpu

se if (env->flags & DELAY_SLOT_CONDITIONAL) { > -qemu_printf("in conditional delay slot (delayed_pc=0x%08x)\n", > - env->delayed_pc); > +qemu_fprintf(f, "in conditional delay slot (delayed_pc=0x%08x)\n", > + env->delayed_pc); > } else if (env->flags & DELAY_SLOT_RTE) { > qemu_fprintf(f, "in rte delay slot (delayed_pc=0x%08x)\n", > env->delayed_pc); > -- > 2.35.3 > Reviewd-by: Yoshinori Sato -- Yosinori Sato

Re: [PATCH] hw/rx: pass random seed to fdt

On Tue, 19 Jul 2022 21:20:33 +0900, Jason A. Donenfeld wrote: > > If the FDT contains /chosen/rng-seed, then the Linux RNG will use it to > initialize early. Set this using the usual guest random number > generation function. This FDT node is part of the DT specification. > >

Re: [PATCH 0/4] target/rx: Track PSW.U in tb->flags

target/rx/cpu.h | 1 + > target/rx/translate.c | 67 +++ > 2 files changed, 37 insertions(+), 31 deletions(-) > > -- > 2.25.1 > Reviewed-by: Yoshinori Sato -- Yosinori Sato

Re: [PATCH] target/rx: swap stack pointers on clrpsw/setpsw instruction

On Sat, 16 Apr 2022 12:20:09 +0900, Tomoaki Kawada wrote: > > The control register field PSW.U determines which stack pointer register > (ISP or USP) is mapped as R0. In QEMU, this is implemented by having a > value copied between ISP or USP and R0 whenever PSW.U is updated or > access to ISP/USP

Re: [PATCH] target/rx: update PC correctly in wait instruction

32(cpu_pc, ctx->base.pc_next); > gen_helper_wait(cpu_env); > } > return true; > -- > 2.35.1 > Reviewed-by: Yoshinori Sato -- Yosinori Sato

Re: [PATCH] target/rx: set PSW.I when executing wait instruction

gt;halted = 1; > env->in_sleep = 1; > +env->psw_i = 1; > raise_exception(env, EXCP_HLT, 0); > } > > -- > 2.35.1 > Reviewed-by: Yoshinori Sato -- Yosinori Sato

Re: [PATCH] linux-user/sh4/termbits: Silence warning about TIOCSER_TEMT double definition

TARGET_IOR('T', 90, int) /* 0x545A > */ /* Get multiport config */ > #define TARGET_TIOCSERSETMULTI TARGET_IOW('T', 91, int) /* 0x545B > -- > 2.27.0 > Reviewed-by: Yoshinori Sato -- Yosinori Sato

Re: [PATCH] target/sh4: Remove old README.sh4 file

> - > -To build an ELF kernel image from the NAND image, 16 bytes have to be > -stripped off the end of every 528 bytes, keeping only 512 of them. The > -following Python code snippet does it: > - > -#! /usr/bin/python > - > -def denand (infd, outfd): > -while True: > -d = infd.read (528) > -if not d: return > -outfd.write (d[:512]) > - > -if __name__ == '__main__': > -import sys > -denand (open (sys.argv[1], 'rb'), > -open (sys.argv[2], 'wb')) > - > -Style isssues > -- > - > -There is currently a mix between my style (space before opening > -parenthesis) and qemu style. This will be resolved before final > -integration is proposed. > -- > 2.27.0 > Reviewed-by: Yoshinori Sato -- Yosinori Sato

[PATCH v3] hw/rx: rx-gdbsim DTB load address aligned of 16byte.

Linux kernel required alined address of DTB. But missing align in dtb load function. Fixed to load to the correct address. v3 changes. Fix round value. v2 changes. Use ROUND_DOWN macro. Signed-off-by: Yoshinori Sato Reviewed-by: Philippe Mathieu-Daudé --- hw/rx/rx-gdbsim.c | 2 +- 1 file

Re: [PATCH v2] hw/rx: rx-gdbsim DTB load address aligned of 16byte.

On Wed, 02 Feb 2022 21:46:22 +0900, Philippe Mathieu-Daudé via wrote: > > On 2/2/22 11:30, Yoshinori Sato wrote: > > Linux kernel required alined address of DTB. > > But missing align in dtb load function. > > Fixed to load to the correct address. > > > >

Re: [PATCH 1/2] hw/char/renesas_sci: Add fifo buffer to backend interface.

On Wed, 02 Feb 2022 03:54:45 +0900, Peter Maydell wrote: > > On Tue, 1 Feb 2022 at 17:47, Yoshinori Sato > wrote: > > > > On Tue, 01 Feb 2022 15:48:58 +0900, > > Thomas Huth wrote: > > > > > > On 31/01/2022 10.42, Yoshinori Sato wrote: > > &g

[PATCH v2] hw/rx: rx-gdbsim DTB load address aligned of 16byte.

Linux kernel required alined address of DTB. But missing align in dtb load function. Fixed to load to the correct address. v2 changes. Use ROUND_DOWN macro. Signed-off-by: Yoshinori Sato Reviewed-by: Philippe Mathieu-Daudé --- hw/rx/rx-gdbsim.c | 2 +- 1 file changed, 1 insertion(+), 1

Re: [PATCH 1/2] hw/char/renesas_sci: Add fifo buffer to backend interface.

On Tue, 01 Feb 2022 15:48:58 +0900, Thomas Huth wrote: > > On 31/01/2022 10.42, Yoshinori Sato wrote: > > SCI does not have a fifo, it is necessary to send and receive > > at a bit rate speed. > > But, qemu's chardev backend does not have a buffer, > > so

[PATCH 1/2] hw/char/renesas_sci: Add fifo buffer to backend interface.

SCI does not have a fifo, it is necessary to send and receive at a bit rate speed. But, qemu's chardev backend does not have a buffer, so it sends received data continuously. By buffering the received data with the FIFO, continuous received data can be received. Signed-off-by: Yoshinori

[PATCH 2/2] test/avocado: Update machibe_rx_gdbsim tests.

Since SCI supports continuous data receive, Added that test. Signed-off-by: Yoshinori Sato --- tests/avocado/machine_rx_gdbsim.py | 29 + 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/tests/avocado/machine_rx_gdbsim.py b/tests/avocado

[PATCH] hw/rx: rx-gdbsim: DTB load address fix.

Linux kernel required alined address of DTB. But missing align in dtb load function. Fixed to load to the correct address. Signed-off-by: Yoshinori Sato --- hw/rx/rx-gdbsim.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/rx/rx-gdbsim.c b/hw/rx/rx-gdbsim.c index 75d1fec6ca..f70472aeaf

Re: [PATCH] target/rx: Remove unused ENV_OFFSET definition

_SUFFIX > #define CPU_RESOLVING_TYPE TYPE_RX_CPU > -- > 2.34.1 > > Reviewed-by: Yoshinori Sato -- Yosinori Sato

Re: [PATCH for-7.0 3/4] target/rx/cpu.h: Don't include qemu-common.h

, so we can > just drop the include. > > Signed-off-by: Peter Maydell Reviewed-by: Yoshinori Sato > --- > target/rx/cpu.h | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/target/rx/cpu.h b/target/rx/cpu.h > index 4ac71aec370..657db84ef0a 100644 > --- a/ta

Re: [PATCH 0/5] hw/sh4: Codeing style fixes

c | 55 +- > include/hw/sh4/sh.h | 20 +- > 10 files changed, 1466 insertions(+), 1408 deletions(-) > > -- > 2.21.4 > > Reviewed-by: Yoshinori Sato -- Yosinori Sato

[PATCH 1/2] target/rx: Fix helper definiton.

Due to an incorrect definition of helper, TCG optimization could sometimes behave unexpectedly. Signed-off-by: Yoshinori Sato --- target/rx/helper.h | 36 ++-- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/target/rx/helper.h b/target/rx/helper.h

[PATCH 0/2] RX target update

I found some problem in RX target. This patches fix it. Yoshinori Sato (2): target/rx: Fix helper definiton. target/rx: gdbstub add acc register operation. target/rx/helper.h | 36 ++-- target/rx/gdbstub.c | 3 ++- 2 files changed, 20 insertions(+), 19

[PATCH 2/2] target/rx: gdbstub add acc register operation.

I added it because the operation of the acc register was not implemented. Signed-off-by: Yoshinori Sato --- target/rx/gdbstub.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/rx/gdbstub.c b/target/rx/gdbstub.c index c811d4810b..b5da5c42cb 100644 --- a/target/rx

Re: [PATCH 3/3] hw/sh4: sh7750 using renesas_sci.

On Tue, 29 Jun 2021 22:23:01 +0900, Peter Maydell wrote: > > On Wed, 16 Jun 2021 at 10:14, Yoshinori Sato > wrote: > > > > Signed-off-by: Yoshinori Sato > > --- > > include/hw/sh4/sh.h | 8 > > hw/sh4/sh7750.c | 41 ++

Re: [RFC PATCH 2/4] !fixup hw/rx: rx62n switch renesas_timer.

On Thu, 24 Jun 2021 18:23:34 +0900, Philippe Mathieu-Daudé wrote: > > Fixup while reviewing. > > Signed-off-by: Philippe Mathieu-Daudé > --- > include/hw/rx/rx62n.h | 3 +-- > hw/rx/rx62n.c | 6 +++--- > hw/rx/Kconfig | 1 - > 3 files changed, 4 insertions(+), 6 deletions(-) >

[PATCH 1/3] hw/timer: Add renesas_timer.

Renesas MCU / SoC have timer modules with similar functionality. SH4-TMU 32bit count down timer. RX-CMT 16bit compare match timer. Signed-off-by: Yoshinori Sato --- include/hw/timer/renesas_timer.h | 89 ++ hw/timer/renesas_timer.c | 532 +++ hw/timer

[PATCH 3/3] hw/sh4: sh7750 switch renesas_timer.

Signed-off-by: Yoshinori Sato --- hw/sh4/sh7750.c | 32 +--- hw/sh4/Kconfig | 2 +- 2 files changed, 30 insertions(+), 4 deletions(-) diff --git a/hw/sh4/sh7750.c b/hw/sh4/sh7750.c index d53a436d8c..bbebac8083 100644 --- a/hw/sh4/sh7750.c +++ b/hw/sh4/sh7750.c

[PATCH 0/3] Integrate renesas MCU/SoC timer module

SH4 TMU and RX CMT have simler functions. Integrate the sh_timer and renesas_cmt. Yoshinori Sato (3): hw/timer: Add renesas_timer. hw/rx: rx62n switch renesas_timer. hw/sh4: sh7750 switch renesas_timer. include/hw/rx/rx62n.h| 4 +- include/hw/timer/renesas_timer.h | 89

[PATCH 2/3] hw/rx: rx62n switch renesas_timer.

Signed-off-by: Yoshinori Sato --- include/hw/rx/rx62n.h | 4 ++-- hw/rx/Kconfig | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/include/hw/rx/rx62n.h b/include/hw/rx/rx62n.h index 3ed80dba0d..c35bf3998c 100644 --- a/include/hw/rx/rx62n.h +++ b/include/hw/rx/rx62n.h

[PATCH 1/3] hw/char: renesas_sci: Refactor for merge all SCI variant..

In order to handle unified all of the SCI, SCIa and SCIF in one part, to separate the transmission and reception portion and a register portion. RenesasSCIBase - common registers operation and event handling. RenesasSCIA - SCIa specific reigisters / functions. Signed-off-by: Yoshinori Sato

[PATCH 2/3] hw/char: renesas_sci Add SCI and SCIF support.

This peripheral using SH7750. Signed-off-by: Yoshinori Sato --- include/hw/char/renesas_sci.h | 43 ++- hw/char/renesas_sci.c | 489 ++ 2 files changed, 531 insertions(+), 1 deletion(-) diff --git a/include/hw/char/renesas_sci.h b/include/hw/char

[PATCH 0/3] renesas_sci update

Renesas SH/RX have various SCI in serial interface. The design of sh_serial is old, so I integrate these SCIs with renesas_sci. Yoshinori Sato (3): hw/char: renesas_sci: Refactor for merge all SCI variant.. hw/char: renesas_sci Add SCI and SCIF support. hw/sh4: sh7750 using renesas_sci

[PATCH 3/3] hw/sh4: sh7750 using renesas_sci.

Signed-off-by: Yoshinori Sato --- include/hw/sh4/sh.h | 8 hw/sh4/sh7750.c | 41 + hw/sh4/Kconfig | 2 +- 3 files changed, 42 insertions(+), 9 deletions(-) diff --git a/include/hw/sh4/sh.h b/include/hw/sh4/sh.h index becb596979

Re: [PATCH 01/11] hw/char: Renesas SCI module.

On Fri, 04 Jun 2021 18:09:44 +0900, Peter Maydell wrote: > > On Thu, 27 May 2021 at 06:30, Yoshinori Sato > wrote: > > > > This module supported SCI / SCIa / SCIF. > > > > Hardware manual. > > SCI / SCIF > > https://www.renesas.com/us/en/doc/p

Re: [PATCH 02/11] hw/char: remove sh_serial.

On Fri, 04 Jun 2021 19:08:07 +0900, Peter Maydell wrote: > > On Thu, 27 May 2021 at 06:24, Yoshinori Sato > wrote: > > > > Migrate to renesas_sci. > > > > Signed-off-by: Yoshinori Sato > > --- > > hw/char/sh_serial.c | 431

Re: [PATCH 02/11] hw/char: remove sh_serial.

On Fri, 04 Jun 2021 19:08:07 +0900, Peter Maydell wrote: > > On Thu, 27 May 2021 at 06:24, Yoshinori Sato > wrote: > > > > Migrate to renesas_sci. > > > > Signed-off-by: Yoshinori Sato > > --- > > hw/char/sh_serial.c | 431

Re: [PATCH 01/11] hw/char: Renesas SCI module.

On Fri, 04 Jun 2021 18:09:44 +0900, Peter Maydell wrote: > > On Thu, 27 May 2021 at 06:30, Yoshinori Sato > wrote: > > > > This module supported SCI / SCIa / SCIF. > > > > Hardware manual. > > SCI / SCIF > > https://www.renesas.com/us/en/doc/p

Re: [PATCH 02/11] hw/char: remove sh_serial.

On Fri, 04 Jun 2021 19:08:07 +0900, Peter Maydell wrote: > > On Thu, 27 May 2021 at 06:24, Yoshinori Sato > wrote: > > > > Migrate to renesas_sci. > > > > Signed-off-by: Yoshinori Sato > > --- > > hw/char/sh_serial.c | 431

Re: [PATCH 07/11] target/rx: Use FloatRoundMode in helper_set_fpsw

On Thu, 27 May 2021 13:14:01 +0900, Richard Henderson wrote: > > Use the proper type for the roundmode array. > > Cc: Philippe Mathieu-Daudé > Cc: Yoshinori Sato > Signed-off-by: Richard Henderson Reviewd-by: Yoshinori Sato > --- > target/rx/op_helper.c | 2

Re: [PATCH 08/11] target/rx: Fix setting of FPSW.CE

he introduction of float_flag_inorm_denormal and > float_flag_result_denormal, taking into account that DN now sets > the softfloat flush-to-zero bits. > > Cc: Philippe Mathieu-Daudé > Cc: Yoshinori Sato > Signed-off-by: Richard Henderson Reviewd-by: Yoshinori Sato > --- >

Re: [PATCH 06/11] target/rx: Handle the FPSW.DN bit in helper_set_fpsw

On Thu, 27 May 2021 13:14:00 +0900, Richard Henderson wrote: > > Both input and output denormals flush to zero when DN is set. > > Cc: Philippe Mathieu-Daudé > Cc: Yoshinori Sato > Signed-off-by: Richard Henderson Reviewd-by: Yoshinori Sato > --- > target/rx/op_hel

[PATCH 03/11] hw/timer: Renesas TMU/CMT module.

TMU - SH4 Timer module. CMT - Compare and match timer used by some Renesas MCUs. The two modules have similar interfaces and have been merged. Signed-off-by: Yoshinori Sato --- include/hw/timer/renesas_timer.h | 96 + hw/timer/renesas_timer.c | 644

[PATCH 07/11] hw/timer: Renesas 8bit timer.

Rewrite timer api. Signed-off-by: Yoshinori Sato --- include/hw/timer/renesas_tmr.h | 58 include/hw/timer/renesas_tmr8.h | 67 hw/timer/renesas_tmr.c | 493 - hw/timer/renesas_tmr8.c | 540 hw/timer

[PATCH 01/11] hw/char: Renesas SCI module.

This module supported SCI / SCIa / SCIF. Hardware manual. SCI / SCIF https://www.renesas.com/us/en/doc/products/mpumcu/001/r01uh0457ej0401_sh7751.pdf SCIa https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf Signed-off-by: Yoshinori Sato --- include/hw/char

[PATCH 09/11] hw/sh4: sh7750 Add CPG.

CPG required new hw modules. Signed-off-by: Yoshinori Sato --- include/hw/sh4/sh7751-cpg.h | 94 hw/sh4/sh7750.c | 25 ++ hw/sh4/sh7751-cpg.c | 457 hw/sh4/meson.build | 1 + 4 files changed, 577 insertions

[PATCH 08/11] hw/rx: rx62n use new hw modules.

Signed-off-by: Yoshinori Sato --- include/hw/rx/rx62n.h | 10 +- hw/rx/rx62n.c | 18 -- hw/rx/Kconfig | 4 ++-- 3 files changed, 19 insertions(+), 13 deletions(-) diff --git a/include/hw/rx/rx62n.h b/include/hw/rx/rx62n.h index 44f5fcc74d..942ed0639f

[PATCH 10/11] hw/sh4: sh7750 use new hw modules.

Signed-off-by: Yoshinori Sato --- include/hw/sh4/sh.h | 8 - hw/sh4/sh7750.c | 87 +++-- hw/sh4/Kconfig | 4 +-- 3 files changed, 79 insertions(+), 20 deletions(-) diff --git a/include/hw/sh4/sh.h b/include/hw/sh4/sh.h index becb596979

[PATCH 06/11] hw/rx: Add RX62N Clock generator

This module generated core and peripheral clock. Signed-off-by: Yoshinori Sato --- include/hw/rx/rx62n-cpg.h | 72 include/hw/rx/rx62n.h | 8 +- hw/rx/rx62n-cpg.c | 344 ++ hw/rx/rx62n.c | 39 +++-- hw/rx/meson.build

[PATCH 04/11] hw/timer: Remove sh_timer.

Migrate to renesas_timer. Signed-off-by: Yoshinori Sato --- include/hw/timer/tmu012.h | 23 --- hw/timer/sh_timer.c | 368 -- MAINTAINERS | 4 +- hw/timer/Kconfig | 4 - hw/timer/meson.build | 1 - 5 files changed, 2

[PATCH 02/11] hw/char: remove sh_serial.

Migrate to renesas_sci. Signed-off-by: Yoshinori Sato --- hw/char/sh_serial.c | 431 MAINTAINERS | 4 +- hw/char/Kconfig | 3 - hw/char/meson.build | 1 - 4 files changed, 2 insertions(+), 437 deletions(-) delete mode 100644 hw

[PATCH 11/11] hw/rx: rx-gdbsim Add bootstrup for linux

linux kernel require initializing some peripherals. Signed-off-by: Yoshinori Sato --- include/hw/rx/rx62n.h | 16 hw/rx/rx-gdbsim.c | 89 +-- hw/rx/rx62n.c | 15 3 files changed, 59 insertions(+), 61 deletions(-) diff --git

[PATCH 05/11] hw/timer: Remove renesas_cmt.

Migrate to renesas_timer. Signed-off-by: Yoshinori Sato --- include/hw/timer/renesas_cmt.h | 43 - hw/timer/renesas_cmt.c | 283 - hw/timer/meson.build | 1 - 3 files changed, 327 deletions(-) delete mode 100644 include/hw/timer

[PATCH 00/11] Unified peripheral emulation for Renesas chips

process the peripheral clocks of SH4 and RX in the same way, so I added a new clock generator. This will generate a peripheral clock from the master clock. Yoshinori Sato (11): hw/char: Renesas SCI module. hw/char: remove sh_serial. hw/timer: Renesas TMU/CMT module. hw/timer: Remove sh_timer. hw/t

Re: [PATCH] target/sh4: Return error if CPUClass::get_phys_page_debug() fails

ical_address(&cpu->env, &physical, &prot, addr, MMU_DATA_LOAD); > +if (get_physical_address(&cpu->env, &physical, &prot, addr, > MMU_DATA_LOAD) > +== MMU_OK) { > +return physical; > + } > > -return physical; > +return -1; > } > > void cpu_load_tlb(CPUSH4State * env) > -- > 2.26.3 > > Reviewed-by: Yoshinori Sato -- Yosinori Sato

Re: [PATCH-for-6.0?] hw/rx/rx-gdbsim: Do not accept invalid memory size

+93,7 @@ static void rx_gdbsim_init(MachineState *machine) > char *sz = size_to_str(mc->default_ram_size); > error_report("Invalid RAM size, should be more than %s", sz); > g_free(sz); > +exit(1); > } > > /* Allocate memory space */ > -- > 2.26.3 > Reviewed-by: Yoshinori Sato -- Yoshinori Sato

Re: [PATCH for-6.0] hw/timer/renesas_tmr: Add default-case asserts in read_tcnt()

le cases 0, 1, 2 and 3 then there cannot > be a flow of execution through the switch default. Add explicit > default cases which assert that they can't be reached, which > should help silence Coverity. > > Signed-off-by: Peter Maydell Reviewed-by: Yoshinori Sato > --- &

Re: [PATCH 00/20] RX target update

On Tue, 01 Sep 2020 05:38:37 +0900, Philippe Mathieu-Daudé wrote: > > [1 ] > [2 ] > Hello Yoshinori, > > Le jeu. 27 août 2020 14:43, Yoshinori Sato a > écrit : > > Hello. > This series Renesas RX updates. > > It consists of the followi

[PATCH 13/20] hw/timer: Add Renesas MTU2

Signed-off-by: Yoshinori Sato --- include/hw/timer/renesas_mtu.h | 90 +++ hw/timer/renesas_mtu.c | 1312 hw/timer/Kconfig |2 + hw/timer/meson.build |1 + 4 files changed, 1405 insertions(+) create mode 100644 include

[PATCH 15/20] hw/net: Add generic Bit-bang MDIO PHY.

Only supported link status. Signed-off-by: Yoshinori Sato --- include/hw/net/mdio.h | 126 hw/net/mdio.c | 264 ++ hw/net/Kconfig| 3 + hw/net/meson.build| 2 + 4 files changed, 395 insertions(+) create mode

[PATCH 16/20] hw/net: Add Renesas On-chip Ethernet MAC

Signed-off-by: Yoshinori Sato --- include/hw/net/renesas_eth.h | 57 +++ hw/net/renesas_eth.c | 875 +++ hw/net/Kconfig | 5 + hw/net/meson.build | 1 + 4 files changed, 938 insertions(+) create mode 100644 include/hw/net

[PATCH 14/20] hw/rx/rx62n: RX62N Add MTU module

Signed-off-by: Yoshinori Sato --- include/hw/rx/rx62n.h | 3 +++ hw/rx/rx62n.c | 28 hw/rx/Kconfig | 1 + 3 files changed, 32 insertions(+) diff --git a/include/hw/rx/rx62n.h b/include/hw/rx/rx62n.h index f463148799..170c8cb6fc 100644 --- a/include

[PATCH 06/20] hw/timer: Renesas 8bit timer emulation.

Rewrite for clock API. Signed-off-by: Yoshinori Sato --- include/hw/timer/renesas_tmr.h | 55 include/hw/timer/renesas_tmr8.h | 67 hw/timer/renesas_tmr.c | 477 hw/timer/renesas_tmr8.c | 540 hw/timer

[PATCH 20/20] MAINTAINERS: Update RX entry

Signed-off-by: Yoshinori Sato --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 5a22c8be42..cee8448a73 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2054,9 +2054,11 @@ F: hw/char/renesas_sci.c F: hw/char/sh_serial.c F: hw/timer/renesas_*.c

[PATCH 18/20] hw/rx: Add Tokudenkairo TKDN-RX62N-BRD

Hardware information. http://www.tokudenkairo.co.jp/rx62n/ (Japanese) Signed-off-by: Yoshinori Sato --- default-configs/rx-softmmu.mak | 1 + hw/rx/tkdn-rx62n.c | 192 + hw/rx/Kconfig | 6 ++ hw/rx/meson.build | 1

[PATCH 10/20] hw/rx: Convert to renesas_timer

Signed-off-by: Yoshinori Sato --- include/hw/rx/rx62n.h | 4 ++-- hw/rx/Kconfig | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/include/hw/rx/rx62n.h b/include/hw/rx/rx62n.h index 75945bae50..1182ca24de 100644 --- a/include/hw/rx/rx62n.h +++ b/include/hw/rx/rx62n.h

[PATCH 05/20] hw/rx: Add RX62N Clock generator

This module generated core and peripheral clock. Signed-off-by: Yoshinori Sato --- include/hw/rx/rx62n-cpg.h | 72 include/hw/rx/rx62n.h | 5 +- hw/rx/rx62n-cpg.c | 344 ++ hw/rx/rx62n.c | 52 +++--- hw/rx/meson.build

[PATCH 12/20] hw/rx/rx62n: Use New SCI module.

Signed-off-by: Yoshinori Sato --- include/hw/rx/rx62n.h | 2 +- hw/rx/rx62n.c | 7 ++- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/include/hw/rx/rx62n.h b/include/hw/rx/rx62n.h index 1182ca24de..f463148799 100644 --- a/include/hw/rx/rx62n.h +++ b/include/hw/rx

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