在 2023/6/2 14:52, Xiaoyao Li 写道:
On 5/31/2023 8:00 PM, Yanan Wang wrote:
Currently, we only avoid emulating L3 cache properties for AMD CPU
when l3-cache is off, but failed to consider this case on CPUID
8000_001D.
This result in a fact that we will still have L3 caches in the VM
although we
在 2023/2/20 10:49, Zhao Liu 写道:
On Fri, Feb 17, 2023 at 05:08:31PM +0800, wangyanan (Y) wrote:
Date: Fri, 17 Feb 2023 17:08:31 +0800
From: "wangyanan (Y)"
Subject: Re: [PATCH RESEND 18/18] i386: Add new property to control L2
cache topo in CPUID.04H
在 2023/2/17 15:26, Zhao Liu 写
在 2023/2/17 15:26, Zhao Liu 写道:
On Fri, Feb 17, 2023 at 12:07:01PM +0800, wangyanan (Y) wrote:
Date: Fri, 17 Feb 2023 12:07:01 +0800
From: "wangyanan (Y)"
Subject: Re: [PATCH RESEND 18/18] i386: Add new property to control L2
cache topo in CPUID.04H
在 2023/2/17 11:35, Zhao Liu 写
在 2023/2/17 11:14, Zhao Liu 写道:
On Thu, Feb 16, 2023 at 05:31:11PM +0800, wangyanan (Y) wrote:
Date: Thu, 16 Feb 2023 17:31:11 +0800
From: "wangyanan (Y)"
Subject: Re: [RFC 12/52] hw/acpi: Replace MachineState.smp access with
topology helpers
Hi Zhao,
在 2023/2/13 17:49, Zhao Liu
在 2023/2/17 11:26, Zhao Liu 写道:
On Thu, Feb 16, 2023 at 08:15:23PM +0800, wangyanan (Y) wrote:
Date: Thu, 16 Feb 2023 20:15:23 +0800
From: "wangyanan (Y)"
Subject: Re: [RFC 41/52] machine: Introduce core_type() hook
Hi Zhao,
在 2023/2/13 17:50, Zhao Liu 写道:
From: Zhao Liu
Since
在 2023/2/17 11:07, Zhao Liu 写道:
On Thu, Feb 16, 2023 at 04:38:38PM +0800, wangyanan (Y) wrote:
Date: Thu, 16 Feb 2023 16:38:38 +0800
From: "wangyanan (Y)"
Subject: Re: [RFC 08/52] machine: Add helpers to get cpu topology info from
MachineState.topo
Hi Zhao,
在 2023/2/13 17:49, Z
在 2023/2/17 11:35, Zhao Liu 写道:
On Thu, Feb 16, 2023 at 09:14:54PM +0800, wangyanan (Y) wrote:
Date: Thu, 16 Feb 2023 21:14:54 +0800
From: "wangyanan (Y)"
Subject: Re: [PATCH RESEND 18/18] i386: Add new property to control L2
cache topo in CPUID.04H
在 2023/2/13 17:36, Zhao Liu
在 2023/2/17 11:35, Zhao Liu 写道:
On Thu, Feb 16, 2023 at 09:14:54PM +0800, wangyanan (Y) wrote:
Date: Thu, 16 Feb 2023 21:14:54 +0800
From: "wangyanan (Y)"
Subject: Re: [PATCH RESEND 18/18] i386: Add new property to control L2
cache topo in CPUID.04H
在 2023/2/13 17:36, Zhao Liu
在 2023/2/13 17:36, Zhao Liu 写道:
From: Zhao Liu
The property x-l2-cache-topo will be used to change the L2 cache
topology in CPUID.04H.
Now it allows user to set the L2 cache is shared in core level or
cluster level.
If user passes "-cpu x-l2-cache-topo=[core|cluster]" then older L2 cache
在 2023/2/15 10:53, Zhao Liu 写道:
On Tue, Feb 14, 2023 at 09:46:50AM +0800, wangyanan (Y) wrote:
Date: Tue, 14 Feb 2023 09:46:50 +0800
From: "wangyanan (Y)"
Subject: Re: [RFC 42/52] hw/machine: Add hybrid_supported in generic topo
properties
Hi Zhao,
在 2023/2/13 17:50, Zhao Liu
Hi Zhao,
在 2023/2/13 17:50, Zhao Liu 写道:
From: Zhao Liu
Since supported core types are architecture specific, we need this hook
to allow archs define its own parsing or validation method.
As the example, add the x86 core_type() which will be used in "-hybrid"
parameter parsing.
在 2023/2/13 17:50, Zhao Liu 写道:
From: Zhao Liu
When MachineState.topo is introduced, the topology related structures
become complicated. So we wrapped the access to topology fields of
MachineState.topo into some helpers, and we are using these helpers
to replace the use of MachineState.smp.
Hi Zhao,
在 2023/2/13 17:49, Zhao Liu 写道:
From: Zhao Liu
At present, in QEMU only arm needs PPTT table to build cpu topology.
Before QEMU's arm supports hybrid architectures, it's enough to limit
the cpu topology of PPTT to smp type through the explicit smp interface
Hi Zhao,
在 2023/2/13 17:49, Zhao Liu 写道:
From: Zhao Liu
When MachineState.topo is introduced, the topology related structures
become complicated. In the general case (hybrid or smp topology),
accessing the topology information needs to determine whether it is
currently smp or hybrid topology,
在 2023/2/15 23:03, Zhao Liu 写道:
On Wed, Feb 15, 2023 at 07:06:32PM +0800, wangyanan (Y) wrote:
Date: Wed, 15 Feb 2023 19:06:32 +0800
From: "wangyanan (Y)"
Subject: Re: [PATCH RESEND 10/18] i386: Update APIC ID parsing rule to
support module level
Hi Zhao,
在 2023/2/13 17:36, Z
Hi Zhao,
在 2023/2/13 17:36, Zhao Liu 写道:
From: Zhuocheng Ding
Support module level in i386 cpu topology structure "X86CPUTopoInfo".
Before updating APIC ID parsing rule with module level, the
apicid_core_width() temporarily combines the core and module levels
together.
If we dont merge this
在 2023/2/13 17:36, Zhao Liu 写道:
From: Zhao Liu
>From AMD's APM, NumSharingCache (CPUID[0x801D].EAX[bits 25:14])
means [1]:
The number of logical processors sharing this cache is the value of
this field incremented by 1. To determine which logical processors are
sharing a cache, determine
Hi Zhao,
在 2023/2/13 17:36, Zhao Liu 写道:
From: Zhao Liu
Currently, by default, the cache topology is encoded as:
1. i/d cache is shared in one core.
2. L2 cache is shared in one core.
3. L3 cache is shared in one die.
This default general setting has caused a misunderstanding, that is, the
在 2023/2/13 17:36, Zhao Liu 写道:
From: Zhuocheng Ding
After i386 supports module level, it's time to add the test for module
level's parsing.
Signed-off-by: Zhuocheng Ding
Co-developed-by: Zhao Liu
Signed-off-by: Zhao Liu
---
tests/unit/test-x86-apicid.c | 19 +++
1 file
Hi Zhao,
在 2023/2/13 17:36, Zhao Liu 写道:
From: Zhuocheng Ding
Add the module level parsing support for APIC ID.
With this support, now the conversion between X86CPUTopoIDs,
X86CPUTopoInfo and APIC ID is completed.
IIUC, contents in patch 6-8 and 10 are all about "Introduce the module-level
在 2023/2/13 17:36, Zhao Liu 写道:
From: Zhao Liu
For function comments in this file, keep the comment style consistent
with other places.
Signed-off-by: Zhao Liu
nit：Better to move this cleanup patch to top of the series.
---
include/hw/i386/topology.h | 33
在 2023/2/13 17:36, Zhao Liu 写道:
From: Zhuocheng Ding
Support module level in i386 cpu topology structure "X86CPUTopoInfo".
Before updating APIC ID parsing rule with module level, the
apicid_core_width() temporarily combines the core and module levels
together.
At present, we don't expose
Hi Zhao,
在 2023/2/13 17:36, Zhao Liu 写道:
From: Zhao Liu
For i-cache and d-cache, the maximum IDs for CPUs sharing cache (
CPUID.04H.00H:EAX[bits 25:14] and CPUID.04H.01H:EAX[bits 25:14]) are
both 0, and this means i-cache and d-cache are shared in the SMT level.
This is correct if there's
在 2023/2/15 11:35, Zhao Liu 写道:
On Wed, Feb 15, 2023 at 10:36:34AM +0800, wangyanan (Y) wrote:
Date: Wed, 15 Feb 2023 10:36:34 +0800
From: "wangyanan (Y)"
Subject: Re: [PATCH RESEND 02/18] tests: Rename test-x86-cpuid.c to
test-x86-apicid.c
在 2023/2/13 17:36, Zhao Liu 写道:
From
在 2023/2/13 17:36, Zhao Liu 写道:
From: Zhuocheng Ding
smp command has the "clusters" parameter but x86 hasn't supported that
level. Though "clusters" was introduced to help define L2 cache topology
[1], using cluster to define x86's L2 cache topology will cause the
compatibility problem:
Well,
在 2023/2/15 15:10, Zhao Liu 写道:
On Wed, Feb 15, 2023 at 11:28:25AM +0800, wangyanan (Y) wrote:
Date: Wed, 15 Feb 2023 11:28:25 +0800
From: "wangyanan (Y)"
Subject: Re: [PATCH RESEND 05/18] i386/cpu: Consolidate the use of
topo_info in cpu_x86_cpuid()
在 2023/2/13 17:36, Zhao Liu
在 2023/2/13 17:36, Zhao Liu 写道:
From: Zhao Liu
In cpu_x86_cpuid(), there are many variables in representing the cpu
topology, e.g., topo_info, cs->nr_cores/cs->nr_threads.
Since the names of cs->nr_cores/cs->nr_threads does not accurately
represent its meaning, the use of
Hi Zhao,
在 2023/2/13 17:36, Zhao Liu 写道:
From: Zhuocheng Ding
>From CPUState.nr_cores' comment, it represents "number of cores within
this CPU package".
After 003f230 (machine: Tweak the order of topology members in struct
CpuTopology), the meaning of smp.cores changed to "the number of
在 2023/2/13 17:36, Zhao Liu 写道:
From: Zhao Liu
In fact, this unit tests APIC ID other than CPUID.
Rename to test-x86-apicid.c to make its name more in line with its
actual content.
Signed-off-by: Zhao Liu
---
MAINTAINERS| 2 +-
在 2023/2/13 17:36, Zhao Liu 写道:
From: Zhuocheng Ding
As module-level topology support is added to X86CPU, now we can enable
the support for the cluster parameter on PC machines. With this support,
we can define a 5-level x86 CPU topology with "-smp":
-smp
在 2023/2/13 17:36, Zhao Liu 写道:
From: Zhao Liu
For function comments in this file, keep the comment style consistent
with other places.
Signed-off-by: Zhao Liu
---
include/hw/i386/topology.h | 33 +
1 file changed, 17 insertions(+), 16 deletions(-)
diff
在 2023/2/14 18:16, Zhao Liu 写道:
On Mon, Feb 13, 2023 at 09:18:05PM +0800, wangyanan (Y) wrote:
Date: Mon, 13 Feb 2023 21:18:05 +0800
From: "wangyanan (Y)"
Subject: Re: [RFC 06/52] hw/cpu: Introduce hybrid CPU topology
Hi Zhao,
在 2023/2/13 17:49, Zhao Liu 写道:
From: Zhao Liu
For s
Hi Zhao,
在 2023/2/13 17:50, Zhao Liu 写道:
From: Zhao Liu
Since hybrid cpu topology configuration can benefit not only x86, but
also other architectures/platforms that have supported (in real
machines) or will support hybrid CPU topology, "-hybrid" can be generic.
So add the generic topology
在 2023/2/13 17:36, Zhao Liu 写道:
From: Zhao Liu
Now smp supports dies and clusters, so add description about these 2
levels in the comment of machine_parse_smp_config().
Fixes: 864c3b5 (hw/core/machine: Introduce CPU cluster topology support)
Suggested-by: Robert Hoo
Signed-off-by: Zhao Liu
Hi Zhao,
在 2023/2/13 17:49, Zhao Liu 写道:
From: Zhao Liu
For smp systems, the parts in one topology level are the same. But now
there are more and more systems with hybrid architectures. Different
parts of the same topology level may have differences. For example,
Intel's Alder Lake series CPU
Hi Zhao，
在 2023/2/13 17:49, Zhao Liu 写道:
From: Zhao Liu
Hybrid topology support will also be added to this file.
In order to maintain the semantic consistency of the file name and
content, the file name is changed to "machine-topo.c".
This file will handle all cpu topology related things,
On 2022/11/1 15:10, Yicong Yang wrote:
From: Yicong Yang
Add *.topology tables for the aarch64's topology test and empty
bios-tables-test-allowed-diff.h
The disassembled differences between actual and expected
PPTT (the table which we actually care about):
+/*
+ * Intel ACPI Component
On 2022/11/1 15:10, Yicong Yang wrote:
From: Yicong Yang
Add test for aarch64's ACPI topology building for all the supported
levels.
Acked-by: Michael S. Tsirkin
Signed-off-by: Yicong Yang
---
tests/qtest/bios-tables-test.c | 19 +++
1 file changed, 19 insertions(+)
On 2022/11/1 15:10, Yicong Yang wrote:
From: Yicong Yang
Add and whitelist *.topology blobs, prepares for the aarch64's ACPI
topology building test.
Signed-off-by: Yicong Yang
Reviewed-by: Yanan Wang
Thanks,
Yanan
---
tests/data/acpi/virt/APIC.topology | 0
On 2022/11/1 15:10, Yicong Yang wrote:
From: Yicong Yang
Update the ACPI tables according to the acpi aml_build change, also
empty bios-tables-test-allowed-diff.h.
The disassembled differences between actual and expected PPTT:
/*
* Intel ACPI Component Architecture
* AML/ASL+
On 2022/11/1 15:10, Yicong Yang wrote:
From: Yicong Yang
Currently we'll always generate a cluster node no matter user has
specified '-smp clusters=X' or not. Cluster is an optional level
and will participant the building of Linux scheduling domains and
only appears on a few platforms. It's
On 2022/11/1 15:10, Yicong Yang wrote:
From: Yicong Yang
Allow changes to test/data/acpi/virt/PPTT, prepare to change the
building policy of the cluster topology.
Signed-off-by: Yicong Yang
Reviewed-by: Yanan Wang
Thanks,
Yanan
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
Hi Yicong,
On 2022/10/31 17:05, Yicong Yang wrote:
From: Yicong Yang
Update the ACPI tables according to the acpi aml_build change.
We may also need the disassembled context of the table change
in the commit message, for review.
For your reference: see patch 6 in [1]:
On 2022/10/31 17:05, Yicong Yang wrote:
From: Yicong Yang
Currently we'll always generate a cluster node no matter user has
specified '-smp clusters=X' or not. Cluster is an optional level
and will participant the building of Linux scheduling domains and
only appears on a few platforms.
It's
Hi Yicong,
On 2022/10/31 17:05, Yicong Yang wrote:
From: Yicong Yang
Add test for aarch64's ACPI topology building for all the supported
levels.
Acked-by: Michael S. Tsirkin
Signed-off-by: Yicong Yang
---
tests/qtest/bios-tables-test.c | 22 ++
1 file changed, 22
Hi Yicong,
On 2022/10/27 11:26, Yicong Yang wrote:
From: Yicong Yang
Currently we'll always generate a cluster node no matter user has
specified '-smp clusters=X' or not. Cluster is an optional level
and will participant the building of Linux scheduling domains and
only appears on a few
Hi Yicong,
On 2022/9/22 21:11, Yicong Yang wrote:
From: Yicong Yang
Currently we'll always generate a cluster node no matter user has
specified '-smp clusters=X' or not. Cluster is an optional level
and it's unncessary to build it if user don't need. So only generate
it when user specify
Hi Gavin,
On 2022/4/20 18:49, Gavin Shan wrote:
This adds cluster-id in CPU instance properties, which will be used
by arm/virt machine. Besides, the cluster-id is also verified or
dumped in various spots:
* hw/core/machine.c::machine_set_cpu_numa_node() to associate
CPU with its NUMA
Hi Gavin,
Sorry I missed the v6.
On 2022/4/20 18:49, Gavin Shan wrote:
Currently, the SMP configuration isn't considered when the CPU
topology is populated. In this case, it's impossible to provide
the default CPU-to-NUMA mapping or association based on the socket
ID of the given CPU.
This
Hi Gavin,
On 2022/4/20 18:49, Gavin Shan wrote:
When the PPTT table is built, the CPU topology is re-calculated, but
it's unecessary because the CPU topology has been populated in
virt_possible_cpu_arch_ids() on arm/virt machine.
This reworks build_pptt() to avoid by reusing the existing IDs
On 2022/4/14 15:56, Gavin Shan wrote:
Hi Yanan,
On 4/14/22 10:27 AM, wangyanan (Y) wrote:
On 2022/4/14 8:06, Gavin Shan wrote:
On 4/13/22 7:49 PM, wangyanan (Y) wrote:
On 2022/4/3 22:59, Gavin Shan wrote:
This adds cluster-id in CPU instance properties, which will be used
by arm/virt
On 2022/4/14 15:35, Gavin Shan wrote:
Hi Yanan,
On 4/14/22 10:49 AM, wangyanan (Y) wrote:
On 2022/4/14 10:37, Gavin Shan wrote:
On 4/14/22 10:27 AM, wangyanan (Y) wrote:
On 2022/4/14 8:08, Gavin Shan wrote:
On 4/13/22 8:39 PM, wangyanan (Y) wrote:
On 2022/4/3 22:59, Gavin Shan wrote
On 2022/4/14 15:45, Gavin Shan wrote:
Hi Yanan,
On 4/14/22 11:09 AM, wangyanan (Y) wrote:
On 2022/4/3 22:59, Gavin Shan wrote:
When the PPTT table is built, the CPU topology is re-calculated, but
it's unecessary because the CPU topology has been populated in
virt_possible_cpu_arch_ids
Hi Gavin,
On 2022/4/3 22:59, Gavin Shan wrote:
When the PPTT table is built, the CPU topology is re-calculated, but
it's unecessary because the CPU topology has been populated in
virt_possible_cpu_arch_ids() on arm/virt machine.
This reworks build_pptt() to avoid by reusing the existing one in
On 2022/4/14 8:33, Gavin Shan wrote:
Hi Igor,
On 4/13/22 9:52 PM, Igor Mammedov wrote:
On Sun, 3 Apr 2022 22:59:53 +0800
Gavin Shan wrote:
When the PPTT table is built, the CPU topology is re-calculated, but
it's unecessary because the CPU topology has been populated in
On 2022/4/14 10:37, Gavin Shan wrote:
Hi Yanan,
On 4/14/22 10:27 AM, wangyanan (Y) wrote:
On 2022/4/14 8:08, Gavin Shan wrote:
On 4/13/22 8:39 PM, wangyanan (Y) wrote:
On 2022/4/3 22:59, Gavin Shan wrote:
Currently, the SMP configuration isn't considered when the CPU
topology is populated
Hi Gavin,
Cc: Daniel and Markus
On 2022/4/14 8:06, Gavin Shan wrote:
Hi Yanan,
On 4/13/22 7:49 PM, wangyanan (Y) wrote:
On 2022/4/3 22:59, Gavin Shan wrote:
This adds cluster-id in CPU instance properties, which will be used
by arm/virt machine. Besides, the cluster-id is also verified
On 2022/4/14 8:08, Gavin Shan wrote:
Hi Yanan,
On 4/13/22 8:39 PM, wangyanan (Y) wrote:
On 2022/4/3 22:59, Gavin Shan wrote:
Currently, the SMP configuration isn't considered when the CPU
topology is populated. In this case, it's impossible to provide
the default CPU-to-NUMA mapping
Hi Gavin,
On 2022/4/3 22:59, Gavin Shan wrote:
Currently, the SMP configuration isn't considered when the CPU
topology is populated. In this case, it's impossible to provide
the default CPU-to-NUMA mapping or association based on the socket
ID of the given CPU.
This takes account of SMP
Hi Gavin,
On 2022/4/3 22:59, Gavin Shan wrote:
This adds cluster-id in CPU instance properties, which will be used
by arm/virt machine. Besides, the cluster-id is also verified or
dumped in various spots:
* hw/core/machine.c::machine_set_cpu_numa_node() to associate
CPU with its NUMA
On 2022/3/30 20:50, Igor Mammedov wrote:
On Sat, 26 Mar 2022 02:49:59 +0800
Gavin Shan wrote:
Hi Igor,
On 3/25/22 9:19 PM, Igor Mammedov wrote:
On Wed, 23 Mar 2022 15:24:35 +0800
Gavin Shan wrote:
Currently, the SMP configuration isn't considered when the CPU
topology is populated. In
Hi Gavin,
On 2022/3/23 15:24, Gavin Shan wrote:
Currently, the SMP configuration isn't considered when the CPU
topology is populated. In this case, it's impossible to provide
the default CPU-to-NUMA mapping or association based on the socket
ID of the given CPU.
This takes account of SMP
On 2022/3/23 15:24, Gavin Shan wrote:
When CPU-to-NUMA association isn't explicitly provided by users,
the default on is given by mc->get_default_cpu_node_id(). However,
s/on/one
the CPU topology isn't fully considered in the default association
and this causes CPU topology broken warnings
On 2022/3/18 21:27, Igor Mammedov wrote:
On Fri, 18 Mar 2022 21:00:35 +0800
"wangyanan (Y)" wrote:
On 2022/3/18 17:56, Igor Mammedov wrote:
On Fri, 18 Mar 2022 14:23:34 +0800
"wangyanan (Y)" wrote:
Hi Gavin,
On 2022/3/3 11:11, Gavin Shan wrote:
The default CPU
On 2022/3/18 17:56, Igor Mammedov wrote:
On Fri, 18 Mar 2022 14:23:34 +0800
"wangyanan (Y)" wrote:
Hi Gavin,
On 2022/3/3 11:11, Gavin Shan wrote:
The default CPU-to-NUMA association is given by mc->get_default_cpu_node_id()
when it isn't provided explicitly. However, the CPU t
Hi Gavin,
On 2022/3/3 11:11, Gavin Shan wrote:
When the PPTT table is built, the CPU topology is re-calculated, but
it's unecessary because the CPU topology, except the cluster IDs,
has been populated in virt_possible_cpu_arch_ids() on arm/virt machine.
This avoids to re-calculate the CPU
Hi Gavin,
On 2022/3/3 11:11, Gavin Shan wrote:
The default CPU-to-NUMA association is given by mc->get_default_cpu_node_id()
when it isn't provided explicitly. However, the CPU topology isn't fully
considered in the default association and it causes CPU topology broken
warnings on booting Linux
On 2022/3/16 22:55, Cornelia Huck wrote:
Add 7.1 machine types for arm/i440fx/m68k/q35/s390x/spapr.
Signed-off-by: Cornelia Huck
---
hw/arm/virt.c | 9 -
hw/core/machine.c | 3 +++
hw/i386/pc.c | 3 +++
hw/i386/pc_piix.c | 14
Hi Pierre,
On 2022/2/17 21:41, Pierre Morel wrote:
S390 CPU topology may have up to 5 topology containers.
The first container above the cores is level 2, the sockets,
and the level 3, containing sockets are the books.
We introduce here the drawers, drawers is the level containing books.
Hi Pierre,
On 2022/2/17 21:41, Pierre Morel wrote:
S390 CPU topology may have up to 5 topology containers.
The first container above the cores is level 2, the sockets.
We introduce here the books, book is the level containing sockets.
Let's add books, level3, containers to the CPU topology.
Hi,
On 2022/1/26 17:14, Igor Mammedov wrote:
On Wed, 26 Jan 2022 13:24:10 +0800
Gavin Shan wrote:
The default CPU-to-NUMA association is given by mc->get_default_cpu_node_id()
when it isn't provided explicitly. However, the CPU topology isn't fully
considered in the default association and
On 2022/1/12 1:55, Philippe Mathieu-Daudé wrote:
Fix typo in 'make check-help' output.
Signed-off-by: Philippe Mathieu-Daudé
---
tests/Makefile.include | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/Makefile.include b/tests/Makefile.include
index
On 2022/1/12 1:26, Peter Maydell wrote:
Fix a comment in qdev-core.h where we incorrectly referred
to TYPE_IRQ_SPLIT when we meant TYPE_SPLIT_IRQ.
Signed-off-by: Peter Maydell
---
include/hw/qdev-core.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On 2022/1/8 4:18, Richard Henderson wrote:
On 1/7/22 5:38 AM, Thomas Huth wrote:
diff --git a/softmmu/device_tree.c b/softmmu/device_tree.c
index 3965c834ca..9e96f5ecd5 100644
--- a/softmmu/device_tree.c
+++ b/softmmu/device_tree.c
@@ -564,7 +564,7 @@ int qemu_fdt_add_path(void *fdt, const
On 2022/1/7 21:38, Thomas Huth wrote:
If I configure my build with --enable-sanitizers, my GCC (v8.5.0)
complains:
.../softmmu/device_tree.c: In function ‘qemu_fdt_add_path’:
.../softmmu/device_tree.c:560:18: error: ‘retval’ may be used uninitialized
in this function
On 2022/1/4 12:27, Ani Sinha wrote:
On Tue, 4 Jan 2022, wangyanan (Y) wrote:
Hi Ani,
Thanks for your review.
On 2022/1/3 20:01, Ani Sinha wrote:
On Mon, 3 Jan 2022, Yanan Wang wrote:
Run ./tests/data/acpi/rebuild-expected-aml.sh from build directory
to update PPTT binary. Also empty
Hi Ani,
Thanks for your review.
On 2022/1/3 20:01, Ani Sinha wrote:
On Mon, 3 Jan 2022, Yanan Wang wrote:
Run ./tests/data/acpi/rebuild-expected-aml.sh from build directory
to update PPTT binary. Also empty bios-tables-test-allowed-diff.h.
The disassembled differences between actual and
On 2022/1/3 19:32, Andrew Jones wrote:
On Mon, Jan 03, 2022 at 04:46:35PM +0800, Yanan Wang wrote:
Support cluster level in generation of ACPI Processor Properties
Topology Table (PPTT) for ARM virt machines.
Signed-off-by: Yanan Wang
---
hw/arm/virt-acpi-build.c | 15 +++
1
Hi Drew,
Thanks for your review.
On 2022/1/3 19:24, Andrew Jones wrote:
On Mon, Jan 03, 2022 at 04:46:32PM +0800, Yanan Wang wrote:
Currently we generate a PPTT table of n-level processor hierarchy
with n-level loops in build_pptt(). It works fine as now there are
only three CPU topology
Hi Drew,
On 2022/1/3 19:30, Andrew Jones wrote:
On Mon, Jan 03, 2022 at 04:46:33PM +0800, Yanan Wang wrote:
We have a generic build_pptt() in hw/acpi/aml-build.c but it's
currently only used in ARM acpi initialization. Now we are going
to support the new CPU cluster parameter which is
On 2021/12/31 20:11, Philippe Mathieu-Daudé wrote:
On 12/31/21 08:30, wangyanan (Y) wrote:
Hi,
On 2021/12/30 6:52, Philippe Mathieu-Daudé wrote:
qdev_get_gpio_out_connector() is called by sysbus_get_connected_irq()
which is only used by platform-bus.c; restrict it to hw/core/ by
adding
The rest ARM & ACPI part (patches 8-14) have been packed into v6:
v6: https://patchew.org/QEMU/20220103084636.2496-1-wangyana...@huawei.com/
Thanks,
Yanan
On 2021/12/28 17:22, Yanan Wang wrote:
Hi,
This series introduces the new CPU clusters topology parameter
and enable the support for it on
On 2021/12/30 6:52, Philippe Mathieu-Daudé wrote:
sysbus_get_connected_irq() and sysbus_is_irq_connected() are only
used by platform-bus.c; restrict them to hw/core/ by adding a local
"sysbus-internal.h" header.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/core/sysbus-internal.h | 16
Hi,
On 2021/12/30 6:52, Philippe Mathieu-Daudé wrote:
qdev_get_gpio_out_connector() is called by sysbus_get_connected_irq()
which is only used by platform-bus.c; restrict it to hw/core/ by
adding a local "qdev-internal.h" header.
Signed-off-by: Philippe Mathieu-Daudé
---
On 2021/12/29 18:44, Philippe Mathieu-Daudé wrote:
On 12/29/21 04:48, wangyanan (Y) wrote:
Hi Philippe,
Thanks for your review.
On 2021/12/29 3:17, Philippe Mathieu-Daudé wrote:
Hi,
On 12/28/21 10:22, Yanan Wang wrote:
The new Cluster-Aware Scheduling support has landed in Linux 5.16
Hi Philippe,
Thanks for your review.
On 2021/12/29 3:17, Philippe Mathieu-Daudé wrote:
Hi,
On 12/28/21 10:22, Yanan Wang wrote:
The new Cluster-Aware Scheduling support has landed in Linux 5.16,
which has been proved to benefit the scheduling performance (e.g.
load balance and wake_affine
On 2021/12/29 3:23, Philippe Mathieu-Daudé wrote:
On 12/28/21 10:22, Yanan Wang wrote:
Wrap the CPU target specific parameters together into a single
variable except generic sockets/cores/threads, to make related
code lines shorter and more concise.
No functional change intended.
I have sent a v5 with four new patches added, so this v4 can be ignored.
v5: https://patchew.org/QEMU/20211228092221.21068-1-wangyana...@huawei.com/
Thanks,
Yanan
On 2021/11/21 20:24, Yanan Wang wrote:
Hi,
This series introduces the new CPU clusters topology parameter
and enable the support
On 2021/12/18 21:04, Philippe Mathieu-Daudé wrote:
Since the named GPIO lines are a "public" interface to the device,
we can directly call qdev_connect_gpio_out_named(), making it
consistent with how the other A20 input source (port92) is wired.
Suggested-by: Peter Maydell
Signed-off-by:
On 2021/12/18 21:04, Philippe Mathieu-Daudé wrote:
qdev_connect_gpio_out_named() is described as qdev_connect_gpio_out(),
and referring to itself in an endless loop, which is confusing. Fix.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/qdev-core.h | 5 +++--
1 file changed, 3
On 2021/12/18 21:04, Philippe Mathieu-Daudé wrote:
qdev_init_gpio_out_named() is described as qdev_init_gpio_out(),
and referring to itself in an endless loop, which is confusing. Fix.
Reported-by: Yanan Wang
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/qdev-core.h | 2 +-
1 file
On 2021/12/18 21:04, Philippe Mathieu-Daudé wrote:
Add empty lines to have a clearer distinction between different
functions declarations.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/qdev-core.h | 11 +++
1 file changed, 11 insertions(+)
Reviewed-by: Yanan Wang
Thanks,
Hi,
On 2021/12/16 21:23, Philippe Mathieu-Daudé wrote:
On 11/21/21 13:24, Yanan Wang wrote:
Wrap the CPU target specific parameters together into a single
variable, so that we don't need to update the other lines but
a single line when new topology parameters are introduced.
Where new params
On 2021/12/16 21:20, Philippe Mathieu-Daudé wrote:
Keep the common TYPE_MACHINE class initialization in
machine_base_class_init(), make it abstract, and move
the non-common code to a new class: "smp-generic-valid".
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
On 2021/12/16 21:20, Philippe Mathieu-Daudé wrote:
Avoid modifying the MachineClass internals by adding the
'smp-generic-invalid' machine, which inherits from TYPE_MACHINE.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
tests/unit/test-smp-parse.c | 25
Ping...
On 2021/11/21 20:24, Yanan Wang wrote:
Hi,
This series introduces the new CPU clusters topology parameter
and enable the support for it on ARM virt machines.
Background and descriptions:
The new Cluster-Aware Scheduling support has landed in Linux 5.16,
which has been proved to
On 2021/12/16 0:48, Philippe Mathieu-Daudé wrote:
Keep the common TYPE_MACHINE class initialization in
machine_base_class_init(), make it abstract, and move
the non-common code to a new class: "smp-generic-valid".
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
Hi Philippe,
On 2021/12/16 0:48, Philippe Mathieu-Daudé wrote:
Avoid modifying the MachineClass internals by adding the
'smp-generic-invalid' machine, which inherits from TYPE_MACHINE.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
tests/unit/test-smp-parse.c | 25
On 2021/11/17 16:08, Philippe Mathieu-Daudé wrote:
Hi Yanan,
On 11/17/21 08:37, wangyanan (Y) wrote:
On 2021/11/15 22:58, Philippe Mathieu-Daudé wrote:
Keep the common TYPE_MACHINE class initialization in
machine_base_class_init(), make it abstract, and move
the non-common code to a new
Hi Philippe,
On 2021/11/15 22:58, Philippe Mathieu-Daudé wrote:
Keep the common TYPE_MACHINE class initialization in
machine_base_class_init(), make it abstract, and move
the non-common code to a new class: "smp-without-dies-valid".
Signed-off-by: Philippe Mathieu-Daudé
---
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